Fujitsu MHF2021AT, MHE2043AT, MHE2064AT, MHF2043AT User Manual

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MHE2064AT, MHE2043AT MHF2043AT, MHF2021AT

DISK DRIVE

C141-E057-02EN

PRODUCT MANUAL

FOR SAFE OPERATION

Handling of This Manual

This manual contains important information for using this product. Read thoroughly before using the product. Use this product only after thoroughly reading and understanding especially the section “Important Alert Items” in this manual. Keep this manual handy, and keep it carefully.

FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering damage to their property. Use the product according to this manual.

IMPORTANT NOTE TO USERS

READ THE ENTIRE MANUAL CAREFULLY BEFORE USING THIS PRODUCT. INCORRECT USE OF THE PRODUCT MAY RESULT IN INJURY OR DAMAGE TO USERS, BYSTANDERS OR PROPERTY.

While FUJITSU has sought to ensure the accuracy of all information in this manual, FUJITSU assumes no liability to any party for any damage caused by any error or omission contained in this manual, its updates or supplements, whether such errors or omissions result from negligence, accident, or any other cause. In addition, FUJITSU assumes no liability with respect to the application or use of any product or system in accordance with the descriptions or instructions contained herein; including any liability for incidental or consequential damages arising therefrom. FUJITSU DISCLAIMS ALL WARRANTIES REGARDING THE INFORMATION CONTAINED HEREIN, WHETHER EXPRESSED, IMPLIED, OR STATUTORY.

FUJITSU reserves the right to make changes to any products described herein without further notice and without obligation.

The contents of this manual may be revised without prior notice.

The contents of this manual shall not be disclosed in any way or reproduced in any media without the express written permission of Fujitsu Limited.

 FUJITSU LIMITED 1998

C141-E057-01EN

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Revision History

(1/1)

Edition Date Revised section (*1)

(Added/Deleted/Altered)

01 1998-06-20 — — 02 1998-09-10

Details

*1 Section(s) with asterisk (*) refer to the previous edition when those were deleted.

C141-E057-02EN

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This manual describes the MHE Series and MHF Series, 2.5-inch hard disk drives. These drives have a built-in controller that is compatible with the ATA interface.

This manual describes the specifications and functions of the drives and explains in detail how to incorporate the drives into user systems. This manual assumes that the reader has a basic knowledge of hard disk drives and their implementations in computer systems.

This manual consists of seven chapters and sections explaining the special terminology and abbreviations used in this manual:

Overview of Manual

CHAPTER 1 Device Overview

This chapter gives an overview of the MHE Series and MHF Series and describes their features.

Preface

CHAPTER 2 Device Configuration

This chapter describes the internal configurations of the MHE Series and MHF Series and the configuration of the systems in which they operate.

CHAPTER 3 Installation Conditions

This chapter describes the external dimensions, installation conditions, and switch settings of the MHE Series and MHF Series.

CHAPTER 4 Theory of Device Operation

This chapter describes the operation theory of the MHE Series and MHF Series.

CHAPTER 5 Interface

This chapter describes the interface specifications of the MHE Series and MHF Series.

CHAPTER 6 Operations

This chapter describes the operations of the MHE Series and MHF Series.

Terminology

This section explains the special terminology used in this manual.

Abbreviation

This section gives the meanings of the definitions used in this manual.

C141-E057-01EN i

Preface

This indicates a hazarous situation could result in

minor or moderate personal injury if the user does

not perform the procedure correctly. This alert signal

also indicates that damages to the product or other

property, may occur if the user does not perform the

procedure correctly.

This indicates information that could help the user

use the product more efficiently.

Conventions for Alert Messages

This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word.

The following are the alert signals and their meanings:

In the text, the alert signal is centered, followed below by the indented message. A wider line space precedes and follows the alert message to show where the alert message begins and ends. The following is an example:

(Example)

Data corruption: Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure that the disk drive is not affected by external magnetic fields.

The main alert messages in the text are also listed in the “Important Alert Items.”

Operating Environment

This product is designed to be used in offices or computer rooms.

For details regarding the operating environment of use, refer to the (Cnnn-Xnnn) and the (Cnnn-Xnnn).

Attention

Please forward any comments you may have regarding this manual.

To make this manual easier for users to understand, opinions from readers are needed. Please write your opinions or requests on the Comment at the back of this manual and forward it to the address described in the sheet.

ii C141-E057-01EN

Liability Exception

“Disk drive defects” refers to defects that involve adjustment, repair, or replacement.

Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.

Preface

C141-E057-01EN iii

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Important Alert Items

A hazardous situation could result in minor or moderate personal

injury if the user does not perform the procedure correctly. Also,

damage to the predate or other property, may occur if the user does not

perform the procedure correctly.

Alert message

Page

Normal Operation

Data corruption: Avoid mounting the disk near strong

magnetic soures such as loud speakers. Ensure that the disk

drive is not affected by extrnal magnetic fields.

Stastic: When handling the device, disconnect the body

ground (500 kΩ or greater). Do not touch the printed circuit

board, but hold it by the edges.

3-7

Important Alert Messages

The important alert messages in this manual are as follows:

Task

C141-E057-02EN v

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MHE2064AT, MHE2043AT

MHF2043AT, MHF2021AT

DISK DRIVE

PRODUCT MANUAL

(C141-E057)

Device Overview

Device Configuration

Installation Conditions

Theory of Device Operation

Interface

Operations

MHE2064AT, MHE2054AT

MHF2043AT, MHF2032AT

MHF2021AT

DISK DRIVE

MAINTENANCE MANUAL

(C141-F031)

Maintenance and Diagnosis

Removal and Replacement Procedure

Manual Organization

•

C141-E057-02EN vii

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CHAPTER 1 Device Overview........................................................................1-1

1.1 Features 1-2

1.1.1 Functions and performance 1-2

1.1.2 Adaptability 1-2

1.1.3 Interface 1-3

1.2 Device Specifications 1-4

1.2.1 Specifications summary 1-4

1.2.2 Model and product number 1-6

1.3 Power Requirements 1-6

1.4 Environmental Specifications 1-8

1.5 Acoustic Noise 1-9

1.6 Shock and Vibration 1-9

1.7 Reliability 1-10

1.8 Error Rate 1-11

1.9 Media Defects 1-11

CHAPTER 2 Device Configuration................................................................2-1

2.1 Device Configuration 2-2

2.2 System Configuration 2-4

2.2.1 ATA interface 2-4

2.2.2 1 drive connection 2-4

2.2.3 2 drives connection 2-4

C141-E057-01EN ix

Contents

CHAPTER 3 Installation Conditions..............................................................3-1

3.1 Dimensions 3-2

3.2 Mounting 3-4

3.3 Cable Connections 3-8

3.3.1 Device connector 3-8

3.3.2 Cable connector specifications 3-9

3.3.3 Device connection 3-9

3.3.4 Power supply connector (CN1) 3-10

3.4 Jumper Settings 3-10

3.4.1 Location of setting jumpers 3-10

3.4.2 Factory default setting 3-11

3.4.3 Master drive-slave drive setting 3-11

3.4.4 CSEL setting 3-12

CHAPTER 4 Theory of Device Operation...................................................... 4-1

4.1 Outline 4-2

4.2 Subassemblies 4-2

4.2.1 Disk 4-2

4.2.2 Head 4-2

4.2.3 Spindle 4-3

4.2.4 Actuator 4-3

4.2.5 Air filter 4-3

4.3 Circuit Configuration 4-4

4.4 Power-on Sequence 4-6

4.5 Self-calibration 4-7

4.5.1 Self-calibration contents 4-7

4.5.2 Execution timing of self-calibration 4-8

4.5.3 Command processing during self-calibration 4-9

4.6 Read/write Circuit 4-9

x C141-E057-01EN

Contents

4.6.1 Read/write preamplifier (PreAMP) 4-9

4.6.2 Write circuit 4-10

4.6.3 Read circuit 4-12

4.6.4 Digital PLL circuit 4-13

4.7 Servo Control 4-14

4.7.1 Servo control circuit 4-14

4.7.2 Data-surface servo format 4-18

4.7.3 Servo frame format 4-18

4.7.4 Actuator motor control 4-19

4.7.5 Spindle motor control 4-20

CHAPTER 5 Interface.....................................................................................5-1

5.1 Physical Interface 5-2

5.1.1 Interface signals 5-2

5.1.2 Signal assignment on the connector 5-3

5.2 Logical Interface 5-6

5.2.1 I/O registers 5-7

5.2.2 Command block registers 5-8

5.2.3 Control block registers 5-13

5.3 Host Commands 5-13

5.3.1 Command code and parameters 5-14

5.3.2 Command descriptions 5-16

5.3.3 Error posting 5-71

5.4 Command Protocol 5-73

5.4.1 Data transferring commands from device to host 5-73

5.4.2 Data transferring commands from host to device 5-75

5.4.3 Commands without data transfer 5-77

5.4.4 Other commands 5-78

5.4.5 DMA data transfer commands 5-78

5.5 Ultra DMA Feature Set 5-80

5.5.1 Overview 5-80

C141-E057-01EN xi

Contents

5.5.2 Phases of operation 5-81

5.5.2.1 Ultra DMA burst initiation phase 5-81

5.5.2.2 Data transfer phase 5-82

5.5.2.3 Ultra DMA burst termination phase 5-82

5.5.3 Ultra DMA data in commands 5-83

5.5.3.1 Initiating an Ultra DMA data in burst 5-83

5.5.3.2 The data in transfer 5-84

5.5.3.3 Pausing an Ultra DMA data in burst 5-84

5.5.3.4 Terminating an Ultra DMA data in burst 5-85

5.5.4 Ultra DMA data out commands 5-88

5.5.4.1 Initiating an Ultra DMA data out burst 5-88

5.5.4.2 The data out transfer 5-88

5.5.4.3 Pausing an Ultra DMA data out burst 5-89

5.5.4.4 Terminating an Ultra DMA data out burst 5-90

5.5.5 Ultra DMA CRC rules 5-92

5.5.6 Series termination required for Ultra DMA 5-94

5.6 Timing 5-95

5.6.1 PIO data transfer 5-95

5.6.2 Single word DMA data transfer 5-97

5.6.3 Multiword DMA data transfer 5-98

5.6.4 Transfer of Ultra DMA data 5-99

5.6.4.1 Starting of Ultra DMA data In Burst 5-99

5.6.4.2 Ultra DMA data burst timing requirements 5-100

5.6.4.3 Sustained Ultra DMA data in burst 5-102

5.6.4.4 Host pausing an Ultra DMA data in burst 5-103

5.6.4.5 Device terminating an Ultra DMA data in burst 5-104

5.6.4.6 Host terminating an Ultra DMA data in burst 5-105

5.6.4.7 Initiating an Ultra DMA data out burst 5-106

5.6.4.8 Sustained Ultra DMA data out burst 5-107

5.6.4.9 Device pausing an Ultra DMA data out burst 5-108

5.6.4.10 Host terminating an Ultra DMA data out burst 5-109

5.6.4.11 Device terminating an Ultra DMA data in burst 5-110

5.6.5 Power-on and reset 5-111

xii C141-E057-01EN

Contents

CHAPTER 6 Operations.................................................................................6-1

6.1 Device Response to the Reset 6-2

6.1.1 Response to power-on 6-2

6.1.2 Response to hardware reset 6-4

6.1.3 Response to software reset 6-5

6.1.4 Response to diagnostic command 6-6

6.2 Address Translation 6-7

6.2.1 Default parameters 6-7

6.2.2 Logical address 6-8

6.3 Power Save 6-9

6.3.1 Power save mode 6-9

6.3.2 Power commands 6-11

6.4 Defect Management 6-11

6.4.1 Spare area 6-12

6.4.2 Alternating defective sectors 6-12

6.5 Read-Ahead Cache 6-14

6.5.1 Data buffer configuration 6-14

6.5.2 Caching operation 6-14

6.5.3 Usage of read segment 6-16

6.5.3.1 Mis-hit (no hit) 6-16

6.5.3.2 Sequential read 6-17

6.5.3.3 Full hit (hit all) 6-20

6.5.3.4 Partially hit 6-21

6.6 Write Cache 6-22

Glossary .................................................................................................GL-1

Acronyms and Abbreviations ........................................................................AB-1

Index ................................................................................................ ...IN-1

C141-E057-01EN xiii

Contents

Figures

Illustrations

Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on 1-7

Figure 2.1 Disk drive outerview (the MHE Series and MHF Series) 2-2 Figure 2.2 Configuration of disk media heads 2-3 Figure 2.3 1 drive system configuration 2-4 Figure 2.4 2 drives configuration 2-4

Figure 3.1 Dimensions (MHE/MHF series) 3-2 Figure 3.2 Orientation (Sample: MHE2064AT) 3-4 Figure 3.3 Mounting frame structure 3-5 Figure 3.4 Surface temperature measurement points (Sample: MHE2064AT)

3-6 Figure 3.5 Service area (Sample: MHE2064AT) 3-7 Figure 3.6 Connector locations (Sample: MHE2064AT) 3-8 Figure 3.7 Cable connections 3-9 Figure 3.8 Power supply connector pins (CN1) 3-10 Figure 3.9 Jumper location 3-10 Figure 3.10 Factory default setting 3-11 Figure 3.11 Jumper setting of master or slave device 3-11 Figure 3.12 CSEL setting 3-12 Figure 3.13 Example (1) of Cable Select 3-12 Figure 3.14 Example (2) of Cable Select 3-13

Figure 4.1 Head structure 4-3 Figure 4.2 Circuit Configuration 4-5 Figure 4.3 Power-on operation sequence 4-7 Figure 4.4 Read/write circuit block diagram 4-11 Figure 4.5 Frequency characteristic of programmable filter 4-12 Figure 4.6 Block diagram of servo control circuit 4-14 Figure 4.7 Physical sector servo configuration on disk surface 4-16 Figure 4.8 Servo frame format 4-18

Figure 5.1 Interface signals 5-2 Figure 5.2 Execution example of READ MULTIPLE command 5-20 Figure 5.3 Read Sector(s) command protocol 5-74 Figure 5.4 Protocol for command abort 5-75

xiv C141-E057-01EN

Contents

Figure 5.5 WRITE SECTOR(S) command protocol 5-76 Figure 5.6 Protocol for the command execution without data transfer 5-

78 Figure 5.7 Normal DMA data transfer 5-79 Figure 5.8 An example of generation of parallel CRC 5-93 Figure 5.9 Ultra DMA termination with pull-up or pull-down 5-94 Figure 5.10 Data transfer timing 5-96 Figure 5.11 Single word DMA data transfer timing (mode 2) 5-97 Figure 5.12 Multiword DMA data transfer timing (mode 2) 5-98 Figure 5.13 Starting of Ultra DMA data In Burst transfer 5-99 Figure 5.14 Sustained Ultra DMA data in burst 5-102 Figure 5.15 Host pausing an Ultra DMA data in burst 5-103 Figure 5.16 Device terminating an Ultra DMA data in burst 5-104 Figure 5.17 Host terminating an Ultra DMA data in burst 5-105 Figure 5.18 Initiating an Ultra DMA data out burst 5-106 Figure 5.19 Sustained Ultra DMA data out burst 5-107 Figure 5.20 Device pausing an Ultra DMA data out burst 5-108 Figure 5.21 Host terminating an Ultra DMA data out burst 5-109 Figure 5.22 Device terminating an Ultra DMA data out burst 5-110 Figure 5.23 Power on Reset Timing 5-111

Tables

Figure 6.1 Response to power-on 6-3 Figure 6.2 Response to hardware reset 6-4 Figure 6.3 Response to software reset 6-5 Figure 6.4 Response to diagnostic command 6-6 Figure 6.5 Address translation (example in CHS mode) 6-8 Figure 6.6 Address translation (example in LBA mode) 6-9 Figure 6.7 Sector slip processing 6-12 Figure 6.8 Alternate cylinder assignment 6-13 Figure 6.9 Data buffer configuration 6-14

Table 1.1 Specifications (MHE2064AT/MHE2043AT) 1-4 Table 1.2 Specifications (MHF2043AT/MHF2021AT) 1-5 Table 1.3 Specifications (MHE2064AT/2043AT/MHF2043AT/2021AT)

1-6 Table 1.4 Model names and product numbers 1-6 Table 1.5 Current and power dissipation 1-7 Table 1.6 Environmental specifications 1-8 Table 1.7 Acoustic noise specification 1-9 Table 1.8 Shock and vibration specification 1-9

C141-E057-02EN xv

Contents

Table 3.1 Surface temperature measurement points and standard values

3-6

Table 3.2 Cable connector specifications 3-9

Table 4.1 Self-calibration execution timechart 4-9 Table 4.2 Write precompensation algorithm 4-10

Table 5.1 Signal assignment on the interface connector 5-3 Table 5.2 I/O registers 5-7 Table 5.3 Command code and parameters 5-14 Table 5.4 Information to be read by IDENTIFY DEVICE command 5-

32 Table 5.5 Features register values and settable modes 5-39 Table 5.6 Diagnostic code 5-46 Table 5.7 Features Register values (subcommands) and functions 5-57 Table 5.8 Format of device attribute value data 5-59 Table 5.9 Format of insurance failure threshold value data 5-60 Table 5.10 Contents of security password 5-64 Table 5.11 Contents of SECURITY SET PASSWORD data 5-68 Table 5.12 Relationship between combination of Identifier and Security

level, and operation of the lock function 5-69 Table 5.13 Command code and parameters 5-71 Table 5.14 Parallel generation equation of CRC polynomial 5-93 Table 5.15 Recommended series termination for Ultra DMA 5-94 Table 5.16 Ultra DMA data burst timing requirements 5-100

Table 6.1 Default parameters 6-7

xvi C141-E057-01EN

CHAPTER 1 Device Overview

1.1 Features

1.2 Device Specifications

1.3 Power Requirements

1.4 Environmental Specifications

1.5 Acoustic Noise

1.6 Shock and Vibration

1.7 Reliability

1.8 Error Rate

1.9 Media Defects

Overview and features are described in this chapter, and specifications and power requirement are described.

The MHE Series and MHF Series controllers. These disk drives use the AT-bus hard disk interface protocol and are compact and reliable.

are 2.5-inch hard disk drives with built-in disk

C141-E057-01EN 1-1

Device Overview

1.1 Features

1.1.1 Functions and performance

The fillowing features of the MHE Series and MHF Series are described.

(1) Compact

The MHE2064AT and MHE2043AT have 3 disks, and its height is 12.5 mm (0.492 inch). The MHF2043AT and MHF2021AT have 1 disk or 2 disks of 65 mm (2.5 inches) diameter, and its height is 9.5 mm (0.374 inch).

(2) Large capacity

The disk drive can record up to 2.16 GB (formatted) on one disk using the (16/17) EPR4ML recording method and 14 recording zone technology. The MHE Series and MHF Series (MHE2043AT), 4.32 GB (MHF2043AT), 2.16 GB (MHF2021AT) respectively.

have a formatted capacity of 6.49 GB (MHE2064AT), 4.32 GB

(3) High-speed Transfer rate

The disk drives (the MHE Series and MHF Series) have an internal data rate up to

13.6 MB/s. The disk drive supports an external data rate up to 33.3 MB/s (UDMA mode 2).

(4) Average positioning time

Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed. The average positioning time is 13 ms (at read).

1.1.2 Adaptability

(1) Power save mode

The power save mode feature for idle operation, stand by and sleep modes makes The disk drives (the MHE Series and MHF Series) ideal for applications where power consumption is a factor.

(2) Wide temperature range

The disk drives (the MHE Series and MHF Series) can be used over a wide temperature range (5°C to 55°C).

(3) Low noise and vibration

In Ready status, the noise of the disk drives (the MHE Series and MHF Series) is only about 30 dBA (measured at 1 m apart from the drive under the idle mode).

1-2 C141-E057-02EN

1.1.3 Interface

(1) Connection to interface

With the built-in ATA interface controller, the disk drives (the MHE Series and MHF Series) can be connected to an ATA interface of a personal computer.

(2) 512-KB data buffer

The disk drives (the MHE Series and MHF Series) uses a 512-KB data buffer to transfer data between the host and the disk media.

In combination with the read-ahead cache system described in item (3) and the write cache described in item (7), the buffer contributes to efficient I/O processing.

(3) Read-ahead cache system

After the execution of a disk read command, the disk drive automatically reads the subsequent data block and writes it to the data buffer (read ahead operation). This cache system enables fast data access. The next disk read command would normally cause another disk access. But, if the read ahead data corresponds to the data requested by the next read command, the data in the buffer can be transferred instead.

1.1 Features

(4) Master/slave

The disk drives (the MHE Series and MHF Series) can be connected to ATA interface as daisy chain configuration. Drive 0 is a master device, drive 1 is a slave device.

(5) Error correction and retry by ECC

If a recoverable error occurs, the disk drives (the MHE Series and MHF Series) themselves attempt error recovery. The ECC has improved buffer error correction for correctable data errors.

(6) Self-diagnosis

The disk drives (the MHE Series and MHF Series) have a diagnostic function to check operation of the controller and disk drives. Executing the diagnostic command invokes self-diagnosis.

(7) Write cache

When the disk drives (the MHE Series and MHF Series) receive a write command, the disk drives post the command completion at completion of transferring data to the data buffer completion of writing to the disk media. This feature reduces the access time at writing.

C141-E057-01EN 1-3

Device Overview

Format Capacity (*1)

6.49 GB

4.32 GB

Number of Heads

Number of Cylinders (User)

8,647

Bytes per Sector

Recording Method

(16/17) EPR4ML

Track Density

14,200 TPI

Bit Density

237.8 Kbpi

Rotational Speed

4,200 rpm ± 1%

Average Latency

7.14 ms

Positioning time (read and seek)

• Minimum (Track to Track)

• Average

• Maximum (Full)

1.5 ms (typ.)

Read: 13 ms (typ.)

23 ms (typ.)

Start/Stop time

• Start (0 rpm to Drive Read)

• Stop (at Power Down)

Typ.: 5 sec

Interface

ATA-4 (Max. Cable length: 0.46 m)

Data Transfer Rate

• To/From Media

7.7 to 13.6 MB/s

• To/From Host

33.3 MB/s Max.

(U-DMA mode 2)

Data Buffer Size

512 KB

Physical Dimensions

(Height × Width × Depth)

12.5 mm × 100.0 mm ×70.0 mm

Weight

145 g

1.2 Device Specifications

1.2.1 Specifications summary

Table 1.1 shows the specfications of the disk drives (MHE2064AT/MHE2043AT).

Table 1.1 Specifications (MHE2064AT/MHE2043AT)

MHE2064AT MHE2043AT

6 4

512

1-4 C141-E057-02EN

1.2 Device Specifications

Format Capacity (*1)

4.32 GB

2.16 GB

Number of Heads

Number of Cylinders (User)

8,647

Bytes per Sector

Recording Method

(16/17) EPR4ML

Track Density

14,200 TPI

Bit Density

237.8 Kbpi

Rotational Speed

4,200 rpm ± 1%

Average Latency

7.14 ms

Positioning time (read and seek)

• Minimum (Track to Track)

• Average

• Maximum (Full)

1.5 ms (typ.)

Read: 13 ms (typ.)

23 ms (typ.)

Start/Stop time

• Start (0 rpm to Drive Read)

• Stop (at Power Down)

Typ.: 5 sec

Interface

ATA-4 (Max. Cable length: 0.46 m)

Data Transfer Rate

• To/From Media

7.7 to 13.6 MB/s

• To/From Host

33.3 MB/s Max.

(U-DMA mode 2)

Data Buffer Size

512 KB

Physical Dimensions

(Height × Width × Depth)

9.5 mm × 100.0 mm × 70.0 mm

Weight

98 g

Table 1.2 shows the specfications of the disk drives (MHF2043AT/MHF2021AT).

Table 1.2 Specifications (MHF2043AT/MHF2021AT)

MHF2043AT MHF2021AT

4 2

512

*1: Capacity under the LBA mode.

C141-E057-02EN 1-5

Device Overview

Formatted Capacity

No. of Cylinder

No. of Heads

No. of Sectors

6,495.06 MB

13,424

4,327.46 MB

8,944

4,327.46 MB

8,944

2,167.60 MB

4,200

Model Name

Capacity

(user area)

Mounting screw

Order No.

6.49 GB

M3, depth 3

CA01757-B060

4.32 GB

M3, depth 3

CA01757-B040

4.32 GB

M3, depth 3

CA01758-B040

2.16 GB

M3, depth 3

CA01758-B020

+5 V

Maximum

100 mV (peak to peak)

Frequency

DC to 1 MHz

Table 1.3 Specifications (MHE2064AT/2043AT/MHF2043AT/2021AT)

Model

Under the CHS mode (normal BIOS specification), formatted capacity, number of cylinders, number of heads, and number of sectors are as follows.

MHE2064AT MHE2043AT MHF2043AT MHF2021AT

1.2.2 Model and product number

Table 1.4 lists the model names and product numbers of the MHE Series and MHF Series.

Table 1.4 Model names and product numbers

MHE2064AT MHE2043AT MHF2043AT

15 63 15 63 15 63 16 63

MHF2021AT

1.3 Power Requirements

(1) Input Voltage

• + 5 V ± 5 %

(2) Ripple

1-6 C141-E057-02EN

(3) Current Requirements and Power Dissipation

Typical RMS Current

Typical Power (*3)

MHE Series

MHF Series

MHE Series

MHF Series

Spin up (*1)

0.9 A

4.5 W

Idle

190 mA

0.95 W

R/W (*2)

430 mA

2.15 W

Standby

70 mA

0.35 W

Sleep

26 mA

0.13 W

Energy

Consumption

Efficiency (*4)

0.0001 W/MB

0.0004 W/MB

Table 1.5 lists the current and power dissipation.

Table 1.5 Current and power dissipation

— —

1.3 Power Requirements

*1 Current at starting spindle motor.

*2 Power requirements reflect nominal values for +5V power.

*3 At 30% disk accessing.

*4 Energy Consumption Efficiency =

Idle power dissipation / Total record capacity (MB)

(4) Current fluctuation (Typ.) at +5V when power is turned on

Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on

C141-E057-01EN 1-7

Device Overview

Item

Specification

Temperature

• Operating

• Non-operating

• Thermal Gradient

5°C to 55°C (ambient)

5°C to 60°C (disk enclosure surface)

40°C to 65°C

20°C/h or less

Humidity

• Operating

• Non-operating

• Maximum Wet Bulb

8% to 90% RH (Non-condensing)

5% to 95% RH (Non-condensing)

Altitude (relative to sea level)

• Operating

• Non-operating

300 to 3,000 m

300 to 12,000 m

(5) Power on/off sequence

The voltage detector circuits (the MHE Series and MHF Series) monitor +5 V. The circuits do not allow a write signal if either voltage is abnormal. These prevent data from being destroyed and eliminates the need to be concerned with the power on/off sequence.

1.4 Environmental Specifications

Table 1.6 lists the environmental specifications.

Table 1.6 Environmental specifications

–

29°C

– –

1-8 C141-E057-01EN

1.5 Acoustic Noise

Item

Specification

Sound Pressure

• Idle mode (DRIVE READY)

30 dBA typical at 1 m

Item

Specification

Vibration (swept sine, one octave per minute)

• Operating

• Non-operating

5 to 500 Hz, 1.0G0-peak (MHE series)

5 to 400 Hz, 1.0G0-peak (MHF series)

(without non-recovered errors) (9.8 m/s

0-peak)

5 to 500 Hz, 5G0-peak (MHE series)

5 to 400 Hz, 5G0-peak (MHF series)

(no damage) (49 m/s

0-peak)

Shock (half-sine pulse)

• Operating

• Non-operating

125G0-peak

(without non-recovered errors) (1,225 m/s

0-peak)

600G0-peak (MHE series) (5,880 m/s

0-peak)

2 ms duration

600G0-peak (MHF series) (5,880 m/s

0-peak)

1 ms duration (no damage)

Table 1.7 lists the acoustic noise specification.

Table 1.7 Acoustic noise specification

Note:

Measure the noise from the cover top surface.

1.6 Shock and Vibration

Table 1.8 lists the shock and vibration specification.

Table 1.8 Shock and vibration specification

C141-E057-02EN 1-9

Device Overview

Conditions of 300,000 h

Current time

250H/month or less 3000H/years

or less

Operating time

20% or less of current time

CSS operations

50/day or less

Total 50,000 or less

Power on/off

1/day or more needed.

Environment

5 to 55°C/8 to 90%

But humidity bulb temperature

29°C or less

1.7 Reliability

(1) Mean time between failures (MTBF)

MTBF is defined as follows:

Total operation time in all fields

MTBF= (H)

number of device failure in all fields

“Disk drive defects” refers to defects that involve repair, readjustment, or replacement. Disk drive defects do not include failures caused by external factors, such as damage caused by handling, inappropriate operating environments, defects in the power supply host system, or interface cable.

(2) Mean time to repair (MTTR)

The mean time to repair (MTTR) is 30 minutes or less, if repaired by a specialist maintenance staff member.

(3) Service life

In situations where management and handling are correct, the disk drive requires no overhaul for five years when the DE surface temperature is less than 48°C. When the DE surface temperature exceeds 48°C, the disk drives requires no overhaul for five years or 20,000 hours of operation, whichever occurs first. Refer to item (3) in Subsection 3.2 for the measurement point of the DE surface temperature. Also the operating conditions except the environment temperature are based on the MTBF conditions.

(4) Data assurance in the event of power failure

Except for the data block being written to, the data on the disk media is assured in the event of any power supply abnormalities. This does not include power supply abnormalities during disk media initialization (formatting) or processing of defects (alternative block assignment).

1-10 C141-E057-01EN

1.8 Error Rate

Known defects, for which alternative blocks can be assigned, are not included in the error rate count below. It is assumed that the data blocks to be accessed are evenly distributed on the disk media.

(1) Unrecoverable read error

Read errors that cannot be recovered by maximum read retries of drive without user’s retry and ECC corrections shall occur no more than 10 times when reading data of 10 recovery procedure, and include read retries accompanying head offset operations.

(2) Positioning error

1.9 Media Defects

bits. Read retries are executed according to the disk drive’s error

Positioning (seek) errors that can be recovered by one retry shall occur no more than 10 times in 10

1.9 Media Defects

Defective sectors are replaced with alternates when the disk (the MHE Series and MHF Series) are formatted prior to shipment from the factory (low level format). Thus, the hosts see a defect-free devices.

Alternate sectors are automatically accessed by the disk drive. The user need not be concerned with access to alternate sectors.

seek operations.

C141-E057-02EN 1-11

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CHAPTER 2 Device Configuration

2.1 Device Configuration

2.2 System Configuration

This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate.

C141-E057-01EN 2-1

Device Configuration

2.1 Device Configuration

Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors, actuators, and a circulating air filter.

MHF20xxATMHE20xxAT

(1) Disk

(2) Head

Figure 2.1 Disk drive outerview (the MHE Series and MHF Series)

The outer diameter of the disk is 65 mm. The inner diameter is 20 mm. The number of disks used varies with the model, as described below. The disks are rated at over 50,000 start/stop operations.

MHE2064AT: 3 disks MHE2043AT: 2 disks

MHF2043AT: 2 disks MHF2021AT: 1 disks

The heads are of the contact start/stop (CSS) type. The head touches the disk surface while the disk is not rotating and automatically lifts when the disk starts.

Figure 2.2 illustrates the configuration of the disks and heads of each model. In the disk surface, servo information necessary for controlling positioning and read/write and user data are written. Numerals 0 to 5 indicate read/write heads.

2-2 C141-E057-02EN

Head

5 4

2.1 Device Configuration

HeadHead

MHE2064AT

(3) Spindle motor

(4) Actuator

Head

MHE2043AT

Figure 2.2 Configuration of disk media heads

The disks are rotated by a direct drive Hall-less DC motor.

The actuator uses a revolving voice coil motor (VCM) structure which consumes low power and generates very little heat. The head assembly at the edge of the actuator arm is controlled and positioned by feedback of the servo information read by the read/write head. If the power is not on or if the spindle motor is stopped, the head assembly stays in the specific CSS zone on the disk and is fixed by a mechanical lock.

MHF2043AT

MHF2021AT

(5) Air circulation system

The disk enclosure (DE) is sealed to prevent dust and dirt from entering. The disk enclosure features a closed loop air circulation system that relies on the blower effect of the rotating disk. This system continuously circulates the air through the circulation filter to maintain the cleanliness of the air within the disk enclosure.

(6) Read/write circuit

The read/write circuit uses a LSI chip for the read/write preamplifier. It improves data reliability by preventing errors caused by external noise.

(7) Controller circuit

The controller circuit consists of an LSI chip to improve reliability. The highspeed microprocessor unit (MPU) achieves a high-performance AT controller.

C141-E057-02EN 2-3

Device Configuration

MHF2021AT

2.2 System Configuration

2.2.1 ATA interface

Figures 2.3 and 2.4 show the ATA interface system configuration. The drive has a 44-pin PC AT interface connector and supports the PIO transfer at 16.6 MB/s (ATA-3, Mode 4), the DMA transfer at 16.6 MB/s (ATA-3, Multiword mode 2) and also the U-DMA at 33.3 MB/s (ATA-3, Mode 2).

2.2.2 1 drive connection

MHE2064AT MHE2043AT

MHC2032AT

MHF2043AT

MHC2040AT

Figure 2.3 1 drive system configuration

2.2.3 2 drives connection

MHE2064AT MHE2043AT

(Host adaptor)

Note:

When the drive that is not conformed to ATA is connected to the disk drive above configuration, the operation is not guaranteed.

MHC2032AT

MHF2043AT

MHC2040AT

MHE2064AT MHE2043AT

MHC2032AT

MHF2043AT

MHC2040AT

Figure 2.4 2 drives configuration

2-4 C141-E057-02EN

2.2 System Configuration

HA (host adaptor) consists of address decoder, driver, and receiver. ATA is an abbreviation of “AT attachment”. The disk drive is conformed to the ATA-4 interface.

At high speed data transfer (PIO mode 3, mode 4, or DMA mode 2 U-DMA mode 2), occurence of ringing or crosstalk of the signal lines (AT bus) between the HA and the disk drive may be a great cause of the obstruction of system reliability. Thus, it is necessary that the capacitance of the signal lines including the HA and cable does not exceed the ATA-4 standard, and the cable length between the HA and the disk drive should be as short as possible.

No need to push the top cover of the disk drive. If the over-power worked, the cover could be contacted with the spindle motor. Thus, that could be made it the cause of failure.

C141-E057-01EN 2-5

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CHAPTER 3 Installation Conditions

3.1 Dimensions

3.2 Mounting

3.3 Cable Connections

3.4 Jumper Settings

This chapter gives the external dimensions, installation conditions, surface temperature conditions, cable connections, and switch settings of the hard disk drives.

C141-E057-01EN 3-1

Installation Conditions

3.1 Dimensions

Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm.

Figure 3.1 Dimensions (MHE series) (1/2)

3-2 C141-E057-01EN

3.1 Dimensions

Figure 3.1 Dimensions (MHF series) (2/2)

C141-E057-01EN 3-3

Installation Conditions

(e) Vertical

(f) Vertical

(d) Vertical

(b) Horizontal

(a) Horizontal

gravity

3.2 Mounting

(1) Orientation

Figure 3.2 illustrates the allowable orientations for the disk drive.

–1

–2

–3

Figure 3.2 Orientation (Sample: MHE2064AT)

3-4 C141-E057-01EN

–4

(2) Frame

Screw

Details of B

Details of A

3.0 or less

2.5

Bottom surface mounting

The MR head bias of the HDD disk enclosure (DE) is zero. The mounting frame is connected to SG.

Use M3 screw for the mounting screw and the screw length should satisfy the specification in Figure 3.3.

The tightening torque must not exceed 3 kgcm. When attaching the HDD to the system frame, do not allow the

system frame to touch parts (cover and base) other than parts to which the HDD is attached.

(3) Limitation of side-mounting

Do not use the center hole. For screw length, see Figure 3.3.

Note) These dimensions are recommended values; if it is not possible to

satisfy them, contact us.

3.2 Mounting

Frame of system cabinet

Figure 3.3 Mounting frame structure

2.5

Frame of system cabinet

Side surface mounting

PCA

2.5

Screw

C141-E057-01EN 3-5

Installation Conditions

No.

Measurement point

Temperature

DE cover

60°C max

(4) Ambient temperature

The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. The ambient temperature must satisfy the temperature conditions described in Section 1.4, and the airflow must be considered to prevent the DE surface temperature from exceeding 60

Provide air circulation in the cabinet such that the PCA side, in particular, receives sufficient cooling. To check the cooling efficiency, measure the surface temperatures of the DE. Regardless of the ambient temperature, this surface temperature must meet the standards listed in Table 3.1. Figure 3.4 shows the temperature measurement point.

°C.

Figure 3.4 Surface temperature measurement points (Sample: MHE2064AT)

Table 3.1 Surface temperature measurement points and standard values

3-6 C141-E057-01EN

(5) Service area

Mounting screw hole

3.2 Mounting

Figure 3.5 shows how the drive must be accessed (service areas) during and after installation.

Cable connection

Mounting screw hole

Figure 3.5 Service area (Sample: MHE2064AT)

Data corruption: Avoid mounting the disk drive near strong

magnetic sources such as loud speakers. Ensure that the disk drive is not affected by external magnetic fields. Also, do not press the cover of the disk drive. Pressing it too much, the cover and the spindle motor contacts and it is fear of causes of the trouble being.

Stastic: When handling the device, disconnect the body ground (500 k

Ω or greater). Do not touch the printed circuit board, but

hold it by the edges.

C141-E057-02EN 3-7

Installation Conditions

3.3 Cable Connections

3.3.1 Device connector

The disk drive has the connectors and terminals listed below for connecting external devices. Figure 3.6 shows the locations of these connectors and terminals.

PCA

Connector, setting pins

Figure 3.6 Connector locations (Sample: MHE2064AT)

3-8 C141-E057-01EN

3.3.2 Cable connector specifications

ATA interface and power

supply cable (44-pin type)

Cable socket

(44-pin type)

89361-144

Table 3.2 lists the recommended specifications for the cable connectors.

Table 3.2 Cable connector specifications

Name Model Manufacturer

For the host interface cable, use a ribbon cable. A twisted cable or a cable with wires that have become separated from the ribbon may cause crosstalk between signal lines. This is because the interface is designed for ribbon cables and not for cables carrying differential signals.

3.3 Cable Connections

BERG

3.3.3 Device connection

Figure 3.7 shows how to connect the devices.

Figure 3.7 Cable connections

C141-E057-01EN 3-9

Installation Conditions

3.3.4 Power supply connector (CN1)

Figure 3.8 shows the pin assignment of the power supply connector (CN1).

Figure 3.8 Power supply connector pins (CN1)

3.4 Jumper Settings

3.4.1 Location of setting jumpers

Figure 3.9 shows the location of the jumpers to select drive configuration and functions.

Figure 3.9 Jumper location

3-10 C141-E057-01EN

3.4.2 Factory default setting

Open

Figure 3.10 shows the default setting position at the factory.

3.4 Jumper Settings

Figure 3.10 Factory default setting

3.4.3 Master drive-slave drive setting

Master device (device #0) or slave device (device #1) is selected.

Open

1 C

Open

AC1

Short

BD2

(b) Slave drive(a) Master drive

Figure 3.11 Jumper setting of master or slave device

Note:

Pins A and C should be open.

C141-E057-02EN 3-11

Installation Conditions

3.4.4 CSEL setting

Figure 3.12 shows the cable select (CSEL) setting.

Note:

Open

AC1

BD2

Short

The CSEL setting is not depended on setting between pins Band D.

Figure 3.12 CSEL setting

Figure 3.13 and 3.14 show examples of cable selection using unique interface cables.

By connecting the CSEL of the master device to the CSEL Line (conducer) of the cable and connecting it to ground further, the CSEL is set to low level. The device is identified as a master device. At this time, the CSEL of the slave device does not have a conductor. Thus, since the slave device is not connected to the CSEL conductor, the CSEL is set to high level. The device is identified as a slave device.

Figure 3.13 Example (1) of Cable Select

3-12 C141-E057-02EN

Figure 3.14 Example (2) of Cable Select

3.4 Jumper Settings

C141-E057-01EN 3-13

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CHAPTER 4 Theory of Device Operation

4.1 Outline

4.2 Subassemblies

4.3 Circuit Configuration

4.4 Power-on Sequence

4.5 Self-calibration

4.6 Read/write Circuit

4.7 Servo Control

This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks.

C141-E057-01EN 4-1

Theory of Device Operation

4.1 Outline

This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk drive. Second part (Sections 4.3 through 4.7) explains a servo information recorded in the disk drive and drive control method.

4.2 Subassemblies

The disk drive consists of a disk enclosure (DE) and printed circuit assembly (PCA).

The DE contains all movable parts in the disk drive, including the disk, spindle, actuator, read/write head, and air filter. For details, see Subsections 4.2.1 to 4.2.5.

The PCA contains the control circuits for the disk drive. The disk drive has one PCA. For details, see Sections 4.3.

4.2.1 Disk

4.2.2 Head

The DE contains disks with an outer diameter of 65 mm and an inner diameter of 20 mm. The MHE2064AT have three disks and MHE2043AT have two disks and MHF2043AT have two disks and MHF2021AT have one disk.

The head contacts the disk each time the disk rotation stops; the life of the disk is 50,000 contacts or more. Servo data is recorded on top disk.

Servo data is recorded on each cylinder (total 60). Servo data written at factory is read out by the read/write head. For servo data, see Section 4.7.

Figure 4.1 shows the read/write head structures. MHE2064AT has 6 read/write heads and MHE2043AT has 4 read/write heads and MHF2043AT has 4 read/write heads and MHF2021AT has 2 read/write head. These heads are raised from the disk surface as the spindle motor the rated rotation speed.

4-2 C141-E057-02EN

Head

5 4

4.2 Subassemblies

HeadHead

MHE2064AT

4.2.3 Spindle

4.2.4 Actuator

MHE2043AT

Figure 4.1 Head structure

The spindle consists of a disk stack assembly and spindle motor. The disk stack assembly is activated by the direct drive sensor-less DC spindle motor, which has a speed of 4,200 rpm signal generated by counter electromotive voltage of the spindle motor at starting.

The actuator consists of a voice coil motor (VCM) and a head carriage. The VCM moves the head carriage along the inner or outer edge of the disk. The head carriage position is controlled by feeding back the difference of the target position that is detected and reproduced from the servo information read by the read/write head.

±1%. The spindle is controlled with detecting a PHASE

MHF2043AT

Head

MHF2021AT

4.2.5 Air filter

There are two types of air filters: a breather filter and a circulation filter.

The breather filter makes an air in and out of the DE to prevent unnecessary pressure around the spindle when the disk starts or stops rotating. When disk drives are transported under conditions where the air pressure changes a lot, filtered air is circulated in the DE.

The circulation filter cleans out dust and dirt from inside the DE. The disk drive cycles air continuously through the circulation filter through an enclosed loop air cycle system operated by a blower on the rotating disk.

C141-E057-02EN 4-3

Theory of Device Operation

4.3 Circuit Configuration

Figure 4.2 shows the disk drive circuit configuration.

(1) Read/write circuit

The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and read channel (RDC).

The PreAMP consists of the write current switch circuit, that flows the write current to the head coil, and the voltage amplifier circuit, that amplitudes the read output from the head.

The RDC is the read demodulation circuit using the extended partial response class 4 (EPR4), and contains the Viterbi detector, programmable filter, adaptable transversal filter, times base generator, and data separator circuits. The RDC also contains the 16/17 group coded recording (GCR) encoder and decoder and servo demodulation circuit.

(2) Servo circuit

The position and speed of the voice coil motor are controlled by 2 closed-loop servo using the servo information recorded on the data surface. The servo information is an analog signal converted to digital for processeing by a MPU and then reconverted to an analog signal for control of the voice coil motor.

The MPU precisely sets each head on the track according on the servo information on the media surface.

(3) Spindle motor driver circuit

The circuit measures the interval of a PHASE signal generated by counterelectromotive voltage of a motor at the MPU and controls the motor speed comparing target speed.

(4) Controller circuit

Major functions are listed below.

• Data buffer (512 KB) management

• ATA interface control and data transfer control

• Sector format control

• Defect management

• ECC control

• Error recovery and self-diagnosis

4-4 C141-E057-01EN

16 bit

4.3 Circuit Configuration

Figure 4.2 Circuit Configuration

C141-E057-01EN 4-5

Theory of Device Operation

4.4 Power-on Sequence

Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described below.

a) After the power is turned on, the disk drive executes the MPU bus test,

internal register read/write test, and work RAM read/write test. When the self-diagnosis terminates successfully, the disk drive starts the spindle motor.

b) The disk drive executes self-diagnosis (data buffer read/write test) after

enabling response to the ATA bus.

c) After confirming that the spindle motor has reached rated speed, the disk

drive releases the heads from the actuator magnet lock mechanism by applying current to the VCM. This unlocks the heads which are parked at the inner circumference of the disks.

d) The disk drive positions the heads onto the SA area and reads out the system

information.

e) The disk drive executes self-seek-calibration. This collects data for VCM

tarque and mechanical external forces applied to the actuator, and updates the calibrating value.

f) The drive becomes ready. The host can issue commands.

4-6 C141-E057-01EN

4.5 Self-calibration

Figure 4.3 Power-on operation sequence

4.5 Self-calibration

The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical external forces on the actuator, and VCM tarque. This enables precise seek and read/write operations.

4.5.1 Self-calibration contents

(1) Sensing and compensating for external forces

The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution. The torque vary with the disk drive and the cylinder where the head is positioned. To execute stable fast seek operations, external forces are occasionally sensed.

The firmware of the drive measures and stores the force (value of the actuator motor drive current) that balances the torque for stopping head stably. This includes the current offset in the power amplifier circuit and DAC system.

C141-E057-01EN 4-7

Theory of Device Operation

The forces are compensated by adding the measured value to the specified current value to the power amplifier. This makes the stable servo control.

To compensate torque varing by the cylinder, the disk is divided into 8 areas from the innermost to the outermost circumference and the compensating value is measured at the measuring cylinder on each area at factory calibration. The measured values are stored in the SA cylinder. In the self-calibration, the compensating value is updated using the value in the SA cylinder.

(2) Compensating open loop gain

Torque constant value of the VCM has a dispersion for each drive, and varies depending on the cylinder that the head is positioned. To realize the high speed seek operation, the value that compensates torque constant value change and loop gain change of the whole servo system due to temperature change is measured and stored.

For sensing, the firmware mixes the disturbance signal to the position signal at the state that the head is positioned to any cylinder. The firmware calculates the loop gain from the position signal and stores the compensation value against to the target gain as ratio.

For compensating, the direction current value to the power amplifier is multiplied by the compensation value. By this compensation, loop gain becomes constant value and the stable servo control is realized.

To compensate torque constant value change depending on cylinder, whole cylinders from most inner to most outer cylinder are divided into 8 partitions at calibration in the factory, and the compensation data is measured for representive cylinder of each partition. This measured value is stored in the SA area. The compensation value at self-calibration is calculated using the value in the SA area.

4.5.2 Execution timing of self-calibration

Self-calibration is executed when:

• The power is turned on.

• The disk drive receives the RECALIBRATE command from the host.

• The self-calibration execution timechart of the disk drive specifies self-

calibration.

The disk drive performs self-calibration according to the timechart based on the time elapsed from power-on. The timechart is shown in Table 4.1. After poweron, self-calibration is performed about every five or ten or fifteen minutes for the first 60 minutes or six RECALIBRATE command executions, and about every 30 minutes after that.

4-8 C141-E057-01EN

Table 4.1 Self-calibration execution timechart

Time elapsed

At power-on

Initial calibration

About 5 minutes

About 10 minutes

About 20 minutes

About 10 minutes

About 30 minutes

About 15 minutes

About 45 minutes

About 15 minutes

About 60 minutes

8..

Every about 30

minutes

(accumulated)

1 2 3 4 5 6 7

4.6 Read/write Circuit

4.5.3 Command processing during self-calibration

If the disk drive receives a command execution request from the host while executing self-calibration according to the timechart, the disk drive terminates self-calibration and starts executing the command precedingly. In other words, if a disk read or write service is necessary, the disk drive positions the head to the track requested by the host, reads or writes data, and restarts calibration.

This enables the host to execute the command without waiting for a long time, even when the disk drive is performing self-calibration. The command execution wait time is about maximum 100 ms.

4.6 Read/write Circuit

The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the read circuit, and the time base generator in the read channel (RDC). Figure 4.4 is a block diagram of the read/write circuit.

4.6.1 Read/write preamplifier (PreAMP)

One PreAMP is mounted on the FPC. The PreAMP consists of an read preamplifier and a write current switch and senses a write error. Each channel is connected to each data head. The head IC switches the heads by the chip select signals (*CS) and the head select signals. The IC generates a write error sense

C141-E057-01EN 4-9

Theory of Device Operation

Compensation

+16

+32

signal (WUS) when a write error occurs due to head short-circuit or head disconnection.

The Pre AMP sets the write current and bias current which flows through MR devices.

4.6.2 Write circuit

The write data is output from the hard disk controller (HDC) with the NRZ data format, and sent to the encoder circuit in the RDC. The NRZ write data is converted from 16-bit data to 17-bit data by the encoder circuit then sent to the PreAMP, and the data is written onto the media.

(1) 16/17 GCR

The disk drive converts data using the 16/17 (0, 12, 8) group coded recording (GCR) algorithm. This code follows a format in which 0 to 12 “0”s are inserted while the code bit is “1” and 0 to 8 “0”s are inserted while the 0DD/EVEN bit is “1”.

(2) Write precompensation

Write precompensation compensates, during a write process, for write nonleneartiry generated at reading. Table 4.2 shows the write precompensation algorithm.

Table 4.2 Write precompensation algorithm

Bits

111001 111010

111111 000000 000001

010000

–7 –6

–1

±0

4-10 C141-E057-01EN

100000

4.6 Read/write Circuit

Figure 4.4 Read/write circuit block diagram

C141-E057-01EN 4-11

Theory of Device Operation

-3 dB

4.6.3 Read circuit

The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the flash digitizer circuit. This clock signal is converted into the NRZ data by the 16/17 GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.

(1) AGC circuit

The AGC circuit automatically regulates the output amplitude to a constant value even when the input amplitude level fluctuates. The AGC amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer/inner head positions.

(2) Programmable filter

The programmable filter circuit has a low-pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost-up function that equalizes the waveform of the read signal.

Cut-off frequency of the low-pass filter and boost-up gain are controlled from the register in read channel by an instruction of the serial data signal from MPU (M5). The MPU optimizes the cut-off frequency and boost-up gain according to the transfer frequency of each zone.

Figure 4.5 shows the frequency characteristic sample of the programmalbe filter.

Figure 4.5 Frequency characteristic of programmable filter

4-12 C141-E057-01EN

(3) Flash digitizer circuit

This circuit is 10-tap sampled analog transversal filter circuit that cosine-equalizes the head read signal to the partial response class 4 (EPR4) waveform.

(4) Viterbi detection circuit

The sample hold waveform output from the flash digitizer circuit is sent to the Viterbi detection circuit. The Viterbi detection circuit demodulates data according to the survivor path sequence.

(5) 16/17 GCR decoder

This circuit converts the 17-bit read data into the 16-bit NRZ data.

4.6.4 Digital PLL circuit

The drive uses constant density recording to increase total capacity. This is different from the conventional method of recording data with a fixed data transfer rate at all data area. In the constant density recording method, data area is divided into zones by radius and the data transfer rate is set so that the recording density of the inner cylinder of each zone is nearly constant. The drive divides data area into 14 zones to set the data transfer rate.

4.6 Read/write Circuit

The MPU transfers the data transfer rate setup data (SD/SC) to the RDC that includes the Digital PLL circuit to change the data transfer rate.

C141-E057-01EN 4-13

Theory of Device Operation

Amp

4.7 Servo Control

The actuator motor and the spindle motor are submitted to servo control. The actuator motor is controlled for moving and positioning the head to the track containing the desired data. To turn the disk at a constant velocity, the actuator motor is controlled according to the servo data that is written on the data side beforehand.

4.7.1 Servo control circuit

Figure 4.6 is the block diagram of the servo control circuit. The following describes the functions of the blocks:

Figure 4.6 Block diagram of servo control circuit

(1) Microprocessor unit (MPU)

(3)

(4)

Power

(7)

(6)(5)

The MPU includes the DSP unit, and the MPU starts the spindle motor, moves the heads to the reference cylinders, seeks the specified cylinder, and executes calibration according to the internal operations of the MPU. Main internal operation of the MPU are shown below.

4-14 C141-E057-01EN

4.7 Servo Control

The major internal operations are listed below.

a. Spindle motor start

Starts the spindle motor and accelerates it to normal speed when power is applied.

b. Move head to reference cylinder

Drives the VCM to position the head at the any cylinder in the data area. The logical initial cylinder is at the outermost circumference (cylinder 0).

c. Seek to specified cylinder

Drives the VCM to position the head to the specified cylinder.

d. Calibration

Senses and stores the thermal offset between heads and the mechanical forces on the actuator, and stores the calibration value.

C141-E057-01EN 4-15

Theory of Device Operation

revolution)

direction

Erase: DC erase area

CYL-n (n: even number)

Servo frame (60 servo frames

Circumference

Figure 4.7 Physical sector servo configuration on disk surface

Diameter

4-16 C141-E057-01EN

(2) Servo burst capture circuit

The servo burst capture circuit reproduces signals (position signals) that indicate the head position from the servo data on the data surface. SERVO A, SERVO B, SERVO C and SERVO D burst signals shown in Figure 4.8 followed the servo mark, cylinder gray and index information are output from the servo area on the data surface via the data head. The servo signals A/D-converts the amplitudes of the POSA, POSB, POSC and POSD signals at the peak hold circuit in the servo burst capture circuit at the timing of the STROB signal. At that time the AGC circuit is in hold mode. The A/D converted data is recognized by the MPU as position information with A-B and C-D processed.

(3) D/A converter (DAC)

The D/A converter (DAC) converts the VCM drive current value (digital value) calculated by the DSP unit into analog values and transfers them to the power amplifier.

(4) Power amplifier

4.7 Servo Control

The power amplifier feeds currents, corresponding to the DAC output signal voltage to the VCM.

(5) Spindle motor control circuit

The spindle motor control circuit controls the sensor-less spindle motor. This circuit detects number of revolution of the motor by the interrupt generated periodically, compares with the target revolution speed, then flows the current into the motor coil according to the differentation (abberration).

(6) Driver circuit

The driver circuit is a power amplitude circuit that receives signals from the spindle motor control circuit and feeds currents to the spindle motor.

(7) VCM current sense resistor (CSR)

This resistor controls current at the power amplifier by converting the VCM current into voltage and feeding back.

C141-E057-01EN 4-17

Theory of Device Operation

4.7.2 Data-surface servo format

Figure 4.7 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.7 are described below.

(1) Inner guard band

The head is in contact with the disk in this space when the spindle starts turning or stops, and the rotational speed of the spindle can be controlled on this cylinder area for head moving.

(2) Data area

This area is used as the user data area SA area.

(3) Outer guard band

This area is located at outer position of the user data area, and the rotational speed of the spindle can be controlled on this cylinder area for head moving.

4.7.3 Servo frame format

As the servo information, the IDD uses the two-phase servo generated from the gray code and servo A to D. This servo information is used for positioning operation of radius direction and position detection of circumstance direction.

The servo frame consists of 6 blocks; write/read recovery, servo mark, gray code, servo A to D, and PAD. Figure 4.8 shows the servo frame format.

Figure 4.8 Servo frame format

4-18 C141-E057-01EN

(1) Write/read recovery

This area is used to absorb the write/read transient and to stabilize the AGC.

(2) Servo mark

This area gererates a timing for demodulating the gray code and positiondemodulating the servo A to D by detecting the servo mark.

(3) Gray code (including index bit)

This area is used as cylinder address. The data in this area is converted into the binary data by the gray code demodulation circuit

(4) Servo A, servo B, servo C, servo D

This area is used as position signals between tracks, and the IDD control at ontrack so that servo A level equals to servo B level.

(5) PAD

4.7 Servo Control

This area is used as a gap between servo and data.

4.7.4 Actuator motor control

The voice coil motor (VCM) is controlled by feeding back the servo data recorded on the data surface. The MPU fetches the position sense data on the servo frame at a constant interval of sampling time, executes calculation, and updates the VCM drive current.

The servo control of the actuator includes the operation to move the head to the reference cylinder, the seek operation to move the head to the target cylinder to read or write data, and the track-following operation to position the head onto the target track.

(1) Operation to move the head to the reference cylinder

The MPU moves the head to the reference cylinder when the power is turned. The reference cylinder is in the data area.

When power is applied the heads are moved from the inner circumference shunt zone to the normal servo data zone in the following sequence:

a) Micro current is fed to the VCM to press the head against the inne r

circumference.

b) Micro current is fed to the VCM to move the head toward the outer

circumference.

c) When the servo mark is detected the head is moved slowly toward the outer

circumference at a constant speed.

C141-E057-01EN 4-19

Theory of Device Operation

d) If the head is stopped at the reference cylinder from there. Track following

control starts.

(2) Seek operation

Upon a data read/write request from the host, the MPU confirms the necessity of access to the disk. If a read/write instruction is issued, the MPU seeks the desired track.

The MPU feeds the VCM current via the D/A converter and power amplifier to move the head. The MPU calculates the difference (speed error) between the specified target position and the current position for each sampling timing during head moving. The MPU then feeds the VCM drive current by setting the calculated result into the D/A converter. The calculation is digitally executed by the firmware. When the head arrives at the target cylinder, the track is followed.

(3) Track following operation

Except during head movement to the reference cylinder and seek operation under the spindle rotates in steady speed, the MPU does track following control. To position the head at the center of a track, the DSP drives the VCM by feeding micro current. For each sampling time, the VCM drive current is determined by filtering the position difference between the target position and the position clarified by the detected position sense data. The filtering includes servo compensation. These are digitally controlled by the firmware.

4.7.5 Spindle motor control

Hall-less three-phase twelve-pole motor is used for the spindle motor, and the 3phase full/half-wave analog current control circuit is used as the spindle motor driver (called SVC hereafter). The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by sending several signals from the MPU to the SVC. There are three modes for the spindle control; start mode, acceleration mode, and stable rotation mode.

(1) Start mode

When power is supplied, the spindle motor is started in the following sequence:

a) After the power is turned on, the MPU sends a signal to the SVC to charge

the charge pump capacitor of the SVC. The charged amount defines the current that flows in the spindle motor.

b) When the charge pump capacitor is charged enough, the MPU sets the SVC

to the motor start mode. Then, a current (approx. 0.7 A) flows into the spindle motor.

c) The SVC generates a phase switching signal by itself, and changes the phase

of the current flowed in the motor in the order of (V-phase to U-phase), (Wphase to U-phase), (W-phase to V-phase), (U-phase to V-phase), (U-phase to W-phase), and (V-phase to W-phase) (after that, repeating this order).

4-20 C141-E057-01EN

d) During phase switching, the spindle motor starts rotating in low speed, and

generates a counter electromotive force. The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection.

e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a

sepcific period, the MPU resets the SVC and starts from the beginning. When a PHASE signal is sent, the SVC enters the acceleration mode.

(2) Acceleration mode

In this mode, the MPU stops to send the phase switching signal to the SVC. The SVC starts a phase switching by itself based on the counter electromotive force. Then, rotation of the spindle motor accelerates. The MPU calcurates a rotational speed of the spindle motor based on the PHASE signal from the SVC, and accelerates till the rotational speed reaches 4,200 rpm. When the rotational speed reaches 4,200 rpm, the SVC enters the stable rotation mode.

(3) Stable rotation mode

The MPU calcurates a time for one revolution of the spindle motor based on the PHASE signal from the SVC. The MPU takes a difference between the current time and a time for one revolution at 4,200 rpm that the MPU already recognized. Then, the MPU keeps the rotational speed to 4,200 rpm by charging or discharging the charge pump for the different time. For example, when the actual rotational speed is 4,000 rpm, the time for one revolution is 15.000 ms. And, the time for one revolution at 4,200 rpm is 14.286 ms. Therefore, the MPU charges the charge pump for 0.714 ms current into the motor higher and the rotational speed up. When the actual rotational speed is faster than 4,200 rpm, the MPU discharges the pump the other way. This control (charging/discharging) is performed every 1 revolution.

4.7 Servo Control

× k (k: constant value). This makes the flowed

C141-E057-01EN 4-21

This page is intentionally left blank.

CHAPTER 5 Interface

5.1 Physical Interface

5.2 Logical Interface

5.3 Host Commands

5.4 Command Protocol

5.5 Ultra DMA Feature Set

5.6 Timing

This chapter gives details about the interface, and the interface commands and timings.

C141-E057-01EN 5-1

Interface

DASP-: DEVICE ACTIVE/SLAVE PRESENT

5.1 Physical Interface

5.1.1 Interface signals

Figure 5.1 shows the interface signals.

DIOW-: I/O WRITE STOP: STOP DURING ULTRA DMA DATA BURSTS

DIOR-: I/O READ HDMARDY: DMA READY DURING ULTRA DMA DATA IN BURSTS HSTROBE: DATA STROBE DURING ULTRA DMA DATA OUT BURSTS

INTRQ: INTERRUPT REQUEST

IOCS16-: 16-BIT I/O

PDIAG: PASSED DIAGNOSTICS

IORDY: I/O READY DDMARDY: DMA READY DURING ULTRA DMA DATA OUT BURSTS DSTROBE: DATA STROBE DURING ULTRA DMA DATA IN BURSTS

5-2 C141-E057-01EN

Figure 5.1 Interface signals

5.1.2 Signal assignment on the connector

Pin No.

Signal

Pin No.

Signal

(KEY)

DMARQ

DIOW-, STOP

DIOR-, HDMRDY,

IORDY, DDMARDY,

INTRQ

+5 VDC

(KEY)

GND

CSEL

+5 VDC

unused

Table 5.1 shows the signal assignment on the interface connector.

Table 5.1 Signal assignment on the interface connector

5.1 Physical Interface

A C

E 1 3 5 7

9 11 13 15 17 19 21 23

ENCSEL ENCSEL

RESET– DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND

B D

F 2 4 6

8 10 12 14 16 18 20 22 24

GND MSTR

GND DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15

GND GND

HSTROBE

DSTROBE 29 31 33 35 37 39 41 43

C141-E057-01EN 5-3

DMACK–

DA1

DA0

CS0–

DASP–

GND

30 32 34 36 38 40 42 44

GND IOCS16– PDIAG DA2 CS1– GND

Interface

[signal]

[I/O]

[Description]

ENCSEL

This signal is used to set master/slave using the CSEL signal (pin 28).

Pins A and C Open: Sets master/slave by the MSTR signal

without using the CSEL signal.

Short: Sets master/slave using the CSEL signal.

The MSTR signal is ignored.

MSTR

MSTR, I, Master/slave setting

1: Master 0: Slave

RESET-

Reset signal from the host. This signal is low active and is

asserted for a minimum of 25 µs during power on.

DATA 0-15

I/O

Sixteen-bit bi-directional data bus between the host and the

device. These signals are used for data transfer

DIOW-

Signal asserted by the host to write to the device register or data

port.

STOP

DIOW- must be negated by the host before starting the Ultra

DMA transfer. The STOP signal must be negated by the host

before data is transferred during the Ultra DMA transfer. During

data transfer in Ultra DMA mode, the assertion of the STOP

signal asserted by the host later indicates that the transfer has been

suspended.

DIOR-

Read strobe signal from the host to read the device register or data

port

HDMARDY-

Flow control signal for Ultra DMA data In transfer (READ DMA

command). This signal is asserted by the host to inform the

device that the host is ready to receive the Ultra DMA data In

transfer. The host can negate the HDMARDY- signal to suspend

the Ultra DMA data In transfer.

HSTROBE

Data Out Strobe signal from the host during Ultra DMA data Out

transfer (WRITE DMA command). Both the rising and falling

edges of the HSTROBE signal latch data from Data 15-0 into the

device. The host can suspend the inversion of the HSTROBE

signal to suspend the Ultra DMA data Out transfer.

INTRQ

Interrupt signal to the host.

This signal is negated in the following cases:

assertion of RESET- signal

Reset by SRST of the Device Control register

Write to the command register by the host

Read of the status register by the host

Completion of sector data transfer

(without reading the Status register)

The signal output line has a high impedance when no devices are

selected or interruption is disabled.

−

5-4 C141-E057-01EN

[signal]

[I/O]

[Description]

IOCS16-

This signal indicates 16-bit data bus is addressed in PIO data transfer.

This signal is an open collector output.

−

When IOCS16- is not asserted:

8 bit data is transferred through DATA0 to DATA7 signals.

When IOCS16- is asserted:

16 bit data is transferred through DATA0 to DATA15 signals.

CS0-

Chip select signal decoded from the host address bus. This signal

is used by the host to select the command block registers.

CS1-

Chip select signal decoded from the host address bus. This signal

is used by the host to select the control block registers.

DA 0-2

Binary decoded address signals asserted by the host to access task

file registers.

KEY

Key pin for prevention of erroneous connector insertion

PDIAG-

I/O

This signal is an input mode for the master device and an output

mode for the slave device in a daisy chain configuration. This

signal indicates that the slave device has been completed self

diagnostics.

This signal is pulled up to +5 V through 10 kΩ resistor at each device.

DASP-

I/O

This is a time-multiplexed signal that indicates that the device is

active and a slave device is present.

This signal is pulled up to +5 V through 10 kΩ resistor at each device.

IORDY

This signal requests the host system to delay the transfer cycle

when the device is not ready to respond to a data transfer request

from the host system.

DDMARDY

Flow control signal for Ultra DMA data Out transfer (WRITE

DMA command). This signal is asserted by the device to inform

the host that the device is ready to receive the Ultra DMA data

Out transfer. The device can negate the DDMARDY- signal to

suspend the Ultra DMA data Out transfer.

DSTROBE

Data In Strobe signal from the device during Ultra DMA data In

transfer. Both the rising and falling edges of the DSTROBE

signal latch data from Data 15-0 into the host. The device can

suspend the inversion of the DSTROBE signal to suspend the

Ultra DMA data In transfer.

CSEL

This signal to configure the device as a master or a slave device.

When CSEL signal is grounded,, the IDD is a master device.

When CSEL signal is open,, the IDD is a slave device.

This signal is pulled up with 240 kΩ resistor at each device.

DMACK-

The host system asserts this signal as a response that the host

system receive data or to indicate that data is valid.

−

5.1 Physical Interface

−

C141-E057-01EN 5-5

Interface

[signal]

[I/O]

[Description]

DMARQ

This signal is used for DMA transfer between the host system and

the device. The device asserts this signal when the device

completes the preparation of DMA data transfer to the host system

(at reading) or from the host system (at writing).

The direction of data transfer is controlled by the DIOR and

DIOW signals. This signal hand shakes with the DMACK-signal.

In other words, the device negates the DMARQ signal after the

host system asserts the DMACK signal. When there is other data

to be transferred, the device asserts the DMARQ signal again.

When the DMA data transfer is performed, IOCS16-, CS0- and

CS1- signals are not asserted. The DMA data transfer is a 16-bit

data transfer.

+5 VDC

+5 VDC power supplying to the device.

GND

Grounded signal at each signal wire.

Note:

“I” indicates input signal from the host to the device.

“O” indicates output signal from the device to the host.

“I/O” indicates common output or bi-directional signal between the host and the device.

5.2 Logical Interface

The device can operate for command execution in either address-specified mode; cylinder-head-sector (CHS) or Logical block address (LBA) mode. The IDENTIFY DEVICE information indicates whether the device supports the LBA mode. When the host system specifies the LBA mode by setting bit 6 in the Device/Head register to 1, HS3 to HS0 bits of the Device/Head register indicates the head No. under the LBA mode, and all bits of the Cylinder High, Cylinder Low, and Sector Number registers are LBA bits.

The sector No. under the LBA mode proceeds in the ascending order with the start point of LBA0 (defined as follows).

LBA0 = [Cylinder 0, Head 0, Sector 1]

Even if the host system changes the assignment of the CHS mode by the INITIALIZE DEVICE PARAMETER command, the sector LBA address is not changed.

LBA = [((Cylinder No.) sector/track)] + (Sector No.)

5-6 C141-E057-01EN

× (Number of head) + (Head No.)) × (Number of

− 1

5.2.1 I/O registers

I/O registers

Read operation

Write operation

Command block registers

LHLLL

Data

X’1F0’

LHLLH

Error Register

Features

X’1F1’

LHLHL

Sector Count

X’1F2’

LHLHH

Sector Number

X’1F3’

LHHLL

Cylinder Low

X’1F4’

LHHLH

Cylinder High

X’1F5’

LHHHL

Device/Head

X’1F6’

LHHHH

Status

Command

X’1F7’

LLXXX

(Invalid)

Control block registers

HLHHL

Alternate Status

Device Control

X’3F6’

HLHHH

X’3F7’

address

–

Communication between the host system and the device is done through inputoutput (I/O) registers of the device.

These I/O registers can be selected by the coded signals, CS0-, CS1-, and DA0 to DA2 from the host system. Table 5.2. shows the coding address and the function of I/O registers.

5.2 Logical Interface

Table 5.2 I/O registers

CS0

DA0DA1DA2CS1

— —

Host I/O

—

C141-E057-01EN 5-7

Notes:

1. The Data register for read or write operation can be accessed by 16 bit data bus (DATA0 to DATA15).

2. The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus (DATA0 to DATA7).

3. When reading the Drive Address register, bit 7 is high-impedance state.

4. H indicates signal level High and L indicates signal level Low.

And the LBA mode is specified, the Device/Head, Cylinder High, Cylinder Low, and Sector Number registers indicate LBA bits 27 to 24, 23 to 16, 15 to 8, and 7 to 0.

Interface

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

- Bit 7:

Interface CRC Error (ICRC). This bit indicates that a CRC error

occurred during Ultra DMA transfer.

- Bit 6:

Uncorrectable Data Error (UNC). This bit indicates that an

uncorrectable data error has been encountered.

- Bit 5:

Unused

- Bit 4:

ID Not Found (IDNF). This bit indicates an error except for bad

sector, uncorrectable error and SB not found.

- Bit 3:

Unused

- Bit 2:

Aborted Command (ABRT). This bit indicates that the requested

command was aborted due to a device status error (e.g. Not Ready,

Write Fault) or the command code was invalid.

- Bit 1:

Track 0 Not Found (TK0NF). This bit indicates that track 0 was not

found during RECALIBRATE command execution.

- Bit 0:

Address Mark Not Found (AMNF). This bit indicates that the SB Not

Found error occurred.

5.2.2 Command block registers

(1) Data register (X’1F0’)

The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or DMA mode.

(2) Error register (X’1F1’)

The Error register indicates the status of the command executed by the device. The contents of this register are valid when the ERR bit of the Status register is 1.

This register contains a diagnostic code after power is turned on, a reset , or the EXECUTIVE DEVICE DIAGNOSTIC command is executed.

[Status at the completion of command execution other than diagnostic command]

ICRC UNC X IDNF X ABRT TK0NF AMNF

X: Unused

5-8 C141-E057-01EN

[Diagnostic code]

X’01’:

No Error Detected.

X’02’:

HDC Register Compare Error

X’03’:

Data Buffer Compare Error.

X’05’:

ROM Sum Check Error.

X’80’:

Device 1 (slave device) Failed.

Error register of the master device is valid under two devices (master

and slave) configuration. If the slave device fails, the master device

posts X’80’ OR (the diagnostic code) with its own status (X’01’ to

X’05’).

However, when the host system selects the slave device, the diagnostic

code of the slave device is posted.

(3) Features register (X’1F1’)

5.2 Logical Interface

The Features register provides specific feature to a command. For instance, it is used with SET FEATURES command to enable or disable caching.

(4) Sector Count register (X’1F2’)

The Sector Count register indicates the number of sectors of data to be transferred in a read or write operation between the host system and the device. When the value in this register is X’00’, the sector count is 256.

When this register indicates X’00’ at the completion of the command execution, this indicates that the command is completed succefully. If the command is not completed scuccessfully, this register indicates the number of sectors to be transferred to complete the request from the host system. That is, this register indicates the number of remaining sectors that the data has not been transferred due to the error.

The contents of this register has other definition for the following commands; INITIALIZE DEVICE PARAMETERS, SET FEATURES, IDLE, STANDBY and SET MULTIPLE MODE.

(5) Sector Number register (X’1F3’)

The contents of this register indicates the starting sector number for the subsequent command. The sector number should be between X’01’ and [the number of sectors per track defined by INITIALIZE DEVICE PARAMETERS command.

Under the LBA mode, this register indicates LBA bits 7 to 0.

C141-E057-01EN 5-9

Interface

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

- Bit 7:

Unused

- Bit 6:

L. 0 for CHS mode and 1 for LBA mode.

- Bit 5:

Unused

- Bit 4:

DEV bit. 0 for the master device and 1 for the slave device.

- Bit 3:

HS3 CHS mode head address 3 (23). LBA bit 27.

- Bit 2:

HS2 CHS mode head address 2 (22). LBA bit 26.

- Bit 1:

HS1 CHS mode head address 1 (21). LBA bit 25.

- Bit 0:

HS0 CHS mode head address 0 (20). LBA bit 24.

(6) Cylinder Low register (X’1F4’)

The contents of this register indicates low-order 8 bits of the starting cylinder address for any disk-access.

At the end of a command, the contents of this register are updated to the current cylinder number.

Under the LBA mode, this register indcates LBA bits 15 to 8.

(7) Cylinder High register (X’1F5’)

The contents of this register indicates high-order 8 bits of the disk-access start cylinder address.

At the end of a command, the contents of this register are updated to the current cylinder number. The high-order 8 bits of the cylinder address are set to the Cylinder High register.

Under the LBA mode, this register indicates LBA bits 23 to 16.

(8) Device/Head register (X’1F6’)

The contents of this register indicate the device and the head number.

When executing INITIALIZE DEVICE PARAMETERS command, the contents of this register defines “the number of heads minus 1” (a maximum head No.).

X L X DEV HS3 HS2 HS1 HS0

5-10 C141-E057-01EN

(9) Status register (X’1F7’)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DRQ

- Bit 7:

Busy (BSY) bit. This bit is set whenever the Command register is

accessed. Then this bit is cleared when the command is completed.

However, even if a command is being executed, this bit is 0 while data

transfer is being requested (DRQ bit = 1).When BSY bit is 1, the host

system should not write the command block registers. If the host

system reads any command block register when BSY bit is 1, the

contents of the Status register are posted. This bit is set by the device

under following conditions:

(a) Within 400 ns after RESET- is negated or SRST is set in the

Device Control register, the BSY bit is set. the BSY bit is cleared,

when the reset process is completed.

The BSY bit is set for no longer than 15 seconds after the IDD

accepts reset.

(b) Within 400 ns from the host system starts writing to the

Command register.

of the READ SECTOR(S), WRITE SECTOR(S), or WRITE

BUFFER command.

Within 5 µs following transfer of 512 bytes of data and the

appropriate number of ECC bytes during execution of READ

LONG or WRITE LONG command.

- Bit 6:

Device Ready (DRDY) bit. This bit indicates that the device is

capable to respond to a command.

The IDD checks its status when it receives a command. If an error is

detected (not ready state), the IDD clears this bit to 0. This is cleared

to 0 at power-on and it is cleared until the rotational speed of the

spindle motor reaches the steady speed.

The contents of this register indicate the status of the device. The contents of this register are updated at the completion of each command. When the BSY bit is cleared, other bits in this register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are invalid. When the host system reads this register while an interrupt is pending, it is considered to be the Interrupt Acknowledge (the host system acknowledges the interrupt). Any pending interrupt is cleared (negating INTRQ signal) whenever this register is read.

5.2 Logical Interface

BSY DRDY DF DSC

0 0 ERR

C141-E057-01EN 5-11

Interface

- Bit 5:

The Device Write Fault (DF) bit. This bit indicates that a device fault

(write fault) condition has been detected.

If a write fault is detected during command execution, this bit is

latched and retained until the device accepts the next command or

reset.

- Bit 4:

Device Seek Complete (DSC) bit. This bit indicates that the device

heads are positioned over a track.

In the IDD, this bit is always set to 1 after the spin-up control is

completed.

- Bit 3:

Data Request (DRQ) bit. This bit indicates that the device is ready to

transfer data of word unit or byte unit between the host system and the

device.

- Bit 2:

Always 0.

- Bit 1:

Always 0.

- Bit 0:

Error (ERR) bit. This bit indicates that an error was detected while the

previous command was being executed. The Error register indicates

the additional information of the cause for the error.

(10) Command register (X’1F7’)

The Command register contains a command code being sent to the device. After this register is written, the command execution starts immediately.

Table 5.3 lists the executable commands and their command codes. This table also lists the neccesary parameters for each command which are written to certain registers before the Command register is written.

5-12 C141-E057-01EN

5.2.3 Control block registers

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DRQ

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

nIEN

- Bit 2:

SRST is the host software reset bit. When this bit is set, the device is

held reset state. When two device are daisy chained on the interface,

setting this bit resets both device simultaneously.

The slave device is not required to execute the DASP- handshake.

- Bit 1:

nIEN bit enables an interrupt (INTRQ signal) from the device to the

host. When this bit is 0 and the device is selected, an interruption

(INTRQ signal) can be enabled through a tri-state buffer. When this

bit is 1 or the device is not selected, the INTRQ signal is in the high-

impedance state.

(1) Alternate Status register (X’3F6’)

The Alternate Status register contains the same information as the Status register of the command block register.

The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset.

5.3 Host Commands

BSY DRDY DF DSC

(2) Device Control register (X’3F6’)

The Device Control register contains device interrupt and software reset.

X X X X X SRST

0 0 ERR

5.3 Host Commands

The host system issues a command to the device by writing necessary parameters in related registers in the command block and writing a command code in the Command register.

The device can accept the command when the BSY bit is 0 (the device is not in the busy status).

The host system can halt the uncompleted command execution only at execution of hardware or software reset.

C141-E057-01EN 5-13

Interface

Command code (Bit)

Parameters used

READ SECTOR(S)

READ MULTIPLE

READ DMA

READ VERIFY SECTOR(S)

WRITE MULTIPLE

WRITE DMA

WRITE VERIFY

WRITE SECTOR(S)

INITIALIZE DEVICE PARAMETERS

IDENTIFY DEVICE

IDENTIFY DEVICE DMA

SET FEATURES

SET MULTIPLE MODE

SET MAX ADDRESS

READ NATIVE MAX ADDRESS

EXECUTE DEVICE DIAGNOSTIC

READ LONG

WRITE LONG

READ BUFFER

WRITE BUFFER

110101100010111

Command name

When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the data transfer) and the host system writes to the command register, the correct device operation is not guaranteed.

5.3.1 Command code and parameters

Table 5.3 lists the supported commands, command code and the registers that needed parameters are written.

Table 5.3 Command code and parameters (1 of 2)

7 6 5 4 3 2 1 0 FR SC SN CY DH 0 0 1 0 0 0 0 R N Y Y Y Y

1 1 0 0 0 1 0 0 N Y Y Y Y 1 1 0 0 1 0 0 R N Y Y Y Y 0 1 0 0 0 0 0 R N Y Y Y Y 1 1 0 0 0 1 0 1 N Y Y Y Y 1 1 0 0 1 0 1 R N Y Y Y Y 0 0 1 1 1 1 0 0 N Y Y Y Y

0 0 1 1 0 0 0 R N Y Y Y Y RECALIBRATE 0 0 0 1 X X X X N N N N D SEEK 0 1 1 1 X X X X N N Y Y Y

1 0 0 1 0 0 0 1 N Y N N Y

1 1 1 0 1 1 0 0 N N N N D

1 1 1 0 1 1 1 1 Y N* N N D

1 1 0 0 0 1 1 0 N Y N N D

1 1 1 1 1 0 0 1 N Y Y Y Y

1 1 1 1 1 0 0 0 N N N N D

1 0 0 1 0 0 0 0 N N N N D*

IDLE

5-14 C141-E057-01EN

0 0 1 0 0 0 1 R N Y Y Y Y

0 0 1 1 0 0 1 R N Y Y Y Y

1 1 1 0 0 1 0 0 N N N N D

1 1 1 0 1 0 0 0 N N N N D

N Y N N D

Table 5.3 Command code and parameters (2 of 2)

Command code (Bit)

Parameters used

IDLE IMMEDIATE

110101100010001

110101100010110

STANDBY IMMEDIATE

110101100010000

110101101001011

CHECK POWER MODE

110101101001000

SECURITY DISABLE PASSWORD

SECURITY ERASE PREPARE

SECURITY ERASE UNIT

SECURITY FREEZE LOCK

SECURITY SET PASSWORD

SECURITY UNLOCK

FLUSH CACHE

Command name

7 6 5 4 3 2 1 0 FR SC SN CY DH

5.3 Host Commands

N N N N D

STANDBY

N Y N N D

N N N N D

SLEEP

N N N N D

SMART 1 0 1 1 0 0 0 0 Y Y Y Y D

1 1 1 1 0 1 1 0 N N N N D 1 1 1 1 0 0 1 1 N N N N D 1 1 1 1 0 1 0 0 N N N N D 1 1 1 1 0 1 0 1 N N N N D 1 1 1 1 0 0 0 1 N N N N D 1 1 1 1 0 0 1 0 N N N N D 1 1 1 0 0 1 1 1 N N N N D

Notes:

FR: Features Register

CY: Cylinder Registers

SC: Sector Count Register

DH: Drive/Head Register

SN: Sector Number Register

R: Retry at error

1 = Without retry

0 = With retry

Y: Necessary to set parameters

C141-E057-01EN 5-15

Interface

At command issuance (I/O registers setting contents)

(CM)

(DH)

Head No. / LBA [MSB]

(CH)

Start cylinder address [MSB] / LBA

(CL)

Start cylinder address [LSB] / LBA

(SN)

Start sector No. / LBA [LSB]

(SC)

Transfer sector count

(FR)

At command completion (I/O registers contents to be read)

(ST)

Status information

(DH)

Head No. / LBA [MSB]

(CH)

End cylinder address [MSB] / LBA

(CL)

End cylinder address [LSB] / LBA

(SN)

End sector No. / LBA [LSB]

(SC)

(ER)

Error information

Y*: Necessary to set parameters under the LBA mode.

N: Not necessary to set parameters (The parameter is ignored if it is set.)

N*: May set parameters

D: The device parameter is valid, and the head parameter is ignored.

D*: The command is addressed to the master device, but both the master device

and the slave device execute it.

X: Do not care

5.3.2 Command descriptions

The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O registers at command conpletion are shown as following in this subsection.

Example: READ SECTOR(S) WITH RETRY

Bit 7 6 5 4 3 2 1 0

1F7

1F6 1F5

1F4 1F3 1F2 1F1

0 0 1 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

1F7

1F6 1F5

1F4 1F3 1F2 1F1

X’00’

5-16 C141-E057-01EN

5.3 Host Commands

CM: Command register FR: Features register

DH: Device/Head register ST: Status register

CH: Cylinder High register ER: Error register

CL: Cylinder Low register L: LBA (logical block address) setting bit

SN: Sector Number register DV: Device address. bit

SC: Sector Count register x, xx: Do not care (no necessary to set)

Note:

1. When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the CH, CL and SN registers indicate the LBA bits (bits of the DH register are the MSB (most significant bit) and bits of the SN register are the LSB (least significant bit).

2. At error occurrance, the SC register indicates the remaining sector count of data transfer.

3. In the table indicating I/O registers contents in this subsection, bit indication is omitted.

(1) READ SECTOR(S) (X’20’ or X’21’)

This command reads data of sectors specified in the Sector Count register from the address specified in the Device/Head, Cylinder High, Cylinder Low and Sector Number registers. Number of sectors can be specified to 256 sectors in maximum. To specify 256 sectors reading, ‘00’ is specified. For the DRQ, INTRQ, and BSY protocols related to data transfer, see Subsection 5.4.1.

If the head is not on the track specified by the host, the device performs a implied seek. After the head reaches to the specified track, the device reads the target sector.

If an error occurs, retry reads are attempted to read the target sector before reporting an error, irrespective of the R bit setting.

The DRQ bit of the Status register is always set prior to the data transfer regardless of an error condition.

Upon the completion of the command execution, command block registers contain the cylinder, head, and sector addresses (in the CHS mode) or logical block address (in the LBA mode) of the last sector read.

If an unrecoverable error occurs in a sector, the read operation is terminated at the sector where the error occured.

C141-E057-01EN 5-17

Interface

At command issuance (I/O registers setting contents)

(CM)

(DH)

Start head No. /LBA [MSB]

(CH)

(CL)

(SN)

(SC)

(FR)

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count

At command completion (I/O registers contents to be read)

(ST)

Status information

(DH)

End head No. /LBA [MSB]

(CH)

(CL)

(SN)

(SC)

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

00 (*1)

Error information

Command block registers contain the cylinder, the head, and the sector addresses of the sector (in the CHS mode) or the logical block address (in the LBA mode) where the error occurred, and remaining number of sectors of which data was not transferred.

1F7

1F6

1F5

1F4

1F3

1F2

1F1

R = 0 →with Retry R = 1

→without Retry

1F7

1F6

1F5

1F4

1F3

1F2

1F1

0 0 1 0 0 0 0 R

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

(2) READ MULTIPLE (X’C4’)

This command operates similarly to the READ SECTOR(S) command. The device does not generate an interrupt (assertion of the INTRQ signal) on each every sector. An interrupt is generateed after the transfer of a block of sectors for which the number is specified by the SET MULTIPLE MODE command.

5-18 C141-E057-01EN

5.3 Host Commands

The implementation of the READ MULTIPLE command is identical to that of the READ SECTOR(S) command except that the number of sectors is specified by the SET MULTIPLE MODE command are transferred without intervening interrupts. In the READ MULTIPLE command operation, the DRQ bit of the Status register is set only at the start of the data block, and is not set on each sector.

The number of sectors (block count) to be transferred without interruption is specifed by the SET MULTIPLE MODE command. The SET MULTIPLE MODE command should be executed prior to the READ MULTIPLE command.

When the READ MULTIPLE command is issued, the Sector Count register contains the number of sectors requested (not a number of the block count or a number of sectors in a block).

Upon receipt of this command, the device executes this command even if the value of the Sector Count register is less than the defined block count (the value of the Sector Count should not be 0).

If the number of requested sectors is not divided evenly (having the same number of sectors [block count]), as many full blocks as possible are transferred, then a final partial block is transferred. The number of sectors in the partial block to be transferred is n where n = remainder of (“number of sectors”/”block count”).

If the READ MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when the READ MULTIPLE command is disabled, the device rejects the READ MULTIPLE command with an ABORTED COMMAND error.

If an unrecoverable error occurs, reading sector is stopped at the sector where the error occurred. Command block registers contain the cylinder, the head, the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector where the error occurred, and remaining number of sectors that had not transferred after the sector where the error occurred.

An interrupt is generated when the DRQ bit is set at the beginning of each block or a partial block.

Figure 5.2 shows an example of the execution of the READ MULTIPLE command.

• Block count specified by SET MULTIPLE MODE command = 4 (number of

sectors in a block)

• READ MULTIPLE command specifies;

Number of requested sectors = 9 (Sector Count register = 9)

↓

Number of sectors in incomplete block = remainder of 9/4 =1

C141-E057-01EN 5-19

Interface

At command issuance (I/O registers setting contents)

(CM)

(DH)

Start head No. /LBA [MSB]

(CH)

(CL)

(SN)

(SC)

(FR)

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count

At command completion (I/O registers contents to be read)

(ST)

Status information

(DH)

End head No. /LBA [MSB]

(CH)

(CL)

(SN)

(SC)

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

Error information

Figure 5.2 Execution example of READ MULTIPLE command

1F7

1F6 1F5

1F4 1F3 1F2 1F1

1F7 1F6 1F5

1F4

1F3

1F2

1F1

1 1 0 0 0 1 0 0

(*1)

*1 If the command is terminated due to an error, the remaining number of

sectors for which data was not transferred is set in this register.

5-20 C141-E057-01EN

(3) READ DMA (X’C8’ or X’C9’)

At command issuance (I/O registers setting contents)

(CM)

(DH)

Start head No. /LBA [MSB]

(CH)

(CL)

(SN)

(SC)

(FR)

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count

This command operates similarly to the READ SECTOR(S) command except for following events.

• The data transfer starts at the timing of DMARQ signal assertion.

• The device controls the assertion or negation timing of the DMARQ signal.

• The device posts a status as the result of command execution only once at

completion of the data transfer.

When an error, such as an unrecoverable medium error, that the command execution cannot be continued is detected, the data transfer is stopped without transferring data of sectors after the erred sector. The device generates an interrupt using the INTRQ signal and posts a status to the host system. The format of the error information is the same as the READ SECTOR(S) command.

In LBA mode

The logical block address is specified using the start head No., start cylinder No., and first sector No. fields. At command completion, the logical block address of the last sector and remaining number of sectors of which data was not transferred, like in the CHS mode, are set.

5.3 Host Commands

The host system can select the DMA transfer mode by using the SET FEATURES command.

1) Single word DMA transfer mode 0 to 2

2) Multiword DMA transfer mode 0 to 2

3) Ultra DMA transfer mode 0 to 2

1F7

1F6 1F5

1F4 1F3 1F2 1F1

1 1 0 0 1 0 0 R

C141-E057-01EN 5-21

R = 0 → with Retry R = 1

→ without Retry

Interface

At command completion (I/O registers contents to be read)

(ST)

Status information

(DH)

End head No. /LBA [MSB]

(CH)

(CL)

(SN)

(SC)

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

00 (*1)

Error information

1F7

1F6 1F5

1F4

1F3

1F2

1F1

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

(4) READ VERIFY SECTOR(S) (X’40’ or X’41’)

This command operates similarly to the READ SECTOR(S) command except that the data is not transferred to the host system.

After all requested sectors are verified, the device clears the BSY bit of the Status register and generates an interrupt. Upon the completion of the command execution, the command block registers contain the cylinder, head, and sector number of the last sector verified.

If an unrecoverable error occurs, the verify operation is terminated at the sector where the error occurred. The command block registers contain the cylinder, the head, and the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector where the error occurred. The Sector Count register indicates the number of sectors that have not been verified.

If a correctable error is found, the device sets the CORR bit of the Status register to 1 after the command is completed (before the device generates an interrupt).

5-22 C141-E057-01EN

5.3 Host Commands

At command issuance (I/O registers setting contents)

(CM)

(DH)

Start head No. /LBA [MSB]

(CH)

(CL)

(SN)

(SC)

(FR)

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count

At command completion (I/O registers contents to be read)

(ST)

Status information

(DH)

End head No. /LBA [MSB]

(CH)

(CL)

(SN)

(SC)

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

00 (*1)

Error information

1F7

1F6

1F5

1F4

1F3

1F2

1F1

R = 0 →with Retry R = 1

→without Retry

1F7

1F6

1F5

1F4

1F3

1F2

1F1

0 1 0 0 0 0 0 R

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

(5) WRITE SECTOR(S) (X’30’ or X’31’)

This command writes data of sectors from the address specified in the Device/Head, Cylinder High, Cylinder Low, and Sector Number registers to the address specified in the Sector Count register. Number of sectors can be specified to 256 sectors in maximum. Data transfer begins at the sector specified in the Sector Number register. For the DRQ, INTRQ, and BSY protocols related to data transfer, see Subsection 5.4.2.

If the head is not on the track specified by the host, the device performs a implied seek. After the head reaches to the the specified track, the device writes the target sector.

If an error occurs when writing to the target sector, retries are attempted before reporting the error, irrespective of the R bit setting.

C141-E057-01EN 5-23

Interface

(CM)

(DH)

Start head No. /LBA [MSB]

(CH)

(CL)

(SN)

(SC)

(FR)

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count

(ST)

Status information

(DH)

End head No. /LBA [MSB]

(CH)

(CL)

(SN)

(SC)

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

00 (*1)

Error information

The data stored in the buffer, and CRC code and ECC bytes are written to the data field of the corresponding sector(s). Upon the completion of the command execution, the command block registers contain the cylinder, head, and sector addresses of the last sector written.

If an error occurs during multiple sector write operation, the write operation is terminated at the sector where the error occured. Command block registers contain the cylinder, the head, the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector where the error occurred. Then the host can read the command block registers to determine what error has occurred and on which sector the error has occurred.

At command issuance (I/O registers setting contents)

1F7

1F6

1F5

1F4

1F3

1F2

1F1

R = 0 →with Retry R = 1

→without Retry

At command completion (I/O registers contents to be read)

1F7

1F6

1F5

1F4

1F3

1F2

1F1

0 0 1 1 0 0 0 R

5-24 C141-E057-01EN

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

(6) WRITE MULTIPLE (X’C5’)

This command is similar to the WRITE SECTOR(S) command. The device does not generate interrupts (assertion of the INTRQ) signal) on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE MODE command.

The implementation of the WRITE MULTIPLE command is identical to that of the WRITE SECTOR(S) command except that the number of sectors is specified by the SET MULTIPLE MODE command are transferred without intervening interrupts. In the WRITE MULTIPLE command operation, the DRQ bit of the Status register is required to set only at the start of the data block, not on each sector.

When the WRITE MULTIPLE command is issued, the Sector Count register contains the number of sectors requested (not a number of the block count or a number of sectors in a block).

5.3 Host Commands

Upon receipt of this command, the device executes this command even if the value of the Sector Count register is less than the defined block count the value of the Sector Count should not be 0).

If the WRITE MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when WRITE MULTIPLE command is disabled, the device rejects the WRITE MULTIPLE command with an ABORTED COMMAND error.

Disk errors encountered during execution of the WRITE MULTIPLE command are posted after attempting to write the block or the partial block that was transferred. Write operation ends at the sector where the error was encountered even if the sector is in the middle of a block. If an error occurs, the subsequent block shall not be transferred. Interrupts are generated when the DRQ bit of the Status register is set at the beginning of each block or partial block.

The contents of the command block registers related to addresses after the transfer of a data block containing an erred sector are undefined. To obtain a valid error information, the host should retry data transfer as an individual request.

C141-E057-01EN 5-25

Fujitsu MHF2021AT, MHE2043AT, MHE2064AT, MHF2043AT User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Preface

Contents

Illustrations

CHAPTER 1 Device Overview

1.1 Features

1.1.1 Functions and performance

1.1.2 Adaptability

1.1.3 Interface

1.2 Device Specifications

1.2.1 Specifications summary

1.2.2 Model and product number

1.3 Power Requirements

1.4 Environmental Specifications

1.5 Acoustic Noise

1.6 Shock and Vibration

1.7 Reliability

1.8 Error Rate

1.9 Media Defects

CHAPTER 2 Device Configuration

2.1 Device Configuration

2.2 System Configuration

2.2.1 ATA interface

2.2.2 1 drive connection

2.2.3 2 drives connection

CHAPTER 3 Installation Conditions

3.1 Dimensions

3.2 Mounting

3.3 Cable Connections

3.3.1 Device connector

3.3.2 Cable connector specifications

3.3.3 Device connection

3.3.4 Power supply connector (CN1)

3.4 Jumper Settings

3.4.1 Location of setting jumpers

3.4.2 Factory default setting

3.4.3 Master drive-slave drive setting

3.4.4 CSEL setting

CHAPTER 4 Theory of Device Operation

4.1 Outline

4.2 Subassemblies

4.2.1 Disk

4.2.2 Head

4.2.3 Spindle

4.2.4 Actuator

4.2.5 Air filter

4.3 Circuit Configuration

4.4 Power-on Sequence

4.5 Self-calibration

4.5.1 Self-calibration contents

4.5.2 Execution timing of self-calibration

4.6 Read/write Circuit

4.5.3 Command processing during self-calibration

4.6.1 Read/write preamplifier (PreAMP)

4.6.2 Write circuit

4.6.3 Read circuit

4.6.4 Digital PLL circuit

4.7 Servo Control

4.7.1 Servo control circuit

4.7.2 Data-surface servo format

4.7.3 Servo frame format

4.7.4 Actuator motor control

4.7.5 Spindle motor control

CHAPTER 5 Interface

5.1 Physical Interface

5.1.1 Interface signals

5.1.2 Signal assignment on the connector

5.2 Logical Interface

5.2.1 I/O registers

5.2.2 Command block registers

5.2.3 Control block registers

5.3 Host Commands

5.3.1 Command code and parameters

5.3.2 Command descriptions