Fujitsu MHA2032AT, MHA2021AT User Manual

MHA2021AT, MHA2032AT

DISK DRIVES

PRODUCT MANUAL

C141-E042-01EN

FOR SAFE OPERATION

Handling of This Manual

This manual contains important information for using this product. Read thoroughly before using
the product. Use this product only after thoroughly reading and understanding especially the
section “Important Alert Items” in this manual. Keep this manual handy, and keep it carefully.

FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering
damage to their property. Use the product according to this manual.

IMPORTANT NOTE TO USERS

READ THE ENTIRE MANUAL CAREFULLY BEFORE USING THIS PRODUCT.
INCORRECT USE OF THE PRODUCT MAY RESULT IN INJURY OR DAMAGE TO
USERS, BYSTANDERS OR PROPERTY.

While FUJITSU has sought to ensure the accuracy of all information in this manual, FUJITSU
assumes no liability to any party for any damage caused by any error or omission contained in this
manual, its updates or supplements, whether such errors or omissions result from negligence,
accident, or any other cause. In addition, FUJITSU assumes no liability with respect to the
application or use of any product or system in accordance with the descriptions or instructions
contained herein; including any liability for incidental or consequential damages arising therefrom.
FUJITSU DISCLAIMS ALL WARRANTIES REGARDING THE INFORMATION
CONTAINED HEREIN, WHETHER EXPRESSED, IMPLIED, OR STATUTORY.

FUJITSU reserves the right to make changes to any products described herein without further
notice and without obligation.

The contents of this manual may be revised without prior notice.

The contents of this manual shall not be disclosed in any way or reproduced in any media without
the express written permission of Fujitsu Limited.

All Rights Reserved, Copyright  FUJITSU LIMITED 1997

C141-E042-01EN

Revision History

(1/1)

Edition Date Revised section (*1)

(Added/Deleted/Altered)

01 1997-07-15 — —

Details

*1 Section(s) with asterisk (*) refer to the previous edition when those were deleted.

C141-E042-01EN

This manual describes the MHA2021AT and MHA2032AT, 2.5-inch hard disk
drives. These drives have a built-in controller that is compatible with the ATA
interface.

This manual describes the specifications and functions of the drives and explains
in detail how to incorporate the drives into user systems. This manual assumes
that the reader has a basic knowledge of hard disk drives and their implementations
in computer systems.

This manual consists of seven chapters and sections explaining the special
terminology and abbreviations used in this manual:

Overview of Manual

CHAPTER 1 Drive Overview

This chapter gives an overview of the MHA2021AT and MHA2032AT and
describes their features.

Preface

CHAPTER 2 Drive Configuration

This chapter describes the internal configurations of the MHA2021AT and
MHA2032AT and the configuration of the systems in which they operate.

CHAPTER 3 Drive Installation

This chapter describes the external dimensions, installation conditions, and switch
settings of the MHA2021AT and MHA2032AT.

CHAPTER 4 Theory of Drive Operation

This chapter describes the operation theory of the MHA2021AT and
MHA2032AT.

CHAPTER 5 Interface Specifications

This chapter describes the interface specifications of the MHA2021AT and
MHA2032AT.

CHAPTER 6 Interface Operations

This chapter describes the operations of the MHA2021AT and MHA2032AT.

CHAPTER 7 Miscellaneous

This chapter describes how to reformat the MHA2021AT and MHA2032AT.

Terminology

This section explains the special terminology used in this manual.

C141-E042-01EN i

Preface

Abbreviation

This section gives the meanings of the definitions used in this manual.

Conventions for Alert Messages

This manual uses the following conventions to show the alert messages. An alert
message consists of an alert signal and alert statements. The alert signal consists
of an alert symbol and a signal word or just a signal word.

The following are the alert signals and their meanings:

This indicates a hazarous situation could result in
minor or moderate personal injury if the user does
not perform the procedure correctly. This alert
signal also indicates that damages to the product or
other property, may occur if the user does not
perform the procedure correctly.

This indicates information that could help the user
use the product more efficiently.

In the text, the alert signal is centered, followed below by the indented message. A
wider line space precedes and follows the alert message to show where the alert
message begins and ends. The following is an example:

(Example)

Data corruption: Avoid mounting the disk drive near strong
magnetic sources such as loud speakers. Ensure that the disk drive is
not affected by external magnetic fields.

The main alert messages in the text are also listed in the “Important Alert Items.”

Operating Environment

This product is designed to be used in offices or computer rooms.

For details regarding the operating environment of use, refer to the
(Cnnn-Xnnn) and the
(Cnnn-Xnnn).

Attention

Please forward any comments you may have regarding this manual.

ii C141-E042-01EN

To make this manual easier for users to understand, opinions from readers are
needed. Please write your opinions or requests on the Comment at the back of this
manual and forward it to the address described in the sheet.

Liability Exception

“Disk drive defects” refers to defects that involve adjustment, repair, or
replacement.

Fujitsu is not liable for any other disk drive defects, such as those caused by user
misoperation or mishandling, inappropriate operating environments, defects in the
power supply or cable, problems of the host system, or other causes outside the
disk drive.

Preface

C141-E042-01EN iii

Important Alert Items

Important Alert Messages

The important alert messages in this manual are as follows:

A hazardous situation could result in minor or moderate personal
injury if the user does not perform the procedure correctly. Also,
damage to the predate or other property, may occur if the user does
not perform the procedure correctly.

Task Alert message Page

Normal Operation Data corruption: Avoid mounting the disk near strong

magnetic soures such as loud speakers. Ensure that the disk
drive is not affected by extrnal magnetic fields.

3-6

C141-E042-01EN v

Contents

CHAPTER 1 Device Overview .......................................................................1-1

1.1 Features 1-2

1.1.1 Functions and performance 1-2

1.1.2 Adaptability 1-2

1.1.3 Interface 1-2

1.2 Device Specifications 1-4

1.2.1 Specifications summary 1-4

1.2.2 Model and product number 1-5

1.3 Power Requirements 1-5

1.4 Environmental Specifications 1-7

1.5 Acoustic Noise 1-7

1.6 Shock and Vibration 1-8

1.7 Reliability 1-8

1.8 Error Rate 1-9

1.9 Media Defects 1-9

CHAPTER 2 Device Configuration................................................................2-1

2.1 Device Configuration 2-2

2.2 System Configuration 2-4

2.2.1 ATA interface 2-4

2.2.2 1 drive connection 2-4

2.2.3 2 drives connection 2-5

C141-E042-01EN vii

Contents

CHAPTER 3 Installation Conditions..............................................................3-1

3.1 Dimensions 3-2

3.2 Mounting 3-3

3.3 Cable Connections 3-7

3.3.1 Device connector 3-7

3.3.2 Cable connector specifications 3-8

3.3.3 Device connection 3-8

3.3.4 Power supply connector (CN1) 3-9

3.4 Jumper Settings 3-9

3.4.1 Location of setting jumpers 3-9

3.4.2 Factory default setting 3-10

3.4.3 Master drive-slave drive setting 3-10

3.4.4 CSEL setting 3-11

CHAPTER 4 Theory of Device Operation......................................................4-1

4.1 Outline 4-2

4.2 Subassemblies 4-2

4.2.1 Disk 4-2

4.2.2 Head 4-2

4.2.3 Spindle 4-3

4.2.4 Actuator 4-3

4.2.5 Air filter 4-3

4.3 Circuit Configuration 4-4

4.4 Power-on Sequence 4-6

4.5 Self-calibration 4-7

4.5.1 Self-calibration contents 4-7

4.5.2 Execution timing of self-calibration 4-8

4.5.3 Command processing during self-calibration 4-9

4.6 Read/write Circuit 4-9

4.6.1 Read/write preamplifier (PreAMP) 4-9

4.6.2 Write circuit 4-10

viii C141-E042-01EN

Contents

4.6.3 Read circuit 4-12

4.6.4 Time base generator circuit 4-13

4.7 Servo Control 4-14

4.7.1 Servo control circuit 4-14

4.7.2 Data-surface servo format 4-18

4.7.3 Servo frame format 4-18

4.7.4 Actuator motor control 4-19

4.7.5 Spindle motor control 4-20

CHAPTER 5 Interface.....................................................................................5-1

5.1 Physical Interface 5-2

5.1.1 Interface signals 5-2

5.1.2 Signal assignment on the connector 5-2

5.2 Logical Interface 5-6

5.2.1 I/O registers 5-6

5.2.2 Command block registers 5-8

5.2.3 Control block registers 5-13

5.3 Host Commands 5-13

5.3.1 Command code and parameters 5-14

5.3.2 Command descriptions 5-16

5.3.3 Error posting 5-67

5.4 Command Protocol 5-69

5.4.1 Data transferring commands from device to host 5-69

5.4.2 Data transferring commands from host to device 5-71

5.4.3 Commands without data transfer 5-73

5.4.4 Other commands 5-74

5.4.5 DMA data transfer commands 5-74

5.5 Timing 5-76

5.5.1 PIO data transfer 5-76

5.5.2 Single word DMA data transfer 5-78

5.5.3 Multiword DMA data transfer 5-79

5.5.4 Power-on and reset 5-79

C141-E042-01EN ix

Contents

CHAPTER 6 Operations..................................................................................6-1

6.1 Device Response to the Reset 6-2

6.1.1 Response to power-on 6-2

6.1.2 Response to hardware reset 6-4

6.1.3 Response to software reset 6-5

6.1.4 Response to diagnostic command 6-6

6.2 Address Translation 6-7

6.2.1 Default parameters 6-7

6.2.2 Logical address 6-8

6.3 Power Save 6-9

6.3.1 Power save mode 6-9

6.3.2 Power commands 6-11

6.4 Defect Management 6-11

6.4.1 Spare area 6-12

6.4.2 Alternating defective sectors 6-12

6.5 Read-Ahead Cache 6-14

6.5.1 Data buffer configuration 6-14

6.5.2 Caching operation 6-14

6.5.3 Usage of read segment 6-16

6.6 Write Cache 6-22

Glossary ..................................................................................................GL-1

Acronyms and Abbreviations........................................................................ AB-1

Index ...................................................................................................IN-1

x C141-E042-01EN

Figures

Contents

Illustrations

Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on 1-6

Figure 2.1 Disk drive outerview 2-2
Figure 2.2 Configuration of disk media heads 2-3
Figure 2.3 1 drive system configuration 2-4
Figure 2.4 2 drives configuration 2-5

Figure 3.1 Dimensions 3-2
Figure 3.2 Orientation 3-3
Figure 3.3 Mounting frame structure 3-4
Figure 3.4 Surface temperature measurement points 3-5
Figure 3.5 Service area 3-6
Figure 3.6 Connector locations 3-7
Figure 3.7 Cable connections 3-8
Figure 3.8 Power supply connector pins (CN1) 3-9
Figure 3.9 Jumper location 3-9
Figure 3.10 Factory default setting 3-10
Figure 3.11 Jumper setting of master or slave device 3-10
Figure 3.12 CSEL setting 3-11
Figure 3.13 Example (1) of Cable Select 3-11
Figure 3.14 Example (2) of Cable Select 3-12

Figure 4.1 Head structure 4-3
Figure 4.2 Circuit Configuration 4-5
Figure 4.3 Power-on operation sequence 4-7
Figure 4.4 Read/write circuit block diagram 4-11
Figure 4.5 Frequency characteristic of programmable filter 4-12
Figure 4.6 Block diagram of servo control circuit 4-14
Figure 4.7 Physical sector servo configuration on disk surface 4-16
Figure 4.8 Servo frame format 4-18

Figure 5.1 Interface signals 5-2
Figure 5.2 Execution example of READ MULTIPLE command 5-20
Figure 5.3 Read Sector(s) command protocol 5-70
Figure 5.4 Protocol for command abort 5-71
Figure 5.5 WRITE SECTOR(S) command protocol 5-72

C141-E042-01EN xi

Contents

Figure 5.6 Protocol for the command execution without data transfer 5-73
Figure 5.7 Normal DMA data transfer 5-75
Figure 5.8 Data transfer timing 5-77
Figure 5.9 Single word DMA data transfer timing (mode 2) 5-78
Figure 5.10 Multiword DMA data transfer timing (mode 2) 5-79
Figure 5.11 Power on Reset Timing 5-80

Figure 6.1 Response to power-on 6-3
Figure 6.2 Response to hardware reset 6-4
Figure 6.3 Response to software reset 6-5
Figure 6.4 Response to diagnostic command 6-6
Figure 6.5 Address translation (example in CHS mode) 6-8
Figure 6.6 Address translation (example in LBA mode) 6-9
Figure 6.7 Sector slip processing 6-12
Figure 6.8 Alternate cylinder assignment 6-13
Figure 6.9 Data buffer configuration 6-14

Tables

Table 1.1 Specifications 1-4
Table 1.2 Model names and product numbers 1-5
Table 1.3 Current and power dissipation 1-6
Table 1.4 Environmental specifications 1-7
Table 1.5 Acoustic noise specification 1-7
Table 1.6 Shock and vibration specification 1-8

Table 3.1 Surface temperature measurement points and standard values 3-5
Table 3.2 Cable connector specifications 3-8

Table 4.1 Self-calibration execution timechart 4-9
Table 4.2 Write precompensation algorithm 4-10
Table 4.3 Write clock freqeuncy and recording density (BPI) of each zone

4-13

Table 5.1 Signal assignment on the interface connector 5-3
Table 5.2 I/O registers 5-7
Table 5.3 Command code and parameters 5-14
Table 5.4 Information to be read by IDENTIFY DEVICE command 5-32
Table 5.5 Features register values and settable modes 5-38
Table 5.6 Diagnostic code 5-43
Table 5.7 Features Register values (subcommands) and functions 5-54
Table 5.8 Format of device attribute value data 5-56
Table 5.9 Format of insurance failure threshold value data 5-57

xii C141-E042-01EN

Contents

Table 5.10 Contents of security password 5-59
Table 5.11 Contents of SECURITY SET PASSWORD data 5-64
Table 5.12 Relationship between combination of Identifier and Security level,

and operation of the lock function 5-65

Table 5.13 Command code and parameters 5-67

Table 6.1 Default parameters 6-7

C141-E042-01EN xiii

CHAPTER 1 Device Overview

1.1 Features

1.2 Device Specifications

1.3 Power Requirements

1.4 Environment Specifications

1.5 Acoustic Noise

1.6 Shock and Vibration

1.7 Reliability

1.8 Error Rate

1.9 Media Defects

Overview and features are described in this chapter, and specifications and power
requirement are described.

The MHA2021AT and MHA2032AT are 2.5-inch hard disk drives with built-in
disk controllers. These disk drives use the AT-bus hard disk interface protocol
and are compact and reliable.

C141-E042-01EN 1-1

Device Overview

1.1 Features

1.1.1 Functions and performance

(1) Compact

The disk has 1 or 2 disks of 65 mm (2.5 inches) diameter, and its height is 12.5
mm (0.492 inch).

(2) Large capacity

The disk drive can record up to 1,083 MB (formatted) on one disk using the (8/9)
PRML recording method and 13 recording zone technology. The MHA2021AT
and MHA2032AT have a formatted capacity of 2,167 MB and 3,251 MB
respectively.

(3) High-speed Transfer rate

The disk drive has an internal data rate up to 8.92 MB/s. The disk drive supports
an external data rate up to 16.6 MB/s.

(4) Average positioning time

Use of a rotary voice coil motor in the head positioning mechanism greatly
increases the positioning speed. The average positioning time is 13 ms (at read).

1.1.2 Adaptability

(1) Power save mode

The power save mode feature for idle operation, stand by and sleep modes makes
the disk drive ideal for applications where power consumption is a factor.

(2) Wide temperature range

The disk drive can be used over a wide temperature range (5°C to 55°C).

(3) Low noise and vibration

In Ready status, the noise of the disk drive is only about 30 dBA (measured at 1 m
apart from the drive under the idle mode).

1.1.3 Interface

(1) Connection to interface

With the built-in ATA interface controller, the disk drive can be connected to an
ATA interface of a personal computer.

1-2 C141-E042-01EN

(2) 128-KB data buffer

The disk drive uses a 128-KB data buffer to transfer data between the host and the
disk media.

In combination with the read-ahead cache system described in item (3) and the
write cache described in item (7), the buffer contributes to efficient I/O
processing.

(3) Read-ahead cache system

After the execution of a disk read command, the disk drive automatically reads
the subsequent data block and writes it to the data buffer (read ahead operation).
This cache system enables fast data access. The next disk read command would
normally cause another disk access. But, if the read ahead data corresponds to the
data requested by the next read command, the data in the buffer can be transferred
instead.

(4) Master/slave

The disk drive can be connected to ATA interface as daisy chain configuration.
Drive 0 is a master device, drive 1 is a slave device.

1.1 Features

(5) Error correction and retry by ECC

If a recoverable error occurs, the disk drive itself attempts error recovery. The
ECC has improved buffer error correction for correctable data errors.

(6) Self-diagnosis

The disk drive has a diagnostic function to check operation of the controller and
disk drive. Executing the diagnostic command invokes self-diagnosis.

(7) Write cache

When the disk drive receives a write command, the disk drive posts the command
completion at completion of transferring data to the data buffer completion of
writing to the disk media. This feature reduces the access time at writing.

C141-E042-01EN 1-3

Device Overview

1.2 Device Specifications

1.2.1 Specifications summary

Table 1.1 shows the specfications of the disk drive.

Table 1.1 Specifications

MHA2021AT MHA2032AT

Format Capacity (*1) 2.16 GB 3.25 GB
Number of Heads 4 6
Number of Cylinders (User) 6,372
Bytes per Sector 512
Recording Method (8/9) PRML
Track Density 10,555 TPI
Bit Density 157,422 BPI
Rotational Speed 4,000 rpm ± 1%
Average Latency 7.5 ms
Positioning time (read and seek)

• Minimum (Track to Track)

• Average

• Maximum (Full)

Start/Stop time

• Start (0 rpm to Drive Read)

• Stop (at Power Down)
(when the command is stopped) (when the power is off)

Interface ATA-3 (Max. Cable length: 0.46 m)
Data Transfer Rate

• To/From Media

• To/From Host

Typ.: 5 sec, Max.: 10 sec
Typ.: 5 sec, Max.: 15 sec

(burst PIO mode 4, burst DMA mode 2)

2.5 ms (typ.)

Read: 13 ms (typ.)

23 ms (typ.)

4.93 to 8.92 MB/s

16.6 MB/s Max.

Data Buffer Size 128 KB
Physical Dimensions

(Height × Width × Depth)
Weight 145 g

1-4 C141-E042-01EN

12.5 mm × 100.0 mm × 70.0 mm
(0.49" × 3.94" × 2.75")

1.3 Power Requirements

*1: Capacity under the LBA mode.

Under the CHS mode (normal BIOS specification), formatted capacity,
number of cylinders, number of heads, and number of sectors are as
follows.

Model Formatted Capacity No. of Cylinder No. of Heads No. of Sectors

MHA2021AT 2,167.60 MB 4,200 16 63
MHA2032AT 3,251.40 MB 6,300 16 63

1.2.2 Model and product number

Table 1.2 lists the model names and product numbers.

Table 1.2 Model names and product numbers

Model Name Capacity

(user area)

MHA2021AT 2.16 GB M3, depth 3 CA01640-B040
MHA2032AT 3.25 GB M3, depth 3 CA01640-B060

1.3 Power Requirements

(1) Input Voltage

+ 5 V ± 5 %

•

(2) Ripple

Maximum 100 mV (peak to peak)
Frequency DC to 1 MHz

Mounting screw Order No.

+5 V

C141-E042-01EN 1-5

Device Overview

(3) Current Requirements and Power Dissipation

Table 1.3 lists the current and power dissipation.

Table 1.3 Current and power dissipation

Typical RMS Current Typical Power (*2)

Spin up (*1) 1.0 A Watts 5.0 W
Idle 0.236 A T.B.D T.B.D 1.18 W
R/W (*3) 0.5 A T.B.D T.B.D 2.5 W
Standby 0.076 A T.B.D T.B.D 0.38 W
Sleep 0.03 AT.B.D T.B.D 0.15 W

*1 Current at starting spindle motor.

*2 Power requirements reflect nominal values for +5V power.

*3 At 30% disk accessing.

(4) Current fluctuation (Typ.) at +5V when power is turned on

Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on

(5) Power on/off sequence

The voltage detector circuit monitors +5 V. The circuit does not allow a write
signal if either voltage is abnormal. This prevents data from being destroyed and
eliminates the need to be concerned with the power on/off sequence.

1-6 C141-E042-01EN

1.4 Environmental Specifications

Table 1.4 lists the environmental specifications.

Table 1.4 Environmental specifications

Temperature

1.5 Acoustic Noise

• Operating

• Non-operating

• Thermal Gradient

Humidity

• Operating

• Non-operating

• Maximum Wet Bulb

Altitude (relative to sea level)

• Operating

• Non-operating

1.5 Acoustic Noise

Table 1.5 lists the acoustic noise specification.

5°C to 55°C (ambient)
5°C to 60°C (disk enclosure surface)
–40°C to 65°C
20°C/h or less

8% to 90% RH (Non-condensing)
5% to 95% RH (Non-condensing)
29°C

–300 to 3,000 m (–200 to 10000 ft)
–300 to 12,000 m (–200 to 40000 ft)

Table 1.5 Acoustic noise specification

Sound Pressure

• Idle mode (DRIVE READY) 30 dBA typical at 1 m

C141-E042-01EN 1-7

Device Overview

1.6 Shock and Vibration

Table 1.6 lists the shock and vibration specification.

Table 1.6 Shock and vibration specification

Vibration (swept sine, one octave per minute)

• Operating

• Non-operating

Shock (half-sine pulse, 2 ms duration)

• Operating

• Non-operating

1.7 Reliability

(1) Mean time between failures (MTBF)

The mean time between failures (MTBF) is 300,000 H or more (operation: 24
hours/day, 7 days/week).

This does not include failures occurring during the first three months after
installation.

MTBF is defined as follows:

5 to 500 Hz, 1.0G0-peak
(without non-recovered errors) (9.8 m/s

2

5 to 500 Hz, 5G0-peak (no damage) (49 m/s

100G0-peak
(without non-recovered errors) (980 m/s

500G0-peak (no damage) (4,900 m/s

2

0-peak)

0-peak)

2

0-peak)

2

0-peak)

Total operation time in all fields

MTBF= (H)

number of device failure in all fields

“Disk drive defects” refers to defects that involve repair, readjustment, or
replacement. Disk drive defects do not include failures caused by external
factors, such as damage caused by handling, inappropriate operating
environments, defects in the power supply host system, or interface cable.

(2) Mean time to repair (MTTR)

The mean time to repair (MTTR) is 30 minutes or less, if repaired by a specialist
maintenance staff member.

1-8 C141-E042-01EN

(3) Service life

In situations where management and handling are correct, the disk drive requires
no overhaul for five years when the DE surface temperature is less than 48°C.
When the DE surface temperature exceeds 48°C, the disk drives requires no
overhaul for five years or 20,000 hours of operation, whichever occurs first.
Refer to item (3) in Subsection 3.2 for the measurement point of the DE surface
temperature.

(4) Data assurance in the event of power failure

Except for the data block being written to, the data on the disk media is assured in
the event of any power supply abnormalities. This does not include power supply
abnormalities during disk media initialization (formatting) or processing of
defects (alternative block assignment).

1.8 Error Rate

Known defects, for which alternative blocks can be assigned, are not included in
the error rate count below. It is assumed that the data blocks to be accessed are
evenly distributed on the disk media.

1.9 Media Defects

(1) Unrecoverable read error

Read errors that cannot be recovered by maximum 126 times read retries without
user’s retry and ECC corrections shall occur no more than 10 times when reading
data of 10

14

recovery procedure, and include read retries accompanying head offset
operations.

(2) Positioning error

Positioning (seek) errors that can be recovered by one retry shall occur no more
than 10 times in 10

1.9 Media Defects

Defective sectors are replaced with alternates when the disk is formatted prior to
shipment from the factory (low level format). Thus, the host sees a defect-free
device.

Alternate sectors are automatically accessed by the disk drive. The user need not
be concerned with access to alternate sectors.

bits. Read retries are executed according to the disk drive’s error

7

seek operations.

C141-E042-01EN 1-9

CHAPTER 2 Device Configuration

2.1 Device Configuration

2.2 System Configuration

This chapter describes the internal configurations of the hard disk drives and the
configuration of the systems in which they operate.

C141-E042-01EN 2-1

Device Configuration

2.1 Device Configuration

Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE),
read/write preamplifier, and controller PCA. The disk enclosure contains the disk
media, heads, spindle motors, actuators, and a circulating air filter.

(1) Disk

(2) Head

Figure 2.1 Disk drive outerview

The outer diameter of the disk is 65 mm. The inner diameter is 20 mm. The
number of disks used varies with the model, as described below. The disks are
rated at over 50,000 start/stop operations.

MHA2021AT: 2 disk

MHA2032AT: 3 disks

The heads are of the contact start/stop (CSS) type. The head touches the disk
surface while the disk is not rotating and automatically lifts when the disk starts.

Figure 2.2 illustrates the configuration of the disks and heads of each model. In
the disk surface, servo information necessary for controlling positioning and
read/write and user data are written. Numerals 0 to 5 indicate read/write heads.

2-2 C141-E042-01EN

Head

0
1

2
3

2.1 Device Configuration

Head

0
1

2
3

4

5

(3) Spindle motor

(4) Actuator

MHA2021AT

Figure 2.2 Configuration of disk media heads

The disks are rotated by a direct drive Hall-less DC motor.

The actuator uses a revolving voice coil motor (VCM) structure which consumes
low power and generates very little heat. The head assembly at the edge of the
actuator arm is controlled and positioned by feedback of the servo information
read by the read/write head. If the power is not on or if the spindle motor is
stopped, the head assembly stays in the specific CSS zone on the disk and is fixed
by a mechanical lock.

MHA2032AT

C141-E042-01EN 2-3

Device Configuration

(5) Air circulation system

The disk enclosure (DE) is sealed to prevent dust and dirt from entering. The disk
enclosure features a closed loop air circulation system that relies on the blower
effect of the rotating disk. This system continuously circulates the air through the
circulation filter to maintain the cleanliness of the air within the disk enclosure.

(6) Read/write circuit

The read/write circuit uses a LSI chip for the read/write preamplifier. It improves
data reliability by preventing errors caused by external noise.

(7) Controller circuit

The controller circuit consists of an LSI chip to improve reliability. The high­speed microprocessor unit (MPU) achieves a high-performance AT controller.

2.2 System Configuration

2.2.1 ATA interface

Figures 2.3 and 2.4 show the ATA interface system configuration. The drive has
a 44-pin PC AT interface connector and supports the PIO transfer at 16.6 MB/s
(ATA-3, Mode 4), the DMA transfer at 16.6 MB/s (ATA-3, Multiword mode 2).

2.2.2 1 drive connection

Figure 2.3 1 drive system configuration

MHA2021AT
MHA2032AT

2-4 C141-E042-01EN

2.2.3 2 drives connection

2.2 System Configuration

(Host adaptor)

MHA2021AT
MHA2032AT

MHA2021AT
MHA2032AT

Note:

When the drive that is not conformed to ATA is connected to the disk drive above
configuration, the operation is not guaranteed.

Figure 2.4 2 drives configuration

HA (host adaptor) consists of address decoder, driver, and receiver.
ATA is an abbreviation of “AT attachment”. The disk drive is
conformed to the ATA-3 interface.

At high speed data transfer (PIO mode 3, mode 4, or DMA mode 2),
occurence of ringing or crosstalk of the signal lines (AT bus)
between the HA and the disk drive may be a great cause of the
obstruction of system reliability. Thus, it is necessary that the
capacitance of the signal lines including the HA and cable does not
exceed the ATA-3 standard, and the cable length between the HA
and the disk drive should be as short as possible.

C141-E042-01EN 2-5

CHAPTER 3 Installation Conditions

3.1 Dimensions

3.2 Mounting

3.3 Cable Connections

3.4 Jumper Settings

This chapter gives the external dimensions, installation conditions, surface
temperature conditions, cable connections, and switch settings of the hard disk
drives.

C141-E042-01EN 3-1

Installation Conditions

3.1 Dimensions

Figure 3.1 illustrates the dimensions of the disk drive and positions of the
mounting screw holes. All dimensions are in mm.

Figure 3.1 Dimensions

3-2 C141-E042-01EN

3.2 Mounting

(1) Orientation

Figure 3.2 illustrates the allowable orientations for the disk drive.

3.2 Mounting

(b) Horizontal –1(a) Horizontal –1

(c) Vertical –1 (d) Vertical –2

(e) Vertical –3 (f) Vertical –4

Figure 3.2 Orientation

C141-E042-01EN 3-3

Installation Conditions

(2) Frame

The MR head bias of the HDD disk enclosure (DE) is zero. The mounting frame
is connected to SG.

Use M3 screw for the mounting screw and the screw length should
satisfy the specification in Figure 3.3.

The tightening torque must not exceed 3 kgcm.
When attaching the HDD to the system frame, do not allow the

system frame to touch parts (cover and base) other than parts to
which the HDD is attached.

(3) Limitation of side-mounting

Do not use the center hole. For screw length, see Figure 3.3.

Bottom surface mounting

2

A

Frame of system
cabinet

3.0 or less

DE

2.5

2.5

Frame of system
cabinet

Screw

3.0 or less

Details of A

Details of B

Figure 3.3 Mounting frame structure

Side surface
mounting

PCA

Screw

2.52.5

B

3-4 C141-E042-01EN

(4) Ambient temperature

The temperature conditions for a disk drive mounted in a cabinet refer to the
ambient temperature at a point 3 cm from the disk drive. The ambient
temperature must satisfy the temperature conditions described in Section 1.4, and
the airflow must be considered to prevent the DE surface temperature from
exceeding 60°C.

Provide air circulation in the cabinet such that the PCA side, in particular,
receives sufficient cooling. To check the cooling efficiency, measure the surface
temperatures of the DE. Regardless of the ambient temperature, this surface
temperature must meet the standards listed in Table 3.1. Figure 3.4 shows the
temperature measurement point.

3.2 Mounting

1

Figure 3.4 Surface temperature measurement points

Table 3.1 Surface temperature measurement points and standard values

No. Measurement point Temperature

1 DE cover 60°C max

C141-E042-01EN 3-5

Installation Conditions

(5) Service area

Figure 3.5 shows how the drive must be accessed (service areas) during and after
installation.

Mounting screw hole

Cable connection

(6) External magnetic fields

Data corruption: Avoid mounting the disk drive near strong
magnetic sources such as loud speakers. Ensure that the disk drive
is not affected by external magnetic fields.

Mounting screw hole

Figure 3.5 Service area

3-6 C141-E042-01EN

3.3 Cable Connections

3.3.1 Device connector

The disk drive has the connectors and terminals listed below for connecting
external devices. Figure 3.6 shows the locations of these connectors and
terminals.

3.3 Cable Connections

Connector,
setting pins

PCA

Figure 3.6 Connector locations

C141-E042-01EN 3-7

Installation Conditions

3.3.2 Cable connector specifications

Table 3.2 lists the recommended specifications for the cable connectors.

Table 3.2 Cable connector specifications

Name Model Manufacturer

ATA interface and
power supply cable
(44-pin type)

(44-pin type)

(44-pin type)

For the host interface cable, use a ribbon cable. A twisted cable or
a cable with wires that have become separated from the ribbon may
cause crosstalk between signal lines. This is because the interface
is designed for ribbon cables and not for cables carrying differential
signals.

3.3.3 Device connection

Figure 3.7 shows how to connect the devices.

Cable socket

Cable

89361-144 BERG

FV08-A440 Junkosha

Figure 3.7 Cable connections

3-8 C141-E042-01EN

3.3.4 Power supply connector (CN1)

Figure 3.8 shows the pin assignment of the power supply connector (CN1).

3.4 Jumper Settings

Figure 3.8 Power supply connector pins (CN1)

3.4 Jumper Settings

3.4.1 Location of setting jumpers

Figure 3.9 shows the location of the jumpers to select drive configuration and
functions.

Figure 3.9 Jumper location

C141-E042-01EN 3-9

Installation Conditions

3.4.2 Factory default setting

Figure 3.10 shows the default setting position at the factory.

Figure 3.10 Factory default setting

3.4.3 Master drive-slave drive setting

Master device (device #0) or slave device (device #1) is selected.

Figure 3.11 Jumper setting of master or slave device

Note:

Pins A and C should be open.

3-10 C141-E042-01EN

3.4.4 CSEL setting

Figure 3.12 shows the cable select (CSEL) setting.

3.4 Jumper Settings

Note:

The CSEL setting is not depended on setting between pins Band D.

Figure 3.12 CSEL setting

Figure 3.13 and 3.14 show examples of cable selection using unique interface
cables.

By connecting the CSEL of the master device to the CSEL Line (conducer) of the
cable and connecting it to ground further, the CSEL is set to low level. The
device is identified as a master device. At this time, the CSEL of the slave device
does not have a conductor. Thus, since the slave device is not connected to the
CSEL conductor, the CSEL is set to high level. The device is identified as a slave
device.

Figure 3.13 Example (1) of Cable Select

C141-E042-01EN 3-11

Installation Conditions

Figure 3.14 Example (2) of Cable Select

3-12 C141-E042-01EN

CHAPTER 4 Theory of Device Operation

4.1 Outline

4.2 Subassemblies

4.3 Circuit Configuration

4.4 Power-on sequence

4.5 Self-calibration

4.6 Read/Write circuit

4.7 Servo Control

This chapter explains basic design concepts of the disk drive. Also, this chapter
explains subassemblies of the disk drive, each sequence, servo control, and
electrical circuit blocks.

C141-E042-01EN 4-1

Theory of Device Operation

4.1 Outline

This chapter consists of two parts. First part (Section 4.2) explains mechanical
assemblies of the disk drive. Second part (Sections 4.3 through 4.7) explains a
servo information recorded in the disk drive and drive control method.

4.2 Subassemblies

The disk drive consists of a disk enclosure (DE) and printed circuit assembly
(PCA).

The DE contains all movable parts in the disk drive, including the disk, spindle,
actuator, read/write head, and air filter. For details, see Subsections 4.2.1 to 4.2.5.

The PCA contains the control circuits for the disk drive. The disk drive has one
PCA. For details, see Sections 4.3.

4.2.1 Disk

4.2.2 Head

The DE contains disks with an outer diameter of 65 mm and an inner diameter of
20 mm. The MHA2032 has three disks and MHA2021AT has two disks.

The head contacts the disk each time the disk rotation stops; the life of the disk is
50,000 contacts or more. Servo data is recorded on top disk.

Servo data is recorded on each cylinder (total 54). Servo data written at factory is
read out by the read/write head. For servo data, see Section 4.7.

Figure 4.1 shows the read/write head structures. MHA2021AT has 4 read/write
heads and MHA2032AT has 6 read/write heads. These heads are raised from the
disk surface as the spindle motor the rated rotation speed.

4-2 C141-E042-01EN

Head

0
1

2
3

4.2 Subassemblies

Head

0
1

2
3

4
5

4.2.3 Spindle

4.2.4 Actuator

4.2.5 Air filter

MHA2021AT

Figure 4.1 Head structure

The spindle consists of a disk stack assembly and spindle motor. The disk stack
assembly is activated by the direct drive sensor-less DC spindle motor, which has
a speed of 4,000 rpm ±1%. The spindle is controlled with detecting a PHASE
signal generated by counter electromotive voltage of the spindle motor at starting.

The actuator consists of a voice coil motor (VCM) and a head carriage. The
VCM moves the head carriage along the inner or outer edge of the disk. The head
carriage position is controlled by feeding back the difference of the target position
that is detected and reproduced from the servo information read by the read/write
head.

MHA2032AT

There are two types of air filters: a breather filter and a circulation filter.

The breather filter makes an air in and out of the DE to prevent unnecessary
pressure around the spindle when the disk starts or stops rotating. When disk
drives are transported under conditions where the air pressure changes a lot,
filtered air is circulated in the DE.

The circulation filter cleans out dust and dirt from inside the DE. The disk drive
cycles air continuously through the circulation filter through an enclosed loop air
cycle system operated by a blower on the rotating disk.

C141-E042-01EN 4-3

Theory of Device Operation

4.3 Circuit Configuration

Figure 4.2 shows the disk drive circuit configuration.

(1) Read/write circuit

The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and
read channel (RDC).

The PreAMP consists of the write current switch circuit, that flows the write
current to the head coil, and the voltage amplifier circuit, that amplitudes the read
output from the head.

The RDC is the read demodulation circuit using the partial response class 4
(PR4), and contains the Viterbi detector, programmable filter, adaptable
transversal filter, times base generator, and data separator circuits. The RDC also
contains the 8/9 group coded recording (GCR) encoder and decoder and servo
demodulation circuit.

(2) Servo circuit

The position and speed of the voice coil motor are controlled by 2 closed-loop
servo using the servo information recorded on the data surface. The servo
information is an analog signal converted to digital for processeing by a MPU and
then reconverted to an analog signal for control of the voice coil motor.

The MPU precisely sets each head on the track according on the servo
information on the media surface.

(3) Spindle motor driver circuit

The circuit measures the interval of a PHASE signal generated by counter­electromotive voltage of a motor at the MPU and controls the motor speed
comparing target speed.

(4) Controller circuit

Major functions are listed below.

Data buffer (128 KB) management

•

ATA interface control and data transfer control

•

Sector format control

•

Defect management

•

ECC control

•

Error recovery and self-diagnosis

•

4-4 C141-E042-01EN

4.3 Circuit Configuration

Figure 4.2 Circuit Configuration

C141-E042-01EN 4-5

Theory of Device Operation

4.4 Power-on Sequence

Figure 4.3 describes the operation sequence of the disk drive at power-on. The
outline is described below.

a) After the power is turned on, the disk drive executes the MPU bus test,

internal register read/write test, and work RAM read/write test. When the
self-diagnosis terminates successfully, the disk drive starts the spindle motor.

b) The disk drive executes self-diagnosis (data buffer read/write test) after

enabling response to the ATA bus.

c) After confirming that the spindle motor has reached rated speed, the disk

drive releases the heads from the actuator magnet lock mechanism by
applying current to the VCM. This unlocks the heads which are parked at the
inner circumference of the disks.

d) The disk drive positions the heads onto the SA area and reads out the system

information.

e) The disk drive executes self-seek-calibration. This collects data for VCM

tarque and mechanical external forces applied to the actuator, and updates the
calibrating value.

f) The drive becomes ready. The host can issue commands.

4-6 C141-E042-01EN

4.5 Self-calibration

Figure 4.3 Power-on operation sequence

4.5 Self-calibration

The disk drive occasionally performs self-calibration in order to sense and
calibrate mechanical external forces on the actuator, and VCM tarque. This
enables precise seek and read/write operations.

4.5.1 Self-calibration contents

(1) Sensing and compensating for external forces

The actuator suffers from torque due to the FPC forces and winds accompanying
disk revolution. The torque vary with the disk drive and the cylinder where the
head is positioned. To execute stable fast seek operations, external forces are
occasionally sensed.

The firmware of the drive measures and stores the force (value of the actuator
motor drive current) that balances the torque for stopping head stably. This
includes the current offset in the power amplifier circuit and DAC system.

C141-E042-01EN 4-7

Theory of Device Operation

The forces are compensated by adding the measured value to the specified current
value to the power amplifier. This makes the stable servo control.

To compensate torque varing by the cylinder, the disk is divided into 8 areas from
the innermost to the outermost circumference and the compensating value is
measured at the measuring cylinder on each area at factory calibration. The
measured values are stored in the SA cylinder. In the self-calibration, the
compensating value is updated using the value in the SA cylinder.

(2) Compensating open loop gain

Torque constant value of the VCM has a dispersion for each drive, and varies
depending on the cylinder that the head is positioned. To realize the high speed
seek operation, the value that compensates torque constant value change and loop
gain change of the whole servo system due to temperature change is measured
and stored.

For sensing, the firmware mixes the disturbance signal to the position signal at the
state that the head is positioned to any cylinder. The firmware calculates the loop
gain from the position signal and stores the compensation value against to the
target gain as ratio.

For compensating, the direction current value to the power amplifier is multiplied
by the compensation value. By this compensation, loop gain becomes constant
value and the stable servo control is realized.

To compensate torque constant value change depending on cylinder, whole
cylinders from most inner to most outer cylinder are divided into 8 partitions at
calibration in the factory, and the compensation data is measured for representive
cylinder of each partition. This measured value is stored in the SA area. The
compensation value at self-calibration is calculated using the value in the SA
area.

4.5.2 Execution timing of self-calibration

Self-calibration is executed when:

The power is turned on.

•

The disk drive receives the RECALIBRATE command from the host.

•

The self-calibration execution timechart of the disk drive specifies self-

•

calibration.

The disk drive performs self-calibration according to the timechart based on the
time elapsed from power-on. The timechart is shown in Table 4.1. After power­on, self-calibration is performed about every five or ten or fifteen minutes for the
first 60 minutes or six RECALIBRATE command executions, and about every 30
minutes after that.

4-8 C141-E042-01EN

Table 4.1 Self-calibration execution timechart

Time elapsed Time elapsed

(accumulated)

1 At power-on Initial calibration
2 About 5 minutes About 5 minutes
3 About 5 minutes About 10 minutes
4 About 10 minutes About 20 minutes
5 About 10 minutes About 30 minutes
6 About 15 minutes About 45 minutes
7 About 15 minutes About 60 minutes
8

.
.
.
.

Every about 30
minutes

4.6 Read/write Circuit

4.5.3 Command processing during self-calibration

If the disk drive receives a command execution request from the host while
executing self-calibration according to the timechart, the disk drive terminates
self-calibration and starts executing the command precedingly. In other words, if
a disk read or write service is necessary, the disk drive positions the head to the
track requested by the host, reads or writes data, and restarts calibration.

This enables the host to execute the command without waiting for a long time,
even when the disk drive is performing self-calibration. The command execution
wait time is about maximum 100 ms.

4.6 Read/write Circuit

The read/write circuit consists of the read/write preamplifier (PreAMP), the write
circuit, the read circuit, and the time base generator in the read channel (RDC).
Figure 4.4 is a block diagram of the read/write circuit.

4.6.1 Read/write preamplifier (PreAMP)

One PreAMP is mounted on the FPC. The PreAMP consists of an read
preamplifier and a write current switch and senses a write error. Each channel is
connected to each data head. The head IC switches the heads by the chip select
signals (*CS) and the head select signals. The IC generates a write error sense

C141-E042-01EN 4-9

Theory of Device Operation

signal (WUS) when a write error occurs due to head short-circuit or head
disconnection.

4.6.2 Write circuit

The write data is output from the hard disk controller (HDC) with the NRZ data
format, and sent to the encoder circuit in the RDC with synchronizing with the
write clock. The NRZ write data is converted from 8-bit data to 9-bit data by the
encoder circuit then sent to the PreAMP, and the data is written onto the media.

(1) 8/9 GCR

The disk drive converts data using the 8/9 (0, 4, 4) group coded recording (GCR)
algorithm. This code format is 0 to 4 code bit “0”s are placed between “1”s.

(2) Write precompensation

Write precompensation compensates, during a write process, for write non­leneartiry generated at reading. Table 4.2 shows the write precompensation
algorithm.

Table 4.2 Write precompensation algorithm

Bit Bit Bit Compensation

n – 1 n n + 1 Bit n

0 1 1 None
1 1 0 Late
1 1 1 Late

Late: Bit n is time shifted (delayed) from its nominal time position towards the

bit n+1 time position.

4-10 C141-E042-01EN

4.6 Read/write Circuit

Figure 4.4 Read/write circuit block diagram

C141-E042-01EN 4-11

Theory of Device Operation

4.6.3 Read circuit

The head read signal from the PreAMP is regulated by the automatic gain control
(AGC) circuit. Then the output is converted into the sampled read data pulse by
the programmable filter circuit and the adaptive equalizer circuit. This clock
signal is converted into the NRZ data by the 8/9 GCR decoder circuit based on the
read data maximum-likelihood-detected by the Viterbi detection circuit, then is
sent to the HDC.

(1) AGC circuit

The AGC circuit automatically regulates the output amplitude to a constant value
even when the input amplitude level fluctuates. The AGC amplifier output is
maintained at a constant level even when the head output fluctuates due to the
head characteristics or outer/inner head positions.

(2) Programmable filter

The programmable filter circuit has a low-pass filter function that eliminates
unnecessary high frequency noise component and a high frequency boost-up
function that equalizes the waveform of the read signal.

-3 dB

Cut-off frequency of the low-pass filter and boost-up gain are controlled from
each DAC circuit in read channel by an instruction of the serial data signal from
MPU (M5). The MPU optimizes the cut-off frequency and boost-up gain
according to the transfer frequency of each zone.

Figure 4.5 shows the frequency characteristic sample of the programmalbe filter.

Figure 4.5 Frequency characteristic of programmable filter

(3) Adaptive equalizer circuit

This circuit is 3-tap sampled analog transversal filter circuit that cosine-equalizes
the head read signal to the partial response class 4 (PR4) waveform.

4-12 C141-E042-01EN

(4) Viterbi detection circuit

The sample hold waveform output from the adaptive equalizer circuit is sent to
the Viterbi detection circuit. The Viterbi detection circuit demodulates data
according to the survivor path sequence.

(5) Data separator circuit

The data separator circuit generates clocks in synchronization with the output of
the adaptive equalizer circuit. To write data, the VFO circuit generates clocks in
synchronization with the clock signals from a synthesizer.

(6) 8/9 GCR decoder

This circuit converts the 9-bit read data into the 8-bit NRZ data.

4.6.4 Time base generator circuit

The drive uses constant density recording to increase total capacity. This is
different from the conventional method of recording data with a fixed data
transfer rate at all data area. In the constant density recording method, data area
is divided into zones by radius and the data transfer rate is set so that the
recording density of the inner cylinder of each zone is nearly constant. The drive
divides data area into 13 zones to set the data transfer rate. Table 4.3 describes
the data transfer rate and recording density (BPI) of each zone.

4.6 Read/write Circuit

Table 4.3 Write clock freqeuncy and recording density (BPI) of each zone

Zone 0 1 2345

Cylinder 0

to

295

Transfer rate
[MB/s]

Zone 6 7 8 9 10 11 12

Cylinder 2606

Transfer rate
[MB/s]

The MPU transfers the data transfer rate setup data (SDATA/SCLK) to the RDC
that includes the time base generator circuit to change the data transfer rate.

8.92 8.92 8.71 8.29 7.88 7.54

to

3137

7.19 6.67 6.44 6.04 5.63 5.29 4.93

296

to

445

3138

to

3888

446

to

809

3889

to

4238

810

to

1455

4239

to

4823

1456

to

2080

4824

to

5400

2081

to

2605

5401

to

5873

5874

6371

to

C141-E042-01EN 4-13

Theory of Device Operation

4.7 Servo Control

The actuator motor and the spindle motor are submitted to servo control. The
actuator motor is controlled for moving and positioning the head to the track
containing the desired data. To turn the disk at a constant velocity, the actuator
motor is controlled according to the servo data that is written on the data side
beforehand.

4.7.1 Servo control circuit

Figure 4.6 is the block diagram of the servo control circuit. The following
describes the functions of the blocks:

Figure 4.6 Block diagram of servo control circuit

(1) Microprocessor unit (MPU)

The MPU includes the AD converter and DSP unit, etc., and the MPU starts the
spindle motor, moves the heads to the reference cylinders, seeks the specified
cylinder, and executes calibration according to the internal operations of the
MPU.

4-14 C141-E042-01EN

4.7 Servo Control

The major internal operations are listed below.

a. Spindle motor start

Starts the spindle motor and accelerates it to normal speed when power is
applied.

b. Move head to reference cylinder

Drives the VCM to position the head at the any cylinder in the data area. The
logical initial cylinder is at the outermost circumference (cylinder 0).

c. Seek to specified cylinder

Drives the VCM to position the head to the specified cylinder.

d. Calibration

Senses and stores the thermal offset between heads and the mechanical forces
on the actuator, and stores the calibration value.

C141-E042-01EN 4-15

Theory of Device Operation

Figure 4.7 Physical sector servo configuration on disk surface

4-16 C141-E042-01EN

(2) Servo burst capture circuit

The servo burst capture circuit reproduces signals (position signals) that indicate
the head position from the servo data on the data surface. SERVO A, SERVO B,
SERVO C and SERVO D burst signals shown in Figure 4.8 followed the servo
mark, cylinder gray and index information are output from the servo area on the
data surface via the data head. The servo signals A/D-converts the amplitudes of
the POSA, POSB, POSC and POSD signals at the peak hold circuit in the servo
burst capture circuit at the timing of the STROB signal. At that time the AGC
circuit is in hold mode. The difference between A/D-converted data is obtained
in the MPU recognizes it as the position information.

(3) A/D converter (ADC)

The A/D converter (ADC) receives the peak-held servo signals, converts them to
digital, and transfers the digital signal to the DSP unit.

(4) D/A converter (DAC)

The D/A converter (DAC) converts the VCM drive current value (digital value)
calculated by the DSP unit into analog values and transfers them to the power
amplifier.

4.7 Servo Control

(5) Power amplifier

The power amplifier feeds currents, corresponding to the DAC output signal
voltage to the VCM.

(6) Spindle motor control circuit

The spindle motor control circuit controls the sensor-less spindle motor. This
circuit detects number of revolution of the motor by the interrupt generated
periodically, compares with the target revolution speed, then flows the current
into the motor coil according to the differentation (abberration).

(7) Driver circuit

The driver circuit is a power amplitude circuit that receives signals from the
spindle motor control circuit and feeds currents to the spindle motor.

(8) VCM current sense resistor (CSR)

This resistor controls current at the power amplifier by converting the VCM
current into voltage and feeding back.

C141-E042-01EN 4-17

Theory of Device Operation

4.7.2 Data-surface servo format

Figure 4.7 describes the physical layout of the servo frame. The three areas
indicated by (1) to (3) in Figure 4.7 are described below.

(1) Inner guard band

The head is in contact with the disk in this space when the spindle starts turning
or stops, and the rotational speed of the spindle can be controlled on this cylinder
area for head moving.

(2) Data area

This area is used as the user data area SA area.

(3) Outer guard band

This area is located at outer position of the user data area, and the rotational speed
of the spindle can be controlled on this cylinder area for head moving.

4.7.3 Servo frame format

As the servo information, the IDD uses the two-phase servo generated from the
gray code and servo A to D. This servo information is used for positioning
operation of radius direction and position detection of circumstance direction.

The servo frame consists of 6 blocks; write/read recovery, servo mark, gray code,
servo A to D, and PAD. Figure 4.8 shows the servo frame format.

5.0 µs0.7

µ

s

4.3 µs

1.7 µs

1.3 µs

1.3 µs

2.5 µs1.3 µs

Figure 4.8 Servo frame format

4-18 C141-E042-01EN

(1) Write/read recovery

This area is used to absorb the write/read transient and to stabilize the AGC.

(2) Servo mark

This area gererates a timing for demodulating the gray code and position­demodulating the servo A to D by detecting the servo mark.

(3) Gray code (including index bit)

This area is used as cylinder address. The data in this area is converted into the
binary data by the gray code demodulation circuit

(4) Servo A, servo B, servo C, servo D

This area is used as position signals between tracks, and the IDD control at on­track so that servo A level equals to servo B level.

(5) PAD

4.7 Servo Control

This area is used as a gap between servo and data.

4.7.4 Actuator motor control

The voice coil motor (VCM) is controlled by feeding back the servo data recorded
on the data surface. The MPU fetches the position sense data on the servo frame
at a constant interval of sampling time, executes calculation, and updates the
VCM drive current.

The servo control of the actuator includes the operation to move the head to the
reference cylinder, the seek operation to move the head to the target cylinder to
read or write data, and the track-following operation to position the head onto the
target track.

(1) Operation to move the head to the reference cylinder

The MPU moves the head to the reference cylinder when the power is turned.
The reference cylinder is in the data area.

When power is applied the heads are moved from the inner circumference shunt
zone to the normal servo data zone in the following sequence:

a) Micro current is fed to the VCM to press the head against the inner

circumference.

b) Micro current is fed to the VCM to move the head toward the outer

circumference.

c) When the servo mark is detected the head is moved slowly toward the outer

circumference at a constant speed.

C141-E042-01EN 4-19

Theory of Device Operation

d) If the head is stopped at the reference cylinder from there. Track following

control starts.

(2) Seek operation

Upon a data read/write request from the host, the MPU confirms the necessity of
access to the disk. If a read/write instruction is issued, the MPU seeks the desired
track.

The MPU feeds the VCM current via the D/A converter and power amplifier to
move the head. The MPU calculates the difference (speed error) between the
specified target position and the current position for each sampling timing during
head moving. The MPU then feeds the VCM drive current by setting the
calculated result into the D/A converter. The calculation is digitally executed by
the firmware. When the head arrives at the target cylinder, the track is followed.

(3) Track following operation

Except during head movement to the reference cylinder and seek operation under
the spindle rotates in steady speed, the MPU does track following control. To
position the head at the center of a track, the DSP drives the VCM by feeding
micro current. For each sampling time, the VCM drive current is determined by
filtering the position difference between the target position and the position
clarified by the detected position sense data. The filtering includes servo
compensation. These are digitally controlled by the firmware.

4.7.5 Spindle motor control

Hall-less three-phase twelve-pole motor is used for the spindle motor, and the 3­phase full/half-wave analog current control circuit is used as the spindle motor
driver (called SVC hereafter). The firmware operates on the MPU manufactured
by Fujitsu. The spindle motor is controlled by sending several signals from the
MPU to the SVC. There are three modes for the spindle control; start mode,
acceleration mode, and stable rotation mode.

(1) Start mode

When power is supplied, the spindle motor is started in the following sequence:

a) After the power is turned on, the MPU sends a signal to the SVC to charge

the charge pump capacitor of the SVC. The charged amount defines the
current that flows in the spindle motor.

b) When the charge pump capacitor is charged enough, the MPU sets the SVC

to the motor start mode. Then, a current (approx. 0.7 A) flows into the
spindle motor.

c) The SVC generates a phase switching signal by itself, and changes the phase

of the current flowed in the motor in the order of (V-phase to U-phase), (W­phase to U-phase), (W-phase to V-phase), (U-phase to V-phase), (U-phase to
W-phase), and (V-phase to W-phase) (after that, repeating this order).

4-20 C141-E042-01EN

d) During phase switching, the spindle motor starts rotating in low speed, and

generates a counter electromotive force. The SVC detects this counter
electromotive force and reports to the MPU using a PHASE signal for speed
detection.

e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a

sepcific period, the MPU resets the SVC and starts from the beginning.
When a PHASE signal is sent, the SVC enters the acceleration mode.

(2) Acceleration mode

In this mode, the MPU stops to send the phase switching signal to the SVC. The
SVC starts a phase switching by itself based on the counter electromotive force.
Then, rotation of the spindle motor accelerates. The MPU calcurates a rotational
speed of the spindle motor based on the PHASE signal from the SVC, and
accelerates till the rotational speed reaches 4,000 rpm. When the rotational speed
reaches 4,000 rpm, the SVC enters the stable rotation mode.

(3) Stable rotation mode

The MPU calcurates a time for one revolution of the spindle motor based on the
PHASE signal from the SVC. The MPU takes a difference between the current
time and a time for one revolution at 4,000 rpm that the MPU already recognized.
Then, the MPU keeps the rotational speed to 4,000 rpm by charging or
discharging the charge pump for the different time. For example, when the actual
rotational speed is 3,800 rpm, the time for one revolution is 15.789 ms. And, the
time for one revolution at 4,000 rpm is 15 ms. Therefore, the MPU discharges the
charge pump for 0.789 ms × k (k: constant value). This makes the flowed current
into the motor lower and the rotational speed down. When the actual rotational
speed is later than 4,000 rpm, the MPU charges the pump the other way. This
control (charging/discharging) is performed every 1 revolution.

4.7 Servo Control

C141-E042-01EN 4-21

CHAPTER 5 Interface

5.1 Physical Interface

5.2 Logical Interface

5.3 Host Commands

5.4 Command Protocol

5.5 Timing

This chapter gives details about the interface, and the interface commands and
timings.

C141-E042-01EN 5-1

Interface

5.1 Physical Interface

5.1.1 Interface signals

Figure 5.1 shows the interface signals.

Figure 5.1 Interface signals

5.1.2 Signal assignment on the connector

Table 5.1 shows the signal assignment on the interface connector.

5-2 C141-E042-01EN

Table 5.1 Signal assignment on the interface connector

Pin No. Signal Pin No. Signal

5.1 Physical Interface

A
C

E
1
3
5
7

9
11
13
15
17
19
21
23
25

ENCSEL
ENCSEL
(KEY)
RESET–
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
GND
DMARQ
IOW–
IOR–

B
D
F

2
4
6

8
10
12
14
16
18
20
22
24
26

GND
MSTR
(KEY)
GND
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
(KEY)
GND
GND

GND
27
29
31
33
35
37
39
41
43

IORDY
DMACK–
INTRQ
DA1
DA0
CS0–
DASP–
+5 VDC
GND

28
30
32
34
36
38
40
42
44

CSEL

GND

IOCS16–

PDIAG

DA2

CS1–

GND

+5 VDC

unused

[signal] [I/O] [Description]

ENCSEL I This s i gn a l is u s ed t o s et m as t er / s la v e us i n g th e C S E L si g n a l ( p in 2 8 ) .

Pins A and C Open: Sets master/slave by the MSTR signal

without using the CSEL signal.

Short: Sets master/slave using the CSEL signal.

The MSTR signal is ignored.

C141-E042-01EN 5-3

Interface

[signal] [I/O] [Description]

MSTR I MSTR, I, Master/slave setting

1: Master 0: Slave

RESET- I Reset signal from the host. This signal is low active and is

asserted for a minimum of 25 ms during power on.

DATA 0-15 I/O Sixteen-bit bi-directional data bus between the host and the

device. These signals are used for data transfer

IOW- I Write strobe signal. The rising edge of this signal gates DATA0

to DATA15 signals or DATA0 to DATA7 signals into a register

or the data port on the device.
[signal] [I/O] [Description]
IOR- I Read strobe signal. The falling edge of this signal enables

DATA0 to DATA15 or DATA0 to DATA7 data from the device

register or data port onto the data bus. The rising edge of this

signal latches the data at the host.
INTRQ O Interrupt signal to the host.

This signal is negated in the following cases:

assertion of RESET- signal

−

Reset by SRST of the Device Control register

−

Write to the command register by the host

−

Read of the status register by the host

−

Completion of sector data transfer

−

(without reading the Status register)

The signal output line has a high impedance when no devices are

selected or interruption is disabled.
IOCS16- O Th i s s ig n a l i n d i ca t e s 1 6 - b it d a t a b u s is a d d r e s s e d in P I O d a t a t r a n sf e r .

This signal is an open collector output.

When IOCS16- is not asserted:

−

8 bit data is transferred through DATA0 to DATA7 signals.
When IOCS16- is asserted:

−

16 bit data is transferred through DATA0 to DATA15 signals.

CS0- I Chip select signal decoded from the host address bus. This signal

is used by the host to select the command block registers.
CS1- I Chip select signal decoded from the host address bus. This signal

is used by the host to select the control block registers.
DA 0-2 I Binary decoded address signals asserted by the host to access task

file registers.
KEY - Key pin for prevention of erroneous connector insertion

5-4 C141-E042-01EN

5.1 Physical Interface

[signal] [I/O] [Description]

PIDAG- I/O This signal is an input mode for the master device and an output

mode for the slave device in a daisy chain configuration. This
signal indicates that the slave device has been completed self
diagnostics.

This signal is pulled up to +5 V through 10 kΩ resistor at each device.

DASP- I/O This is a time-multiplexed signal that indicates that the device is

active and a slave device is present.
This signal is pulled up to +5 V through 10 kΩ resistor at each device.

IORDY O This signal requests the host system to delay the transfer cycle

when the device is not ready to respond to a data transfer request
from the host system.

CSEL I This signal to configure the device as a master or a slave device.

When CSEL signal is grounded,, the IDD is a master device.
When CSEL signal is open,, the IDD is a slave device.
This signal is pulled up with 240 kΩ resistor.

DMACK- I The host system asserts this signal as a response that the host

system receive data or to indicate that data is valid.

DMARQ O This signal is used for DMA transfer between the host system and

the device. The device asserts this signal when the device
completes the preparation of DMA data transfer to the host
system (at reading) or from the host system (at writing).

The direction of data transfer is controlled by the IOR and IOW
signals. This signal hand shakes with the DMACK-signal. In
other words, the device negates the DMARQ signal after the host
system asserts the DMACK signal. When there is other data to be
transferred, the device asserts the DMARQ signal again.

When the DMA data transfer is performed, IOCS16-, CS0- and
CS1- signals are not asserted. The DMA data transfer is a 16-bit

data transfer.
+5 VDC I +5 VDC power supplying to the device.
GND - Grounded

Note:

“I” indicates input signal from the host to the device.

“O” indicates output signal from the device to the host.

“I/O” indicates common output or bi-directional signal between the host
and the device.

C141-E042-01EN 5-5

Interface

5.2 Logical Interface

The device can operate for command execution in either address-specified mode;
cylinder-head-sector (CHS) or Logical block address (LBA) mode. The
IDENTIFY DEVICE information indicates whether the device supports the LBA
mode. When the host system specifies the LBA mode by setting bit 6 in the
Device/Head register to 1, HS3 to HS0 bits of the Device/Head register indicates
the head No. under the LBA mode, and all bits of the Cylinder High, Cylinder
Low, and Sector Number registers are LBA bits.

The sector No. under the LBA mode proceeds in the ascending order with the
start point of LBA0 (defined as follows).

LBA0 = [Cylinder 0, Head 0, Sector 1]

Even if the host system changes the assignment of the CHS mode by the
INITIALIZE DEVICE PARAMETER command, the sector LBA address is not
changed.

LBA = [((Cylinder No.) × (Number of head) + (Head No.)) × (Number of
sector/track)] + (Sector No.) − 1

5.2.1 I/O registers

Communication between the host system and the device is done through input­output (I/O) registers of the device.

These I/O registers can be selected by the coded signals, CS0-, CS1-, and DA0 to
DA2 from the host system. Table 5.2. shows the coding address and the function
of I/O registers.

5-6 C141-E042-01EN

Table 5.2 I/O registers

5.2 Logical Interface

DA0DA1DA2CS1–CS0–

I/O registers

Read operation Write operation

Command block registers

L H L L L Data Data X’1F0’
L H L L H Error Register Features X’1F1’
L H L H L Sector Count Sector Count X’1F2’
L H L H H Sector Number Sector Number X’1F3’
L H H L L Cylinder Low Cylinder Low X’1F4’
L H H L H Cylinder High Cylinder High X’1F5’
L H H H L Device/Head Device/Head X’1F6’
L H H H H Status Command X’1F7’
L L X X X (Invalid) (Invalid) —

Control block registers

H L H H L Alternate Status Device Control X’3F6’
H L H H H — — X’3F7’

Host I/O

address

Notes:

1. The Data register for read or write operation can be accessed by 16 bit data
bus (DATA0 to DATA15).

2. The registers for read or write operation other than the Data registers can be
accessed by 8 bit data bus (DATA0 to DATA7).

3. When reading the Drive Address register, bit 7 is high-impedance state.

4. H indicates signal level High and L indicates signal level Low.

5. The LBA mode is specified, the Device/Head, Cylinder High, Cylinder
Low, and Sector Number registers indicate LBA bits 27 to 24, 23 to 16, 15
to 8, and 7 to 0.

C141-E042-01EN 5-7

Interface

5.2.2 Command block registers

(1) Data register (X’1F0’)

The Data register is a 16-bit register for data block transfer between the device
and the host system. Data transfer mode is PIO or LBA mode.

(2) Error register (X’1F1’)

The Error register indicates the status of the command executed by the device.
The contents of this register are valid when the ERR bit of the Status register is 1.

This register contains a diagnostic code after power is turned on, a reset , or the
EXECUTIVE DEVICE DIAGNOSTIC command is executed.

[Status at the completion of command execution other than diagnostic command]

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ICRC UNC X IDNF X ABRT TK0NF X

X: Unused

- Bit 7: Interface CRC Error (ICRC). This bit indicates that a CRC error
occurred during Ultra DMA transfer.

- Bit 6: Uncorrectable Data Error (UNC). This bit indicates that an
uncorrectable data error has been encountered.

- Bit 5: Unused

- Bit 4: ID Not Found (IDNF). This bit indicates an error except for bad
sector, uncorrectable error and SB not found.

- Bit 3: Unused

- Bit 2: Aborted Command (ABRT). This bit indicates that the requested
command was aborted due to a device status error (e.g. Not Ready,
Write Fault) or the command code was invalid.

- Bit 1: Track 0 Not Found (TK0NF). This bit indicates that track 0 was not
found during RECALIBRATE command execution.

- Bit 0: Address Mark Not Found (AMNF). This bit indicates that the SB Not
Found error occurred.

5-8 C141-E042-01EN

[Diagnostic code]

X’01’: No Error Detected.
X’02’: HDC Register Compare Error
X’03’: Data Buffer Compare Error.
X’05’: ROM Sum Check Error.
X’80’: Device 1 (slave device) Failed.

Error register of the master device is valid under two devices (master
and slave) configuration. If the slave device fails, the master device
posts X’80’ OR (the diagnostic code) with its own status (X’01’ to
X’05’).

However, when the host system selects the slave device, the diagnostic
code of the slave device is posted.

(3) Features register (X’1F1’)

5.2 Logical Interface

The Features register provides specific feature to a command. For instance, it is
used with SET FEATURES command to enable or disable caching.

(4) Sector Count register (X’1F2’)

The Sector Count register indicates the number of sectors of data to be transferred
in a read or write operation between the host system and the device. When the
value in this register is X’00’, the sector count is 256.

When this register indicates X’00’ at the completion of the command execution,
this indicates that the command is completed succefully. If the command is not
completed scuccessfully, this register indicates the number of sectors to be
transferred to complete the request from the host system. That is, this register
indicates the number of remaining sectors that the data has not been transferred
due to the error.

The contents of this register has other definition for the following commands;
INITIALIZE DEVICE PARAMETERS, SET FEATURES, IDLE, STANDBY
and SET MULTIPLE MODE.

(5) Sector Number register (X’1F3’)

The contents of this register indicates the starting sector number for the
subsequent command. The sector number should be between X’01’ and [the
number of sectors per track defined by INITIALIZE DEVICE PARAMETERS
command.

Under the LBA mode, this register indicates LBA bits 7 to 0.

C141-E042-01EN 5-9

Interface

(6) Cylinder Low register (X’1F4’)

The contents of this register indicates low-order 8 bits of the starting cylinder
address for any disk-access.

At the end of a command, the contents of this register are updated to the current
cylinder number.

Under the LBA mode, this register indcates LBA bits 15 to 8.

(7) Cylinder High register (X’1F5’)

The contents of this register indicates high-order 8 bits of the disk-access start
cylinder address.

At the end of a command, the contents of this register are updated to the current
cylinder number. The high-order 8 bits of the cylinder address are set to the
Cylinder High register.

Under the LBA mode, this register indicates LBA bits 23 to 16.

(8) Device/Head register (X’1F6’)

The contents of this register indicate the device and the head number.

When executing INITIALIZE DEVICE PARAMETERS command, the contents
of this register defines “the number of heads minus 1”.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

X L X DEV HS3 HS2 HS1 HS0

- Bit 7: Unused

- Bit 6: L. 0 for CHS mode and 1 for LBA mode.

- Bit 5: Unused

- Bit 4: DEV bit. 0 for the master device and 1 for the slave device.

- Bit 3: HS3 CHS mode head address 3 (2

- Bit 2: HS2 CHS mode head address 3 (2

- Bit 1: HS1 CHS mode head address 1 (2

- Bit 0: HS0 CHS mode head address 3 (2

3

). LBA bit 27.

2

). LBA bit 26.

1

). LBA bit 25.

0

). LBA bit 24.

5-10 C141-E042-01EN

(9) Status register (X’1F7’)

The contents of this register indicate the status of the device. The contents of this
register are updated at the completion of each command. When the BSY bit is
cleared, other bits in this register should be validated within 400 ns. When the
BSY bit is 1, other bits of this register are invalid. When the host system reads
this register while an interrupt is pending, it is considered to be the Interrupt
Acknowledge (the host system acknowledges the interrupt). Any pending
interrupt is cleared (negating INTRQ signal) whenever this register is read.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BSY DRDY DF DSC DRQ CORR 0 ERR

- Bit 7: Busy (BSY) bit. This bit is set whenever the Command register is

5.2 Logical Interface

accessed. Then this bit is cleared when the command is completed.
However, even if a command is being executed, this bit is 0 while data
transfer is being requested (DRQ bit = 1).When BSY bit is 1, the host
system should not write the command block registers. If the host
system reads any command block register when BSY bit is 1, the
contents of the Status register are posted. This bit is set by the device
under following conditions:

(a) Within 400 ns after RESET- is negated or SRST is set in the

Device Control register, the BSY bit is set. the BSY bit is cleared,
when the reset process is completed.

The BSY bit is set for no longer than 15 seconds after the IDD
accepts reset.

(b) Within 400 ns from the host system starts writing to the

Command register.

(c) Within 5 µs following transfer of 512 bytes data during execution

of the READ SECTOR(S), WRITE SECTOR(S), or WRITE
BUFFER command.

Within 5 µs following transfer of 512 bytes of data and the
appropriate number of ECC bytes during execution of READ
LONG or WRITE LONG command.

- Bit 6: Device Ready (DRDY) bit. This bit indicates that the device is
capable to respond to a command.

The IDD checks its status when it receives a command. If an error is
detected (not ready state), the IDD clears this bit to 0. This is cleared
to 0 at power-on and it is cleared until the rotational speed of the
spindle motor reaches the steady speed.

C141-E042-01EN 5-11

Interface

- Bit 5: The Device Write Fault (DF) bit. This bit indicates that a device fault
(write fault) condition has been detected.

If a write fault is detected during command execution, this bit is
latched and retained until the device accepts the next command or
reset.

- Bit 4: Device Seek Complete (DSC) bit. This bit indicates that the device
heads are positioned over a track.

In the IDD, this bit is always set to 1 after the spin-up control is
completed.

- Bit 3: Data Request (DRQ) bit. This bit indicates that the device is ready to
transfer data of word unit or byte unit between the host system and the
device.

- Bit 2: Corrected Data (CORR) bit. This bit indicates that a correctable data
error was encountered and the error has been corrected. This condition
does not halt the data transfer.

- Bit 1: Always 0.

- Bit 0: Error (ERR) bit. This bit indicates that an error was detected while the
previous command was being executed. The Error register indicates
the additional information of the cause for the error.

(10) Command register (X’1F7’)

The Command register contains a command code being sent to the device. After
this register is written, the command execution starts immediately.

Table 5.3 lists the executable commands and their command codes. This table
also lists the neccesary parameters for each command which are written to certain
registers before the Command register is written.

5-12 C141-E042-01EN

5.2.3 Control block registers

(1) Alternate Status register (X’3F6’)

The Alternate Status register contains the same information as the Status register
of the command block register.

The only difference from the Status register is that a read of this register does not
imply Interrupt Acknowledge and INTRQ signal is not reset.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BSY DRDY DF DSC DRQ CORR 0 ERR

(2) Device Control register (X’3F6’)

The Device Control register contains device interrupt and software reset.

5.3 Host Commands

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

XXXXXSRST nIEN 0

- Bit 2: SRST is the host software reset bit. When this bit is set, the device is
held reset state. When two device are daisy chained on the interface,
setting this bit resets both device simultaneously.

The slave device is not required to execute the DASP- handshake.

- Bit 1: nIEN bit enables an interrupt (INTRQ signal) from the device to the
host. When this bit is 0 and the device is selected, an interruption
(INTRQ signal) can be enabled through a tri-state buffer. When this
bit is 1 or the device is not selected, the INTRQ signal is in the high­impedance state.

5.3 Host Commands

The host system issues a command to the device by writing necessary parameters
in related registers in the command block and writing a command code in the
Command register.

The device can accept the command when the BSY bit is 0 (the device is not in
the busy status).

The host system can halt the uncompleted command execution only at execution
of hardware or software reset.

C141-E042-01EN 5-13

Interface

When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the data
transfer) and the host system writes to the command register, the correct device
operation is not guaranteed.

5.3.1 Command code and parameters

Table 5.3 lists the supported commands, command code and the registers that
needed parameters are written.

Table 5.3 Command code and parameters (1 of 2)

Command name

76543210FRSCSNCYDH

READ SECTOR(S) 0 0 1 0 0 0 0 R N Y Y Y Y
READ MULTIPLE 1 1 0 0 0 1 0 0 N Y Y Y Y
READ DMA 1 1 0 0 1 0 0 R N Y Y Y Y
READ VERIFY SECTOR(S) 0 1 0 0 0 0 0 R N Y Y Y Y
WRITE MULTIPLE 1 1 0 0 0 1 0 1 N Y Y Y Y
WRITE DMA 1 1 0 0 1 0 1 R N Y Y Y Y
WRITE VERIFY 0 0 1 1 1 1 0 0 N Y Y Y Y
WRITE SECTOR(S) 0 0 1 1 0 0 0 R N Y Y Y Y
RECALIBRATE 0 0 0 1 X X X X N N N N D
SEEK 0 1 1 1 X X X X N N Y Y Y
INITIALIZE DEVICE

PARAMETERS
IDENTIFY DEVICE 1 1 1 0 1 1 0 0 N N N N D

10010001NYNNY

Command code (Bit) Parameters used

IDENTIFY DEVICE DMA 1 1 1 0 1 1 0 0 N N N N D
SET FEATURES 1 1 1 0 1 1 1 1 Y N* N N D
SET MULTIPLE MODE 1 1 0 0 0 1 1 0 N Y N N D
EXECUTE DEVICE DIAGNOSTIC 1 0 0 1 0 0 0 0 N N N N D*
READ LONG 0 0 1 0 0 0 1 R N Y Y Y Y
WRITE LONG 0 0 1 1 0 0 1 R N Y Y Y Y
READ BUFFER 1 1 1 0 0 1 0 0 N N N N D
WRITE BUFFER 1 1 1 0 1 0 0 0 N N N N D
IDLE 1101011000101111NYNND

5-14 C141-E042-01EN

5.3 Host Commands

Table 5.3 Command code and parameters (2 of 2)

Command code (Bit) Parameters used

Command name

76543210FRSCSNCYDH

IDLE IMMEDIATE 1101011000100011NNNND

STANDBY 1101011000101100NYNND

STANDBY IMMEDIATE 1101011000100000NNNND

SLEEP 1101011010010110NNNND

CHECK POWER MODE 1101011010010001NNNND

SMART 1 0 1 1 0 0 0 0 Y Y Y Y D
SECURITY DISABLE PASSWORD 1 1 1 1 0 1 1 0 N N N N D
SECURITY ERASE PREPARE 1 1 1 1 0 0 1 1 N N N N D
SECURITY ERASE UNIT 1 1 1 1 0 1 0 0 N N N N D
SECURITY FREEZE LOCK 1 1 1 1 0 1 0 1 N N N N D
SECURITY SET PASSWORD 1 1 1 1 0 0 0 1 N N N N D
SECURITY UNLOCK 1 1 1 1 0 0 1 0 N N N N D

Notes:

FR: Features Register

CY: Cylinder Registers

SC: Sector Count Register

DH: Drive/Head Register

SN: Sector Number Register

R: Retry at error

1 = Without retry

0 = with retry

Y: Necessary to set parameters

C141-E042-01EN 5-15

Interface

Y*: Necessary to set parameters under the LBA mode.

N: Not necessary to set parameters (The parameter is ignored if it is set.)

N*: May set parameters

D: The device parameter is valid, and the head parameter is ignored.

D*: The command is addressed to the master device, but both the master device

and the slave device execute it.

X: Do not care

5.3.2 Command descriptions

The contents of the I/O registers to be necessary for issuing a command and the
example indication of the I/O registers at command conpletion are shown as
following in this subsection.

Example: READ SECTOR(S) WITH RETRY

At command issuance (I/O registers setting contents)

Bit 76543210

1F7H(CM) 00100000
1F6H(DH)

1F5H(CH) Start cylinder address [MSB] / LBA
1F4H(CL) Start cylinder address [LSB] / LBA
1F3H(SN) Start sector No. / LBA [LSB]

1F2H(SC) Transfer sector count
1F1H(FR) xx

At command completion (I/O registers contents to be read)

Bit 76543210

1F7H(ST) Error information

1F6H(DH)

L

×

L

×

DV Head No. / LBA [MSB]

×

DV Head No. / LBA [MSB]

×

1F5H(CH) End cylinder address [MSB] / LBA
1F4H(CL) End cylinder address [LSB] / LBA
1F3H(SN) End sector No. / LBA [LSB]

1F2H(SC) X’00’

1F1H(ER) Error information

5-16 C141-E042-01EN

5.3 Host Commands

CM: Command register FR: Features register

DH: Device/Head register ST: Status register

CH: Cylinder High register ER: Error register

CL: Cylinder Low register L: LBA (logical block address) setting bit

SN: Sector Number register DV: Device address. bit

SC: Sector Count register x, xx: Do not care (no necessary to set)

Note:

1. When the L bit is specified to 1, the lower 4 bits of the DH register and all
bits of the CH, CL and SN registers indicate the LBA bits (bits of the DH
register are the MSB (most significant bit) and bits of the SN register are
the LSB (least significant bit).

2. At error occurrance, the SC register indicates the remaining sector count of data
transfer.

3. In the table indicating I/O registers contents in this subsection, bit indication is
omitted.

(1) READ SECTOR(S) (X’20’ or X’21’)

This command reads data of sectors specified in the Sector Count register from
the address specified in the Device/Head, Cylinder High, Cylinder Low and
Sector Number registers. Number of sectors can be specified to 256 sectors in
maximum. To specify 256 sectors reading, ‘00’ is specified. For the DRQ,
INTRQ, and BSY protocols related to data transfer, see Subsection 5.4.1.

If the head is not on the track specified by the host, the device performs a implied
seek. After the head reaches to the specified track, the device reads the target
sector.

When the command is specified without retry (R bit = 1), the device reports an ID
NOT FOUND error if the device attempts to read the target sector up to 8 times.

When the command is specified with retry (R bit = 0), the device attempts to read
the target sector up to 126 times.

The DRQ bit of the Status register is always set prior to the data transfer
regardless of an error condition.

Upon the completion of the command execution, command block registers
contain the cylinder, head, and sector addresses (in the CHS mode) or logical
block address (in the LBA mode) of the last sector read.

If an error occurs in a sector, the read operation is terminated at the sector where the
error occured.

C141-E042-01EN 5-17

Interface

Command block registers contain the cylinder, the head, and the sector addresses
of the sector (in the CHS mode) or the logical block address (in the LBA mode)
where the error occurred, and remaining number of sectors of which data was not
transferred.

At command issuance (I/O registers setting contents)

1F7H(CM) 0010000R
1F6H(DH)

1F5H(CH)
1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(FR)

H

×

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

R = 0 →with Retry
R = 1 →without Retry

At command completion (I/O registers contents to be read)

1F7H(ST) Status information

1F6H(DH)

1F5H(CH)

×

End cylinder No. [MSB] / LBA

L

DV Start head No. /LBA

×

[MSB]

L

DV End head No. /LBA

×

[MSB]

1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(ER)

H

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

(2) READ MULTIPLE (X’C4’)

This command operates similarly to the READ SECTOR(S) command. The
device does not generate an interrupt (assertion of the INTRQ signal) on each
every sector. An interrupt is generateed after the transfer of a block of sectors for
which the number is specified by the SET MULTIPLE MODE command.

End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information

5-18 C141-E042-01EN

5.3 Host Commands

The implementation of the READ MULTIPLE command is identical to that of the
READ SECTOR(S) command except that the number of sectors is specified by
the SET MULTIPLE MODE command are transferred without intervening
interrupts. In the READ MULTIPLE command operation, the DRQ bit of the
Status register is set only at the start of the data block, and is not set on each
sector.

The number of sectors (block count) to be transferred without interruption is
specifed by the SET MULTIPLE MODE command. The SET MULTIPLE
MODE command should be executed prior to the READ MULTIPLE command.

When the READ MULTIPLE command is issued, the Sector Count register
contains the number of sectors requested (not a number of the block count or a
number of sectors in a block).

Upon receipt of this command, the device executes this command even if the
value of the Sector Count register is less than the defined block count (the value
of the Sector Count should not be 0).

If the number of requested sectors is not divided evenly (having the same number
of sectors [block count]), as many full blocks as possible are transferred, then a
final partial block is transferred. The number of sectors in the partial block to be
transferred is n where n = remainder of (“number of sectors”/”block count”).

If the READ MULTIPLE command is issued before the SET MULTIPLE MODE
command is executed or when the READ MULTIPLE command is disabled, the
device rejects the READ MULTIPLE command with an ABORTED COMMAND
error.

If an error occurs, reading sector is stopped at the sector where the error occurred.
Command block registers contain the cylinder, the head, the sector addresses (in
the CHS mode) or the logical block address (in the LBA mode) of the sector
where the error occurred, and remaining number of sectors that had not
transferred after the sector where the error occurred.

An interrupt is generated when the DRQ bit is set at the beginning of each block or a
partial block.

Figure 5.2 shows an example of the execution of the READ MULTIPLE
command.

Block count specified by SET MULTIPLE MODE command = 4 (number of

•

sectors in a block)
READ MULTIPLE command specifies;

•

Number of requested sectors = 9 (Sector Count register = 9)

↓

Number of sectors in incomplete block = remainder of 9/4 =1

C141-E042-01EN 5-19

Interface

Figure 5.2 Execution example of READ MULTIPLE command

At command issuance (I/O registers setting contents)

1F7H(CM) 11000100
1F6H(DH)

L

×

DV Start head No. /LBA

×

[MSB]
1F5H(CH)
1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(FR)

H

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

At command completion (I/O registers contents to be read)

1F7H(ST) Status information

1F6H(DH)

L

×

DV End head No. /LBA

×

[MSB]
1F5H(CH)
1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(ER)

H

End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]

(*1)

00
Error information

*1 If the command is terminated due to an error, the remaining number of

sectors for which data was not transferred is set in this register.

5-20 C141-E042-01EN

(3) READ DMA (X’C8’ or X’C9’)

This command operates similarly to the READ SECTOR(S) command except for
following events.

The data transfer starts at the timing of DMARQ signal assertion.

•

The device controls the assertion or negation timing of the DMARQ signal.

•

The device posts a status as the result of command execution only once at

•

completion of the data transfer.

When an error, such as an unrecoverable medium error, that the command
execution cannot be continued is detected, the data transfer is stopped without
transferring data of sectors after the erred sector. The device generates an
interrupt using the INTRQ signal and posts a status to the host system. The
format of the error information is the same as the READ SECTOR(S) command.

In LBA mode

The logical block address is specified using the start head No., start cylinder No.,
and first sector No. fields. At command completion, the logical block address of
the last sector and remaining number of sectors of which data was not transferred,
like in the CHS mode, are set.

5.3 Host Commands

The host system can select the DMA transfer mode by using the SET FEATURES
command.

1) Single word DMA transfer mode 0 to 2

2) Multiword DMA transfer mode 0 to 2

At command issuance (I/O registers setting contents)

1F7H(CM) 1100100R

1F6H(DH)

L

×

DV Start head No. /LBA

×

[MSB]

1F5H(CH)

1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(FR)

H

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

R = 0 → with Retry
R = 1 → without Retry

C141-E042-01EN 5-21

Interface

At command completion (I/O registers contents to be read)

1F7H(ST) Status information

1F6H(DH)

1F5H(CH)
1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(ER)

H

L

×

End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

(4) READ VERIFY SECTOR(S) (X’40’ or X’41’)

This command operates similarly to the READ SECTOR(S) command except that
the data is not transferred to the host system.

After all requested sectors are verified, the device clears the BSY bit of the Status
register and generates an interrupt. Upon the completion of the command
execution, the command block registers contain the cylinder, head, and sector
number of the last sector verified.

×

DV End head No. /LBA

[MSB]

If an error occurs, the verify operation is terminated at the sector where the error
occurred. The command block registers contain the cylinder, the head, and the
sector addresses (in the CHS mode) or the logical block address (in the LBA
mode) of the sector where the error occurred. The Sector Count register indicates
the number of sectors that have not been verified.

If a correctable error is found, the device sets the CORR bit of the Status register
to 1 after the command is completed (before the device generates an interrupt).

5-22 C141-E042-01EN

5.3 Host Commands

At command issuance (I/O registers setting contents)

1F7H(CM) 0100000R

1F6H(DH)

1F5H(CH)

1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(FR)

H

×

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

R = 0 →with Retry
R = 1 →without Retry

At command completion (I/O registers contents to be read)

1F7H(ST) Status information

1F6H(DH)

1F5H(CH)

×

End cylinder No. [MSB] / LBA

L

DV Start head No. /LBA

×

[MSB]

L

DV End head No. /LBA

×

[MSB]

1F4
1F3
1F2
1F1

(CL)

H

(SN)

H

(SC)

H

(ER)

H

End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

(5) WRITE SECTOR(S) (X’30’ or X’31’)

This command writes data of sectors from the address specified in the
Device/Head, Cylinder High, Cylinder Low, and Sector Number registers to the
address specified in the Sector Count register. Number of sectors can be specified
to 256 sectors in maximum. Data transfer begins at the sector specified in the
Sector Number register. For the DRQ, INTRQ, and BSY protocols related to data
transfer, see Subsection 5.4.2.

If the head is not on the track specified by the host, the device performs a implied
seek. After the head reaches to the the specified track, the device writes the target
sector.

If the command is specified with retry, the device attempts to retry up to 31 times.

C141-E042-01EN 5-23

Interface

The data stored in the buffer, and CRC code and ECC bytes are written to the data
field of the corresponding sector(s). Upon the completion of the command
execution, the command block registers contain the cylinder, head, and sector
addresses of the last sector written.

If an error occurs during multiple sector write operation, the write operation is
terminated at the sector where the error occured. Command block registers
contain the cylinder, the head, the sector addresses (in the CHS mode) or the
logical block address (in the LBA mode) of the sector where the error occurred.
Then the host can read the command block registers to determine what error has
occurred and on which sector the error has occurred.

At command issuance (I/O registers setting contents)

1F7H(CM) 0011000R
1F6H(DH)

1F5H(CH)
1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(FR)

H

×

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

R = 0 →with Retry
R = 1 →without Retry

At command completion (I/O registers contents to be read)

1F7H(ST) Status information

1F6H(DH)

1F5H(CH)
1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(ER)

H

×

End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information

L

DV Start head No. /LBA

×

[MSB]

L

DV End head No. /LBA

×

[MSB]

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

5-24 C141-E042-01EN

(6) WRITE MULTIPLE (X’C5’)

This command is similar to the WRITE SECTOR(S) command. The device does
not generate interrupts (assertion of the INTRQ) signal) on each sector but on the
transfer of a block which contains the number of sectors for which the number is
defined by the SET MULTIPLE MODE command.

The implementation of the WRITE MULTIPLE command is identical to that of
the WRITE SECTOR(S) command except that the number of sectors is specified
by the SET MULTIPLE MODE command are transferred without intervening
interrupts. In the WRITE MULTIPLE command operation, the DRQ bit of the
Status register is required to set only at the start of the data block, not on each
sector.

The number of sectors (block count) to be transferred without interruption is
specifed by the SET MULTIPLE MODE command. The SET MULTIPLE
MODE command should be executed prior to the WRITE MULTIPLE command.

When the WRITE MULTIPLE command is issued, the Sector Count register contains
the number of sectors requested (not a number of the block count or a number of
sectors in a block).

5.3 Host Commands

Upon receipt of this command, the device executes this command even if the
value of the Sector Count register is less than the defined block count the value of
the Sector Count should not be 0).

If the number of requested sectors is not divided evenly (having the same number
of sectors [block count]), as many full blocks as possible are transferred, then a
final partial block is transferred. The number of sectors in the partial block to be
transferred is n where n = remainder of (“number of sectors”/”block count”).

If the WRITE MULTIPLE command is issued before the SET MULTIPLE
MODE command is executed or when WRITE MULTIPLE command is disabled,
the device rejects the WRITE MULTIPLE command with an ABORTED
COMMAND error.

Disk errors encountered during execution of the WRITE MULTIPLE command are
posted after attempting to write the block or the partial block that was transferred.
Write operation ends at the sector where the error was encountered even if the sector is
in the middle of a block. If an error occurs, the subsequent block shall not be
transferred. Interrupts are generated when the DRQ bit of the Status register is set at
the beginning of each block or partial block.

The contents of the command block registers related to addresses after the transfer
of a data block containing an erred sector are undefined. To obtain a valid error
information, the host should retry data transfer as an individual request.

C141-E042-01EN 5-25

Interface

At command issuance (I/O registers setting contents)

1F7H(CM) 11000101
1F6H(DH)

L

×

DV Start head No. /LBA

×

[MSB]
1F5H(CH)
1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(FR)

H

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

At command completion (I/O registers contents to be read)

1F7H(ST) Status information

1F6H(DH)

L

×

DV End head No. /LBA

×

[MSB]
1F5H(CH)
1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(ER)

H

End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00

H

Error information

(7) WRITE DMA (X’CA’ or X’CB’)

This command operates similarly to the WRITE SECTOR(S) command except
for following events.

The data transfer starts at the timing of DMARQ signal assertion.

•

The device controls the assertion or negation timing of the DMARQ signal.

•

The device posts a status as the result of command execution only once at

•

completion of the data transfer or completion of processing in the device.
The device posts a status as the result of command execution only once at

•

completion of the data transfer.

When an error, such as an unrecoverable medium error, that the command
execution cannot be continued is detected, the data transfer is stopped without
transferring data of sectors after the erred sector. The device generates an
interrupt using the INTRQ signal and posts a status to the host system. The
format of the error information is the same as the WRITE SECTOR(S) command.

5-26 C141-E042-01EN

5.3 Host Commands

A host system can select the following transfer mode using the SET FEATURES
command.

1) Single word DMA transfer mode 0 to 2

2) Multiword DMA transfer mode 0 to 2

At command issuance (I/O registers setting contents)

1F7H(CM) 1100101R

1F6H(DH)

1F5H(CH)

1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(FR)

H

×

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

R = 0 →with Retry
R = 1 →without Retry

At command completion (I/O registers contents to be read)

1F7H(ST) Status information

1F6H(DH)

1F5H(CH)

×

End cylinder No. [MSB] / LBA

L

DV Start head No. /LBA

×

[MSB]

L

DV End head No. /LBA

×

[MSB]

1F4
1F3
1F2
1F1

(CL)

H

(SN)

H

(SC)

H

(ER)

H

End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

(8) WRITE VERIFY (X’3C’)

This command operates similarly to the WRITE SECTOR(S) command except
that the device verifies each sector immediately after being written. The verify
operation is a read and check for data errors without data transfer. Any error that
is detected during the verify operation is posted.

C141-E042-01EN 5-27

Interface

After all sectors are verified, the last interruption (INTRQ for command
termination) is generated.

At command issuance (I/O registers setting contents)

1F7H(CM) 00111100
1F6H(DH)

L

×

DV Start head No. /LBA

×

[MSB]
1F5H(CH)
1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(FR)

H

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

At command completion (I/O registers contents to be read)

1F7H(ST) Status information

1F6H(DH)

L

×

DV End head No. /LBA

×

[MSB]
1F5H(CH)
1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(ER)

H

End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

(9) RECALIBRATE (X’1x’, x: X’0’ to X’F’)

This command performs the calibration. Upon receipt of this command, the
device sets BSY bit of the Status register and performs a calibration. When the
device completes the calibration, the device updates the Status register, clears the
BSY bit, and generates an interrupt.

This command can be issued in the LBA mode.

5-28 C141-E042-01EN

5.3 Host Commands

At command issuance (I/O registers setting contents)

1F7H(CM) 0001xxxx

1F6H(DH)
1F5H(CH)

1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(FR)

H

×××

xx
xx
xx
xx
xx

DV xx

At command completion (I/O registers contents to be read)

1F7H(ST) Status information
1F6H(DH)
1F5H(CH)

1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(ER)

H

×××

xx
xx
xx
xx
Error information

DV xx

Note:

Also executable in LBA mode.

(10) SEEK (X’7x’, x : X’0’ to X’F’)

This command performs a seek operation to the track and selects the head
specified in the command block registers. After completing the seek operation,
the device clears the BSY bit in the Status register and generates an interrupt.

The IDD always sets the DSC bit (Drive Seek Complete status) of the Status
register to 1.

In the LBA mode, this command performs the seek operation to the cylinder and
head position in which the sector is specified with the logical block address.

C141-E042-01EN 5-29

Interface

At command issuance (I/O registers setting contents)

1F7H(CM) 0111xxxx
1F6H(DH)

1F5H(CH)
1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(FR)

H

Cylinder No. [MSB] / LBA
Cylinder No. [LSB] / LBA
Sector No. / LBA [LSB]
xx
xx

L

×

DV Head No. /LBA [MSB]

×

At command completion (I/O registers contents to be read)

1F7H(ST) Status information

1F6H(DH)

1F5H(CH)
1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(ER)

H

Cylinder No. [MSB] / LBA
Cylinder No. [LSB] / LBA
Sector No. / LBA [LSB]
xx
Error information

L

×

DV Head No. /LBA [MSB]

×

(11) INITIALIZE DEVICE PARAMETERS (X’91’)

The host system can set the number of sectors per track and the maximum head
number (maximum head number is “number of heads minus 1”) per cylinder with
this command. Upon receipt of this command, the device sets the BSY bit of
Status register and saves the parameters. Then the device clears the BSY bit and
generates an interrupt.

When the SC register is specified to X’00’, an ABORTED COMMAND error is
posted. Other than X’00’ is specified, this command terminates normally.

The parameters set by this command are retained even after reset or power save
operation regardless of the setting of disabling the reverting to default setting.

In LBA mode

The device ignores the L bit specification and operates with the CHS mode
specification. An accessible area of this command within head moving in the LBA
mode is always within a default area. It is recommended that the host system refers
the addressable user sectors (total number of sectors) in word 60 to 61 of the parameter
information by the IDENTIFY DEVICE command.

5-30 C141-E042-01EN

5.3 Host Commands

At command issuance (I/O registers setting contents)

1F7H(CM) 10010001

1F6H(DH)
1F5H(CH)

1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(FR)

H

×××

xx
xx
xx
Number of sectors/track
xx

DV Max. head No.

At command completion (I/O registers contents to be read)

1F7H(ST) Status information
1F6H(DH)
1F5H(CH)

1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(ER)

H

×××

xx
xx
xx
Number of sectors/track
Error infomation

DV Max. head No.

(12) IDENTIFY DEVICE (X’EC’)

The host system issues the IDENTIFY DEVICE command to read parameter
information (512 bytes) from the device. Upon receipt of this command, the drive
sets the BSY bit of Status register and sets required parameter information in the
sector buffer. The device then sets the DRQ bit of the Status register, and
generates an interrupt. After that, the host system reads the information out of the
sector buffer. Table 5.4 shows the arrangements and values of the parameter
words and the meaning in the buffer.

C141-E042-01EN 5-31

Interface

At command issuance (I/O registers setting contents)

1F7H(CM) 11101100
1F6H(DH)

1F5H(CH)
1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(FR)

H

×××

xx
xx
xx
xx
xx

DV xx

At command completion (I/O registers contents to be read)

1F7H(ST) Status information

1F6H(DH)

1F5H(CH)
1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(ER)

H

×××

xx
xx
xx
xx
Error information

DV xx

Table 5.4 Information to be read by IDENTIFY DEVICE command (1 of 3)

Word Value Description

0 X’0c5a’ General Configuration *1
1 X’1068’

X’189C’

Number of cylinders MHA2021AT: X’1068’

MHA2032AT: X’189C’
2 X’0000’ Reserved
3 X’0010’ Number of Heads
4 X’0000’ Undefined
5 X’0000’ Undefined
6 X’003F’ Number of sectors per track

7-9 X’000000000000’ Undefined

10-19 Set by a device Serial number (ASCII code) *2

20 X’0000’ Undefined

5-32 C141-E042-01EN

5.3 Host Commands

Word Value Description

21 X’0000’ Undefined
22 X’0004’ Number of ECC bytes transferred at READ LONG or

WRITE LONG command
23-26 – Firmware revision (ASCII code) *3
27-46 – Model name (ASCII code) *4

47 X’8020’ Maximum number of sectors per interrupt on

READ/WRITE MULTIPLE command

48 X’0000’ Reserved
49 X’0B00’ Capabilities *5
50 X’0000’ Reserved
51 X’0200’ PIO data transfer mode *6
52 X’0000’ Reserved
53 X’0003’ Enable/disable setting of words 54-58 and 64-70, 88 *7
54 (Variable) Number of current Cylinders
55 (Variable) Number of current Head
56 (Variable) Number of current sectors per track

57-58 (Variable) Total number of current sectors

59 *8 Transfer sector count currently set by READ/WRITE

MULTIPLE command *8
60-61 X’00409980’

X’0060E640’

Total number of user addressable sectors (LBA mode only)

MHA2021AT: X’00409980’

MHA2032AT: X’0060E640’
62 X’0000’ Reserved
63 X’xx07’ Multiword DMA transfer mode *9
64 X’0003’ Advance PIO transfer mode support status *10
65 X’0078’ Minimum multiword DMA transfer cycle time per word :

120 [ns]

66 X’0078’ Manufacturer’s recommended DMA transfer cycle time :

120 [ns]

67 X’00F0’ Minimum PIO transfer cycle time without IORDY flow

control : 240 [ns]

68 X’0078’ Minimum PIO transfer cycle time with IORDY flow control

: 120 [ns]

69-79 X’00’ Reserved

80 X’000E’ Major version number *11

C141-E042-01EN 5-33

Interface

Word Value Description

81 X’0000’ Minor version number (not reported)
82 X’000B’ Support of command sets *12
83 X’4000’ Support of command sets (fixed)

84-87 X’00’ Reserved

88 X’0000’ Ultra DMA transfer mode *13

89-127 X’00’ Reserved

128 (Variable) Security status *13
129-159 X’00’ Undefined
160-255 X’00’ Reserved

Table 5.4 Information to be read by IDENTIFY DEVICE COMMAND (2 of 3)

*1 Word 0: General configuration 0

Bit 15: ATA device = 0, ATAPI device = 1 0
Bit 14-12: Undefined 0
Bit 11: Rotational speed tolerance is more than 0.5 %. 1
Bit 10: Disk-data transfer rate 10 Mbps. 1
Bit 9: Disk-data transfer rate is faster than 5 Mbps

but 10 Mbps or slower 0
Bit 8: Disk-data transfer rate is 5 Mbps or slower. 0
Bit 7: Removable disk drive 0
Bit 6: Fixed drive. 1
Bit 5: Spindle motor control option implemented. 0
Bit 4: Head switching time is more than 15 microseconds. 1
Bit 3: Not MFM encoded. 1
Bit 2: Soft sectored. 0
Bit 1: Hard sectored. 1
Bit 0: Reserved 0

*2 Word 10-19: Serial number; ASCII code (20 characters, right-justified)
*3 Word 23-26: Firmware revision; ASCII code (8 characters, Left-justified)

5-34 C141-E042-01EN

5.3 Host Commands

*4 Word 27-46: Model name;

ASCII code (40 characters, Left-justified), remainder filled with blank code
(X’20’)

One of two model names; MHA2021AT or MHA2032AT

*5 Word 49: Capabilities

Bit 15-14: Reserved
Bit 13: Standby timer value. Factory default is 0.
Bit 12: Reserved
Bit 11: IORDY support 1=Supported
Bit 10: IORDY inhibition 0=Disable inhibition
Bit 9-0: Undefined
Bit 9, 8: Always 1
Bit 7-0: Undefined

*6 Word 51: PIO data transfer mode

Bit 15-8: PIO data transfer mode X’02’=PIO mode 2
Bit 7-0: Undefined

*7 Word 53: Enable/disable setting of word 54-58 and 64-70

Bit 15-3: Reserved
Bit 2: Enable/disable setting of word 88 1=Enable
Bit 1: Enable/disable setting of word 64-70 1=Enable
Bit 0: Enable/disable setting of word 54-58 1=Enable

*8 Word 59: Transfer sector count currently set by READ/WRITE MULTIPLE

command
Bit 15-9: Reserved
Bit 8: Multiple sector transfer 1=Enable
Bit 7-0: Transfer sector count currently set by READ/WRITE

MULTIPLE command without interrupt supports 2, 4, 8, 16 and
32 sectors.

C141-E042-01EN 5-35

Interface

Table 5.4 Information to be read by IDENTIFY DEVICE COMMAND (3 of 3)

*9 Word 63: Multiword DMA transfer mode

Bit 15-8: Currently used multiword DMA transfer mode
Bit 7-0: Supportable multiword DMA transfer mode

Bit 2=1 Mode 2
Bit 1=1 Mode 1
Bit 0=1 Mode 0

*10 Word 64: Advance PIO transfer mode support status

Bit 15-8: Reserved
Bit 7-0: Advance PIO transfer mode

Bit 1 = 1 Mode 4
Bit 0 = 1 Mode 3

*11 WORD 80

Bit 15-4: Reserved
Bit 3: ATA-3 supported = 1
Bit 2: ATA-2 supported = 1
Bit 1: ATA-1 supported = 1
Bit 0: Undefined

*12 WORD 82

Bit 15-4: Reserved
Bit 3: Power Management feature set supported = 1
Bit 2: Removable feature set supported = 0
Bit 1: Security feature set supported = 1
Bit 0: SMART feature set supported = 1

*13 WORD 88

Bit 15-8: Currently used Ultra DMA transfer mode
Bit 7-0: Supportable Ultra DMA transfer mode

Bit 2 = 1 Mode 2
Bit 1 = 1 Mode 1

5-36 C141-E042-01EN

Bit 0 = 1 Mode 0

*14 WORD 128

Bit 15-9: Reserved
Bit 8: Security level. 0: High, 1: Maximum
Bit 7-5: Reserved
Bit 4: 1: Security counter expired
Bit 3: 1: Security frozen
Bit 2: 1: Security locked
Bit 1: 1: Security enabled
Bit 0: 1: Security supported

(13) IDENTIFY DEVICE DMA (X’EE’)

When this command is not used to transfer data to the host in DMA mode, this
command functions in the same way as the Identify Device command.

5.3 Host Commands

At command issuance (I/O registers setting contents)

1F7H(CM) 11101110

1F6H(DH)
1F5H(CH)

1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(FR)

H

×××

xx
xx
xx
xx
xx

DV xx

At command completion (I/O registers contents to be read)

1F7H(ST) Status information
1F6H(DH)
1F5H(CH)

1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(ER)

H

×××

xx
xx
xx
xx
Error information

DV xx

C141-E042-01EN 5-37

Interface

(14) SET FEATURES (X’EF’)

The host system issues the SET FEATURES command to set parameters in the
Features register for the purpose of changing the device features to be executed.
For the transfer mode (Feature register = 03), detail setting can be done using the
Sector Count register.

Upon receipt of this command, the device sets the BSY bit of the Status register
and saves the parameters in the Features register. Then, the device clears the
BSY bit, and generates an interrupt.

If the value in the Features register is not supported or it is invalid, the device
posts an ABORTED COMMAND error.

Table 5.5 lists the available values and operational modes that may be set in the
Features register.

Table 5.5 Features register values and settable modes

Features
Register

X’02’ Enables the write cache function.
X’03’ Transfer mode depends on the contents of the Sector Count register.

(Details are given later.)
X’55’ Disables read cache function.
X’66’ Disables the reverting to power-on default settings after software reset.
X’82’ Disables the write cache function.

X’AA’ Enables the read cache function.
X’BB’ Specifies the transfer of 4-byte ECC for READ LONG and WRITE

LONG commands.

X’CC’ Enables the reverting to power-on default settings after software reset.

At power-on or after hardware reset, the default mode is the same as that is set
with a value greater than X’AA’ (except for write cache). If X’66’ is specified, it
allows the seting value greater than X’AA’ which may have been modified to a
new value since power-on, to remain the same even after software reset.

Drive operation mode

5-38 C141-E042-01EN

5.3 Host Commands

At command issuance (I/O registers setting contents)

1F7H(CM) 11101111

1F6H(DH)
1F5H(CH)

1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(FR)

H

×××

xx
xx
xx
xx or transfer mode
[See Table 5.6]

DV xx

At command completion (I/O registers contents to be read)

1F7H(ST) Status information
1F6H(DH)
1F5H(CH)

1F4

(CL)

H

1F3

(SN)

H

1F2

(SC)

H

1F1

(ER)

H

×××

xx
xx
xx
xx
Error information

DV xx

The host sets X’03’ to the Features register. By issuing this command with
setting a value to the Sector Count register, the transfer mode can be selected.
Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits
specifies the binary mode value.

The IDD supports following values in the Sector Count register value. If other
value than below is specified, an ABORTED COMMAND error is posted.

PIO default transfer mode 00000 000 (X’00’)

PIO default transfer mode 00000 001 (X’01’)
(without IORDY)

PIO flow control transfer mode X 00001 000 (X’08’: Mode 0)

00001 001 (X’09’: Mode 1)

00001 010 (X’0A’: Mode 2)

00001 011 (X’0B’: Mode 3)

00001 100 (X’0C’: Mode 4)

C141-E042-01EN 5-39