查询MBM29DL321BD-80供应商
FUJITSU SEMICONDUCTOR
DATA SHEET
FLASH MEMORY
CMOS
32M (4M × 8/2M × 16) BIT
MBM29DL32XTD/BD
FEATURES
■
• 0.33 µm Process Technology
• Simultaneous Read/Write operations (dual bank)
Multiple devices available with different bank sizes (Refer to Table 1)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
• Single 3.0 V read, program, and erase
Minimizes system level power requirements
PRODUCT LINE UP
■
DS05-20873-4E
Dual Operation
-80/90/12
(Continued)
Part No. MBM29DL32XTD/MBM29DL32XBD
V
= 3.3 V
Ordering Part No.
Max. Address Access Time (ns) 80 90 120
Max. CE
Max. OE
PACKAGES
■
Em\edded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
Access Time (ns) 80 90 120
Access Time (ns) 30 35 50
48-pin plastic TSOP (I)
Marking Side
(FPT-48P-M19)
CC
V
CC
= 3.0 V
+0.3 V
–0.3 V
+0.6 V
–0.3 V
80 — —
—9012
48-pin plastic TSOP (I)
Marking Side
(FPT-48P-M20)
57-ball plastic FBGA
(BGA-57P-M01)
MBM29DL32XTD/BD
-80/90/12
(Continued)
• Compatible with JEDEC-standard commands
Uses same software commands as E
2
PROMs
• Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
57-ball FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
80 ns maximum access time
• Sector erase architecture
Eight 4K word and sixty-three 32K word sectors in word mode
Eight 8K byte and sixty-three 64K byte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Hidden ROM (Hi-ROM) region
64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
/ACC input pin
•WP
At V
, allows protection of boot sectors, regardless of sector protection/unprotection status
IL
At V
, allows removal of boot sector protection
IH
At V
, increases program performance
ACC
TM
• Embedded Erase
Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
•Data
• Ready/Busy output (RY/BY
Polling and Toggle Bit feature for detection of program or erase cycle completion
)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
•Low V
write inhibit ≤ 2.5 V
CC
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection
Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
Temporary sector group unprotection via the RESET
• In accordance with CFI (C
ommon Flash Memory Interface)
pin.
2
GENERAL DESCRIPTION
■
MBM29DL32XTD/BD
-80/90/12
The MBM29DL32XTD/BD are a 32M-bit, 3.0 V - only Flash memory organized as 4M bytes of 8 bits each or 2M
words of 16 bits each. The MBM29DL32XTD/BD are offered in a 48-pin TSOP(I) and FBGA Package. These
devices are designed to be programmed in-system with the standard system 3.0 V V
5.0 V V
are not required for write or erase operations. The devices can also be reprogrammed in standard
CC
supply. 12.0 V VPP and
CC
EPROM programmers.
MBM29DL32XTD/BD are organized into two banks, Bank 1 and Bank 2, which can be considered to be two
separate memory arrays as far as certain operations are concerned. These devices are the same as Fujitsu’s
standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access
from a non-busy bank of the array while an embedded write (either a program or an erase) operation is
simultaneously taking place on the other bank.
In the MBM29DL32XTD/BD , a new design concept is implemented, so called “Sliding Bank Architecture”. Under
this concept, the MBM29DL32XTD/BD can be produced a series of devices with different Bank 1/Bank 2 size
combinations; 0.5 Mb/31.5 Mb, 4 Mb/28 Mb, 8 Mb/24 Mb, 16 Mb/16 Mb.
The standard MBM29DL32XTD/BD offer access times 80 ns, 90 ns and 120 ns , allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE
write enable (WE), and output enable (OE) controls.
The MBM29DL32XTD/BD are pin and command set compatible with JEDEC standard E
2
PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry . Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
),
The MBM29DL32XTD/BD are programmed by e x ecuting the program command sequence . This will inv ok e the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before e xecuting the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29DL32XTD/BD are erased when shipped from the
factory .
The devices f eature single 3.0 V pow er supply operation f or both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
by the Toggle Bit feature on DQ
, or the RY/BY output pin. Once the end of a prog ram or er ase cycle has been
6
detector automatically
CC
7
completed, the devices internally reset to the read mode.
Fujitsu’s Flash technology combines years of EPROM and E
2
PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29DL32XTD/BD memories electrically erase the entire
chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The b ytes/words are progr ammed
one byte/word at a time using the EPROM programming mechanism of hot electron injection.
,
3
MBM29DL32XTD/BD
Table 1 MBM29DL32XTD/BD Device Bank Divisions
-80/90/12
Device
Part Number
MBM29DL321TD/BD
MBM29DL322TD/BD 4 Mbit
MBM29DL323TD/BD 8 Mbit
MBM29DL324TD/BD 16 Mbit
Organization
8/× 16
×
Megabits Sector sizes Megabits Sector sizes
0.5 Mbit Eight 8K byte/4K word 31.5 Mbit
Bank 1 Bank 2
Eight 8K byte/4K word,
seven 64K byte/32K word
Eight 8K byte/4K word,
fifteen 64K byte/32K word
Eight 8K byte/4K word,
thirty-one 64K byte/
32K word
28 Mbit
24 Mbit
16 Mbit
Sixty-three
64K byte/32K word
Fifty-six
64K byte/32K word
Forty-eight
64K byte/32K word
Thirty-two
64K byte/32K word
4
PIN ASSIGNMENTS
■
MBM29DL32XTD/BD
TSOP(I)
-80/90/12
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
RESET
N.C.
WP/ACC
RY/BY
A
A17
A7
A6
A5
A4
A3
A2
A1
A1
A2
A3
A4
A5
A6
A7
A17
A18
RY/BY
WP/ACC
N.C.
RESET
WE
A
A19
A8
A9
A10
A11
A12
A13
A14
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
18
16
17
18
19
20
21
22
23
24
24
23
22
21
20
19
18
17
16
15
14
13
12
11
20
10
9
8
7
6
5
4
3
2
1
(Marking Side)
Standard Pinout
FPT-48P-M19
(Marking Side)
Reverse Pinout
FPT-48P-M20
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
A16
BYTE
VSS
DQ 15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
V
SS
CE
A
0
A0
CE
V
SS
OE
DQ
0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A-1
VSS
BYTE
A16
5
MBM29DL32XTD/BD
-80/90/12
(Continued)
FBGA
(TOP VIEW)
Marking side
A3A1 A2 A4 A6A5
B1 B2 B3 B4 B5 B6
C1 C2 C3 C4 C5 C6
D1 D2 D3 D4 D5 D6
E1 E2 E3 E4 E5 E6
F1 F2 F3 F4 F5 F6
G1 G2 G3 G4 G5 G6
H1 H2 H3 H4 H5 H6
(BGA-57P-M01)
A1 A
B1 A
C1 A
D1 A
E1 A
3
4
2
1
0
F1 CE F2 DQ
G1 OE G2 DQ
H1 V
SS
A2 A
B2 A
C2 A
D2 A
7
17
6
5
E2 DQ
H2 DQ
A3 RY/BY A4 WE A5 A
B3 WP/ACC B4 RESET B5 A
C3 A
D3 A
0
8
9
1
E3 DQ
F3 DQ
G3 DQ
H3 DQ
18
20
2
10
11
3
C4 N.C. C5 A
D4 A
19
E4 DQ
F4 DQ
G4 V
CC
H4 DQ
5
12
4
D5 A
E5 DQ
F5 DQ
G5 DQ
H5 DQ
9
8
10
11
7
14
13
6
A6 A
B6 A
C6 A
D6 A
E6 A
13
12
14
15
16
F6 BYTE
G6 DQ15/A
H6 V
SS
Regarding additional No Internal Connection balls, please contact a Fujitsu representative for more
information.
-1
6
BLOCK DIAGRAM
■
V CC
V SS
MBM29DL32XTD/BD
-80/90/12
A
0 to A20
(A-1)
RESET
WE
CE
OE
BYTE
WP/ACC
DQ 0 to DQ 15
State
Control
&
Command
Register
Bank 2 Address
RY/BY
Status
Bank 1 Address
Control
Cell Matrix
(Bank 2)
X-Decoder
X-Decoder
Cell Matrix
(Bank 1)
Y-Gating & Data Latch
Y-Gating &
Data Latch
DQ 0 to DQ 15
7
MBM29DL32XTD/BD
LOGIC SYMBOL
■
-80/90/12
Table 2 MBM29DL32XTD/BD Pin Configuration
Pin Function
21
A-1
A0 to A20
CE
OE
WE
RESET
BYTE
WP/ACC
DQ 0 to DQ 15
RY/BY
16 or 8
A
, A0 to A
-1
DQ
0
RY/BY
RESET
BYTE
WP
to DQ
CE
OE
WE
/ACC
Address Inputs
20
Data Inputs/Outputs
15
Chip Enable
Output Enable
Write Enable
Ready/Busy Output
Hardware Reset Pin/Temporary Sector
Group Unprotection
Selects 8-bit or 16-bit mode
Hardware Write Protection/Program
Acceleration
N.C. No Internal Connection
V
SS
V
CC
Device Ground
Device Power Supply
8
DEVICE BUS OPERATION
■
Table 3 MBM29DL32XTD/BD User Bus Operations (BYTE
MBM29DL32XTD/BD
= VIH)
-80/90/12
Operation CE
Auto-Select Manufacturer Code (1) L L H L L L V
Auto-Select Device Code (1) L L H H L L V
Read (3) L L H A
OE WE A0A1A6A9DQ0 to DQ15RESET WP/ACC
Code H X
ID
Code H X
ID
A1A6A
0
D
9
OUT
HX
Standby HXXXXXX HIGH-Z H X
Output Disable L H H X X X X HIGH-Z H X
Write (Program/Erase) L H L A
Enable Sector Group Protection (2), (4) L V
ID
Verify Sector Group Protection (2), (4) L L H L H L V
A1A6A
0
9
LHLVIDXHX
ID
Temporary Sector Group Unprotection (5) XXXXXXX X V
D
IN
HX
Code H X
ID
X
Reset (Hardware)/Standby XXXXXXX HIGH-Z L X
Boot Block Sector Write Protection XXXXXXX X X L
Table 4 MBM29DL32XTD/BD User Bus Operations (BYTE
Operation CE
OE WE
DQ15/
A
-1
A0A1A6A9DQ0 to DQ7RESET WP/ACC
Auto-Select Manufacturer Code (1) L L H L L L L V
Auto-Select Device code (1) L L H L H L L V
= VIL)
Code H X
ID
Code H X
ID
Read (3) L L H A
A0A1A6A
-1
D
9
OUT
HX
Standby HXXX XXXX HIGH-Z H X
Output Disable L H H X X X X X HIGH-Z H X
Write (Program/Erase) L H L A
Enable Sector Group Protection
(2), (4)
Verify Sector Group Protection
(2), (4)
Temporary Sector Group
Unprotection (5)
LV
ID
LLHLLHLV
XXX X XXXX X V
A0A1A6A
-1
9
D
IN
HX
LLHLVIDXHX
Code H X
ID
ID
X
Reset (Hardware)/Standby X X X X X X X X HIGH-Z L X
Boot Block Sector Write Protection X X X X X X X X X X L
Legend:
L = V
, H = VIH, X = VIL or VIH, = Pulse input. See DC Characteristics for voltage levels.
IL
Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See
Table 12.
2. Refer to the section on Sector Group Protection.
3. WE
can be VIL if OE is VIL, OE at VIH initiates the write operations.
4. V
= 3.3 V ± 10%
CC
5. It is also used for the extended sector group protection.
9
MBM29DL32XTD/BD
ABSOLUTE MAXIMUM RATINGS(See WARNING)
■
-80/90/12
Parameter Symbol Conditions
Unit
Min. Max.
Rating
Storage Temperature Tstg
Ambient Temperature with
Power Applied
T
A
–55 +125 °C
–40 +85 °C
Voltage with Respect to
Ground All pins except A
OE
, RESET (Note 1)
Power Supply Voltage
(Note 1)
A
, OE, and RESET
9
(Note 2)
WP
/ACC (Note 3) V
,
9
, V
V
IN
OUT
V
CC
V
IN
IN
–0.5 V
–0.5 +4.0 V
–0.5 +13.0 V
–0.5 +10.5 V
+0.5 V
CC
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Notes: 1. Minimum DC voltage on input or I/O pins are –0.5 V. During voltage transitions, inputs may negative
overshoot V
+0.5 V. During voltage transitions, outputs ma y positive ov ershoot to V
2. Minimum DC input voltage on A
and RESET pins may negative overshoot V
voltage on A
up to 20 ns. when V
3. Minimum DC input voltage on WP
negative ov ershoot V
to –2.0 V for periods of up to 20 ns. Maximum DC v oltage on output and I/O pins are VCC
SS
+2.0 V for periods of up to 20 ns.
CC
, OE and RESET pins are –0.5 V. During voltage transitions, A9, OE
9
to –2.0 V for periods of up to 20 ns. Maximum DC input
SS
, OE and RESET pins are +13.0 V which may positive overshoot to 14.0 V for periods of
9
is applied.
CC
/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may
to –2.0 V for periods of up to 20 ns. Maximum DC input v oltage on WP/ACC pin
SS
iis +10.5V which may positive overshoot to +10.5V for periods of up to 20ns when Vcc is applied.
RECOMMENDED OPERATING CONDITIONS
■
Value
Parameter Symbol Conditions
Min. Max.
Ambient Temperature T
Power Supply Voltage V
MBM29DL32XTD/BD-80
A
MBM29DL32XTD/BD-90/12
MBM29DL32XTD/BD-80
CC
MBM29DL32XTD/BD-90/12
–20 +70 °C
–40 +85 °C
+3.0 +3.6 V
+2.7 +3.6 V
Operating ranges define those limits between which the functionality of the devices are guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
10
Unit
MAXIMUM OVERSHOOT
■
MBM29DL32XTD/BD
-80/90/12
+0.6 V
–0.5 V
–2.0 V
CC +2.0 V
V
V CC +0.5 V
+2.0 V
20 ns
20 ns
20 ns
Figure 1 Maximum Negative Overshoot Waveform
20 ns
20 ns20 ns
+14.0 V
+13.0 V
V
CC +0.5 V
Figure 2 Maximum Positive Overshoot Waveform 1
20 ns
20 ns20 ns
*: This waveform is applied for A9, OE, and RESET.
Figure 3 Maximum Positive Overshoot Waveform 2
11
MBM29DL32XTD/BD
ELECTRICAL CHARACTERISTICS
■
1. DC Characteristics
Parameter Symbol Conditions
-80/90/12
Value
Unit
Min. Max.
Input Leakage Current I
Output Leakage Current I
A
, OE, RESET Inputs Leakage
9
Current
V
Active Current (Note 1) I
CC
V
Active Current (Note 2) I
CC
Current (Standby) I
V
CC
V
Current (Standby, Reset) I
CC
V
Current
CC
(Automatic Sleep Mode) (Note 3)
VCC Active Current (Note 5)
(Read-While-Program)
V
Active Current (Note 5)
CC
(Read-While-Erase)
V
Active Current
CC
(Erase-Suspend-Program)
I
I
I
I
I
LI
LO
LIT
CC1
CC2
CC3
CC4
CC5
CC6
CC7
CC8
VIN = VSS to VCC, VCC = VCC Max. –1.0 +1.0
V
= VSS to VCC, VCC = VCC Max. –1.0 +1.0
OUT
VCC = VCC Max.
A
, OE, RESET = 12.5 V
9
CE = VIL, OE = VIH,
f = 5 MHz
CE
= VIL, OE = VIH,
f = 1 MHz
CE = VIL, OE = V
IH
Byte
Word 18
Byte
Word 7
VCC = VCC Max., CE = VCC ± 0.3 V,
RESET = V
± 0.3 V
CC
VCC = VCC Max.,WE/ACC = VCC ±
0.3 V, RESET
= V
± 0.3 V
SS
—35µA
16
—
7
—
—35mA
—5µA
—5µA
VCC = VCC Max., CE = VSS ± 0.3 V,
RESET
V
= V
± 0.3 V
CC
= VCC ± 0.3 V or VSS ± 0.3 V
IN
—5µA
Byte — 51
CE = VIL, OE = V
IH
Word — 53
Byte — 51
CE = VIL, OE = V
IH
Word — 53
CE = VIL, OE = V
IH
—35mA
µ
µ
mA
mA
mA
mA
A
A
ACC Accelerated Program
Current
Input Low Level V
Input High Level V
I
ACC
IL
IH
VCC = VCC Max.
WP/ACC = V
ACC
Max.
—20mA
—–0.50.6V
—2.0V
+0.3 V
CC
Voltage for WP/ACC Sector
Protection/Unprotection and
V
ACC
—8.59.5V
Program Acceleration
V oltage f or Autoselect and Sector
Protection (A
, OE, RESET)
9
V
ID
— 11.5 12.5 V
(Note 4)
(Continued)
Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component.
2. I
active while Embedded Algorithm (program or erase) is in progress.
CC
3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
4. Applicable for only V
applying.
CC
5. Embedded Algorithm (program or erase) is in progress. (@5 MHz)
12
(Continued)
Parameter Symbol Conditions
Output Low Voltage Level V
MBM29DL32XTD/BD
-80/90/12
Value
Unit
Min. Max.
OL
IOL = 4.0 mA, VCC = VCC Min. — 0.45 V
V
OH1
IOH = –2.0 mA, VCC = VCC Min. 2.4 — V
Output High Voltage Level
Low V
Lock-Out Voltage V
CC
V
OH2
LKO
IOH = –100 µAV
–0.4 — V
CC
—2.32.5V
Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component.
2. I
active while Embedded Algorithm (program or erase) is in progress.
CC
3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
4. Applicable for only V
applying.
CC
5. Embedded Algorithm (program or erase) is in progress. (@5 MHz)
13
MBM29DL32XTD/BD
2. AC Characteristics
• Read Only Operations Characteristics
Parameter
symbols
JEDEC Standard
Description Test setup
-80/90/12
80
(Note)90(Note)12(Note)
Unit
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AXQX
—t
—
t
RC
t
ACC
t
CE
t
OE
t
DF
t
DF
t
OH
READY
t
ELFL
t
ELFH
Note: Test Conditions:
Output Load:1 TTL gate and 30 pF (MBM29DL32XTD/BD 80)
1 TTL gate and 100 pF (MBM29DL32XTD/BD 90/12)
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Input: 1.5 V
Output:1.5 V
Read Cycle Time — Min. 80 90 120 ns
Address to Output Delay
CE
OE = V
IL
Max. 80 90 120 ns
IL
= V
Chip Enable to Output Delay OE = VILMax. 80 90 120 ns
Output Enable to Output Delay — Max. 30 35 50 ns
Chip Enable to Output High-Z — Max. 25 30 30 ns
Output Enable to Output High-Z — Max. 25 30 30 ns
Output Hold Time from Addresses,
CE or OE, Whichever Occurs First
RESET Pin Low to Read Mode — Max. 20 20 20
—Min.000ns
µ
CE or BYTE Switching Low or High — Max. 5 5 5 ns
s
14
Device
Under
Test
IN3064
or Equivalent
6.2 kΩ
CL
Figure 4 Test Conditions
3.3 V
2.7 kΩ
Diodes = IN3064
or Equivalent
• Write/Erase/Program Operations
MBM29DL32XTD/BD
-80/90/12
Parameter symbols
JEDEC Standard
t
AVAV
t
AVWL
—t
t
WLAX
—t
t
DVWH
t
WHDX
—t
—t
—t
t
GHWL
t
GHEL
t
WC
t
ASO
t
AHT
t
t
OEH
CEPH
OEPH
t
GHWL
t
GHEL
AS
AH
DS
DH
Description 80 90 12 Unit
Write Cycle Time Min. 80 90 120 ns
Address Setup Time Min. 0 0 0 ns
Address Setup Time to OE Low During
Toggle Bit Polling
Min. 12 15 15 ns
Address Hold Time Min. 45 45 50 ns
Address Hold Time from CE or OE High
During Toggle Bit Polling
Min. 0 0 0 ns
Data Setup Time Min. 30 35 50 ns
Data Hold Time Min. 0 0 0 ns
Output Enable
Hold Time
Read Min. 0 0 0 ns
Toggle and Data
Polling Min. 10 10 10 ns
CE High During Toggle Bit Polling Min. 20 20 20 ns
OE High During Toggle Bit Polling Min. 20 20 20 ns
Read Recover Time Before Write Min. 0 0 0 ns
Read Recover Time Before Write Min. 0 0 0 ns
t
ELWL
t
WLEL
t
WHEH
t
EHWH
t
WLWH
t
ELEH
t
WHWL
t
EHEL
t
WHWH1
t
WHWH2
—t
—t
—t
—t
—t
—t
t
CS
t
WS
t
CH
t
WH
t
WP
t
CP
t
WPH
t
CPH
t
WHWH1
t
WHWH2
VCS
VIDR
VACCR
VLHT
WPP
OESP
CE Setup Time Min. 0 0 0 ns
WE Setup Time Min. 0 0 0 ns
CE Hold Time Min. 0 0 0 ns
WE Hold Time Min. 0 0 0 ns
Write Pulse Width Min. 35 35 50 ns
CE Pulse Width Min. 35 35 50 ns
Write Pulse Width High Min. 25 30 30 ns
CE Pulse Width High Min. 25 30 30 ns
Byte Programming Operation Typ. 8 8 8 µs
Sector Erase Operation (Note 1) Typ. 1 1 1 sec
VCC Setup Time Min. 50 50 50 µs
Rise Time to VID (Note 2) Min. 500 500 500 ns
Rise Time to VID (Note 2) Min. 500 500 500 ns
Voltage Transition Time (Note 2) Min. 4 4 4 µs
Write Pulse Width (Note 2) Min. 100 100 100 µs
OE Setup Time to WE Active (Note 2) Min. 4 4 4 µs
(Continued)
15
MBM29DL32XTD/BD
(Continued)
-80/90/12
Parameter symbols
Description 80 90 12 Unit
JEDEC Standard
—t
—t
—t
—t
—t
—t
—t
—t
—t
—t
CSP
RB
RP
RH
FLQZ
FHQV
BUSY
EOE
TOW
SPD
CE Setup Time to WE Active (Note 2) Min. 4 4 4 µs
Recover Time from RY/BY Min. 0 0 0 ns
RESET Pulse Width Min. 500 500 500 ns
RESET High Level Period before Read Min. 200 200 200 ns
BYTE Switching Low to Output High-Z Max. 30 30 40 ns
BYTE Switching High to Output Active Max. 80 90 120 ns
Program/Erase Valid to RY/BY Delay Max. 90 90 90 ns
Delay Time from Embedded Output Enable Max. 80 90 120 ns
Erase Time-Out Time Min. 50 50 50 µs
Erase Suspend Transition Time Max. 20 20 20 µs
Notes: 1. This does not include the preprogramming time.
2. This timing is for Sector Group Protection operation.
16
ERASE AND PROGRAMMING PERFORMANCE
■
MBM29DL32XTD/BD
-80/90/12
Parameter
Sector Erase Time — 1 10 sec
Word Programming Time — 16 360
Byte Programming Time — 8 300
Chip Programming Time — — 100 sec
Program/Erase Cycle 100,000 — — cycles —
PIN CAPACITANCE
■
Parameter
symbol
C
IN
C
OUT
C
IN2
Parameter description Test setup Typ. Max. Unit
Input Capacitance VIN = 0 6 7.5 pF
Output Capacitance V
Control Pin Capacitance VIN = 0 8 11 pF
Min. Typ. Max.
Limits
= 0 8.5 12 pF
OUT
Unit Comments
Excludes programming time
prior to erasure
s
µ
µ
Excludes system-level
overhead
s
Excludes system-level
overhead
C
IN3
Note: Test conditions TA = 25°C, f = 1.0 MHzs
WP/ACC Pin Capacitance VIN = 0 21.5 22.5 pF
17
MBM29DL32XTD/BD
TIMING DIAGRAM
■
• Key to Switching Waveforms
WAVEFORM INPUTS OUTPUTS
-80/90/12
Addresses
Must Be
Steady
May
Change
from H to L
May
Change
from L to H
“H” or “L”
Any Change
Permitted
Does Not
Apply
t RC
Addresses Stable
Will Be
Steady
Will Be
Changing
from H to L
Will Be
Changing
from L to H
Changing
State
Unknown
Center Line is
HighImpedance
“Off” State
18
CE
OE
WE
Outputs
t ACC
t OE
t OEH
t CE
High-Z
Output Valid
Figure 5.1 AC Waveforms for Read Operations
t DF
t OH
High-Z
Addresses
t ACC
MBM29DL32XTD/BD
t RC
Addresses Stable
-80/90/12
CE
RESET
Outputs
t RH
t RP t RH t CE
t OH
High-Z
Output Valid
Figure 5.2 AC Waveforms for Hardware Reset/Read Operations
19
MBM29DL32XTD/BD
-80/90/12
Data Polling
PA
Addresses
3rd Bus Cycle
555H
t WC
t AS
PA
t AH
CE
t CS
t CH
OE
t GHWL
t WPH
t WHWH1
t WP
WE
t DS
t DH
Data
A0H
PD
DQ 7
D OUT
Notes: 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ
4. D
is the output of the complement of the data written to the device.
7
is the output of the data written to the device.
OUT
5. Figure indicates last two bus cycles out of four bus cycle sequence.
6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
t RC
t CE
t OE
t OH
D OUT
20
Figure 6 AC Waveforms for Alternate WE Controlled Program Operations
MBM29DL32XTD/BD
Data Polling3rd Bus Cycle
-80/90/12
Addresses
555H
t WC
PA PA
t AS
t AH
WE
t WS
t WH
OE
t CPH
t GHEL
t CP
t WHWH1
CE
t DS
t DH
Data
A0H
PD
Notes: 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ
4. D
is the output of the complement of the data written to the device.
7
is the output of the data written to the device.
OUT
5. Figure indicates last two bus cycles out of four bus cycle sequence.
6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
DQ 7
OUT
D
Figure 7 AC Waveforms for Alternate CE Controlled Program Operations
21
MBM29DL32XTD/BD
-80/90/12
Addresses
CE
OE
WE
Data
V CC
555H
t WC
t CS
t GHWL
t VCS
t WP
t DS
2AAH 555H
t AS t AH
t CH
t WPH
t DH
555H
2AAH SA *
55H55H 80H AAHAAH
10H/
30H
*: SA is the sector address for Sector Erase. Addresses = 555H (W ord), AAAH (Byte) for Chip Erase .
Note: These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Figure 8 AC Waveforms for Chip/Sector Erase Operations
22
CE
MBM29DL32XTD/BD
-80/90/12
t CH
t OE
t DF
OE
t OEH
WE
t CE
*
t EOEt BUSY
DQ7 =
Valid Data
DQ0 to DQ6
Valid Data
DQ7
DQ0 to DQ6
Data
t WHWH1 or 2
Data
DQ7
0 to DQ6 = Output Flag
DQ
RY/BY
* :DQ7 = Valid Data (The device has completed the Embedded operation).
Figure 9 AC Waveforms for Data Polling during Embedded Algorithm Operations
High-Z
High-Z
23
MBM29DL32XTD/BD
Address
CE
-80/90/12
tAHT tAHTtASO tAS
tCEPH
WE
OE
DQ 6/DQ2
RY/BY
tDH
Data
tBUSY
tOEPH
tOE tCE
Toggle
Data
Toggle
Data
Toggle
Data
tOEHtOEH
*
Stop
Toggling
* :DQ6 stops toggling (The device has completed the Embedded operation).
Figure 10 AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
Output
Valid
24
MBM29DL32XTD/BD
Read Command CommandRead Read Read
tRC tRC tRC tRCtWC tWC
-80/90/12
Address BA1 BA1 BA1
tAS
BA2
(555H)
tAH
tACC
tCE
BA2
(PA)
tAHT
tAS
BA2
(PA)
CE
tOE
tCEPH
OE
tGHWL
tWP
tOEH
tDF
WE
tDH
tDS tDF
DQ
Valid
Output
Valid
Intput
Valid
Output
Valid
Intput
Valid
Output
Status
(A0H) (PD)
Note: This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1: Address of Bank 1.
BA2: Address of Bank 2.
Figure 11 Bank-to-bank Read/Write Timing Diagram
WE
DQ6
DQ2
Enter
Embedded
Erasing
Erase
Suspend
Erase
Toggle
DQ
2 and DQ6
with OE or CE
Erase Suspend
Read
Enter Erase
Suspend Program
Erase
Suspend
Program
Note: DQ2 is read from the erase-suspended sector.
Figure 12 DQ2 vs. DQ
6
Erase Suspend
Read
Erase
Resume
Erase Erase
Complete
25
MBM29DL32XTD/BD
CE
WE
RY/BY
Figure 13 RY/BY Timing Diagram during Program/Erase Operations
-80/90/12
The rising edge of the last write pulse
Entire programming
or erase operations
t BUSY
WE
RESET
RY/BY
tRP
t RB
tREADY
Figure 14 RESET, RY/BY Timing Diagram
26
CE
BYTE
MBM29DL32XTD/BD
CE
t
-80/90/12
DQ0 to DQ
DQ15/A
BYTE
DQ0 to DQ
DQ15/A
CE
14
ELFH
t
-1
Data Output
0
to DQ7)
(DQ
FHQV
t
-1
A
Data Output
(DQ0 to DQ14)
15
DQ
Figure 15 Timing Diagram for Word Mode Configuration
ELFL
14
-1
t
Data Output
0
(DQ
to DQ14)
15
DQ
t
ACC
Data Output
0
to DQ7)
(DQ
-1
A
FLQZ
t
Figure 16 Timing Diagram for Byte Mode Configuration
The falling edge of the last write signal
CE or WE
BYTE
SET
t
(tAS)
Input
Valid
tHOLD
(tAH)
Figure 17 BYTE Timing Diagram for Write Operations
27
MBM29DL32XTD/BD
20, A19, A18
A
A17, A16, A15
A14, A13, A12
A0
A1
A6
VID
3 V
A9
SGAX
t VLHT
-80/90/12
SGAY
ID
V
3 V
OE
t VLHT
WE
t OESP
CE
t CSP
Data
t VCS
V
CC
SGAX : Sector Group Address for initial sector
SGAY : Sector Group Address for next sector
Note: A
is VIL on byte mode.
-1
Figure 18 AC Waveforms for Sector Group Protection
t VLHTt VLHT
t WPP
01H
t OE
28
CC
V
VID
3 V
RESET
CE
WE
tVCS
tVIDR
MBM29DL32XTD/BD
tVLHT
-80/90/12
3 V
RY/BY
tVLHT
Program or Erase Command Sequence
Unprotection period
tVLHT
Figure 19 Temporary Sector Group Unprotection Timing Diagram
29
MBM29DL32XTD/BD
-80/90/12
VCC
RESET
Add SGAXSGAX
A0
1
A
A6
CE
OE
tVIDR
tVCS
tVLHT
tWC tWC
tWP
SGAY
TIME-OUT
WE
Data
60H
60H
SGAX : Sector Group Address to be protected
SGAY : Next Sector Group Address to be protected
TIME-OUT : Time-Out window = 250 µs (min)
Figure 20 Extended Sector Group Protection Timing Diagram
40H
tOE
01H
60H
30
CC
V
VACC
3 V
WP/ACC
CE
WE
tVCS
tVACCR
MBM29DL32XTD/BD
tVLHT
-80/90/12
3 V
RY/BY
tVLHT
Program or Erase Command Sequence
Acceleration period
Figure 21 Accelerated Program Timing Diagram
tVLHT
31
MBM29DL32XTD/BD
FLEXIBLE SECTOR-ERASE ARCHITECTURE
■
Table 5.1 Sector Address Tables (MBM29DL321TD)
Sector address
Bank Sector
SA0 000000XXXX 64/32 00000H to 0FFFFH 000000H to 007FFFH
SA1 000001XXXX 64/32 10000H to 1FFFFH 008000H to 00FFFFH
SA2 000010XXXX 64/32 20000H to 2FFFFH 010000H to 017FFFH
SA3 000011XXXX 64/32 30000H to 3FFFFH 018000H to 01FFFFH
SA4 000100XXXX 64/32 40000H to 4FFFFH 020000H to 027FFFH
SA5 000101XXXX 64/32 50000H to 5FFFFH 028000H to 02FFFFH
SA6 000110XXXX 64/32 60000H to 6FFFFH 030000H to 037FFFH
SA7 000111XXXX 64/32 70000H to 7FFFFH 038000H to 03FFFFH
SA8 001000XXXX 64/32 80000H to 8FFFFH 040000H to 047FFFH
SA9 001001XXXX 64/32 90000H to 9FFFFH 048000H to 04FFFFH
SA10001010XXXX 64/32 A0000H to AFFFFH 050000H to 057FFFH
SA11001011XXXX 64/32 B0000H to BFFFFH 058000H to 05FFFFH
SA12001100XXXX 64/32 C0000H to CFFFFH 060000H to 067FFFH
SA13001101XXXX 64/32 D0000H to DFFFFH 068000H to 06FFFFH
SA14001110XXXX 64/32 E0000H to EFFFFH 070000H to 077FFFH
SA15001111XXXX 64/32 F0000H to FFFFFH 078000H to 07FFFFH
SA16010000XXXX 64/32 100000H to 10FFFFH 080000H to 087FFFH
Bank 2
SA17010001XXXX 64/32 110000H to 11FFFFH 088000H to 08FFFFH
SA18010010XXXX 64/32 120000H to 12FFFFH 090000H to 097FFFH
SA19010011XXXX 64/32 130000H to 13FFFFH 098000H to 09FFFFH
SA20010100XXXX 64/32 140000H to 14FFFFH 0A0000H to 0A7FFFH
SA21010101XXXX 64/32 150000H to 15FFFFH 0A8000H to 0AFFFFH
SA22010110XXXX 64/32 160000H to 16FFFFH 0B0000H to 0B7FFFH
SA23010111XXXX 64/32 170000H to 17FFFFH 0B8000H to 0BFFFFH
SA24011000XXXX 64/32 180000H to 18FFFFH 0C0000H to 0C7FFFH
SA25011001XXXX 64/32 190000H to 19FFFFH 0C8000H to 0CFFFFH
SA26011010XXXX 64/32 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
SA27011011XXXX 64/32 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
SA28011100XXXX 64/321C0000H to 1CFFFFH 0E0000H to 0E7FFFH
SA29011101XXXX 64/321D0000H to 1DFFFFH 0E8000H to 0EFFFFH
SA30011110XXXX 64/32 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
SA31011111XXXX 64/32 1F0000H to 1FFFFFH 0F8000H to 0FFFFFH
SA32100000XXXX 64/32 200000H to 20FFFFH 100000H to 107FFFH
SA33100001XXXX 64/32 210000H to 21FFFFH 108000H to 10FFFFH
SA34100010XXXX 64/32 220000H to 22FFFFH 110000H to 117FFFH
Bank address
A20A19A18A17A16A
-80/90/12
A
14A13A12A11
15
Sector
size
(Kbytes/
Kwords)
(×8)
Address range
(×16)
Address range
32
(Continued)
(Continued)
Bank Sector
SA351X0011XXXX 64/32 230000H to 23FFFFH 118000H to 11FFFFH
SA361X0100XXXX 64/32 240000H to 24FFFFH 120000H to 127FFFH
SA371X0101XXXX 64/32 250000H to 25FFFFH 128000H to 12FFFFH
SA381X0110XXXX 64/32 260000H to 26FFFFH 130000H to 137FFFH
SA391X0111XXXX 64/32 270000H to 27FFFFH 138000H to 13FFFFH
SA401X1000XXXX 64/32 280000H to 28FFFFH 140000H to 147FFFH
SA411X1001XXXX 64/32 290000H to 29FFFFH 148000H to 14FFFFH
SA421X1010XXXX 64/32 2A0000H to 2AFFFFH 150000H to 157FFFH
SA431X1011XXXX 64/32 2B0000H to 2BFFFFH 158000H to 15FFFFH
SA441X1100XXXX 64/322C0000H to 2CFFFFH 160000H to 167FFFH
SA451X1101XXXX 64/322D0000H to 2DFFFFH 168000H to 16FFFFH
SA461X1110XXXX 64/32 2E0000H to 2EFFFFH 170000H to 177FFFH
SA471X1111XXXX 64/32 2F0000H to 2FFFFFH 178000H to 17FFFFH
Bank 2
SA48110000XXXX 64/32 300000H to 30FFFFH 180000H to 187FFFH
SA49110001XXXX 64/32 310000H to 31FFFFH 188000H to 18FFFFH
SA50110010XXXX 64/32 320000H to 32FFFFH 190000H to 197FFFH
SA51110011XXXX 64/32 330000H to 33FFFFH 198000H to 19FFFFH
SA52110100XXXX 64/32 340000H to 34FFFFH 1A0000H to 1A7FFFH
SA53110101XXXX 64/32 350000H to 35FFFFH 1A8000H to 1AFFFFH
SA54110110XXXX 64/32 360000H to 36FFFFH 1B0000H to 1B7FFFH
SA55110111XXXX 64/32 370000H to 37FFFFH 1B8000H to 1BFFFFH
SA56111000XXXX 64/32 380000H to 38FFFFH 1C0000H to 1C7FFFH
SA57111001XXXX 64/32 390000H to 39FFFFH 1C8000H to 1CFFFFH
SA58111010XXXX 64/32 3A0000H to 3AFFFFH 1D0000H to 1D7FFFH
SA59111011XXXX 64/32 3B0000H to 3BFFFFH 1D8000H to 1DFFFFH
SA60111100XXXX 64/323C0000H to 3CFFFFH 1E0000H to 1E7FFFH
SA61111101XXXX 64/323D0000H to 3DFFFFH 1E8000H to 1EFFFFH
SA62111110XXXX 64/32 3E0000H to 3EFFFFH 1F0000H to 1F7FFFH
SA63111111000X 8/4 3F0000H to 3F1FFFH 1F8000H to 1F8FFFH
SA64111111001X 8/4 3F2000H to 3F3FFFH 1F9000H to 1F9FFFH
SA65111111010X 8/4 3F4000H to 3F5FFFH 1FA000H to 1FAFFFH
Bank 1
SA66111111011X 8/4 3F6000H to 3F7FFFH 1FB000H to 1FBFFFH
SA67111111100X 8/4 3F8000H to 3F9FFFH 1FC000H to 1FCFFFH
SA68111111101X 8/4 3FA000H to 3FBFFFH 1FD000H to 1FDFFFH
SA69111111110X 8/4 3FC000H to 3FDFFFH 1FE000H to 1FEFFFH
SA70111111111X 8/4 3FE000H to 3FFFFFH1FF000H to 1FFFFFH
Sector address
Bank address
A20A19A18A17A16A
A
14A13A12A11
15
MBM29DL32XTD/BD
Sector
size
(Kbytes/
Kwords)
(×8)
Address range
Address range
-80/90/12
(×16)
Note: The address range is A
The address range is A
MBM29DL321TD Top Boot Sector Architecture
: A-1 if in byte mode (BYTE = VIL).
20
: A0 if in word mode (BYTE = VIH).
20
33
MBM29DL32XTD/BD
Table 5.2 Sector Address Tables (MBM29DL321BD)
Sector address
Bank Sector
SA70111111XXXX 64/32 3F0000H to 3FFFFFH 1F8000H to 1FFFFFH
SA69111110XXXX 64/32 3E0000H to 3EFFFFH 1F0000H to 1F7FFFH
SA68111101XXXX 64/323D0000H to 3DFFFFH 1E8000H to 1EFFFFH
SA67111100XXXX 64/323C0000H to 3CFFFFH 1E0000H to 1E7FFFH
SA66111011XXXX 64/32 3B0000H to 3BFFFFH 1D8000H to 1DFFFFH
SA65111010XXXX 64/32 3A0000H to 3AFFFFH 1D0000H to 1D7FFFH
SA64111001XXXX 64/32 390000H to 39FFFFH 1C8000H to 1CFFFFH
SA63111000XXXX 64/32 380000H to 38FFFFH 1C0000H to 1C7FFFH
SA62110111XXXX 64/32 370000H to 37FFFFH 1B8000H to 1BFFFFH
SA61110110XXXX 64/32 360000H to 36FFFFH 1B0000H to 1B7FFFH
SA60110101XXXX 64/32 350000H to 35FFFFH 1A8000H to 1AFFFFH
SA59110100XXXX 64/32 340000H to 34FFFFH 1A0000H to 1A7FFFH
SA58110011XXXX 64/32 330000H to 33FFFFH 198000H to 19FFFFH
SA57110010XXXX 64/32 320000H to 32FFFFH 190000H to 197FFFH
SA56110001XXXX 64/32 310000H to 31FFFFH 188000H to 18FFFFH
SA55110000XXXX 64/32 300000H to 30FFFFH 180000H to 187FFFH
SA54101111XXXX 64/32 2F0000H to 2FFFFFH 178000H to 17FFFFH
Bank 2
SA53101110XXXX 64/32 2E0000H to 2EFFFFH 170000H to 177FFFH
SA52101101XXXX 64/322D0000H to 2DFFFFH 168000H to 16FFFFH
SA51101100XXXX 64/322C0000H to 2CFFFFH 160000H to 167FFFH
SA50101011XXXX 64/32 2B0000H to 2BFFFFH 158000H to 15FFFFH
SA49101010XXXX 64/32 2A0000H to 2AFFFFH 150000H to 157FFFH
SA48101001XXXX 64/32 290000H to 29FFFFH 148000H to 14FFFFH
SA47101000XXXX 64/32 280000H to 28FFFFH 140000H to 147FFFH
SA46100111XXXX 64/32 270000H to 27FFFFH 138000H to 13FFFFH
SA45100110XXXX 64/32 260000H to 26FFFFH 130000H to 137FFFH
SA44100101XXXX 64/32 250000H to 25FFFFH 128000H to 12FFFFH
SA43100100XXXX 64/32 240000H to 24FFFFH 120000H to 127FFFH
SA42100011XXXX 64/32 230000H to 23FFFFH 118000H to 11FFFFH
SA41100010XXXX 64/32 220000H to 22FFFFH 110000H to 117FFFH
SA40100001XXXX 64/32 210000H to 21FFFFH 108000H to 10FFFFH
SA39100000XXXX 64/32 200000H to 20FFFFH 100000H to 107FFFH
SA38011111XXXX 64/32 1F0000H to 1FFFFFH 0F8000H to 0FFFFFH
SA37011110XXXX 64/32 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
SA36011101XXXX 64/321D0000H to 1DFFFFH 0E8000H to 0EFFFFH
SA35011100XXXX 64/321C0000H to 1CFFFFH 0E0000H to 0E7FFFH
Bank address
A20A19A18A17A16A
A
15
-80/90/12
14A13A12A11
Sector
size
(Kbytes/
Kwords)
(×8)
Address range
(×16)
Address range
(Continued)
34
(Continued)
Bank Sector
SA34011011XXXX 64/32 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
SA33011010XXXX 64/32 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
SA32011001XXXX 64/32 190000H to 19FFFFH 0C8000H to 0CFFFFH
SA31011000XXXX 64/32 180000H to 18FFFFH 0C0000H to 0C7FFFH
SA30010111XXXX 64/32 170000H to 17FFFFH 0B8000H to 0BFFFFH
SA29010110XXXX 64/32 160000H to 16FFFFH 0B0000H to 0B7FFFH
SA28010101XXXX 64/32 150000H to 15FFFFH 0A8000H to 0AFFFFH
SA27010100XXXX 64/32 140000H to 14FFFFH 0A0000H to 0A7FFFH
SA26010011XXXX 64/32 130000H to 13FFFFH 098000H to 09FFFFH
SA25010010XXXX 64/32 120000H to 12FFFFH 090000H to 097FFFH
SA24010001XXXX 64/32 110000H to 11FFFFH 088000H to 08FFFFH
SA23010000XXXX 64/32 100000H to 10FFFFH 080000H to 087FFFH
SA22001111XXXX 64/32 0F0000H to 0FFFFFH 078000H to 07FFFFH
Bank 2
SA21001110XXXX 64/32 0E0000H to 0EFFFFH 070000H to 077FFFH
SA20001101XXXX 64/320D0000H to 0DFFFFH 068000H to 06FFFFH
SA19001100XXXX 64/320C0000H to 0CFFFFH 060000H to 067FFFH
SA18001011XXXX 64/32 0B0000H to 0BFFFFH 058000H to 05FFFFH
SA17001010XXXX 64/32 0A0000H to 0AFFFFH 050000H to 057FFFH
SA16001001XXXX 64/32 090000H to 09FFFFH 048000H to 04FFFFH
SA15001000XXXX 64/32 080000H to 08FFFFH 040000H to 047FFFH
SA14000111XXXX 64/32 070000H to 07FFFFH 038000H to 03FFFFH
SA13000110XXXX 64/32 060000H to 06FFFFH 030000H to 037FFFH
SA12000101XXXX 64/32 050000H to 05FFFFH 028000H to 02FFFFH
SA11000100XXXX 64/32 040000H to 04FFFFH 020000H to 027FFFH
SA10000011XXXX 64/32 030000H to 03FFFFH 018000H to 01FFFFH
SA9 000010XXXX 64/32 020000H to 02FFFFH 010000H to 017FFFH
SA8 000001XXXX 64/32 010000H to 01FFFFH 008000H to 00FFFFH
SA7 000000111X 8/4 00E000H to 00FFFFH007000H to 007FFFH
SA6 000000110X 8/4 00C000H to 00DFFFH 006000H to 006FFFH
SA5 000000101X 8/4 00A000H to 00BFFFH 005000H to 005FFFH
Bank 1
SA4 000000100X 8/4 008000H to 009FFFH 004000H to 004FFFH
SA3 000000011X 8/4 006000H to 007FFFH 003000H to 003FFFH
SA2 000000010X 8/4 004000H to 005FFFH 002000H to 002FFFH
SA1 000000001X 8/4 002000H to 003FFFH 001000H to 001FFFH
SA0 000000000X 8/4 000000H to 001FFFH 000000H to 000FFFH
Sector address
Bank address
A20A19A18A17A16A
A
14A13A12A11
15
MBM29DL32XTD/BD
Sector
size
(Kbytes/
Kwords)
(×8)
Address range
Address range
-80/90/12
(×16)
Note: The address range is A
The address range is A
MBM29DL321BD Bottom Boot Sector Architecture
: A-1 if in byte mode (BYTE = VIL).
20
: A0 if in word mode (BYTE = VIH).
20
35
MBM29DL32XTD/BD
Table 6.1 Sector Address Tables (MBM29DL322TD)
Sector address
Bank Sector
SA0 000000XXXX 64/32 000000H to 00FFFFH 000000H to 007FFFH
SA1 000001XXXX 64/32 010000H to 01FFFFH 008000H to 00FFFFH
SA2 000010XXXX 64/32 020000H to 02FFFFH 010000H to 017FFFH
SA3 000011XXXX 64/32 030000H to 03FFFFH 018000H to 01FFFFH
SA4 000100XXXX 64/32 040000H to 04FFFFH 020000H to 027FFFH
SA5 000101XXXX 64/32 050000H to 05FFFFH 028000H to 02FFFFH
SA6 000110XXXX 64/32 060000H to 06FFFFH 030000H to 037FFFH
SA7 000111XXXX 64/32 070000H to 07FFFFH 038000H to 03FFFFH
SA8 001000XXXX 64/32 080000H to 08FFFFH 040000H to 047FFFH
SA9 001001XXXX 64/32 090000H to 09FFFFH 048000H to 04FFFFH
SA10001010XXXX 64/32 0A0000H to 0AFFFFH 050000H to 057FFFH
SA11001011XXXX 64/32 0B0000H to 0BFFFFH 058000H to 05FFFFH
SA12001100XXXX 64/320C0000H to 0CFFFFH 060000H to 067FFFH
SA13001101XXXX 64/320D0000H to 0DFFFFH 068000H to 06FFFFH
SA14001110XXXX 64/32 0E0000H to 0EFFFFH 070000H to 077FFFH
SA15001111XXXX 64/32 0F0000H to 0FFFFFH 078000H to 07FFFFH
SA16010000XXXX 64/32 100000H to 10FFFFH 080000H to 087FFFH
Bank 2
SA17010001XXXX 64/32 110000H to 11FFFFH 088000H to 08FFFFH
SA18010010XXXX 64/32 120000H to 12FFFFH 090000H to 097FFFH
SA19010011XXXX 64/32 130000H to 13FFFFH 098000H to 09FFFFH
SA20010100XXXX 64/32 140000H to 14FFFFH 0A0000H to 0A7FFFH
SA21010101XXXX 64/32 150000H to 15FFFFH 0A8000H to 0AFFFFH
SA22010110XXXX 64/32 160000H to 16FFFFH 0B0000H to 0B7FFFH
SA23010111XXXX 64/32 170000H to 17FFFFH 0B8000H to 0BFFFFH
SA24011000XXXX 64/32 180000H to 18FFFFH 0C0000H to 0C7FFFH
SA25011001XXXX 64/32 190000H to 19FFFFH 0C8000H to 0CFFFFH
SA26011010XXXX 64/32 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
SA27011011XXXX 64/32 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
SA28011100XXXX 64/321C0000H to 1CFFFFH 0E0000H to 0E7FFFH
SA29011101XXXX 64/321D0000H to 1DFFFFH 0E8000H to 0EFFFFH
SA30011110XXXX 64/32 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
SA31011111XXXX 64/32 1F0000H to 1FFFFFH 0F8000H to 0FFFFFH
SA32100000XXXX 64/32 200000H to 20FFFFH 100000H to 107FFFH
SA33100001XXXX 64/32 210000H to 21FFFFH 108000H to 10FFFFH
SA34100010XXXX 64/32 220000H to 22FFFFH 110000H to 117FFFH
Bank address
A20A19A18A17A16A
A
15
-80/90/12
14A13A12A11
Sector
size
(Kbytes/
Kwords)
(×8)
Address range
(×16)
Address range
(Continued)
36
(Continued)
Bank Sector
SA35100011XXXX 64/32 230000H to 23FFFFH 118000H to 11FFFFH
SA36100100XXXX 64/32 240000H to 24FFFFH 120000H to 127FFFH
SA37100101XXXX 64/32 250000H to 25FFFFH 128000H to 12FFFFH
SA38100110XXXX 64/32 260000H to 26FFFFH 130000H to 137FFFH
SA39100111XXXX 64/32 270000H to 27FFFFH 138000H to 13FFFFH
SA40101000XXXX 64/32 280000H to 28FFFFH 140000H to 147FFFH
SA41101001XXXX 64/32 290000H to 29FFFFH 148000H to 14FFFFH
SA42101010XXXX 64/32 2A0000H to 2AFFFFH 150000H to 157FFFH
SA43101011XXXX 64/32 2B0000H to 2BFFFFH 158000H to 15FFFFH
SA44101100XXXX 64/322C0000H to 2CFFFFH 160000H to 167FFFH
Bank 2
SA45101101XXXX 64/322D0000H to 2DFFFFH 168000H to 16FFFFH
SA46101110XXXX 64/32 2E0000H to 2EFFFFH 170000H to 177FFFH
SA47101111XXXX 64/32 2F0000H to 2FFFFFH 178000H to 17FFFFH
SA48110000XXXX 64/32 300000H to 30FFFFH 180000H to 187FFFH
SA49110001XXXX 64/32 310000H to 31FFFFH 188000H to 18FFFFH
SA50110010XXXX 64/32 320000H to 32FFFFH 190000H to 197FFFH
SA51110011XXXX 64/32 330000H to 33FFFFH 198000H to 19FFFFH
SA52110100XXXX 64/32 340000H to 34FFFFH 1A0000H to 1A7FFFH
SA53110101XXXX 64/32 350000H to 35FFFFH 1A8000H to 1AFFFFH
SA54110110XXXX 64/32 360000H to 36FFFFH 1B0000H to 1B7FFFH
SA55110111XXXX 64/32 370000H to 37FFFFH 1B8000H to 1BFFFFH
SA56111000XXXX 64/32 380000H to 38FFFFH 1C0000H to 1C7FFFH
SA57111001XXXX 64/32 390000H to 39FFFFH 1C8000H to 1CFFFFH
SA58111010XXXX 64/32 3A0000H to 3AFFFFH 1D0000H to 1D7FFFH
SA59111011XXXX 64/32 3B0000H to 3BFFFFH 1D8000H to 1DFFFFH
SA60111100XXXX 64/323C0000H to 3CFFFFH 1E0000H to 1E7FFFH
SA61111101XXXX 64/323D0000H to 3DFFFFH 1E8000H to 1EFFFFH
SA62111110XXXX 64/32 3E0000H to 3EFFFFH 1F0000H to 1F7FFFH
Bank 1
SA63111111000X 8/4 3F0000H to 3F1FFFH 1F8000H to 1F8FFFH
SA64111111001X 8/4 3F2000H to 3F3FFFH 1F9000H to 1F9FFFH
SA65111111010X 8/4 3F4000H to 3F5FFFH 1FA000H to 1FAFFFH
SA66111111011X 8/4 3F6000H to 3F7FFFH 1FB000H to 1FBFFFH
SA67111111100X 8/4 3F8000H to 3F9FFFH 1FC000H to 1FCFFFH
SA68111111101X 8/4 3FA000H to 3FBFFFH 1FD000H to 1FDFFFH
SA69111111110X 8/4 3FC000H to 3FDFFFH 1FE000H to 1FEFFFH
SA70111111111X 8/4 3FE000H to 3FFFFFH1FF000H to 1FFFFFH
Sector address
Bank address
A20A19A18A17A16A
A
14A13A12A11
15
MBM29DL32XTD/BD
Sector
size
(Kbytes/
Kwords)
(×8)
Address range
Address range
-80/90/12
(×16)
Note: The address range is A
The address range is A
MBM29DL322TD Top Boot Sector Architecture
: A-1 if in byte mode (BYTE = VIL).
20
: A0 if in word mode (BYTE = VIH).
20
37
MBM29DL32XTD/BD
Table 6.2 Sector Address Tables (MBM29DL322BD)
Sector address
Bank Sector
SA70111111XXXX 64/32 3F0000H to 3FFFFFH 1F8000H to 1FFFFFH
SA69111110XXXX 64/32 3E0000H to 3EFFFFH 1F0000H to 1F7FFFH
SA68111101XXXX 64/323D0000H to 3DFFFFH 1E8000H to 1EFFFFH
SA67111100XXXX 64/323C0000H to 3CFFFFH 1E0000H to 1E7FFFH
SA66111011XXXX 64/32 3B0000H to 3BFFFFH 1D8000H to 1DFFFFH
SA65111010XXXX 64/32 3A0000H to 3AFFFFH 1D0000H to 1D7FFFH
SA64111001XXXX 64/32 390000H to 39FFFFH 1C8000H to 1CFFFFH
SA63111000XXXX 64/32 380000H to 38FFFFH 1C0000H to 1C7FFFH
SA62110111XXXX 64/32 370000H to 37FFFFH 1B8000H to 1BFFFFH
SA61110110XXXX 64/32 360000H to 36FFFFH 1B0000H to 1B7FFFH
SA60110101XXXX 64/32 350000H to 35FFFFH 1A8000H to 1AFFFFH
SA59110100XXXX 64/32 340000H to 34FFFFH 1A0000H to 1A7FFFH
SA58110011XXXX 64/32 330000H to 33FFFFH 198000H to 19FFFFH
SA57110010XXXX 64/32 320000H to 32FFFFH 190000H to 197FFFH
SA56110001XXXX 64/32 310000H to 31FFFFH 188000H to 18FFFFH
SA55110000XXXX 64/32 300000H to 30FFFFH 180000H to 187FFFH
SA54101111XXXX 64/32 2F0000H to 2FFFFFH 178000H to 17FFFFH
Bank 2
SA53101110XXXX 64/32 2E0000H to 2EFFFFH 170000H to 177FFFH
SA52101101XXXX 64/322D0000H to 2DFFFFH 168000H to 16FFFFH
SA51101100XXXX 64/322C0000H to 2CFFFFH 160000H to 167FFFH
SA50101011XXXX 64/32 2B0000H to 2BFFFFH 158000H to 15FFFFH
SA49101010XXXX 64/32 2A0000H to 2AFFFFH 150000H to 157FFFH
SA48101001XXXX 64/32 290000H to 29FFFFH 148000H to 14FFFFH
SA47101000XXXX 64/32 280000H to 28FFFFH 140000H to 147FFFH
SA46100111XXXX 64/32 270000H to 27FFFFH 138000H to 13FFFFH
SA45100110XXXX 64/32 260000H to 26FFFFH 130000H to 137FFFH
SA44100101XXXX 64/32 250000H to 25FFFFH 128000H to 12FFFFH
SA43100100XXXX 64/32 240000H to 24FFFFH 120000H to 127FFFH
SA42100011XXXX 64/32 230000H to 23FFFFH 118000H to 11FFFFH
SA41100010XXXX 64/32 220000H to 22FFFFH 110000H to 117FFFH
SA40100001XXXX 64/32 210000H to 21FFFFH 108000H to 10FFFFH
SA39100000XXXX 64/32 200000H to 20FFFFH 100000H to 107FFFH
SA38011111XXXX 64/32 1F0000H to 1FFFFFH 0F8000H to 0FFFFFH
SA37011110XXXX 64/32 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
SA36011101XXXX 64/321D0000H to 1DFFFFH 0E8000H to 0EFFFFH
SA35011100XXXX 64/321C0000H to 1CFFFFH 0E0000H to 0E7FFFH
Bank address
A20A19A18A17A16A
A
15
-80/90/12
14A13A12A11
Sector
size
(Kbytes/
Kwords)
(×8)
Address range
(×16)
Address range
(Continued)
38
(Continued)
Bank Sector
SA34011011XXXX 64/32 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
SA33011010XXXX 64/32 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
SA32011001XXXX 64/32 190000H to 19FFFFH 0C8000H to 0CFFFFH
SA31011000XXXX 64/32 180000H to 18FFFFH 0C0000H to 0C7FFFH
SA30010111XXXX 64/32 170000H to 17FFFFH 0B8000H to 0BFFFFH
SA29010110XXXX 64/32 160000H to 16FFFFH 0B0000H to 0B7FFFH
SA28010101XXXX 64/32 150000H to 15FFFFH 0A8000H to 0AFFFFH
SA27010100XXXX 64/32 140000H to 14FFFFH 0A0000H to 0A7FFFH
SA26010011XXXX 64/32 130000H to 13FFFFH 098000H to 09FFFFH
Bank 2
SA25010010XXXX 64/32 120000H to 12FFFFH 090000H to 097FFFH
SA24010001XXXX 64/32 110000H to 11FFFFH 088000H to 08FFFFH
SA23010000XXXX 64/32 100000H to 10FFFFH 080000H to 087FFFH
SA22001111XXXX 64/32 0F0000H to 0FFFFFH 078000H to 07FFFFH
SA21001110XXXX 64/32 0E0000H to 0EFFFFH 070000H to 077FFFH
SA20001101XXXX 64/320D0000H to 0DFFFFH 068000H to 06FFFFH
SA19001100XXXX 64/320C0000H to 0CFFFFH 060000H to 067FFFH
SA18001011XXXX 64/32 0B0000H to 0BFFFFH 058000H to 05FFFFH
SA17001010XXXX 64/32 0A0000H to 0AFFFFH 050000H to 057FFFH
SA16001001XXXX 64/32 090000H to 09FFFFH 048000H to 04FFFFH
SA15001000XXXX 64/32 080000H to 08FFFFH 040000H to 047FFFH
SA14000111XXXX 64/32 070000H to 07FFFFH 038000H to 03FFFFH
SA13000110XXXX 64/32 060000H to 06FFFFH 030000H to 037FFFH
SA12000101XXXX 64/32 050000H to 05FFFFH 028000H to 02FFFFH
SA11000100XXXX 64/32 040000H to 04FFFFH 020000H to 027FFFH
SA10000011XXXX 64/32 030000H to 03FFFFH 018000H to 01FFFFH
SA9 000010XXXX 64/32 020000H to 02FFFFH 010000H to 017FFFH
SA8 000001XXXX 64/32 010000H to 01FFFFH 008000H to 00FFFFH
Bank 1
SA7 000000111X 8/4 00E000H to 00FFFFH007000H to 007FFFH
SA6 000000110X 8/4 00C000H to 00DFFFH 006000H to 006FFFH
SA5 000000101X 8/4 00A000H to 00BFFFH 005000H to 005FFFH
SA4 000000100X 8/4 008000H to 009FFFH 004000H to 004FFFH
SA3 000000011X 8/4 006000H to 007FFFH 003000H to 003FFFH
SA2 000000010X 8/4 004000H to 005FFFH 002000H to 002FFFH
SA1 000000001X 8/4 002000H to 003FFFH 001000H to 001FFFH
SA0 000000000X 8/4 000000H to 001FFFH 000000H to 000FFFH
Sector address
Bank address
A20A19A18A17A16A
A
14A13A12A11
15
MBM29DL32XTD/BD
Sector
size
(Kbytes/
Kwords)
(×8)
Address range
Address range
-80/90/12
(×16)
Note: The address range is A
The address range is A
MBM29DL322BD Bottom Boot Sector Architecture
: A-1 if in byte mode (BYTE = VIL).
20
: A0 if in word mode (BYTE = VIH).
20
39
MBM29DL32XTD/BD
Table 7.1 Sector Address Tables (MBM29DL323TD)
Sector address
Bank Sector
SA0 000000XXXX 64/32 000000H to 00FFFFH 000000H to 007FFFH
SA1 000001XXXX 64/32 010000H to 01FFFFH 008000H to 00FFFFH
SA2 000010XXXX 64/32 020000H to 02FFFFH 010000H to 017FFFH
SA3 000011XXXX 64/32 030000H to 03FFFFH 018000H to 01FFFFH
SA4 000100XXXX 64/32 040000H to 04FFFFH 020000H to 027FFFH
SA5 000101XXXX 64/32 050000H to 05FFFFH 028000H to 02FFFFH
SA6 000110XXXX 64/32 060000H to 06FFFFH 030000H to 037FFFH
SA7 000111XXXX 64/32 070000H to 07FFFFH 038000H to 03FFFFH
SA8 001000XXXX 64/32 080000H to 08FFFFH 040000H to 047FFFH
SA9 001001XXXX 64/32 090000H to 09FFFFH 048000H to 04FFFFH
SA10001010XXXX 64/32 0A0000H to 0AFFFFH 050000H to 057FFFH
SA11001011XXXX 64/32 0B0000H to 0BFFFFH 058000H to 05FFFFH
SA12001100XXXX 64/320C0000H to 0CFFFFH 060000H to 067FFFH
SA13001101XXXX 64/320D0000H to 0DFFFFH 068000H to 06FFFFH
SA14001110XXXX 64/32 0E0000H to 0EFFFFH 070000H to 077FFFH
SA15001111XXXX 64/32 0F0000H to 0FFFFFH 078000H to 07FFFFH
SA16010000XXXX 64/32 100000H to 10FFFFH 080000H to 087FFFH
Bank 2
SA17010001XXXX 64/32 110000H to 11FFFFH 088000H to 08FFFFH
SA18010010XXXX 64/32 120000H to 12FFFFH 090000H to 097FFFH
SA19010011XXXX 64/32 130000H to 13FFFFH 098000H to 09FFFFH
SA20010100XXXX 64/32 140000H to 14FFFFH 0A0000H to 0A7FFFH
SA21010101XXXX 64/32 150000H to 15FFFFH 0A8000H to 0AFFFFH
SA22010110XXXX 64/32 160000H to 16FFFFH 0B0000H to 0B7FFFH
SA23010111XXXX 64/32 170000H to 17FFFFH 0B8000H to 0BFFFFH
SA24011000XXXX 64/32 180000H to 18FFFFH 0C0000H to 0C7FFFH
SA25011001XXXX 64/32 190000H to 19FFFFH 0C8000H to 0CFFFFH
SA26011010XXXX 64/32 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
SA27011011XXXX 64/32 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
SA28011100XXXX 64/321C0000H to 1CFFFFH 0E0000H to 0E7FFFH
SA29011101XXXX 64/321D0000H to 1DFFFFH 0E8000H to 0EFFFFH
SA30011110XXXX 64/32 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
SA31011111XXXX 64/32 1F0000H to 1FFFFFH 0F8000H to 0FFFFFH
SA32100000XXXX 64/32 200000H to 20FFFFH 100000H to 107FFFH
SA33100001XXXX 64/32 210000H to 21FFFFH 108000H to 10FFFFH
SA34100010XXXX 64/32 220000H to 22FFFFH 110000H to 117FFFH
Bank address
A20A19A18A17A16A
A
15
-80/90/12
14A13A12A11
Sector
size
(Kbytes/
Kwords)
(×8)
Address range
(×16)
Address range
(Continued)
40
(Continued)
Bank Sector
SA35100011XXXX 64/32 230000H to 23FFFFH 118000H to 11FFFFH
SA36100100XXXX 64/32 240000H to 24FFFFH 120000H to 127FFFH
SA37100101XXXX 64/32 250000H to 25FFFFH 128000H to 12FFFFH
SA38100110XXXX 64/32 260000H to 26FFFFH 130000H to 137FFFH
SA39100111XXXX 64/32 270000H to 27FFFFH 138000H to 13FFFFH
SA40101000XXXX 64/32 280000H to 28FFFFH 140000H to 147FFFH
Bank 2
SA41101001XXXX 64/32 290000H to 29FFFFH 148000H to 14FFFFH
SA42101010XXXX 64/32 2A0000H to 2AFFFFH 150000H to 157FFFH
SA43101011XXXX 64/32 2B0000H to 2BFFFFH 158000H to 15FFFFH
SA44101100XXXX 64/322C0000H to 2CFFFFH 160000H to 167FFFH
SA45101101XXXX 64/322D0000H to 2DFFFFH 168000H to 16FFFFH
SA46101110XXXX 64/32 2E0000H to 2EFFFFH 170000H to 177FFFH
SA47101111XXXX 64/32 2F0000H to 2FFFFFH 178000H to 17FFFFH
SA48110000XXXX 64/32 300000H to 30FFFFH 180000H to 187FFFH
SA49110001XXXX 64/32 310000H to 31FFFFH 188000H to 18FFFFH
SA50110010XXXX 64/32 320000H to 32FFFFH 190000H to 197FFFH
SA51110011XXXX 64/32 330000H to 33FFFFH 198000H to 19FFFFH
SA52110100XXXX 64/32 340000H to 34FFFFH 1A0000H to 1A7FFFH
SA53110101XXXX 64/32 350000H to 35FFFFH 1A8000H to 1AFFFFH
SA54110110XXXX 64/32 360000H to 36FFFFH 1B0000H to 1B7FFFH
SA55110111XXXX 64/32 370000H to 37FFFFH 1B8000H to 1BFFFFH
SA56111000XXXX 64/32 380000H to 38FFFFH 1C0000H to 1C7FFFH
SA57111001XXXX 64/32 390000H to 39FFFFH 1C8000H to 1CFFFFH
SA58111010XXXX 64/32 3A0000H to 3AFFFFH 1D0000H to 1D7FFFH
Bank 1
SA59111011XXXX 64/32 3B0000H to 3BFFFFH 1D8000H to 1DFFFFH
SA60111100XXXX 64/323C0000H to 3CFFFFH 1E0000H to 1E7FFFH
SA61111101XXXX 64/323D0000H to 3DFFFFH 1E8000H to 1EFFFFH
SA62111110XXXX 64/32 3E0000H to 3EFFFFH 1F0000H to 1F7FFFH
SA63111111000X 8/4 3F0000H to 3F1FFFH 1F8000H to 1F8FFFH
SA64111111001X 8/4 3F2000H to 3F3FFFH 1F9000H to 1F9FFFH
SA65111111010X 8/4 3F4000H to 3F5FFFH 1FA000H to 1FAFFFH
SA66111111011X 8/4 3F6000H to 3F7FFFH 1FB000H to 1FBFFFH
SA67111111100X 8/4 3F8000H to 3F9FFFH 1FC000H to 1FCFFFH
SA68111111101X 8/4 3FA000H to 3FBFFFH 1FD000H to 1FDFFFH
SA69111111110X 8/4 3FC000H to 3FDFFFH 1FE000H to 1FEFFFH
SA70111111111X 8/4 3FE000H to 3FFFFFH1FF000H to 1FFFFFH
Sector address
Bank address
A20A19A18A17A16A
A
14A13A12A11
15
MBM29DL32XTD/BD
Sector
size
(Kbytes/
Kwords)
(×8)
Address range
Address range
-80/90/12
(×16)
Note: The address range is A
The address range is A
MBM29DL323TD Top Boot Sector Architecture
: A-1 if in byte mode (BYTE = VIL).
20
: A0 if in word mode (BYTE = VIH).
20
41
MBM29DL32XTD/BD
Table 7.2 Sector Address Tables (MBM29DL323BD)
Sector address
Bank Sector
SA70111111XXXX 64/32 3F0000H to 3FFFFFH 1F8000H to 1FFFFFH
SA69111110XXXX 64/32 3E0000H to 3EFFFFH 1F0000H to 1F7FFFH
SA68111101XXXX 64/323D0000H to 3DFFFFH 1E8000H to 1EFFFFH
SA67111100XXXX 64/323C0000H to 3CFFFFH 1E0000H to 1E7FFFH
SA66111011XXXX 64/32 3B0000H to 3BFFFFH 1D8000H to 1DFFFFH
SA65111010XXXX 64/32 3A0000H to 3AFFFFH 1D0000H to 1D7FFFH
SA64111001XXXX 64/32 390000H to 39FFFFH 1C8000H to 1CFFFFH
SA63111000XXXX 64/32 380000H to 38FFFFH 1C0000H to 1C7FFFH
SA62110111XXXX 64/32 370000H to 37FFFFH 1B8000H to 1BFFFFH
SA61110110XXXX 64/32 360000H to 36FFFFH 1B0000H to 1B7FFFH
SA60110101XXXX 64/32 350000H to 35FFFFH 1A8000H to 1AFFFFH
SA59110100XXXX 64/32 340000H to 34FFFFH 1A0000H to 1A7FFFH
SA58110011XXXX 64/32 330000H to 33FFFFH 198000H to 19FFFFH
SA57110010XXXX 64/32 320000H to 32FFFFH 190000H to 197FFFH
SA56110001XXXX 64/32 310000H to 31FFFFH 188000H to 18FFFFH
SA55110000XXXX 64/32 300000H to 30FFFFH 180000H to 187FFFH
SA54101111XXXX 64/32 2F0000H to 2FFFFFH 178000H to 17FFFFH
Bank 2
SA53101110XXXX 64/32 2E0000H to 2EFFFFH 170000H to 177FFFH
SA52101101XXXX 64/322D0000H to 2DFFFFH 168000H to 16FFFFH
SA51101100XXXX 64/322C0000H to 2CFFFFH 160000H to 167FFFH
SA50101011XXXX 64/32 2B0000H to 2BFFFFH 158000H to 15FFFFH
SA49101010XXXX 64/32 2A0000H to 2AFFFFH 150000H to 157FFFH
SA48101001XXXX 64/32 290000H to 29FFFFH 148000H to 14FFFFH
SA47101000XXXX 64/32 280000H to 28FFFFH 140000H to 147FFFH
SA46100111XXXX 64/32 270000H to 27FFFFH 138000H to 13FFFFH
SA45100110XXXX 64/32 260000H to 26FFFFH 130000H to 137FFFH
SA44100101XXXX 64/32 250000H to 25FFFFH 128000H to 12FFFFH
SA43100100XXXX 64/32 240000H to 24FFFFH 120000H to 127FFFH
SA42100011XXXX 64/32 230000H to 23FFFFH 118000H to 11FFFFH
SA41100010XXXX 64/32 220000H to 22FFFFH 110000H to 117FFFH
SA40100001XXXX 64/32 210000H to 21FFFFH 108000H to 10FFFFH
SA39100000XXXX 64/32 200000H to 20FFFFH 100000H to 107FFFH
SA38011111XXXX 64/32 1F0000H to 1FFFFFH 0F8000H to 0FFFFFH
SA37011110XXXX 64/32 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
SA36011101XXXX 64/321D0000H to 1DFFFFH 0E8000H to 0EFFFFH
SA35011100XXXX 64/321C0000H to 1CFFFFH 0E0000H to 0E7FFFH
Bank address
A20A19A18A17A16A
A
15
-80/90/12
14A13A12A11
Sector
size
(Kbytes/
Kwords)
(×8)
Address range
(×16)
Address range
(Continued)
42
(Continued)
Bank Sector
SA34011011XXXX 64/32 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
SA33011010XXXX 64/32 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
SA32011001XXXX 64/32 190000H to 19FFFFH 0C8000H to 0CFFFFH
SA31011000XXXX 64/32 180000H to 18FFFFH 0C0000H to 0C7FFFH
SA30010111XXXX 64/32 170000H to 17FFFFH 0B8000H to 0BFFFFH
Bank 2
SA29010110XXXX 64/32 160000H to 16FFFFH 0B0000H to 0B7FFFH
SA28010101XXXX 64/32 150000H to 15FFFFH 0A8000H to 0AFFFFH
SA27010100XXXX 64/32 140000H to 14FFFFH 0A0000H to 0A7FFFH
SA26010011XXXX 64/32 130000H to 13FFFFH 098000H to 09FFFFH
SA25010010XXXX 64/32 120000H to 12FFFFH 090000H to 097FFFH
SA24010001XXXX 64/32 110000H to 11FFFFH 088000H to 08FFFFH
SA23010000XXXX 64/32 100000H to 10FFFFH 080000H to 087FFFH
SA22001111XXXX 64/32 0F0000H to 0FFFFFH 078000H to 07FFFFH
SA21001110XXXX 64/32 0E0000H to 0EFFFFH 070000H to 077FFFH
SA20001101XXXX 64/320D0000H to 0DFFFFH 068000H to 06FFFFH
SA19001100XXXX 64/320C0000H to 0CFFFFH 060000H to 067FFFH
SA18001011XXXX 64/32 0B0000H to 0BFFFFH 058000H to 05FFFFH
SA17001010XXXX 64/32 0A0000H to 0AFFFFH 050000H to 057FFFH
SA16001001XXXX 64/32 090000H to 09FFFFH 048000H to 04FFFFH
SA15001000XXXX 64/32 080000H to 08FFFFH 040000H to 047FFFH
SA14000111XXXX 64/32 070000H to 07FFFFH 038000H to 03FFFFH
SA13000110XXXX 64/32 060000H to 06FFFFH 030000H to 037FFFH
SA12000101XXXX 64/32 050000H to 05FFFFH 028000H to 02FFFFH
Bank 1
SA11000100XXXX 64/32 040000H to 04FFFFH 020000H to 027FFFH
SA10000011XXXX 64/32 030000H to 03FFFFH 018000H to 01FFFFH
SA9 000010XXXX 64/32 020000H to 02FFFFH 010000H to 017FFFH
SA8 000001XXXX 64/32 010000H to 01FFFFH 008000H to 00FFFFH
SA7 000000111X 8/4 00E000H to 00FFFFH007000H to 007FFFH
SA6 000000110X 8/4 00C000H to 00DFFFH 006000H to 006FFFH
SA5 000000101X 8/4 00A000H to 00BFFFH 005000H to 005FFFH
SA4 000000100X 8/4 008000H to 009FFFH 004000H to 004FFFH
SA3 000000011X 8/4 006000H to 007FFFH 003000H to 003FFFH
SA2 000000010X 8/4 004000H to 005FFFH 002000H to 002FFFH
SA1 000000001X 8/4 002000H to 003FFFH 001000H to 001FFFH
SA0 000000000X 8/4 000000H to 001FFFH 000000H to 000FFFH
Sector address
Bank address
A20A19A18A17A16A
A
14A13A12A11
15
MBM29DL32XTD/BD
Sector
size
(Kbytes/
Kwords)
(×8)
Address range
Address range
-80/90/12
(×16)
Note: The address range is A
The address range is A
MBM29DL323BD Bottom Boot Sector Architecture
: A-1 if in byte mode (BYTE = VIL).
20
: A0 if in word mode (BYTE = VIH).
20
43
MBM29DL32XTD/BD
Table 8.1 Sector Address Tables (MBM29DL324TD)
Sector address
Bank Sector
SA0 000000XXXX 64/32 000000H to 00FFFFH 000000H to 007FFFH
SA1 000001XXXX 64/32 010000H to 01FFFFH 008000H to 00FFFFH
SA2 000010XXXX 64/32 020000H to 02FFFFH 010000H to 017FFFH
SA3 000011XXXX 64/32 030000H to 03FFFFH 018000H to 01FFFFH
SA4 000100XXXX 64/32 040000H to 04FFFFH 020000H to 027FFFH
SA5 000101XXXX 64/32 050000H to 05FFFFH 028000H to 02FFFFH
SA6 000110XXXX 64/32 060000H to 06FFFFH 030000H to 037FFFH
SA7 000111XXXX 64/32 070000H to 07FFFFH 038000H to 03FFFFH
SA8 001000XXXX 64/32 080000H to 08FFFFH 040000H to 047FFFH
SA9 001001XXXX 64/32 090000H to 09FFFFH 048000H to 04FFFFH
SA10001010XXXX 64/32 0A0000H to 0AFFFFH 050000H to 057FFFH
SA11001011XXXX 64/32 0B0000H to 0BFFFFH 058000H to 05FFFFH
SA12001100XXXX 64/320C0000H to 0CFFFFH 060000H to 067FFFH
SA13001101XXXX 64/320D0000H to 0DFFFFH 068000H to 06FFFFH
SA14001110XXXX 64/32 0E0000H to 0EFFFFH 070000H to 077FFFH
Bank 2
SA15001111XXXX 64/32 0F0000H to 0FFFFFH 078000H to 07FFFFH
SA16010000XXXX 64/32 100000H to 10FFFFH 080000H to 087FFFH
SA17010001XXXX 64/32 110000H to 11FFFFH 088000H to 08FFFFH
SA18010010XXXX 64/32 120000H to 12FFFFH 090000H to 097FFFH
SA19010011XXXX 64/32 130000H to 13FFFFH 098000H to 09FFFFH
SA20010100XXXX 64/32 140000H to 14FFFFH 0A0000H to 0A7FFFH
SA21010101XXXX 64/32 150000H to 15FFFFH 0A8000H to 0AFFFFH
SA22010110XXXX 64/32 160000H to 16FFFFH 0B0000H to 0B7FFFH
SA23010111XXXX 64/32 170000H to 17FFFFH 0B8000H to 0BFFFFH
SA24011000XXXX 64/32 180000H to 18FFFFH 0C0000H to 0C7FFFH
SA25011001XXXX 64/32 190000H to 19FFFFH 0C8000H to 0CFFFFH
SA26011010XXXX 64/32 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
SA27011011XXXX 64/32 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
SA28011100XXXX 64/321C0000H to 1CFFFFH 0E0000H to 0E7FFFH
SA29011101XXXX 64/321D0000H to 1DFFFFH 0E8000H to 0EFFFFH
SA30011110XXXX 64/32 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
SA31011111XXXX 64/32 1F0000H to 1FFFFFH 0F8000H to 0FFFFFH
SA32100000XXXX 64/32 200000H to 20FFFFH 100000H to 107FFFH
Bank 1
SA33100001XXXX 64/32 210000H to 21FFFFH 108000H to 10FFFFH
SA34100010XXXX 64/32 220000H to 22FFFFH 110000H to 117FFFH
Bank address
A20A19A18A17A16A
A
15
-80/90/12
14A13A12A11
Sector
size
(Kbytes/
Kwords)
(×8)
Address range
(×16)
Address range
(Continued)
44
(Continued)
Bank Sector
SA35100011XXXX 64/32 230000H to 23FFFFH 118000H to 11FFFFH
SA36100100XXXX 64/32 240000H to 24FFFFH 120000H to 127FFFH
SA37100101XXXX 64/32 250000H to 25FFFFH 128000H to 12FFFFH
SA38100110XXXX 64/32 260000H to 26FFFFH 130000H to 137FFFH
SA39100111XXXX 64/32 270000H to 27FFFFH 138000H to 13FFFFH
SA40101000XXXX 64/32 280000H to 28FFFFH 140000H to 147FFFH
SA41101001XXXX 64/32 290000H to 29FFFFH 148000H to 14FFFFH
SA42101010XXXX 64/32 2A0000H to 2AFFFFH 150000H to 157FFFH
SA43101011XXXX 64/32 2B0000H to 2BFFFFH 158000H to 15FFFFH
SA44101100XXXX 64/322C0000H to 2CFFFFH 160000H to 167FFFH
SA45101101XXXX 64/322D0000H to 2DFFFFH 168000H to 16FFFFH
SA46101110XXXX 64/32 2E0000H to 2EFFFFH 170000H to 177FFFH
SA47101111XXXX 64/32 2F0000H to 2FFFFFH 178000H to 17FFFFH
SA48110000XXXX 64/32 300000H to 30FFFFH 180000H to 187FFFH
SA49110001XXXX 64/32 310000H to 31FFFFH 188000H to 18FFFFH
SA50110010XXXX 64/32 320000H to 32FFFFH 190000H to 197FFFH
SA51110011XXXX 64/32 330000H to 33FFFFH 198000H to 19FFFFH
Bank 1
SA52110100XXXX 64/32 340000H to 34FFFFH 1A0000H to 1A7FFFH
SA53110101XXXX 64/32 350000H to 35FFFFH 1A8000H to 1AFFFFH
SA54110110XXXX 64/32 360000H to 36FFFFH 1B0000H to 1B7FFFH
SA55110111XXXX 64/32 370000H to 37FFFFH 1B8000H to 1BFFFFH
SA56111000XXXX 64/32 380000H to 38FFFFH 1C0000H to 1C7FFFH
SA57111001XXXX 64/32 390000H to 39FFFFH 1C8000H to 1CFFFFH
SA58111010XXXX 64/32 3A0000H to 3AFFFFH 1D0000H to 1D7FFFH
SA59111011XXXX 64/32 3B0000H to 3BFFFFH 1D8000H to 1DFFFFH
SA60111100XXXX 64/323C0000H to 3CFFFFH 1E0000H to 1E7FFFH
SA61111101XXXX 64/323D0000H to 3DFFFFH 1E8000H to 1EFFFFH
SA62111110XXXX 64/32 3E0000H to 3EFFFFH 1F0000H to 1F7FFFH
SA63111111000X 8/4 3F0000H to 3F1FFFH 1F8000H to 1F8FFFH
SA64111111001X 8/4 3F2000H to 3F3FFFH 1F9000H to 1F9FFFH
SA65111111010X 8/4 3F4000H to 3F5FFFH 1FA000H to 1FAFFFH
SA66111111011X 8/4 3F6000H to 3F7FFFH 1FB000H to 1FBFFFH
SA67111111100X 8/4 3F8000H to 3F9FFFH 1FC000H to 1FCFFFH
SA68111111101X 8/4 3FA000H to 3FBFFFH 1FD000H to 1FDFFFH
SA69111111110X 8/4 3FC000H to 3FDFFFH 1FE000H to 1FEFFFH
SA70111111111X 8/4 3FE000H to 3FFFFFH1FF000H to 1FFFFFH
Sector address
Bank address
A20A19A18A17A16A
A
14A13A12A11
15
MBM29DL32XTD/BD
Sector
size
(Kbytes/
Kwords)
(×8)
Address range
Address range
-80/90/12
(×16)
Note: The address range is A
The address range is A
MBM29DL324TD Top Boot Sector Architecture
: A-1 if in byte mode (BYTE = VIL).
20
: A0 if in word mode (BYTE = VIH).
20
45
MBM29DL32XTD/BD
Table 8.2 Sector Address Tables (MBM29DL324BD)
Sector address
Bank Sector
SA70111111XXXX 64/32 3F0000H to 3FFFFFH 1F8000H to 1FFFFFH
SA69111110XXXX 64/32 3E0000H to 3EFFFFH 1F0000H to 1F7FFFH
SA68111101XXXX 64/323D0000H to 3DFFFFH 1E8000H to 1EFFFFH
SA67111100XXXX 64/323C0000H to 3CFFFFH 1E0000H to 1E7FFFH
SA66111011XXXX 64/32 3B0000H to 3BFFFFH 1D8000H to 1DFFFFH
SA65111010XXXX 64/32 3A0000H to 3AFFFFH 1D0000H to 1D7FFFH
SA64111001XXXX 64/32 390000H to 39FFFFH 1C8000H to 1CFFFFH
SA63111000XXXX 64/32 380000H to 38FFFFH 1C0000H to 1C7FFFH
SA62110111XXXX 64/32 370000H to 37FFFFH 1B8000H to 1BFFFFH
SA61110110XXXX 64/32 360000H to 36FFFFH 1B0000H to 1B7FFFH
SA60110101XXXX 64/32 350000H to 35FFFFH 1A8000H to 1AFFFFH
SA59110100XXXX 64/32 340000H to 34FFFFH 1A0000H to 1A7FFFH
SA58110011XXXX 64/32 330000H to 33FFFFH 198000H to 19FFFFH
SA57110010XXXX 64/32 320000H to 32FFFFH 190000H to 197FFFH
SA56110001XXXX 64/32 310000H to 31FFFFH 188000H to 18FFFFH
Bank 2
SA55110000XXXX 64/32 300000H to 30FFFFH 180000H to 187FFFH
SA54101111XXXX 64/32 2F0000H to 2FFFFFH 178000H to 17FFFFH
SA53101110XXXX 64/32 2E0000H to 2EFFFFH 170000H to 177FFFH
SA52101101XXXX 64/322D0000H to 2DFFFFH 168000H to 16FFFFH
SA51101100XXXX 64/322C0000H to 2CFFFFH 160000H to 167FFFH
SA50101011XXXX 64/32 2B0000H to 2BFFFFH 158000H to 15FFFFH
SA49101010XXXX 64/32 2A0000H to 2AFFFFH 150000H to 157FFFH
SA48101001XXXX 64/32 290000H to 29FFFFH 148000H to 14FFFFH
SA47101000XXXX 64/32 280000H to 28FFFFH 140000H to 147FFFH
SA46100111XXXX 64/32 270000H to 27FFFFH 138000H to 13FFFFH
SA45100110XXXX 64/32 260000H to 26FFFFH 130000H to 137FFFH
SA44100101XXXX 64/32 250000H to 25FFFFH 128000H to 12FFFFH
SA43100100XXXX 64/32 240000H to 24FFFFH 120000H to 127FFFH
SA42100011XXXX 64/32 230000H to 23FFFFH 118000H to 11FFFFH
SA41100010XXXX 64/32 220000H to 22FFFFH 110000H to 117FFFH
SA40100001XXXX 64/32 210000H to 21FFFFH 108000H to 10FFFFH
SA39100000XXXX 64/32 200000H to 20FFFFH 100000H to 107FFFH
SA38011111XXXX 64/32 1F0000H to 1FFFFFH 0F8000H to 0FFFFFH
Bank 1
SA37011110XXXX 64/32 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH
SA36011101XXXX 64/321D0000H to 1DFFFFH 0E8000H to 0EFFFFH
SA35011100XXXX 64/321C0000H to 1CFFFFH 0E0000H to 0E7FFFH
Bank address
A20A19A18A17A16A
A
15
-80/90/12
14A13A12A11
Sector
size
(Kbytes/
Kwords)
(×8)
Address range
(×16)
Address range
(Continued)
46
MBM29DL32XTD/BD
-80/90/12
(Continued)
Bank Sector
SA34011011XXXX 64/32 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH
SA33011010XXXX 64/32 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH
SA32011001XXXX 64/32 190000H to 19FFFFH 0C8000H to 0CFFFFH
SA31011000XXXX 64/32 180000H to 18FFFFH 0C0000H to 0C7FFFH
SA30010111XXXX 64/32 170000H to 17FFFFH 0B8000H to 0BFFFFH
SA29010110XXXX 64/32 160000H to 16FFFFH 0B0000H to 0B7FFFH
SA28010101XXXX 64/32 150000H to 15FFFFH 0A8000H to 0AFFFFH
SA27010100XXXX 64/32 140000H to 14FFFFH 0A0000H to 0A7FFFH
SA26010011XXXX 64/32 130000H to 13FFFFH 098000H to 09FFFFH
SA25010010XXXX 64/32 120000H to 12FFFFH 090000H to 097FFFH
SA24010001XXXX 64/32 110000H to 11FFFFH 088000H to 08FFFFH
SA23010000XXXX 64/32 100000H to 10FFFFH 080000H to 087FFFH
SA22001111XXXX 64/32 0F0000H to 0FFFFFH 078000H to 07FFFFH
SA21001110XXXX 64/32 0E0000H to 0EFFFFH 070000H to 077FFFH
SA20001101XXXX 64/320D0000H to 0DFFFFH 068000H to 06FFFFH
SA19001100XXXX 64/320C0000H to 0CFFFFH 060000H to 067FFFH
SA18001011XXXX 64/32 0B0000H to 0BFFFFH 058000H to 05FFFFH
Bank 1
SA17001010XXXX 64/32 0A0000H to 0AFFFFH 050000H to 057FFFH
SA16001001XXXX 64/32 090000H to 09FFFFH 048000H to 04FFFFH
SA15001000XXXX 64/32 080000H to 08FFFFH 040000H to 047FFFH
SA14000111XXXX 64/32 070000H to 07FFFFH 038000H to 03FFFFH
SA13000110XXXX 64/32 060000H to 06FFFFH 030000H to 037FFFH
SA12000101XXXX 64/32 050000H to 05FFFFH 028000H to 02FFFFH
SA11000100XXXX 64/32 040000H to 04FFFFH 020000H to 027FFFH
SA10000011XXXX 64/32 030000H to 03FFFFH 018000H to 01FFFFH
SA9 000010XXXX 64/32 020000H to 02FFFFH 010000H to 017FFFH
SA8 000001XXXX 64/32 010000H to 01FFFFH 008000H to 00FFFFH
SA7 000000111X 8/4 00E000H to 00FFFFH007000H to 007FFFH
SA6 000000110X 8/4 00C000H to 00DFFFH 006000H to 006FFFH
SA5 000000101X 8/4 00A000H to 00BFFFH 005000H to 005FFFH
SA4 000000100X 8/4 008000H to 009FFFH 004000H to 004FFFH
SA3 000000011X 8/4 006000H to 007FFFH 003000H to 003FFFH
SA2 000000010X 8/4 004000H to 005FFFH 002000H to 002FFFH
SA1 000000001X 8/4 002000H to 003FFFH 001000H to 001FFFH
SA0 000000000X 8/4 000000H to 001FFFH 000000H to 000FFFH
Bank address
A20A19A18A17A16A
Sector address
A
14A13A12A11
15
Sector
size
(Kbytes/
Kwords)
(×8)
Address range
(×16)
Address range
Note: The address range is A
The address range is A
MBM29DL324BD Bottom Boot Sector Architecture
: A-1 if in byte mode (BYTE = VIL).
20
: A0 if in word mode (BYTE = VIH).
20
47
MBM29DL32XTD/BD
Table 9.1 Sector Group Addresses (MBM29DL32XTD)
-80/90/12
(Top Boot Block)
Sector group A
20
A
19
A
18
A
A
17
16
A
15
A
14
A
13
A
12
Sectors
SGA0 000000XXX SA0
01
SGA1 0000
XXXSA1 to SA310
11
SGA2 0001XXXXXSA4 to SA7
SGA3 0010XXXXXSA8 to SA11
SGA4 0011XXXXXSA12 to SA15
SGA5 0100XXXXXSA16 to SA19
SGA6 0101XXXXXSA20 to SA23
SGA7 0110XXXXXSA24 to SA27
SGA8 0111XXXXXSA28 to SA31
SGA9 1000XXXXXSA32 to SA35
SGA10 1001XXXXXSA36 to SA39
SGA11 1010XXXXXSA40 to SA43
SGA12 1011XXXXXSA44 to SA47
SGA13 1100XXXXXSA48 to SA51
SGA14 1101XXXXXSA52 to SA55
SGA15 1110XXXXXSA56 to SA59
00
SGA16 1 1 1 1
X X X SA60 to SA6201
10
SGA17 111111000 SA63
SGA18 111111001 SA64
SGA19 111111010 SA65
SGA20 111111011 SA66
SGA21 111111100 SA67
SGA22 111111101 SA68
SGA23 111111110 SA69
SGA24 111111111 SA70
48
MBM29DL32XTD/BD
Table 9.2 Sector Group Addresses (MBM29DL32XBD)
(Bottom Boot Block)
-80/90/12
Sector group A
20
A
19
A
18
A
A
17
16
A
15
A
14
A
13
A
12
Sectors
SGA0 000000000 SA0
SGA1 000000001 SA1
SGA2 000000010 SA2
SGA3 000000011 SA3
SGA4 000000100 SA4
SGA5 000000101 SA5
SGA6 000000110 SA6
SGA7 000000111 SA7
01
SGA8 0000
X X X SA8 to SA1010
11
SGA9 0001XXXXXSA11 to SA14
SGA10 0010XXXXXSA15 to SA18
SGA11 0011XXXXXSA19 to SA22
SGA12 0100XXXXXSA23 to SA26
SGA13 0101XXXXXSA27 to SA30
SGA14 0110XXXXXSA31 to SA34
SGA15 0111XXXXXSA35 to SA38
SGA16 1000XXXXXSA39 to SA42
SGA17 1001XXXXXSA43 to SA46
SGA18 1010XXXXXSA47 to SA50
SGA19 1011XXXXXSA51 to SA54
SGA20 1100XXXXXSA55 to SA58
SGA21 1101XXXXXSA59 to SA62
SGA22 1110XXXXXSA63 to SA66
00
SGA23 1 1 1 1
X X X SA67 to SA6901
10
SGA24 111111XXX SA70
49
MBM29DL32XTD/BD
FUNCTIONAL DESCRIPTION
■
-80/90/12
• Simultaneous Operation
MBM29DL32XTD/BD have f eature, which is capability of reading data from one bank of memory while a program
or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the
conventional features (read, program, erase, erase-suspend read, and erase-suspend program). The bank
selection can be selected by bank address (A
The MBM29DL321TD/BD have two banks which contain
Bank 1 (8KB × eight sectors) and Bank 2 (64KB × sixty-three sectors).
The MBM29DL322TD/BD have two banks which contain
Bank 1 (8KB × eight sectors, 64KB × seven sectors) and Bank 2 (64KB × fifty-six sectors).
The MBM29DL323TD/BD have two banks which contain
Bank 1 (8KB × eight sectors, 64KB × fifteen sectors) and Bank 2 (64KB × forty-eight sectors).
The MBM29DL324TD/BD have two banks which contain
Bank 1 (8KB × eight sectors, 64KB × thirty-one sectors) and Bank 2 (64KB × thirty-two sectors).
The simultaneous operation can not ex ecute multi-function mode in the same bank. Table 10 sho ws combination
to be possible for simultaneous operation. (Refer to the Figure 11 Back-to-back Read/Write Timing Diagram.)
to A20) with zero latency.
15
Table 10 Simultaneous Operation
Case Bank 1 status Bank 2 status
1 Read Mode Read Mode
2 Read Mode Autoselect Mode
3 Read Mode Program Mode
4 Read Mode Erase Mode *
5 Autoselect Mode Read Mode
6 Program Mode Read Mode
7 Erase Mode * Read Mode
*: An erase operation may also be supended to read from or program to a sector not being erased.
•Read Mode
The MBM29DL32XTD/BD have two control functions which must be satisfied in order to obtain data at the
outputs. CE is the power control and should be used f or a device selection. OE is the output control and should
be used to gate data to the output pins if a device is selected.
Address access time (t
access time (t
enable access time is the delay from the falling edge of OE
addresses have been stab le for at least t
power-up, it is necessary to input hardware reset or to change CE
) is the delay from stable addresses and stable CE to valid data at the output pins. The output
CE
) is equal to the delay from stable addresses to valid output data. The chip enable
ACC
to valid data at the output pins. (Assuming the
time.) When reading out a data without changing addresses after
ACC-tOE
pin from “H” or “L”
50
MBM29DL32XTD/BD
-80/90/12
• Standby Mode
There are two ways to implement the standby mode on the MBM29DL32XTD/BD devices, one using both the
CE
and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achie v ed with CE and RESET inputs both held at V
Under this condition the current consumed is less than 5 µA max. During Embedded Algorithm operation, V
active current (I
) is required even CE = “H”. The de vice can be read with standard access time (tCE) from either
CC2
± 0.3 V.
CC
CC
of these standby modes.
When using the RESET
pin only, a CMOS standby mode is achiev ed with RESET input held at VSS ± 0.3 V (CE
= “H” or “L”). Under this condition the current is consumed is less than 5 µA max. Once the RESET pin is taken
high, the device requires t
In the standby mode the outputs are in the high impedance state, independent of the OE
of wake up time before outputs are valid for read access.
RH
input.
• Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29DL32XTD/BD data. This mode can be used effectively with an application requested low power
consumption such as handy terminals.
To activate this mode, MBM29DL32XTD/BD automatically switch themselves to low power mode when
MBM29DL32XTD/BD addresses remain stably during access fine of 150 ns. It is not necessary to control CE
WE, and OE on the mode. Under the mode, the current consumed is typically 1
During simultaneous operation, V
active current (I
CC
) is required.
CC2
Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,
the mode is canceled automatically and MBM29DL32XTD/BD read-out the data for changed addresses.
A (CMOS Level).
µ
,
• Output Disable
With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins
to be in a high impedance state.
• Autoselect
The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer
and type. This mode is intended for use b y prog r amming equipment for the purpose of automatically matching
the devices to be programmed with its corresponding prog ramming algorithm. This mode is functional ov er the
entire temperature range of the devices.
To activate this mode, the programming equipment must force V
identifier bytes may then be sequenced from the devices outputs by toggling address A
addresses are DON’T CARES except A
, A1, and A6 (A-1). (See Tables 3 and 4.)
0
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29DL32XTD/BD are erased or programmed in a system without access to high vo ltage on the A
command sequence is illustrated in Table 12. (Refer to Autoselect Command section.)
(11.5 V to 12.5 V) on address pin A9. Two
ID
from VIL to VIH. All
0
pin. The
9
51
MBM29DL32XTD/BD
-80/90/12
Byte 0 (A
= VIL) represents the manufacturer’ s code (Fujitsu = 04H) and w ord 1 (A0 = VIH) represents the device
0
identifier code (MBM29DL321TD = 59H and MBM29DL321BD = 5AH for ×8 mode; MBM29DL321TD = 2259H
and MBM29DL321BD = 225AH for ×16 mode). (MBM29DL322TD = 55H and MBM29DL322BD = 56H for ×8
mode; MBM29DL322TD = 2255H and MBM29DL322BD = 2256H for ×16 mode). (MBM29DL323TD = 50H and
MBM29DL323BD = 53H for ×8 mode; MBM29DL323TD = 2250H and MBM29DL323BD = 2253H for ×16 mode).
(MBM29DL324TD = 5CH and MBM29DL324BD = 5FH for ×8 mode; MBM29DL324TD = 225CH and
MBM29DL324BD = 225FH for ×16 mode). These two bytes/words are given in the tables 11.1 to 11.8. All
identifiers for manuf actures and device will exhibit odd parity with DQ
the proper device codes when executing the autoselect, A
In case of applying V
on A9, since both Bank 1 and Bank 2 enters Autoselect mode, the simultenous oper ation
ID
must be VIL. (See Tables 11.1 to 11.8.)
1
defined as the parity bit. In order to read
7
can not be executed.
Table 11.1 MBM29DL321TD/BD Sector Group Protection Verify Autoselect Codes
Type A
12
to A
20
Manufacture’s Code X V
Byte
Device
Code
MBM29DL321TD
Word X 2259H
Byte
MBM29DL321BD
XV
XV
A
6
IL
IL
IL
A
1
V
IL
V
IL
V
IL
A
0
V
IL
V
IH
V
IH
*1
A
-1
V
IL
V
IL
V
IL
Code (HEX)
04H
59H
5AH
Word X 225AH
Sector Group Protection
*1: A
is for Byte mode.
-1
Sector Group
Addresses
V
IL
V
IH
V
IL
V
IL
01H
*2
*2: Outputs 01H at protected sector group addresses and outputs 00H at unprotected sector group addresses.
Table 11.2 Expanded Autoselect Code Table
Type Code
Manufacturer’s Code 04H
(B) 59H A
DQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ
A-1/0
000000000000100
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
-1
01011001
MBM29DL321TD
Device
Code
(W)2259H0010001001011001
(B) 5AH A
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
-1
01011010
MBM29DL321BD
(W) 225AH 0010001001011010
A-1/0
Sector Group Protection 01H
000000000000001
(B): Byte mode
(W): Word mode
0
52
MBM29DL32XTD/BD
Table 11.3 MBM29DL322TD/BD Sector Group Protection Verify Autoselect Codes
-80/90/12
Type A
12
to A
20
Manufacture’s Code X V
Byte
Device
Code
MBM29DL322TD
Word X 2255H
Byte
MBM29DL322BD
XV
XV
A
6
IL
IL
IL
A
1
V
IL
V
IL
V
IL
A
0
V
IL
V
IH
V
IH
*1
A
-1
V
IL
V
IL
V
IL
Code (HEX)
04H
55H
56H
Word X 2256H
Sector Group Protection
is for Byte mode.
*1: A
-1
Sector group
addresses
V
IL
V
IH
V
IL
V
IL
01H
*2
*2: Outputs 01H at protected sector group addresses and outputs 00H at unprotected sector group addresses.
Table 11.4 Expanded Autoselect Code Table
Type Code
Manufacturer’s Code 04H
(B) 55H A
DQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ
A-1/0
000000000000100
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
-1
01010101
MBM29DL322TD
Device
Code
(W)2255H0010001001010101
(B) 56H A
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
-1
01010110
MBM29DL322BD
(W)2256H0010001001010110
0
Sector Group Protection 01H
(B): Byte mode
(W): Word mode
A-1/0
000000000000001
53
MBM29DL32XTD/BD
Table 11.5 MBM29DL323TD/BD Sector Group Protection Verify Autoselect Codes
-80/90/12
Type A
12
to A
20
Manufacture’s Code X V
Byte
Device
Code
MBM29DL323TD
Word X 2250H
Byte
MBM29DL323BD
XV
XV
A
6
IL
IL
IL
A
1
V
IL
V
IL
V
IL
A
0
V
IL
V
IH
V
IH
*1
A
-1
V
IL
V
IL
V
IL
Code (HEX)
04H
50H
53H
Word X 2253H
Sector Group Protection
is for Byte mode.
*1: A
-1
Sector group
addresses
V
IL
V
IH
V
IL
V
IL
01H
*2
*2: Outputs 01H at protected sector group addresses and outputs 00H at unprotected sector group addresses.
Table 11.6 Expanded Autoselect Code Table
Type Code
Manufacturer’s Code 04H
(B) 50H A
DQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ
A-1/0
000000000000100
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
-1
01010000
MBM29DL323TD
Device
Code
(W) 2250H 0010001001010000
(B) 53H A
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
-1
01010011
MBM29DL323BD
(W) 2253H 0010001001010011
0
Sector Group Protection 01H
(B): Byte mode
(W): Word mode
A-1/0
000000000000001
54
MBM29DL32XTD/BD
Table 11.7 MBM29DL324TD/BD Sector Group Protection Verify Autoselect Codes
-80/90/12
Type A
12
to A
20
Manufacture’s Code X V
Byte
Device
Code
MBM29DL324TD
Word X 225CH
Byte
MBM29DL324BD
XV
XV
A
6
IL
IL
IL
A
1
V
IL
V
IL
V
IL
A
0
V
IL
V
IH
V
IH
*1
A
-1
V
IL
V
IL
V
IL
Code (HEX)
04H
5CH
5FH
Word X 225FH
Sector Group Protection
is for Byte mode.
*1: A
-1
Sector group
addresses
V
IL
V
IH
V
IL
V
IL
01H
*2
*2: Outputs 01H at protected sector group addresses and outputs 00H at unprotected sector group addresses.
Table 11.8 Expanded Autoselect Code Table
Type Code
Manufacturer’s Code 04H
(B) 5CH A
DQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ
A-1/0
000000000000100
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
-1
01011100
MBM29DL324TD
Device
Code
(W)225CH0010001001011100
(B) 5FH A
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
-1
01011111
MBM29DL324BD
(W)225FH0010001001011111
0
Sector Group Protection 01H
(B): Byte mode
(W): Word mode
A-1/0
000000000000001
55
MBM29DL32XTD/BD
-80/90/12
•Write
Device erasure and progr amming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressab le memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE
to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on
the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
• Sector Group Protection
The MBM29DL32XTD/BD feature hardware sector group protection. This f eature will disab le both program and
erase operations in any combination of twenty five sector groups of memory. (See Tables 9.1 and 9.2). The
sector group protection feature is enab led using programming equipment at the user’s site . The device is shipped
with all sector groups unprotected.
T o activ ate this mode, the programming equipment must f orce V
V
= 11.5 V), CE = VIL and A0 = A6 = VIL, A1 = VIH. The sector group addresses (A20, A19, A18, A17, A16, A15, A14,
ID
A
, and A12) should be set to the sector to be protected. Tables 5.1 to 8.2 define the sector address for each of
13
on address pin A9 and control pin OE, (suggest
ID
the seventy one (71) individual sectors, and tables 9.1 and 9.2 define the sector group address for each of the
twenty five (25) individual group sectors. Programming of the protection circuitry begins on the falling edge of
the WE
pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant
during the WE pulse. See Figures 18 and 26 for sector group protection waveforms and algorithm.
To verify programming of the protection circuitry, the progr amming equipment m ust force V
with CE and OE at V
and A
) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector.
12
and WE at VIH. Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13,
IL
on address pin A9
ID
Otherwise the device will produce “0” for unprotected sector. In this mode, the lower order addresses, except
for A
, A1, and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for A utoselect manuf acturer
0
and device codes. A
requires to apply to VIL on byte mode.
-1
It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.
Performing a read operation at the address location XX02H, where the higher order addresses (A
A
, A16, A15, A14, A13, and A12) are the desired sector group address will produce a logical “1” at DQ0 for a protected
17
, A19, A18,
20
sector group. See Tables 11.1 to 11.8 for Autoselect codes.
• Temporary Sector Group Unprotection
This feature allows temporary unprotection of previously protected sector groups of the MBM29DL32XTD/BD
devices in order to change data. The Sector Group Unprotection mode is activated b y setting the RESET pin to
high voltage (V
the sector group addresses. Once the V
groups will be protected again. Refer to Figures 19 and 27.
). During this mode, formerly protected sector groups can be programmed or erased by selecting
ID
is taken awa y from the RESET pin, all the pre viously protected sector
ID
56
MBM29DL32XTD/BD
-80/90/12
• RESET
Hardware Reset
The MBM29DL32XTD/BD devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse
requirement and has to be kept low (V
) for at least “tRP” in order to properly reset the internal state machine.
IL
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode “t
devices require an additional “t
” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
READY
” before it will allow read access . When the RESET pin is lo w, the devices will
RH
be in the standby mode for the dur ation of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY
output signal should be ignored during the RESET pulse. See Figure 14 for the timing
diagram. Refer to Temporary Sector Group Unprotection for additional functionality.
• Boot Block Sector Protection
The Write Protection function provides a hardware method of protecting certain boot sectors without using VID.
This function is one of two provided by the WP/ACC pin.
If the system asserts V
on the WP/ACC pin, the device disables program and erase functions in the two
IL
“outermost” 8K byte boot sectors independently of whether those sectors were protected or unprotected using
the method described in “Sector Protection/Unprotection”. The two outermost 8K byte boot sectors are the two
sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the
highest addresses in a top-boot-congfigured device.
(MBM29DL32XTD: SA69 and SA70, MBM29DL32XBD: SA0 and SA1)
If the system asserts V
on the WP/ACC pin, the device reverts to whether the two outermost 8K byte boot
IH
sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two
sectors depends on whether they were last protected or unprotected using the method described in “Sector
protection/unprotection”.
• Accelerated Program Operation
MBM29DL32XTD/BD offers accelerated progr am operation which enables the progr amming in high speed.
If the system asserts V
time required for program operation will reduce to about 60%. This function is primarily intended to allow high
speed program, so caution is needed as the sector group will temporarily be unprotected.
The system would use a fact progr am command sequence when programming during acceleration mode .
Set command to fast mode and reset command from f ast mode are not necessary. When the device enters the
acceleration mode, the device automatically set to fast mode. Therefore, the pressent sequence could be
used for programming and detection of completion during acceleration mode.
Removing V
ACC
from the WP/ACC pin returns the device to normal operation. Do not remove V
ACC pin while programming. See Figure 21.
ACC
to the WP/ACC pin, the device automatically enters the acceleration mode and the
ACC
from WP/
57
MBM29DL32XTD/BD
Table 12 MBM29DL32XTD/BD Command Definitions
-80/90/12
Fourth bus
read/write
cycle
555H
555H
AAH
AAH
Fifth bus
write cycle
2AAH
2AAH
55H
55H SA 30H
Sixth bus
write cycle
555H
10H
Command
sequence
Read/Reset
Read/Reset
Autoselect
Program
Program Suspend
Program Resume
Chip Erase
Sector Erase
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Bus
write
cycles
req’d
First bus
write cycle
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Second bus
write cycle
Third bus
write cycle
1XXXHF0H——————————
555H
3
AAAH 555H AAAH
555H
3
AAAH 555H
555H
4
AAAH 555H AAAH
AAH
AAH
AAH
2AAH
2AAH
2AAH
55H
55H
55H
555H
(BA)
555H
(BA)
AAAH
555H
F0HRARD————
90H——————
A0HPAPD————
1 BAB0H——————————
1 BA30H——————————
555H
6
AAAH 555H AAAH AAAH 555H AAAH
555H
6
AAAH 555H AAAH AAAH 555H
AAH
AAH
2AAH
2AAH
55H
55H
555H
555H
80H
80H
Erase Suspend 1 BAB0H——————————
Erase Resume 1 BA30H——————————
Set to
Fast Mode
Fast
Program *1
Reset from
Fast Mode *1
Extended
Sector Group
Protection *2
Query *3
Hi-ROM
Entry
Hi-ROM
Program *4
Hi-ROM
Erase *4
Hi-ROM
Exit *4
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
555H
3
AAAH 555H AAAH
XXXH
2
XXXH
2
BA
BA XXXH
AAH
2AAH
55H
555H
20H——————
A0HPAPD————————
XXXH
90H
F0H————————
4XXXH60HSPA60HSPA40HSPASD————
55H
1
AAH
555H
3
AAAH 555H AAAH
555H
4
AAAH 555H AAAH
555H
6
AAAH 555H AAAH AAAH 555H
555H
4
AAAH 555H
98H——————————
AAH
AAH
AAH
AAH
2AAH
2AAH
2AAH
2AAH
55H
55H
55H
55H
555H
555H
555H
(HRBA
555H
(HRBA
88H——————
A0HPAPD————
80H
)
90HXXXH00H————
)
555H
AAH
2AAH
55H HRA 30H
AAAH
58
MBM29DL32XTD/BD
-80/90/12
Notes: 1. Address bits A
Address (SA), and Bank Address (BA).
2. Bus operations are defined in Tables 3 and 4.
3. RA = Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A
A
will uniquely select any sector.
12
BA = Bank Address (A
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse.
5. SP A = Sector group address to be protected. Set sector group address (SGA) and (A
SD = Sector group protection verify data. Output 01H at protected sector group addresses and output
00H at unprotected sector group addresses.
6. HRA = Address of the Hi-ROM area
29DL32XTD (Top Boot Type) Word Mode: 1F8000H to 1FFFFFH
29DL32XBD (Bottom Boot Type) Word Mode: 000000H to 007FFFH
7. HRBA =Bank Address of the Hi-ROM area
29DL32XTD (Top Boot Type) :A
29DL32XBD (Bottom Boot Type) :A
8. The system should generate the following address patterns:
Word Mode: 555H or 2AAH to addresses A
Byte Mode: AAAH or 555H to addresses A–1 and A0 to A
9. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
to A20 = X = “H” or “L” for all address commands e xcept or Program Address (PA), Sector
11
, A19, A18, A17, A16, A15, A14, A13, and
20
to A20)
15
, A1, A0) = (0, 1, 0).
6
Byte Mode: 3F0000H to 3FFFFFH
Byte Mode: 000000H to 00FFFFH
15
= A16= A
15
= A16= A
to A
0
17
17
= A
= A
10
18
= A19 = A
18
= A19 = A
10
20
20
= 1
= 0
*1:This command is valid while Fast Mode.
*2:This command is valid while RESET
*3:The valid addresses are A
to A0.
6
= VID.
*4:This command is valid while Hi-ROM mode.
59
MBM29DL32XTD/BD
COMMAND DEFINITIONS
■
-80/90/12
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the
read mode. Some commands are required Bank Address (BA) input. When command sequences are inputed
to bank being read, the commands have priority than reading. Table 12 defines the valid register command
sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the
Sector Erase operation is in progress. Also the Progr am Suspend (B0H) and Program Resume (30H) commands
are valid only while the Program operation is in prog ress. Moreover both Read/Reset commands are functionally
equivalent, resetting the device to the read mode . Please note that commands are alwa ys written at DQ
and DQ
to DQ15 bits are ignored.
8
• Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/
Reset operation is initiated by writing the Read/Reset command sequence into the command register.
Microprocessor read cycles retrieve arra y data from the memory . The de vices remain enabled f or reads until the
command register contents are altered.
The devices will automatically power-up in the Read/Reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures
that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
to DQ7
0
• Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM
programmers typically access the signature codes by raising A
voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
The Autoselect command sequence is initiated by first writing two unloc k cycles. This is f ollowed b y a third write
cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device
codes can be read from the bank, and an actual data of memory cell can be read from the another bank.
Following the command write, a read cycle from address (BA)00H retrieves the manufacture code of 04H. A
read cycle from address (BA)01H for ×16((BA)02H for ×8) returns the device code (MBM29DL321TD = 59H and
MBM29DL321BD = 5AH for ×8 mode; MBM29DL321TD = 2259H and MBM29DL321BD = 225AH for ×16 mode).
(MBM29DL322TD = 55H and MBM29DL322BD = 56H for ×8 mode; MBM29DL322TD = 2255H and
MBM29DL322BD = 2256H for ×16 mode). (MBM29DL323TD = 50H and MBM29DL323BD = 53H for ×8 mode;
MBM29DL323TD = 2250H and MBM29DL323BD = 2253H for ×16 mode). (MBM29DL324TD = 5CH and
MBM29DL324BD = 5FH for ×8 mode; MBM29DL324TD = 225CH and MBM29DL324BD = 225FH for ×16 mode).
(See Tables 11.1 to 11.8.)
All manufacturer and de vice codes will exhibit odd parity with DQ
or unprotection) will be informed by address (BA)02H for ×16 ((BA)04H for ×8). Scanning the sector group
addresses (A
device output DQ
, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at
20
for a protected sector group. The programming verification should be performed by verify
0
sector group protection on the protected sector. (See Tables 8 and 9.)
to a high voltage. However, multiplexing high
9
defined as the parity bit. Sector state (protection
7
60
MBM29DL32XTD/BD
-80/90/12
The manufacture and device codes can be allowed reading from selected bank. To read the manufacture and
device codes and sector protection status from non-selected bank, it is necessary to write Read/Reset command
sequence into the register and then Autoselect command should be written into the bank to be read.
If the software (program code) for Autoselect command is stored into the Flash memory, the device and
manufacture codes should be read from the other bank where is not contain the software.
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command
sequence.
• Byte/Word Programming
The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle
operation. There are two “unlock” write cycles. These are followed by the program set-up command and data
write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is
latched on the rising edge of CE
happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,
the system is not required to provide further controls or timings. The device will automatically provide adequate
internally generated program pulses and verify the programmed cell margin.
or WE, whichever happens first. The rising edge of CE or WE (whichever
The system can determine the status of the program operation by using DQ
(Data Polling), DQ6 (Toggle Bit),
7
or RY/BY. The Data Polling and T oggle Bit must be perf ormed at the memory location which is being programmed.
The automatic programming operation is completed when the data on DQ
is equivalent to data written to this
7
bit at which time the devices return to the read mode and addresses are no longer latched. (See Table 13,
Hardware Sequence Flags.) Therefore, the devices require that a valid address to the devices be supplied by
the system at this particular instance of time. Hence, Data
Polling must be performed at the memory location
which is being programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so ma y either hang up the device or result in an apparent success
according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
Figure 22 illustrates the Embedded Program
TM
Algorithm using typical command strings and bus operations.
•Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the de vice prior to erase. Upon ex ecuting the Embedded Erase
Algorithm command sequence the devices will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ
(Data Polling), DQ6 (Toggle Bit), or
7
RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command
sequence and terminates when the data on DQ
is “1” (See Write Operation Status section.) at which time the
7
device returns to read the mode.
Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)
Figure 23 illustrates the Embedded Erase
TM
Algorithm using typical command strings and bus operations.
61
MBM29DL32XTD/BD
-80/90/12
• Sector Erase
Sector erase is a six bus cycle operation. There are two “unloc k” write cycles. These are f ollow ed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of CE
happens later, while the command (Data = 30H) is latched on the rising edge of CE or WE which happens first.
After time-out of “t
” from the rising edge of the last sector erase command, the sector erase operation will begin.
TOW
Multiple sectors may be erased concurrently b y writing the six bus cycle operations on Table 12. This sequence
is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently
erased. The time between writes must be less than “t
” otherwise that command will not be accepted and
TOW
erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this
condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of “t
from the rising edge of last CE or WE whichever happens first will initiate the execution of the Sector Erase
command(s). If another falling edge of CE or WE, whichever happens first occurs within the “t
window the timer is reset. (Monitor DQ
DQ
, Sector Erase Timer .) Any command other than Sector Erase or Erase Suspend during this time-out period
3
to determine if the sector erase timer window is still open, see section
3
will reset the devices to the read mode, ignoring the previous command string. Resetting the devices once
ex ecution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow
them to complete. (Refer to the Write Operation Status section f or Sector Er ase Timer oper ation.) Loading the
sector erase buffer may be done in any sequence and with any number of sectors (0 to 38).
or WE whichever
” time-out
TOW
TOW
”
Sector erase does not require the user to program the de vices prior to erase. The devices automatically program
all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide an y
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ
RY/BY
.
The sector erase begins after the “t
” time out from the rising edge of CE or WE whichever happens first for
TOW
the last sector erase command pulse and terminates when the data on DQ
section.) at which time the devices return to the read mode. Data
polling and Toggle Bit must be performed at
(Data Polling), DQ6 (Toggle Bit), or
7
is “1” (See Write Operation Status
7
an address within any of the sectors being erased.
Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogr amming)] × Number of Sector
Erase
In case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not perf orme.
Figure 23 illustrates the Embedded Erase
TM
Algorithm using typical command strings and bus operations.
• Erase Suspend/Resume
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perf orm data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Er ase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
(B0H) during the Sector Erase time-out results in immediate termination of the time-out period and suspension
of the erase operation.
Writing the Erase Resume command (30H) resumes the erase operation. The bank addresses of sector being
erasing or suspending should be set when writting the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maxim um
of “t
” to suspend the erase operation. When the devices have entered the erase-suspended mode, the
SPD
62
MBM29DL32XTD/BD
output pin will be at Hi-Z and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must
RY/BY
use the address of the erasing sector for reading DQ
and DQ7 to determine if the erase operation has been
6
-80/90/12
suspended. Further writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the devices def ault to the erase-suspend-read mode . Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successiv ely reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ
to toggle. (See the section on DQ2.)
2
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in the regular Progr am mode e xcept that the data must
be programmed to sectors that are not erase-suspended. Successively reading from the er ase-suspended sector
while the devices are in the erase-suspend-program mode will cause DQ
suspended Program operation is detected by the RY/BY
(DQ
) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address
6
while DQ
can be read from any address within bank being erase-suspended.
6
output pin, Data polling of DQ7 or by the Toggle Bit I
to toggle. The end of the erase-
2
T o resume the operation of Sector Er ase, the Resume command (30H) should be written to the bank being erase
suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend
command can be written after the chip has resumed erasing.
63
MBM29DL32XTD/BD
• Extended Command
(1) Fast Mode
MBM29DL32XTD/BD has Fast Mode function. This mode dispenses with the initial two unclock cycles
required in the standard program command sequence by writing Fast Mode command into the command
register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in
standard program command. (Do not write erase command in this mode.) The read operation is also e xecuted
after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command
register. The first cycle must contain the bank address. (Refer to the Figure 28.) The V
required even CE
(2) Fast Programming
During Fast Mode, the prog ramming can be executed with two b us cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0H) and data write cycles (PA/PD). (Refer to
the Figure 28.)
(3) Extended Sector Group Protection
In addition to normal sector group protection, the MBM29DL32XTD/BD has Extended Sector Group
Protection as extended function. This function enable to protect sector group by forcing V
and write a command sequence. Unlike conv entional procedure, it is not necessary to force V
timing for control pins. The only RESET
sector group protection requires V
the set-up command (60H) into the command register. Then, the sector g roup addresses pins (A
A
, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to the sector group to be protected
17
(recommend to set V
(60H). A sector group is typically protected in 250 µs. To verify programming of the protection circuitry , the
sector group addresses pins (A
be set and write a command (40H). Following the command write, a logical “1” at device output DQ
produce for protected sector in the read operation. If the output data is logical “0”, please repeat to write
extended sector group protection command (60H) again. To terminate the operation, it is necessary to set
RESET
pin to VIH. (Refer to the Figures 20 and 29.)
= VIH during Fast Mode.
ID
for the other addresses pins), and write extended sector group protection command
IL
, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should
20
-80/90/12
active current is
CC
on RESET pin
ID
and control
ID
pin requires VID for sector group protection in this mode. The e xtended
on RESET pin. With this condition, the operation is initiated by writing
, A19, A18,
20
will
0
(4) CFI (Common Flash Memory Interface)
The CFI (Common Flash Memory Interface) specification outlines device and host system software
interrogation handshake which allows specific vendor-specified software algorithms to be used for entire
families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backwardcompatible software support for the specified flash device families. Refer to CFI specification in detail.
The operation is initiated by writing the query command (98H) into the command register. The bank address
should be set when writing this command. Then the device information can be read from the bank, and an
actual data of memory cell be read from the another bank. Following the command write, a read cycle from
specific address retrives device inf ormation. Please note that output data of upper byte (DQ
in word mode (16 bit) read. Refer to the CFI code tab le . To terminate operation, it is necessary to write the
read/reset command sequence into the register. (See Table 15.)
64
to DQ15) is “0”
8
MBM29DL32XTD/BD
-80/90/12
• Hidden ROM (Hi-ROM) Region
The Hi-ROM feature provides a Flash memory region that the system may access through a new command
sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the
device with the ESN protected against modification. Once the Hi-ROM region is protected, any further
modification of that region is impossible. This ensures the security of the ESN once the product is shipped to
the field.
The Hi-ROM region is 64K bytes in length and is stored at the same address of the 8KB ×8 sectors. The
MBM29DL32XTD occupies the address of the byte mode 3F0000H to 3FFFFFH (word mode 1F8000H to
1FFFFFH) and the MBM29DL32XBD type occupies the address of the byte mode 000000H to 00FFFFH (word
mode 000000H to 007FFFH). After the system has written the Enter Hi-ROM command sequence, the system
may read the Hi-ROM region b y using the addresses normally occupied by the boot sectors. That is , the device
sends all commands that would normally be sent to the boot sectors to the Hi-ROM region. This mode of operation
continues until the system issues the Exit Hi-ROM command sequence, or until power is removed from the
device. On po wer-up, or f ollowing a hardware reset, the de vice rev erts to sending commands to the boot sectors.
• Hidden ROM (Hi-ROM) Entry Command
MBM29DL32XTD/BD has a Hidden ROM area with One Time Protect function. This area is to enter the security
code and to unable the change of the code once set. Program/erase is possib le in this area until it is protected.
However, once it is protected, it is impossible to unprotect, so please use this with caution.
Hidden ROM area is 64K Byte and in the same address area of 8KB sector . The address of top boot is 3F0000H
to 3FFFFFH at byte mode (1F8000H to 1FFFFFH at word mode) and the bottom boot is 000000H to 00FFFFH
at byte mode (000000H to 007FFFH at word mode). These areas are normally the boot block area (8KB ×8
sector). Therefore, write the Hidden ROM entry command sequence to enter the Hidden ROM area. It is called
as Hidden ROM mode when the Hidden ROM area appears.
Sector other than the boot block area could be read during Hidden ROM mode. Read/program/earse of the
Hidden ROM area is possible during Hidden ROM mode . Write the Hidden R OM reset command sequence to
exit the Hidden ROM mode . The bank address of the Hidden ROM should be set on the third cycle of this reset
command sequence.
In case of MBM29DL321TD/BD, whose Bank 1 size is 0.5 Mbit, the simultaneous operation cannot execute
multi-function mode between the Hidden ROM area and Bank 2 Region.
• Hidden ROM (Hi-ROM) Program Command
T o program the data to the Hidden R OM area, write the Hidden ROM program command sequence during Hidden
ROM mode. This command is same as the program command in the past except to write the command during
Hidden ROM mode. Therefore the detection of completion method is the same as in the past, using the DQ
data poling, DQ
other than the Hidden ROM area is selected to program, the data of the address will be changed.
toggle bit and RY/BY pin. Need to pa y attention to the address to be programmed. If the address
6
7
• Hidden ROM (Hi-ROM) Erase Command
To erase the Hidden ROM area, write the Hidden ROM erase command sequence during Hidden ROM mode.
This command is same as the sector erase command in the past except to write the command during Hidden
ROM mode. Theref ore the detection of completion method is the same as in the past, using the DQ
DQ
toggle bit and RY/BY pin. Need to pay attention to the sector address to be erased. If the sector address
6
other than the Hidden ROM area is selected, the data of the sector will be changed.
data poling,
7
65
MBM29DL32XTD/BD
-80/90/12
• Hidden ROM (Hi-ROM) Protect Command
There are two methods to protect the Hidden ROM area. One is to write the sector group protect setup
command(60H), set the sector address in the Hidden ROM area and (A
group protect command(60H) during the Hidden ROM mode. The same command sequence could be used
because except that it is in the Hidden ROM mode and that it does not apply high voltage to RESET pin, it is
the same as the extension sector group protect in the past. Please refer to “Function Explanation
Command
(3) Extentended Sector Group Protection” for details of extention sector group protect setting.
6
, A1, A0) = (0,1,0), and write the sector
Extended
The other is to apply high voltage (V
1
A
, A0) = (0,1,0), and apply the write pulse during the Hidden ROM mode. To verify the protect circuit, apply high
voltage (V
When “1” appears to DQ
ID
) to A9, specify (A6, A1, A0) = (0,1,0) and the sector address in the Hidden ROM area, and read.
, the protect setting is completed. “0” will appear to DQ0 if it is not protected. Please
0
ID
) to A9 and OE, set the sector address in the Hidden ROM area and (A6,
apply write pulse agian. The same command sequence could be used for the above method because other than
the Hidden ROM mode, it is the same as the sector group protect in the past. Please ref er to “Function Explanation
Secor Group Protection
” for details of sector group protect setting
Other sector group will be effected if the address other than the Hidden ROM area is selected for the sectoer
group address, so please be carefull. Once it is protected, protection can not be cancelled, so please pa y closest
attention.
• Write Operation Status
Detailed in Table 13 are all the status flags that can determine the status of the bank for the current mode
operation. The read operation from the bank where is not operate Embedded Algorithm returns a data of memory
cell. These bits offer a method for determining whether a Embedded Algorithm is completed properly. The
information on DQ
read, then the DQ
consectively read. This allows the user to determine which sectors are erasing and which are not.
The status flag is not output from bank (non-busy bank) not ex ecuting Embedded Algorithm. For e xample, there
is bank (busy bank) which is now e xecuting Embedded Algorithm. When the read sequence is [1] <b usy bank>,
[2] <non-busy bank>, [3] <busy bank>, the DQ
memory cell is outputted. In the erase-suspend read mode with the same read sequence, DQ
in the [1] and [3].
is address sensitive. This means that if an address from an erasing sector is consectively
2
bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is
2
is toggling in the case of [1] and [3]. In case of [2], the data of
6
will not be toggled
6
In the erase suspend read mode, DQ
outputted.
66
is toggled in the [1] and [3]. In case of [2], the data of memory cell is
2
MBM29DL32XTD/BD
-80/90/12
Table 13 Hardware Sequence Flags
In Progress
Exceeded
Time Limits
Status DQ
Embedded Program Algorithm DQ
DQ
7
Toggle 0 0 1
7
6
DQ5DQ
DQ
3
2
Embedded Erase Algorithm 0 Toggle 0 1 Toggle*
Program
Program Suspend Read
(Program Suspended Sector)
Data Data Data Data Data
Suspended
Mode
Erase
Suspended
Mode
Embedded Program Algorithm DQ
Program Suspend Read
(Non-Program Suspended Sector)
Erase Suspend Read
(Erase Suspended Sector)
Erase Suspend Read
(Non-Erase Suspended Sector)
Erase Suspend Program
(Non-Erase Suspended Sector)
Data Data Data Data Data
1100Toggle
Data Data Data Data Data
Toggle 0 0 1*
DQ
7
Toggle 1 0 1
7
Embedded Erase Algorithm 0 Toggle 1 1 N/A
Erase
Suspended
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
Toggle 1 0 N/A
DQ
7
*: Successive reads from the erasing or erase-suspend sector will cause DQ
suspend sector address will indicate logic “1” at the DQ
Note: 1.DQ
and DQ1 are reserve pins for future use.
0
2.DQ
is Fujitsu internal use only.
4
bit.
2
to toggle. Reading from non-erase
2
67
MBM29DL32XTD/BD
7
•DQ
-80/90/12
Data Polling
The MBM29DL32XTD/BD devices f eature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the
devices will produce the complement of the data last written to DQ
Algorithm, an attempt to read the device will produce the true data last written to DQ
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ
for Data Polling (DQ
) is shown in Figure 24.
7
For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse
sequence.
. Upon completion of the Embedded Program
7
. During the Embedded
7
output. Upon completion of the
7
output. The flowchart
7
For chip erase and sector erase , the Data
Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling m ust be perf ormed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid.
If a program address falls within a protected sector, Data
Polling on DQ7 is active for approximately 1 µs, then
that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for
erasing are protected, Data
Polling on DQ7 is active for appro ximately 400 µs, then the bank returns to read mode.
Once the Embedded Algorithm operation is close to being completed, the MBM29DL32XTD/BD data pins (DQ
may change asynchronously while the output enable (OE) is asserted low. This means that the devices are
driving status information on DQ
Depending on when the system samples the DQ
has completed the Embedded Algorithm operation and DQ
may be still invalid. The valid data on DQ
at one instant of time and then that byte’ s valid data at the ne xt instant of time.
7
output, it may read the status or valid data. Ev en if the de vice
7
has a valid data, the data outputs on DQ0 to DQ6
7
to DQ7 will be read on the successive read attempts.
0
The Data Polling f eature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See Table 13.)
See Figure 9 for the Data
6
•DQ
Polling timing specifications and diagrams.
Toggle Bit I
The MBM29DL32XTD/BD also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
)
7
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE
the devices will result in DQ
cycle is completed, DQ
toggling between one and zero . Once the Embedded Program or Er ase Algorithm
6
will stop toggling and valid data will be read on the next successive attempts. During
6
toggling) data from
programming, the T oggle Bit I is v alid after the rising edge of the fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 µs and then stop
toggling without the data having changed. In erase, the de vices will erase all the selected sectors e xcept f or the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs
and then drop back into read mode, having changed none of the data.
Either CE
cause the DQ
or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
to toggle.
6
68
MBM29DL32XTD/BD
-80/90/12
The system can use DQ
is actively erasing (that is, the Embedded Er ase Algorithm is in progress), DQ
Erase Suspend mode, DQ
DQ
to toggle.
6
To operate toggle bit function properly, CE
to determine whether a sector is actively erasing or is erase-suspended. When a bank
6
toggles. When a bank enters the
6
stops toggling. Successive read cycles during the erase-suspend-program cause
6
or OE must be high when bank address is changed.
See Figure 10 for the Toggle Bit I timing specifications and diagrams.
5
•DQ
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).
The OE
The DQ
and WE pins will control the output disable functions as described in Tables 3 and 4.
failure condition ma y also appear if a user tries to program a non blank location without erasing. In this
5
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ
DQ
bit will indicate a “1.” Please note that this is not a device f ailure condition since the devices were incorrectly
5
used. If this occurs, reset the device with command sequence.
3
•DQ
will produce a “1”. This is a failure condition which indicates that the program or erase
5
bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the
7
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data
Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ
is high (“1”) the internally controlled
3
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data
Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ
prior to and following each subsequent Sector Erase command. If DQ3 were high on
3
the second status check, the command may not have been accepted.
See Table 13: Hardware Sequence Flags.
2
•DQ
Toggle Bit II
This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
devices are in the erase-suspended-read mode, successiv e reads from the er ase-suspended sector will cause
DQ
to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
2
address of the non-erase suspended sector will indicate a logic “1” at the DQ
to toggle during the Embedded Erase Algorithm. If the
2
bit.
2
DQ
is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
6
Program operation is in progress. The behavior of these two status bits, along with that of DQ
, is summarized
7
as follows:
69
MBM29DL32XTD/BD
-80/90/12
For example, DQ
(DQ
toggles while DQ6 does not.) See also Table 14 and Figure 12.
2
Furthermore, DQ
mode, DQ
2
To operate toggle bit function properly, CE
and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
2
can also be used to determine which sector is being erased. When the device is in the erase
2
toggles if this bit is read from an erasing sector.
or OE must be high when bank address is changed.
Table 14 Toggle Bit Status
Mode DQ
Program DQ
7
7
DQ
6
Toggle 1
DQ
2
Erase 0 Toggle Toggle (Note)
Erase-Suspend Read
(Erase-Suspended Sector)
Erase-Suspend Program DQ
Note: Successive reads from the erasing or erase-suspend sector will cause DQ
erase suspend sector address will indicate logic “1” at the DQ
11Toggle
7
Toggle 1 (Note)
to toggle. Reading from non-
2
bit.
2
•RY/BY
Ready/Busy
The MBM29DL32XTD/BD provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/
write or erase operation. When the R Y/BY
commands. If the MBM29DL32XTD/BD are placed in an Erase Suspend mode, the RY/BY
pin is low , the devices will not accept an y additional program or erase
output will be high.
During programming, the RY/BY pin is driv en low after the rising edge of the fourth write pulse. During an erase
operation, the R Y/BY pin is driv en lo w after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during the RESET
pulse. Refer to Figures 13 and 14 f or a detailed timing diagr am. The R Y/BY
pin is pulled high in standby mode.
Since this is an open-drain output, RY/BY
pins can be tied together in parallel with a pull-up resistor to VCC.
• Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode fo r the MBM29DL32XTD/BD de vices . When
this pin is driven high, the devices operate in the w ord (16-bit) mode. The data is read and prog rammed at DQ
to DQ
becomes the lowest address bit and DQ
an 8-bit operation and hence commands are written at DQ
. When this pin is driven low , the de vices operate in b yte (8-bit) mode. Under this mode , the DQ15/A-1 pin
15
to DQ14 bits are tri-stated. Howev er , the command b us cycle is alwa ys
8
to DQ7 and the DQ8 to DQ15 bits are ignored. Refer
0
to Figures 15, 16 and 17 for the timing diagram.
• Data Protection
The MBM29DL32XTD/BD are designed to offer protection against accidental erasure or progr amming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
and power-down transitions or system noise.
power-up
CC
0
70
MBM29DL32XTD/BD
-80/90/12
•Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-do wn, a write cycle is locked out for VCC less
than V
Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the V
is greater than V
unintentional writes when V
(min). If VCC < V
LKO
LKO
, the command register is disabled and all internal program/erase circuits are disabled.
LKO
level
CC
. It is the users responsibility to ensure that the control pins are logically correct to prevent
is above V
CC
LKO
(min).
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
• Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
• Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
• Power-Up Write Inhibit
Po wer-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
71
MBM29DL32XTD/BD
-80/90/12
Table 15 Common Flash Memory Interface Code
Description A
Query-unique ASCII string
“QRY”
to A
0
10h
11h
DQ0 to DQ
6
12h
Primary OEM Command Set
2h: AMD/FJ standard type
Address for Primary
Extended Table
Alternate OEM Command
Set (00h = not applicable)
Address for Alternate OEM
Extended Table
V
Min. (write/erase)
CC
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh 0027h
D7-4: volt, D3-0: 100 mvolt
V
Max. (write/erase)
CC
1Ch 0036h
D7-4: volt, D3-0: 100 mvolt
V
Min. voltage 1Dh 0000h
PP
V
Max. voltage 1Eh 0000h
PP
Typical timeout per single
byte/word write 2
N
µs
Typical timeout for Min. size
buffer write 2
N
µs
T ypical timeout per individual
block erase 2
N
ms
Typical timeout for full chip
erase 2
N
ms
Max. timeout for byte/word
N
write 2
times typical
Max. timeout for buffer write
N
2
times typical
Max. timeout per individual
block erase 2
N
times typical
Max. timeout for full chip
erase 2
Device Size = 2
N
times typical
N
byte
Flash Device Interface
description
Max. number of byte in
multi-byte write = 2
N
Number of Erase Block
1Fh 0004h
20h 0000h
21h 000Ah
22h 0000h
23h 0005h
24h 0000h
25h 0004h
26h 0000h
27h 0016h
28h
29h
2Ah
2Bh
2Ch 0002h
Regions within device
Erase Block Region 1
Information
2Dh
2Eh
2Fh
30h
Erase Block Region 2
Information
31h
32h
33h
34h
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
0002h
0000h
0000h
0000h
0007h
0000h
0020h
0000h
003Eh
0000h
0000h
0001h
15
Query-unique ASCII string
“PRI”
Description A
to A
0
40h
41h
6
42h
Major version number, ASCII 43h 0031h
Minor version number, ASCII 44h 0031h
Address Sensitive Unlock
45h 0000h
0h = Required
1h = Not Required
Erase Suspend
46h 0002h
0h = Not Supported
1h = To Read Only
2h = To Read & Write
Sector Protection
47h 0001h
0h = Not Supported
X = Number of sectors in per
group
Sector Temporary
48h 0001h
Unprotection
00h = Not Supported
01h = Supported
Sector Protection Algorithm 49h 0004h
Number of Sector for Bank 2
4Ah 00XXh
00h = Not Supported
3Fh = MBM29DL321TD
38h = MBM29DL322TD
30h = MBM29DL323TD
20h = MBM29DL324TD
3Fh = MBM29DL321BD
38h = MBM29DL322BD
30h = MBM29DL323BD
20h = MBM29DL324BD
Burst Mode Type
4Bh 0000h
00h = Not Supported
Page Mode Type
4Ch 0000h
00h = Not Supported
ACC (Acceleration) Supply
4Dh 0085h
Minimum
00h = Not Supported,
D7-4: volt, D3-0: 100 mvolt
ACC (Acceleration) Supply
4Eh 0095h
Maximum
00h = Not Supported,
D7-4: volt, D3-0: 100 mvolt
Boot Type
4Fh 00XXh
02h = MBM29DL32XBD
03h = MBM29DL32XTD
DQ0 to DQ
0050h
0052h
0049h
15
72
FLOW CHART
■
EMBEDDED ALGORITHMS
Increment Address
MBM29DL32XTD/BD
Start
Write Program Command
Sequence
(See below)
Data Polling Device
No
Last Address
?
Yes
-80/90/12
Program Command Sequence* (Address/Command):
* :The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
Figure 22 Embedded ProgramTM Algorithm
Programming Completed
555H/AAH
2AAH/55H
555H/A0H
Program Address/Program Data
73
MBM29DL32XTD/BD
EMBEDDED ALGORITHMS
Data Polling or Toggle Bit
-80/90/12
Start
Write Erase Command
Sequence
(See below)
Successfully Completed
Erasure Completed
Chip Erase Command Sequence*
(Address/Command):
555H/AAH
2AAH/55H
555H/80H
555H/AAH
2AAH/55H
555H/10H
Individual Sector/Multiple Sector*
Erase Command Sequence
(Address/Command):
555H/AAH
2AAH/55H
555H/80H
555H/AAH
2AAH/55H
Sector Address/30H
Sector Address/30H
Sector Address/30H
Additional sector
erase commands
are optional.
74
* :The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
Figure 23 Embedded EraseTM Algorithm
No
Start
Read
(DQ 0 to DQ 7)
Addr. = VA
DQ 7 = Data?
No
DQ 5 = 1?
Yes
Read
(DQ 0 to DQ 7)
Addr. = VA
MBM29DL32XTD/BD
VA = Byte address for programming
= Any of the sector addresses within
Yes
the sector being erased during
sector erase or multiple sector
erases operation
= Any of the sector addresses within
the sector not being protected
during chip erase
-80/90/12
DQ 7 = Data?
Fail
Yes
No
Pass
Note: DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 24 Data Polling Algorithm
75
MBM29DL32XTD/BD
-80/90/12
Start
Read
(DQ
0 to DQ 7)
Addr. = VA
VA = Bank address being executed
Embedded Algorithm.
No
Yes
Yes
No
Yes
Pass
No
DQ 6 = Toggle
?
DQ 5 = 1?
Read
(DQ 0 to DQ 7)
Addr. = VA
DQ 6 = Toggle
?
Fail
Note: DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as
DQ
changing to “1” .
5
Figure 25 Toggle Bit Algorithm
76
MBM29DL32XTD/BD
Start
Setup Sector Group Addr.
(A20, A19, A18, A17, A16, A15, A14, A13, A12)
PLSCNT = 1
=
V ID, A 9
=
=
V ID,
V IH
=
V IH
OE
A
6
= CE =
V IL, RESET
A 0
=
V IL, A 1
Activate WE Pulse
-80/90/12
* :A-1 is V
on byte mode.
IL
Increment PLSCNT
No
PLSCNT = 25?
Yes
Remove V ID from A 9
Write Reset Command
Device Failed
No
Time out 100 µs
WE
=
V IH, CE
= OE =
A 0
Yes
No
=
V IL
V IL
V IL,
)*
(A 9 should remain V ID)
Read from Sector Group
(Addr. = SGA,
A
1
=
V IH
, A 6 =
Data = 01H?
Protect Another Sector
Group ?
Remove V ID from A 9
Write Reset Command
Sector Group Protection
Completed
Yes
Figure 26 Sector Group Protection Algorithm
77
MBM29DL32XTD/BD
-80/90/12
Start
RESET = VID
(Note 1)
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector Group
Unprotection Completed
(Note 2)
Notes: 1. All protected sector groups are unprotected.
2. All previously protected sector groups are protected once again.
Figure 27 Temporary Sector Group Unprotection Algorithm
78
FAST MODE ALGORITHM
MBM29DL32XTD/BD
Start
555H/AAH
-80/90/12
Increment Address
2AAH/55H
555H/20H
XXXH/A0H
Program Address/Program Data
Data Polling Device
Verify Byte?
Yes
No
Last Address
?
Yes
Programming Completed
No
Set Fast Mode
In Fast Program
(BA) XXXH/90H
Note: The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
Figure 28 Embedded ProgramTM Algorithm for Fast Mode
Reset Fast Mode
XXXH/F0H
79
MBM29DL32XTD/BD
-80/90/12
Start
Device is Operating in
Temporary Sector Group
Unprotection Mode
Increment PLSCNT
RESET = V
Wait to 4 µs
No
Extended Sector Group
Protection Entry?
To Setup Sector Group
Protection Write XXXH/60H
PLSCNT = 1
To Sector Group Protection
Write SGA/60H
= VIL, A1 = VIH, A6 = VIL)
(A
0
Time Out 250 µs
To Verify Sector Group
Protection Write SGA/40H
= VIL, A1 = VIH, A6 = VIL)
(A
0
ID
Yes
Setup Next Sector Group
Address
80
No
PLSCNT = 25?
Yes
Remove VID from RESET
Write Reset Command
Device Failed
Figure 29 Extended Sector Group Protection Algorithm
No
Read from Sector Group
(A
Address
= VIL, A1 = VIH, A6 = VIL)
0
Data = 01H?
Yes
Protection Other Sector
Group ?
No
Remove
VID from RESET
Write Reset Command
Sector Group Protection
Completed
Yes
ORDERING INFORMATION
■
MBM29DL32XTD/BD
-80/90/12
Standard Products
Fujitsu standard products are available in several packages. The order number is formed by a combination of:
MBM29DL32X T D 80 PFTN
PACKAGE TYPE
PFTN = 48-Pin Thin Small Outline Package
(TSOP) Standard Pinout
PFTR = 48-Pin Thin Small Outline Package
(TSOP) Reverse Pinout
PBT = Fine pitch Ball Grid Array
Package (FBGA)
Valid Combinations
MBM29DL321TD/BD
MBM29DL322TD/BD
MBM29DL323TD/BD
MBM29DL324TD/BD
SPEED OPTION
See Product Selector Guide
DEVICE REVISION
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
MBM29DL32X
32Mega-bit (4M × 8-Bit or 2M × 16-Bit) CMOS Dual Operation Flash Memory
3.0 V-only Read, Program, and Erase
Valid Combinations
Valid Combinations list configurations planned to
80
90
12
PFTN
PFTR
PBT
be supported in volume for this device. Consult
the local Fujitsu sales office to confirm availability
of specific valid combinations and to check on
newly released combinations.
81
MBM29DL32XTD/BD
PACKAGE DIMENSIONS
■
-80/90/12
48-pin plastic TSOP(I)
(FPT-48P-M19)
LEAD No.
1
INDEX
"A"
24 25
20.00±0.20
(.787±.008)
18.40±0.20
*
(.724±.008)
0.10(.004)
19.00±0.20
(.748±.008)
C
1996 FUJITSU LIMITED F48029S-2C-2
48
0.15±0.05
(.006±.002)
0.50±0.10
(.020±.004)
Details of "A" part
0.15(.006) 0.25(.010)
*
12.00±0.20
(.472±.008)
11.50REF
(.460)
0.50(.0197)
TYP
* Resin Protrusion. (Each Side: 0.15 (.006)Max)
0.15(.006)
MAX
0.35(.014)
MAX
+0.10
–0.05
1.10
+.004
.043
–.002
(Mounting height)
0.05(0.02)MIN
0.20±0.10
(.008±.004)
(STAND OFF)
0.10(.004)
M
Dimensions in mm (inches)
48-pin plastic TSOP(I)
(FPT-48P-M20)
LEAD No.
1
INDEX
24 25
19.00±0.20
(.748±.008)
0.10(.004)
18.40±0.20
*
(.724±.008)
20.00±0.20
(.787±.008)
C
1996 FUJITSU LIMITED F48030S-2C-2
"A"
48
0.50±0.10
(.020±.004)
0.15±0.10
(.006±.002)
Details of "A" part
0.15(.006) 0.25(.010)
0.50(.0197)
TYP
11.50(.460)REF
*
12.00±0.20(.472±.008)
* Resin Protrusion. (Each Side: 0.15 (.006)Max)
0.15(.006)
MAX
0.35(.014)
MAX
0.20±0.10
(.008±.004)
0.10(.004)
0.05(0.02)MIN
(STAND OFF)
1.10
.043
(Mounting height)
M
+0.10
–0.05
+.004
–.002
Dimensions in mm (inches)
82
(Continued)
(Continued)
57-pin plastic FBGA
(BGA-57P-M01)
INDEX
13.95±0.05(.549±.002)
7.95±0.05
(.313±.002)
+0.15
–0.10
1.05
+.006
.041 –.004
(5.60(.220))
(4.00(.157))
MBM29DL32XTD/BD
(8.80(.346))
(7.20(.283))
(Mounting height)
0.80(.031)
TYP
(5.60(.220))
0.80(.031)
TYP
-80/90/12
8
7
6
5
4
3
2
1
C0.25(.010)
0.10(.004)
C
1998 FUJITSU LIMITED B57001S-1C-1
0.36±0.10
(.014±.004)
(Stand off)
MLKJHGFEDCBA
57-Ø0.45±0.05
(57-Ø.018±.002)
0.08(.003)
Dimensions in mm (inches)
INDEX BALL
M
83
MBM29DL32XTD/BD
-80/90/12
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUR OPE GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and
measurement equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.
F9909
FUJITSU LIMITED Printed in Japan
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