FUJITSU MB90590, MB90590G DATA SHEET

查询MB90591供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

16-bit Proprietary Microcontroller

CMOS

F2MC-16LX

MB90591/F591A/594/594G/F594A/F594G
MB90V590A/V590G

DESCRIPTION

■■■■

The MB90590/590G series with two FULL-CAN*1 interfaces and FLASH ROM is especially designed for auto­motive and industrial applications. Its main features are tw o on board CAN Interfaces , which conform to V2.0 P art
A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a
normal full CAN approach.
The instruction set of F
instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instruc­tions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing
long word data.
The MB90590/590G series has peripheral resources of 8/10-bit A/D converters, UAR T (SCI), e xtended I/O serial
interface, 8/16-bit PPG timer, I/O timer (input capture (ICU), output compare (OCU)), stepping motor controller,
and sound generator.

*1: Controller Area Network (CAN) - License of Robert Bosch GmbH

2

*2: F

MC stands for FUJITSU Flexible Microcontroller.

2

MC-16LX CPU core inherits an AT architecture of the F2MC*2 family with additional

MB90590/590G Series

DS07-13704-3E

FEATURES

■■■■

•Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from divided-b y -2 of oscillation or one to four times the oscillation
(at oscillation of 4 MHz, 4 MHz to 16 MHz).
Minimum instruction e x ecution time: 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock,
V

CC of 5.0 V)

PACKAGE

■■■■

100-pin Plastic QFP

(FPT-100P-M06)

(Continued)

MB90590/590G Series

(Continued)

• Instruction set to optimize controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
Enhanced signed multiplication/division instruction and RETI instruction functions
Enhanced precision calculation realized by the 32-bit accumulator

• Instruction set designed for high level language (C language) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions

• Program patch function (for two address pointers)

• Enhanced execution speed: 4-byte instruction queue

• Enhanced interrupt function: 8 levels, 34 factors

• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI

• Embedded ROM size and types
Mask ROM: 256 Kbytes/384 Kbytes
Flash ROM: 256 Kbytes/384 Kbytes
Embedded RAM size: 6 Kbytes/8 Kbytes

•Flash ROM
Supports automatic programming, Embedded Algorithm

Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory
Erase can be performed on each block
Block protection with external programming voltage

• Low-power consumption (stand-by) mode
Sleep mode (mode in which CPU operating clock is stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Clock mode
Hardware stand-by mode

•Process

0.5µm CMOS technology

• I/O port
General-purpose I/O ports: 78 ports

•Timer
Watchdog timer: 1 channel
8/16-bit PPG timer: 8/16-bit × 6 channels
16-bit re-load timer: 2 channels

• 16-bit I/O timer
16-bit free-run timer: 1 channel
Input capture: 6 channels
Output compare: 6 channels

• Extended I/O serial interface: 1 channel

• UART (3 channels)
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used.

• Stepping motor controller (4 channels)

2

OS): Up to 10 channels

∗

TM

2

MB90590/590G Series

• External interrupt circuit (8 channels)

2

A module for starting an extended intelligent I/O service (EI
is triggered by an external input.

• Delayed interrupt generation module
Generates an interrupt request for switching tasks.

• 8/10-bit A/D converter (8 channels)
8/10-bit resolution can be selectively used.
Starting by an external trigger input.

• FULL-CAN interfaces: 2
Conforming to Version 2.0 Part A and Part B
Flexible message buffering (mailbox and FIFO buffering can be mixed)

• Sound generator

• 18-bit Time-base counter

• Clock timer: 1 channel

• External bus interface: Maximum address space 16 Mbytes

*: Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.

OS) and generating an external interrupt which

3

MB90590/590G Series

PRODUCT LINEUP

■■■■

Features

Classification Mask ROM product Flash ROM product Evaluation product

ROM size 384/256 Kbytes

RAM size 8/6 Kbytes 8/6 Kbytes 8 Kbytes
Emulator-specific power

supply *

CPU functions

UART (3 channels)

8/10-bit A/D converter

1

MB90591/594/594G MB90F591A/F594A/F594G MB90V590A/V590G

384/256 Kbytes

Boot block

Hard-wired reset vector

 None

The number of instructions: 340
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1 bit, 8 bits, 16 bits
Minimum execution time: 62.5 ns (at machine clock frequency of 16 MHz)
Interrupt processing time: 1.5 µs

(at machine clock frequency of 16 MHz, minimum value)

Clock synchronized transmission (500 kbps / 1 Mbps / 2 Mbps)
Clock asynchronized transmission (4808/5208/9615/10417/19230/38460/62500

/500000 bps at machine clock frequency of 16 MHz)
Transmission can be performed by bi-directional serial transmission or by master/
slave connection.

Conversion precision: 8/10-bit can be selectively used.
Number of inputs: 8
One-shot conversion mode (converts selected channel once only)
Scan conversion mode (converts two or more successive channels and can program

up to 8 channels)
Continuous conversion mode (converts selected channel continuously)
Stop conversion mode (converts selected channel and stop operation repeatedly)

None

8/16-bit PPG timers
(6 channels)

16-bit Reload timer

16-bit
I/O
timer

4

16-bit
Output compares

Input captures

Number of channels: 6 (8/16-bit × 6 channels)
PPG operation of 8-bit or 16-bit
A pulse wave of given intervals and given duty ratios can be output.
Pulse interval: fsys, fsys/2
(at oscillation of 4 MHz, fsys = system clock frequency of 16 MHz, fosc = oscillation
clock frequency)

Number of channels: 2
Operation clock frequency: fsys/2
Supports External Event Count function

Number of channels: 6 (8/16-bit × 6 channels)
Pin input factor: A match signal of compare register

Number of channels: 6
Rewriting a register value upon a pin input (rising, falling, or both edges)

1

, fsys/22, fsys/23, fsys/24, 128µs

1

, fsys/23, fsys/25 (fsys = System clock frequency)

(Continued)

(Continued)

Features

CAN Interface

Stepping motor controller
(4 channels)

MB90590/590G Series

MB90591/594/594G

Number of channels: 2
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering:
Full bit compare / Full bit mask / Two partial bit masks
Supports up to 1Mbps
CAN bit timing setting:

MB90xxx:TSEG2
MB90xxxG:TSEG2

Four high current outputs for each channel
Synchronized two 8-bit PWM’s for each channel

≥ RSJW+2TQ

MB90F591A/F594A/F594G

≥ RSJW

MB90V590A/V590G

External interrupt circuit

Sound generator

Extended I/O serial
interface

Clock timer

Watchdog timer

Flash Memory

Low-power consumption
(stand-by) mode

Number of inputs: 8
Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.

8-bit PWM signal is mixed with tone frequency from 8-bit reload counter
PWM frequency: 62.5K, 31.2K, 15.6K, 7.8KHz (at System clock = 16MHz)
Tone frequency: PWM frequency / 2 / (reload value + 1)

Clock synchronized transmission (31.25K/62.5K/125K/500K/1Mbps at machine clock

frequency of 16 MHz)

LSB first/MSB first
Directly operates with the system clock

Read/Write accessible Second/Minute/Hour registers
Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms

(at oscillation of 4 MHz, minimum value)
Supports automatic programming, Embedded Algorithm

Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed boot sector in Flash
Memory
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage

Flash Writer from Minato Electronics Inc.
Sleep/stop/CPU intermittent operation/clock timer/hardware stand-by

TM

and

Process CMOS
Power supply voltage for

operation*
Package QFP-100 PGA-256

*1:It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.

Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details.

*2:Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)

2

5 V±10 % (MB90V590A, MB90F594A, MB90594, MB90V590G,

MB90F594G, MB90594G)

5 V±5 % (MB90F591A, MB90591)

5

MB90590/590G Series

PIN ASSIGNMENT

■■■■

P14/RX1

P16/SGO

P15/TX1

P13/OUT5

P12/OUT4

99989796959493929190898887868584838281

P20
P21
P22
P23

P24/INT4
P25/INT5

P26/INT6
P27/INT7

P30
P31
Vss
P32
P33

P34/SOT0

P35/SCK0

P36/SIN0
P37/SIN1
P40/SCK1
P41/SOT1

P42/SOT2
P43/SCK2

P44/SIN2

Vcc

P45/SCIN3

P46/SCK3
P47/SOT3

P50/PPG0
P51/PPG1
P52/PPG2

P17/SGA

100

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

C

27
28
29
30

31323334353637383940414243444546474849

(Top view)

P11/OUT3

P07/OUT1

P10/OUT2

P05/IN5

P06/OUT0

P04/IN4

P02/IN2

P03/IN3

P01/IN1

P00/IN0

Vcc

X1

X0

Vss

50

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

P95/INT3
P94/INT2
P93/INT1
RST
P92/INT0
P91/RX0
P90/TX0

SS

DV
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3

CC

DV
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2

SS

DV
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1

CC

DV
P73/PWM2M0
P72/PWM2P0
P71/PWM1M0
P70/PWM1P0

SS

DV
HST
MD2

P54/PPG4

P53/PPG3

P55/PPG5/ADTG

P63/AN3

P62/AN2

Vss

P64/AN4

P65/AN5

P66/AN6

P56/TIN

P67/AN7

AVcc

AVss

AVRL

AVRH

P61/AN1

P60/AN0

MD1

MD0

P57/TOT/WOT

(FPT-100P-M06)

6

MB90590/590G Series

PIN DESCRIPTION

■■■■

No. Pin name Circuit type Function

82 X0
83 X1
77 RST
52 HST C Hardware standby input

P00 to P05

85 to 90

IN0 to IN5 Inputs for the Input Captures

P06 to P07
P10 to P13

91 to 96

OUT0 to OUT5

P14

97

RX1 RX input for CAN Interface 1

P15

98

TX1

P16

99

SGO

A Oscillator pin

B Reset input

D

D

D

D

D

General purpose IO

General purpose IO
Outputs for the Output Compares.

To enable the signal outputs, the corresponding bits of the Port Direc­tion registers should be set to “1”.

General purpose IO

General purpose IO
TX output for CAN Interface 1.

To enable the signal output, the corresponding bit of the Port Direction
register should be set to “1”.

General purpose IO
SGO output for the Sound Generator.

To enable the signal output, the corresponding bit of the Port Direction
register should be set to “1”.

P17

100

SGA

1 to 4 P20 to P23 D General purpose IO

P24 to P27

5 to 8

INT4 to INT7 External interrupt input for INT4 to INT7

9 to 10 P30 to P31 D General purpose IO

12 to 13 P32 to P33 D General purpose IO

P34

14

SOT0

P35

15

SCK0

D

D

D

D

General purpose IO
SGA output for the Sound Generator.

To enable the signal output, the corresponding bit of the Port Direction
register should be set to “1”.

General purpose IO

General purpose IO
SOT output for UART 0.

To enable the signal output, the corresponding bit of the Port Direction
register should be set to “1”.

General purpose IO
SCK input/output for UART 0.

To enable the signal output, the corresponding bit of the Port Direction
register should be set to “1”.

(Continued)

7

MB90590/590G Series

No. Pin name Circuit type Function

16

P36

D

SIN0 SIN input for UART 0

General purpose IO

17

18

19

20

21

22

24

25

26

P37

D

SIN1 SIN input for UART 1

P40

D

SCK1 SCK input/output for UART 1

P41

D

SOT1 SOT output for UART 1

P42

D

SOT2 SOT output for UART 2

P43

D

SCK2 SCK input/output for UART 2

P44

D

SIN2 SIN input for UART 2

P45

D

SIN3 SIN input for the Serial IO

P46

D

SCK3 SCK input/output for the Serial IO

P47

D

SOT3 SOT output for the Serial IO

P50 to P55

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

8

28 to 33

38 to 41

43 to 46

47

48

PPG0 to

PPG5,

ADTG

P60 to P63

AN0 to AN3 Inputs for the A/D Converter

P64 to P67

AN4 to AN7 Inputs for the A/D Converter

P56

TIN TIN input for the 16-bit Reload Timers

P57

TOT/WOT

D

E

E

D

D

Outputs for the Programmable Pulse Generators.
Pin number 33 is also shared with ADTG input for the external trigger
of the A/D Converter.

General purpose IO

General purpose IO

General purpose IO

General purpose IO
TOT output for the 16-bit Reload Timers and WOT output for the

Watch Timer. Only one of three output enable flags in these periph­eral blocks can be set at a time. Otherwise the output signal has no
meaning.

(Continued)

MB90590/590G Series

No. Pin name Circuit type Function

54 to 57

59 to 62

64 to 67

69 to 72

74

P70 to P73

General purpose IO

PWM1P0
PWM1M0
PWM2P0

F

Output for Stepping Motor Controller channel 0.

PWM2M0

P74 to P77

General purpose IO

PWM1P1
PWM1M1
PWM2P1

F

Output for Stepping Motor Controller channel 1.

PWM2M1

P80 to P83

General purpose IO

PWM1P2
PWM1M2
PWM2P2

F

Output for Stepping Motor Controller channel 2.

PWM2M2

P84 to P87

General purpose IO

PWM1P3
PWM1M3
PWM2P3

F

Output for Stepping Motor Controller channel 3.

PWM2M3

P90

General purpose IO

D

TX0 TX output for CAN Interface 0

75

D

RX0 RX input for CAN Interface 0

P92

P91

76

D

INT0 External interrupt input for INT0

P93

78

D

INT1 External interrupt input for INT1

P94

79

D

INT2 External interrupt input for INT2

P95

80

D

INT3 External interrupt input for INT3

58, 68 DV

CC 

53, 63, 73 DVSS 

34 AV

37 AV

CC

SS

Power

supply
Power

supply

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

Dedicated power supply pins for the high current output buffers
(Pin No. 54 to 72)

Dedicated ground pins for the high current output buffers
(Pin No. 54 to 72)

Power supply for analog circuit pin
When turning this power supply on or off, always be sure to first apply
electric potential equal to or greater than AV

CC to VCC.

Ground level for analog circuit

(Continued)

9

MB90590/590G Series

(Continued)

No. Pin name Circuit type Function

35 AVRH

36 AVRL

49, 50 MD0, MD1 C

51 MD2 G

27 C 

23, 84 V

11,42,81 V

CC

SS

Power
supply

Power
supply

Power
supply

Power
supply

Reference voltage input pin for analog circuit
When turning this power supply on or off, always be sure to first apply
electric potential equal to or greater than AVRH to AV

CC.

Reference voltage input pin for analog circuit
Operating mode selection input pins

Connect directly to V

CC or VSS.

Operating mode selection input pin
Connect directly to V

CC or VSS.

This is the power supply stabilization capacitor pin. It should be con­nected externally to an 0.1 µF ceramic capacitor.

Power supply (5.0 V) input pin for digital circuit

Power supply (GND) input pin for digital circuit

10

MB90590/590G Series

I/O CIRCUIT TYPE

■■■■

Circuit Type Circuit Remarks

•

X1

X0

A

Standby control signal

Oscillation feedback resistor:

1 MΩ approx.

Hysteresis input with pull-up Resistor:

•
50 kΩ approx.

B

C

D

R

R

R

R

VCC

P-ch

N-ch

HYS

HYS

HYS

Hysteresis input

•

•CMOS output

• Hysteresis input

(Continued)

11

MB90590/590G Series

Circuit Type Circuit Remarks

Vcc

P-ch

N-ch

E

Analog input

•CMOS output

• Hysteresis input

•

Analog input

R

F

R

R

G

R

HYS

P-ch

High current

N-ch

HYS

HYS

CMOS high current output

•

•

Hysteresis input

• Hysteresis input with pull-down Resistor:
50 kΩ approx.

• Flash version does not hav e pull-do wn re­sistor.

12

MB90590/590G Series

HANDLING DEVICES

■■■■

(1)Preventing latch-up

CMOS IC chips may suffer latch-up under the following conditions:

• A voltage higher than Vcc or lower than Vss is applied to an input or output pin.

• A voltage higher than the rated voltage is applied between Vcc and Vss.

• The AVcc power supply is applied before the Vcc voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply voltage (AV

the digital power-supply voltage.

(2)Treatment of unused pins

Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Theref or the y m ust be pulled up or pulled down through resistors . In this case those resistors should be
more than 2 kΩ.
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.

(3)Using external clock

To use external clock, drive X0 pin only and leave X1 pin unconnected.
Below is a diagram of how to use external clock.

MB90590/590G Series

X0

X1

Using external clock

CC, AVRH, DVCC) exceed

13

MB90590/590G Series

(4)Power supply pins (Vcc/Vss)

In products with multiple V
avoid abnormal operations including latch-up. However, you must connect the pins to an external power and a
ground line to lower the electro-magnetic emission le vel to pre v ent abnormal operation of strobe signals caused
by the rise in the ground level, and to conform to the total current rating.
Make sure to connect V
It is recommended to provide a bypass capacitor of around 0.1 µF between V

CC or VSS pins, pins with the same potential are internally connected in the device to

CC and VSS pins via lowest impedance to power lines.

CC and VSS pin near the device.

Vcc
Vss

Vcc

Vss

Vss

MB90590/590G

Vcc

Vss

Series

Vcc

Vss

Vcc

(5) Pull-up/down resistors

The MB90590/590G Series does not support internal pull-up/down resistors. Use exter n al components where
needed.

(6) Crystal Oscillator Circuit

Noises around X0 or X1 pins may cause abnormal operations. Make sure to pro vide bypass capacitors via the
shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure
that lines of oscillation circuits do not cross the lines of other circuits.

A printed circuit board artwor k surrounding the X0 and X1 pins with a ground area for stabilizing the operation
is highly recommended.

(7) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on the A/D converter power supply (AV
after turning-on the digital power supply (V

CC).

CC, AVRH, AVRL) and analog inputs (AN0 to AN7)

Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage does not exceed AVRH

or AVCC (turning on/off the analog and digital power supplies simulta-

neously is acceptable).

(8) Connection of Unused Pins of A/D Converter

Connect unused pins of A/D converter to AV

CC = VCC, AVSS = AVRH = VSS.

14

MB90590/590G Series

(9) N.C. Pin

The N.C. (internally connected) pin must be opened for use.

(10) Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50

µs or more (0.2 V to 2.7 V).

(11) Indeterminate outputs from ports 0 and 1

During oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the
outputs from ports 0 and 1 become following state.

•If RST

•If RST pin is “L”, the outputs become high-impedance.
Pay attention to the port output timing shown as follow.

RST

pin is “H”, the outputs become indeterminate.

pin is “H”

Oscillation setting time

∗2

Power-on reset

∗1

Vcc (Power-supply pin)

PONR (power-on reset) signal

(external asynchronous reset) signal

RST

RST (internal reset) signal

Oscillation clock signal

KA (internal operation clock A) signal

KB (internal operation clock B) signal

PORT (port output) signal

Period of indeterminated

*1:Power-on reset time: Period of “clock frequency × 217” (Clock frequency of 16 MHz: 8.19 ms)
*2:Oscillation setting time: Period of “clock frequency × 2

pin is “L”

RST

18

” (Clock frequency of 16 MHz: 16.38ms)
Oscillation setting time

Power-on reset

∗1

∗2

Vcc (Power-supply pin)

PONR (power-on reset) signal

(external asynchronous reset) signal

RST

RST (internal reset) signal

Oscillation clock signal

KA (internal operation clock A) signal

KB (internal operation clock B) signal

PORT (port output) signal

*1:Power-on reset time: Period of “clock frequency
*2:Oscillation setting time: Period of “clock frequency

High-impedance

17

× 2

” (Clock frequency of 16 MHz: 8.19 ms)

18

× 2

” (Clock frequency of 16 MHz: 16.38ms)

15

MB90590/590G Series

(12) Initialization

The device contains internal registers which are initialized only by a pow er-on reset. To initialize these registers ,
please turn on the power again.

(13) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions

In the Signed multiplication and division instructions (“DIV A, Ri” and “DIVW A, RWi”), the value of the corre­sponding bank register (DTB, ADB, USB, SSB) is set in “00

H”.

If the values of the corresponding bank registers (DTB,ADB ,USB,SSB) are set to other than “00
by the execution result of the instruction is not stored in the register of the instruction operand.

(14) Using REALOS

The use of EI

2

OS is not possible with the REALOS real time operating system.

H”, the remainder

16