FUJITSU MB90590, MB90590G DATA SHEET

查询MB90591供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

16-bit Proprietary Microcontroller

CMOS

F2MC-16LX

MB90591/F591A/594/594G/F594A/F594G
MB90V590A/V590G

DESCRIPTION

■■■■

The MB90590/590G series with two FULL-CAN*1 interfaces and FLASH ROM is especially designed for auto­motive and industrial applications. Its main features are tw o on board CAN Interfaces , which conform to V2.0 P art
A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a
normal full CAN approach.
The instruction set of F
instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instruc­tions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing
long word data.
The MB90590/590G series has peripheral resources of 8/10-bit A/D converters, UAR T (SCI), e xtended I/O serial
interface, 8/16-bit PPG timer, I/O timer (input capture (ICU), output compare (OCU)), stepping motor controller,
and sound generator.

*1: Controller Area Network (CAN) - License of Robert Bosch GmbH

2

*2: F

MC stands for FUJITSU Flexible Microcontroller.

2

MC-16LX CPU core inherits an AT architecture of the F2MC*2 family with additional

MB90590/590G Series

DS07-13704-3E

FEATURES

■■■■

•Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from divided-b y -2 of oscillation or one to four times the oscillation
(at oscillation of 4 MHz, 4 MHz to 16 MHz).
Minimum instruction e x ecution time: 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock,
V

CC of 5.0 V)

PACKAGE

■■■■

100-pin Plastic QFP

(FPT-100P-M06)

(Continued)

MB90590/590G Series

(Continued)

• Instruction set to optimize controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
Enhanced signed multiplication/division instruction and RETI instruction functions
Enhanced precision calculation realized by the 32-bit accumulator

• Instruction set designed for high level language (C language) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions

• Program patch function (for two address pointers)

• Enhanced execution speed: 4-byte instruction queue

• Enhanced interrupt function: 8 levels, 34 factors

• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI

• Embedded ROM size and types
Mask ROM: 256 Kbytes/384 Kbytes
Flash ROM: 256 Kbytes/384 Kbytes
Embedded RAM size: 6 Kbytes/8 Kbytes

•Flash ROM
Supports automatic programming, Embedded Algorithm

Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory
Erase can be performed on each block
Block protection with external programming voltage

• Low-power consumption (stand-by) mode
Sleep mode (mode in which CPU operating clock is stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Clock mode
Hardware stand-by mode

•Process

0.5µm CMOS technology

• I/O port
General-purpose I/O ports: 78 ports

•Timer
Watchdog timer: 1 channel
8/16-bit PPG timer: 8/16-bit × 6 channels
16-bit re-load timer: 2 channels

• 16-bit I/O timer
16-bit free-run timer: 1 channel
Input capture: 6 channels
Output compare: 6 channels

• Extended I/O serial interface: 1 channel

• UART (3 channels)
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used.

• Stepping motor controller (4 channels)

2

OS): Up to 10 channels

∗

TM

2

MB90590/590G Series

• External interrupt circuit (8 channels)

2

A module for starting an extended intelligent I/O service (EI
is triggered by an external input.

• Delayed interrupt generation module
Generates an interrupt request for switching tasks.

• 8/10-bit A/D converter (8 channels)
8/10-bit resolution can be selectively used.
Starting by an external trigger input.

• FULL-CAN interfaces: 2
Conforming to Version 2.0 Part A and Part B
Flexible message buffering (mailbox and FIFO buffering can be mixed)

• Sound generator

• 18-bit Time-base counter

• Clock timer: 1 channel

• External bus interface: Maximum address space 16 Mbytes

*: Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.

OS) and generating an external interrupt which

3

MB90590/590G Series

PRODUCT LINEUP

■■■■

Features

Classification Mask ROM product Flash ROM product Evaluation product

ROM size 384/256 Kbytes

RAM size 8/6 Kbytes 8/6 Kbytes 8 Kbytes
Emulator-specific power

supply *

CPU functions

UART (3 channels)

8/10-bit A/D converter

1

MB90591/594/594G MB90F591A/F594A/F594G MB90V590A/V590G

384/256 Kbytes

Boot block

Hard-wired reset vector

 None

The number of instructions: 340
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1 bit, 8 bits, 16 bits
Minimum execution time: 62.5 ns (at machine clock frequency of 16 MHz)
Interrupt processing time: 1.5 µs

(at machine clock frequency of 16 MHz, minimum value)

Clock synchronized transmission (500 kbps / 1 Mbps / 2 Mbps)
Clock asynchronized transmission (4808/5208/9615/10417/19230/38460/62500

/500000 bps at machine clock frequency of 16 MHz)
Transmission can be performed by bi-directional serial transmission or by master/
slave connection.

Conversion precision: 8/10-bit can be selectively used.
Number of inputs: 8
One-shot conversion mode (converts selected channel once only)
Scan conversion mode (converts two or more successive channels and can program

up to 8 channels)
Continuous conversion mode (converts selected channel continuously)
Stop conversion mode (converts selected channel and stop operation repeatedly)

None

8/16-bit PPG timers
(6 channels)

16-bit Reload timer

16-bit
I/O
timer

4

16-bit
Output compares

Input captures

Number of channels: 6 (8/16-bit × 6 channels)
PPG operation of 8-bit or 16-bit
A pulse wave of given intervals and given duty ratios can be output.
Pulse interval: fsys, fsys/2
(at oscillation of 4 MHz, fsys = system clock frequency of 16 MHz, fosc = oscillation
clock frequency)

Number of channels: 2
Operation clock frequency: fsys/2
Supports External Event Count function

Number of channels: 6 (8/16-bit × 6 channels)
Pin input factor: A match signal of compare register

Number of channels: 6
Rewriting a register value upon a pin input (rising, falling, or both edges)

1

, fsys/22, fsys/23, fsys/24, 128µs

1

, fsys/23, fsys/25 (fsys = System clock frequency)

(Continued)

(Continued)

Features

CAN Interface

Stepping motor controller
(4 channels)

MB90590/590G Series

MB90591/594/594G

Number of channels: 2
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering:
Full bit compare / Full bit mask / Two partial bit masks
Supports up to 1Mbps
CAN bit timing setting:

MB90xxx:TSEG2
MB90xxxG:TSEG2

Four high current outputs for each channel
Synchronized two 8-bit PWM’s for each channel

≥ RSJW+2TQ

MB90F591A/F594A/F594G

≥ RSJW

MB90V590A/V590G

External interrupt circuit

Sound generator

Extended I/O serial
interface

Clock timer

Watchdog timer

Flash Memory

Low-power consumption
(stand-by) mode

Number of inputs: 8
Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.

8-bit PWM signal is mixed with tone frequency from 8-bit reload counter
PWM frequency: 62.5K, 31.2K, 15.6K, 7.8KHz (at System clock = 16MHz)
Tone frequency: PWM frequency / 2 / (reload value + 1)

Clock synchronized transmission (31.25K/62.5K/125K/500K/1Mbps at machine clock

frequency of 16 MHz)

LSB first/MSB first
Directly operates with the system clock

Read/Write accessible Second/Minute/Hour registers
Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms

(at oscillation of 4 MHz, minimum value)
Supports automatic programming, Embedded Algorithm

Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed boot sector in Flash
Memory
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage

Flash Writer from Minato Electronics Inc.
Sleep/stop/CPU intermittent operation/clock timer/hardware stand-by

TM

and

Process CMOS
Power supply voltage for

operation*
Package QFP-100 PGA-256

*1:It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.

Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details.

*2:Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)

2

5 V±10 % (MB90V590A, MB90F594A, MB90594, MB90V590G,

MB90F594G, MB90594G)

5 V±5 % (MB90F591A, MB90591)

5

MB90590/590G Series

PIN ASSIGNMENT

■■■■

P14/RX1

P16/SGO

P15/TX1

P13/OUT5

P12/OUT4

99989796959493929190898887868584838281

P20
P21
P22
P23

P24/INT4
P25/INT5

P26/INT6
P27/INT7

P30
P31
Vss
P32
P33

P34/SOT0

P35/SCK0

P36/SIN0
P37/SIN1
P40/SCK1
P41/SOT1

P42/SOT2
P43/SCK2

P44/SIN2

Vcc

P45/SCIN3

P46/SCK3
P47/SOT3

P50/PPG0
P51/PPG1
P52/PPG2

P17/SGA

100

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

C

27
28
29
30

31323334353637383940414243444546474849

(Top view)

P11/OUT3

P07/OUT1

P10/OUT2

P05/IN5

P06/OUT0

P04/IN4

P02/IN2

P03/IN3

P01/IN1

P00/IN0

Vcc

X1

X0

Vss

50

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

P95/INT3
P94/INT2
P93/INT1
RST
P92/INT0
P91/RX0
P90/TX0

SS

DV
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3

CC

DV
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2

SS

DV
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1

CC

DV
P73/PWM2M0
P72/PWM2P0
P71/PWM1M0
P70/PWM1P0

SS

DV
HST
MD2

P54/PPG4

P53/PPG3

P55/PPG5/ADTG

P63/AN3

P62/AN2

Vss

P64/AN4

P65/AN5

P66/AN6

P56/TIN

P67/AN7

AVcc

AVss

AVRL

AVRH

P61/AN1

P60/AN0

MD1

MD0

P57/TOT/WOT

(FPT-100P-M06)

6

MB90590/590G Series

PIN DESCRIPTION

■■■■

No. Pin name Circuit type Function

82 X0
83 X1
77 RST
52 HST C Hardware standby input

P00 to P05

85 to 90

IN0 to IN5 Inputs for the Input Captures

P06 to P07
P10 to P13

91 to 96

OUT0 to OUT5

P14

97

RX1 RX input for CAN Interface 1

P15

98

TX1

P16

99

SGO

A Oscillator pin

B Reset input

D

D

D

D

D

General purpose IO

General purpose IO
Outputs for the Output Compares.

To enable the signal outputs, the corresponding bits of the Port Direc­tion registers should be set to “1”.

General purpose IO

General purpose IO
TX output for CAN Interface 1.

To enable the signal output, the corresponding bit of the Port Direction
register should be set to “1”.

General purpose IO
SGO output for the Sound Generator.

To enable the signal output, the corresponding bit of the Port Direction
register should be set to “1”.

P17

100

SGA

1 to 4 P20 to P23 D General purpose IO

P24 to P27

5 to 8

INT4 to INT7 External interrupt input for INT4 to INT7

9 to 10 P30 to P31 D General purpose IO

12 to 13 P32 to P33 D General purpose IO

P34

14

SOT0

P35

15

SCK0

D

D

D

D

General purpose IO
SGA output for the Sound Generator.

To enable the signal output, the corresponding bit of the Port Direction
register should be set to “1”.

General purpose IO

General purpose IO
SOT output for UART 0.

To enable the signal output, the corresponding bit of the Port Direction
register should be set to “1”.

General purpose IO
SCK input/output for UART 0.

To enable the signal output, the corresponding bit of the Port Direction
register should be set to “1”.

(Continued)

7

MB90590/590G Series

No. Pin name Circuit type Function

16

P36

D

SIN0 SIN input for UART 0

General purpose IO

17

18

19

20

21

22

24

25

26

P37

D

SIN1 SIN input for UART 1

P40

D

SCK1 SCK input/output for UART 1

P41

D

SOT1 SOT output for UART 1

P42

D

SOT2 SOT output for UART 2

P43

D

SCK2 SCK input/output for UART 2

P44

D

SIN2 SIN input for UART 2

P45

D

SIN3 SIN input for the Serial IO

P46

D

SCK3 SCK input/output for the Serial IO

P47

D

SOT3 SOT output for the Serial IO

P50 to P55

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

8

28 to 33

38 to 41

43 to 46

47

48

PPG0 to

PPG5,

ADTG

P60 to P63

AN0 to AN3 Inputs for the A/D Converter

P64 to P67

AN4 to AN7 Inputs for the A/D Converter

P56

TIN TIN input for the 16-bit Reload Timers

P57

TOT/WOT

D

E

E

D

D

Outputs for the Programmable Pulse Generators.
Pin number 33 is also shared with ADTG input for the external trigger
of the A/D Converter.

General purpose IO

General purpose IO

General purpose IO

General purpose IO
TOT output for the 16-bit Reload Timers and WOT output for the

Watch Timer. Only one of three output enable flags in these periph­eral blocks can be set at a time. Otherwise the output signal has no
meaning.

(Continued)

MB90590/590G Series

No. Pin name Circuit type Function

54 to 57

59 to 62

64 to 67

69 to 72

74

P70 to P73

General purpose IO

PWM1P0
PWM1M0
PWM2P0

F

Output for Stepping Motor Controller channel 0.

PWM2M0

P74 to P77

General purpose IO

PWM1P1
PWM1M1
PWM2P1

F

Output for Stepping Motor Controller channel 1.

PWM2M1

P80 to P83

General purpose IO

PWM1P2
PWM1M2
PWM2P2

F

Output for Stepping Motor Controller channel 2.

PWM2M2

P84 to P87

General purpose IO

PWM1P3
PWM1M3
PWM2P3

F

Output for Stepping Motor Controller channel 3.

PWM2M3

P90

General purpose IO

D

TX0 TX output for CAN Interface 0

75

D

RX0 RX input for CAN Interface 0

P92

P91

76

D

INT0 External interrupt input for INT0

P93

78

D

INT1 External interrupt input for INT1

P94

79

D

INT2 External interrupt input for INT2

P95

80

D

INT3 External interrupt input for INT3

58, 68 DV

CC 

53, 63, 73 DVSS 

34 AV

37 AV

CC

SS

Power

supply
Power

supply

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

Dedicated power supply pins for the high current output buffers
(Pin No. 54 to 72)

Dedicated ground pins for the high current output buffers
(Pin No. 54 to 72)

Power supply for analog circuit pin
When turning this power supply on or off, always be sure to first apply
electric potential equal to or greater than AV

CC to VCC.

Ground level for analog circuit

(Continued)

9

MB90590/590G Series

(Continued)

No. Pin name Circuit type Function

35 AVRH

36 AVRL

49, 50 MD0, MD1 C

51 MD2 G

27 C 

23, 84 V

11,42,81 V

CC

SS

Power
supply

Power
supply

Power
supply

Power
supply

Reference voltage input pin for analog circuit
When turning this power supply on or off, always be sure to first apply
electric potential equal to or greater than AVRH to AV

CC.

Reference voltage input pin for analog circuit
Operating mode selection input pins

Connect directly to V

CC or VSS.

Operating mode selection input pin
Connect directly to V

CC or VSS.

This is the power supply stabilization capacitor pin. It should be con­nected externally to an 0.1 µF ceramic capacitor.

Power supply (5.0 V) input pin for digital circuit

Power supply (GND) input pin for digital circuit

10

MB90590/590G Series

I/O CIRCUIT TYPE

■■■■

Circuit Type Circuit Remarks

•

X1

X0

A

Standby control signal

Oscillation feedback resistor:

1 MΩ approx.

Hysteresis input with pull-up Resistor:

•
50 kΩ approx.

B

C

D

R

R

R

R

VCC

P-ch

N-ch

HYS

HYS

HYS

Hysteresis input

•

•CMOS output

• Hysteresis input

(Continued)

11

MB90590/590G Series

Circuit Type Circuit Remarks

Vcc

P-ch

N-ch

E

Analog input

•CMOS output

• Hysteresis input

•

Analog input

R

F

R

R

G

R

HYS

P-ch

High current

N-ch

HYS

HYS

CMOS high current output

•

•

Hysteresis input

• Hysteresis input with pull-down Resistor:
50 kΩ approx.

• Flash version does not hav e pull-do wn re­sistor.

12

MB90590/590G Series

HANDLING DEVICES

■■■■

(1)Preventing latch-up

CMOS IC chips may suffer latch-up under the following conditions:

• A voltage higher than Vcc or lower than Vss is applied to an input or output pin.

• A voltage higher than the rated voltage is applied between Vcc and Vss.

• The AVcc power supply is applied before the Vcc voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply voltage (AV

the digital power-supply voltage.

(2)Treatment of unused pins

Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Theref or the y m ust be pulled up or pulled down through resistors . In this case those resistors should be
more than 2 kΩ.
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.

(3)Using external clock

To use external clock, drive X0 pin only and leave X1 pin unconnected.
Below is a diagram of how to use external clock.

MB90590/590G Series

X0

X1

Using external clock

CC, AVRH, DVCC) exceed

13

MB90590/590G Series

(4)Power supply pins (Vcc/Vss)

In products with multiple V
avoid abnormal operations including latch-up. However, you must connect the pins to an external power and a
ground line to lower the electro-magnetic emission le vel to pre v ent abnormal operation of strobe signals caused
by the rise in the ground level, and to conform to the total current rating.
Make sure to connect V
It is recommended to provide a bypass capacitor of around 0.1 µF between V

CC or VSS pins, pins with the same potential are internally connected in the device to

CC and VSS pins via lowest impedance to power lines.

CC and VSS pin near the device.

Vcc
Vss

Vcc

Vss

Vss

MB90590/590G

Vcc

Vss

Series

Vcc

Vss

Vcc

(5) Pull-up/down resistors

The MB90590/590G Series does not support internal pull-up/down resistors. Use exter n al components where
needed.

(6) Crystal Oscillator Circuit

Noises around X0 or X1 pins may cause abnormal operations. Make sure to pro vide bypass capacitors via the
shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure
that lines of oscillation circuits do not cross the lines of other circuits.

A printed circuit board artwor k surrounding the X0 and X1 pins with a ground area for stabilizing the operation
is highly recommended.

(7) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on the A/D converter power supply (AV
after turning-on the digital power supply (V

CC).

CC, AVRH, AVRL) and analog inputs (AN0 to AN7)

Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage does not exceed AVRH

or AVCC (turning on/off the analog and digital power supplies simulta-

neously is acceptable).

(8) Connection of Unused Pins of A/D Converter

Connect unused pins of A/D converter to AV

CC = VCC, AVSS = AVRH = VSS.

14

MB90590/590G Series

(9) N.C. Pin

The N.C. (internally connected) pin must be opened for use.

(10) Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50

µs or more (0.2 V to 2.7 V).

(11) Indeterminate outputs from ports 0 and 1

During oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the
outputs from ports 0 and 1 become following state.

•If RST

•If RST pin is “L”, the outputs become high-impedance.
Pay attention to the port output timing shown as follow.

RST

pin is “H”, the outputs become indeterminate.

pin is “H”

Oscillation setting time

∗2

Power-on reset

∗1

Vcc (Power-supply pin)

PONR (power-on reset) signal

(external asynchronous reset) signal

RST

RST (internal reset) signal

Oscillation clock signal

KA (internal operation clock A) signal

KB (internal operation clock B) signal

PORT (port output) signal

Period of indeterminated

*1:Power-on reset time: Period of “clock frequency × 217” (Clock frequency of 16 MHz: 8.19 ms)
*2:Oscillation setting time: Period of “clock frequency × 2

pin is “L”

RST

18

” (Clock frequency of 16 MHz: 16.38ms)
Oscillation setting time

Power-on reset

∗1

∗2

Vcc (Power-supply pin)

PONR (power-on reset) signal

(external asynchronous reset) signal

RST

RST (internal reset) signal

Oscillation clock signal

KA (internal operation clock A) signal

KB (internal operation clock B) signal

PORT (port output) signal

*1:Power-on reset time: Period of “clock frequency
*2:Oscillation setting time: Period of “clock frequency

High-impedance

17

× 2

” (Clock frequency of 16 MHz: 8.19 ms)

18

× 2

” (Clock frequency of 16 MHz: 16.38ms)

15

MB90590/590G Series

(12) Initialization

The device contains internal registers which are initialized only by a pow er-on reset. To initialize these registers ,
please turn on the power again.

(13) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions

In the Signed multiplication and division instructions (“DIV A, Ri” and “DIVW A, RWi”), the value of the corre­sponding bank register (DTB, ADB, USB, SSB) is set in “00

H”.

If the values of the corresponding bank registers (DTB,ADB ,USB,SSB) are set to other than “00
by the execution result of the instruction is not stored in the register of the instruction operand.

(14) Using REALOS

The use of EI

2

OS is not possible with the REALOS real time operating system.

H”, the remainder

16

BLOCK DIAGRAM

■■■■

MB90590/590G Series

X0,X1

RST
HST

SOT0 to SOT2

SCK0 to SCK2

SIN0 to SIN2

SOT3
SCK3

SIN3

AVCC
AVSS

AN0 to AN7

AVRH
AVRL
ADTG

Clock

Controller

RAM 6/8 K

ROM/Flash

256 K/384 K

Prescaler × 3

UART 3ch

Prescaler

Serial I/O

10-bit ADC

8ch

2

F

MC-16LX

CPU

MC-16 Bus

2

F

16-bit

IO Timer

16-bit Input

Capture

6ch

16-bit Output

Compare

4ch

8/16-bit

PPG

6ch

CAN

2ch

SMC

4ch

IN0 to IN5

OUT0 to OUT5

PPG0 to PPG5

RX0, RX1

TX0, TX1

PWM1M0 to PWM1M3
PWM1P0 to PWM1P3

PWM2M0 to PWM2M3
PWM2P0 to PWM2P3

DVCC

DVSS

TIN

TOT/WOT

16-bit Reload

Timer 2ch

Watch

Timer

External

Interrupt

Circuit 8ch

Sound

Generator

INT0 to INT7

SGO

SGA

17

MB90590/590G Series

MEMORY SPACE

■■■■

The memory space of the MB90590/590G Series is shown below

FFFFFF

FF0000H
FEFFFF
FE0000H

FDFFFF

FD0000H

FCFFFF

FC0000H

FBFFFFH

FB0000H

FAFFFF

FA0000H
F9FFFF

F90000H

00FFFFH

004000H

0028FFH

002100H

0020FF

MB90V590A/V590G

H

ROM (FF bank)

H

ROM (FE bank)

H

ROM (FD bank)

H

ROM (FC bank)

FFFFFF
FF0000H
FEFFFFH
FE0000H

FDFFFFH

FD0000H

FCFFFF

FC0000H

ROM (FB bank)

H

ROM (FA bank)

H

ROM (F9 bank)

ROM

(Image of FF bank)

00FFFFH

004000H

RAM 2K

H 0020FFH

MB90594/F594A/

594G/F594G

H

ROM (FF bank)

ROM (FE bank)

ROM (FD bank)

H

ROM (FC bank)

ROM

(Image of FF bank)

FFFFFF

FF0000H

FEFFFFH

FE0000H

FDFFFFH
FD0000H

FCFFFF
FC0000H
FBFFFFH

FB0000H

FAFFFFH

FA0000H

F9FFFF

F90000H

00FFFFH

004000H

0028FF
002100H

MB90591/F591A

H

ROM (FF bank)

ROM (FE bank)

ROM (FD bank)

H

ROM (FB bank)

ROM (FA bank)

H

ROM (F9 bank)

ROM

(Image of FF bank)

H

RAM 2K

001FFFH

001900H

0018FF

000100H

0000BFH

000000H

Peripheral

H

RAM 6K

Peripheral

001FFFH

001900H

0018FF

000100H

0000BFH

000000H

Peripheral

H

RAM 6K

001FFFH
001900H

0018FF

Peripheral

H

RAM 6K

000100H

Peripheral

0000BFH
000000H

Peripheral

Memory space map

Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C

compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 are assigned to the same
address, enabling reference of the table on the ROM without stating “far”.
For example, if an attempt has been made to access 00C000

H , the contents of the ROM at FFC000H are

accessed. Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in
the image for the 00 bank. The ROM data at FF4000
for 004000
to FFFFFF

H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H

H.

H to FFFFFFH looks, therefore, as if it were the image

18

MB90590/590G Series

I/O MAP

■■■■

Address Register Abbreviation Access Peripheral Initial value

00

H Port 0 Data Register PDR0 R/W Port 0 XXXXXXXXB

01H Port 1 Data Register PDR1 R/W Port 1 XXXXXXXXB
02H Port 2 Data Register PDR2 R/W Port 2 XXXXXXXXB
03H Port 3 Data Register PDR3 R/W Port 3 XXXXXXXXB
04H Port 4 Data Register PDR4 R/W Port 4 XXXXXXXXB
05H Port 5 Data Register PDR5 R/W Port 5 XXXXXXXXB
06H Port 6 Data Register PDR6 R/W Port 6 XXXXXXXXB
07H Port 7 Data Register PDR7 R/W Port 7 XXXXXXXXB
08H Port 8 Data Register PDR8 R/W Port 8 XXXXXXXXB
09H Port 9 Data Register PDR9 R/W Port 9 _ _ XXXXXXB

0AH to 0FH Reserved

10

H Port 0 Direction Register DDR0 R/W Port 0 0 0 0 0 0 0 0 0B

11H Port 1 Direction Register DDR1 R/W Port 1 0 0 0 0 0 0 0 0B
12H Port 2 Direction Register DDR2 R/W Port 2 0 0 0 0 0 0 0 0B
13H Port 3 Direction Register DDR3 R/W Port 3 0 0 0 0 0 0 0 0B
14H Port 4 Direction Register DDR4 R/W Port 4 0 0 0 0 0 0 0 0B
15H Port 5 Direction Register DDR5 R/W Port 5 0 0 0 0 0 0 0 0B
16H Port 6 Direction Register DDR6 R/W Port 6 0 0 0 0 0 0 0 0B
17H Port 7 Direction Register DDR7 R/W Port 7 0 0 0 0 0 0 0 0B
18H Port 8 Direction Register DDR8 R/W Port 8 0 0 0 0 0 0 0 0B
19H Port 9 Direction Register DDR9 R/W Port 9 _ _ 0 0 0 0 0 0B
1AH Reserved
1B

H Analog Input Enable Register ADER R/W Port 6, A/D 1 1 1 1 1 1 1 1B

1CH to 1FH Reserved

20

H Serial Mode Control Register 0 UMC0 R/W

0 0 0 0 0 1 0 0B

21H Serial Status Register 0 USR0 R/W 0 0 0 1 0 0 0 0B
22H

Serial Input/Output Data Register 0

UIDR0/

UODR0

R/W XXXXXXXXB

UART0

23H Rate and Data Register 0 URD0 R/W 0 0 0 0 0 0 0XB
24H Serial Mode Control Register 1 UMC1 R/W

0 0 0 0 0 1 0 0B

25H Serial Status Register 1 USR1 R/W 0 0 0 1 0 0 0 0B
26H

Serial Input/Output Data Register 1

UIDR1/

UODR1

R/W XXXXXXXXB

UART1

27H Rate and Data Register 1 URD1 R/W 0 0 0 0 0 0 0XB

(Continued)

19

MB90590/590G Series

Address Register Abbreviation Access Peripheral Initial value

28

H Serial Mode Control Register 2 UMC2 R/W

29H Serial Status Register 2 USR2 R/W 0 0 0 1 0 0 0 0B
2AH

Serial Input/Output Data

Register 2

UIDR2/

UODR2

R/W XXXXXXXXB

UART2

2BH Rate and Data Register 2 URD2 R/W 0 0 0 0 0 0 0XB

2CH

Serial Mode Control Register

(low-order)

SMCS R/W

0 0 0 0 0 1 0 0B

_ _ _ _0 0 0 0B

2DH

Serial Mode Control Register

(high-order)

SMCS R/W 0 0 0 0 0 0 1 0B

Serial IO

2EH Serial Data Register SDR R/W XXXXXXXXB
2FH Edge Selector Register SES R/W _ _ _ _ _ _ _0B

30H External Interrupt Enable Register ENIR R/W
31H

External Interrupt Request Register

EIRR R/W XXXXXXXXB

0 0 0 0 0 0 0 0B

External Interrupt

32H External Interrupt Level Register ELVR R/W 0 0 0 0 0 0 0 0B
33H External Interrupt Level Register ELVR R/W 0 0 0 0 0 0 0 0B
34H A/D Control Status Register 0 ADCS0 R/W

0 0 0 0 0 0 0 0B

35H A/D Control Status Register 1 ADCS1 R/W 0 0 0 0 0 0 0 0B

A/D Converter

36H A/D Data Register 0 ADCR0 R XXXXXXXXB
37H A/D Data Register 1 ADCR1 R/W 0 0 0 0 1 0 XXB
38H
39H

3AH

PPG0 Operation Mode Control Register
PPG1 Operation Mode Control Register

PPG0,1 Output Pin Control Register

PPGC0 R/W
PPGC1 R/W 0 _ 0 0 0 0 0 1B

PPG01 R/W 0 0 0 0 0 0 0 0B

16-bit Programmable

Pulse

Generator 0/1

0 _ 0 0 0 _ _ 1B

3BH Reserved
3CH
3DH
3EH

PPG2 Operation Mode Control Register
PPG3 Operation Mode Control Register

PPG2,3 Output Pin Control Register

PPGC2 R/W
PPGC3 R/W 0 _ 0 0 0 0 0 1B

PPG23 R/W 0 0 0 0 0 0 0 0B

16-bit Programmable

Pulse

Generator 2/3

0 _ 0 0 0 _ _1B

3FH Reserved

40
41H
42H

PPG4 Operation Mode Control Register

H

PPG5 Operation Mode Control Register

PPG4,5 Output Pin Control Register

PPGC4 R/W
PPGC5 R/W 0 _ 0 0 0 0 0 1B

PPG45 R/W 0 0 0 0 0 0 0 0B

16-bit Programmable

Pulse

Generator 4/5

0 _ 0 0 0 _ _ 1B

20

43H Reserved
44
45H
46H

PPG6 Operation Mode Control Register

H

PPG7 Operation Mode Control Register

PPG6,7 Output Pin Control Register

PPGC6 R/W
PPGC7 R/W 0 _ 0 0 0 0 0 1B

PPG67 R/W 0 0 0 0 0 0 0 0B

47H Reserved

16-bit Programmable

Pulse

Generator 6/7

0 _ 0 0 0 _ _ 1B

(Continued)

MB90590/590G Series

Address Register Abbreviation Access Peripheral Initial value

48

49H
4AH
4BH Reserved
4CH
4DH
4EH

4FH Reserved

PPG8 Operation Mode Control Register

H

PPG9 Operation Mode Control Register

PPG8,9 Output Pin Control Register

PPGA Operation Mode Control Register
PPGB Operation Mode Control Register

PPGA,B Output Pin Control Register

PPGC8 R/W
PPGC9 R/W 0 _ 0 0 0 0 0 1B
PPG89 R/W 0 0 0 0 0 0 0 0B

PPGCA R/W
PPGCB R/W 0 _ 0 0 0 0 0 1B

PPGAB R/W 0 0 0 0 0 0 0 0B

16-bit Programmable

Pulse

Generator 8/9

16-bit Programmable

Pulse

Generator A/B

0 _ 0 0 0 _ _ 1B

0 _ 0 0 0 _ _ 1B

50

51H

52H

53H

54H

55H

56H

H

Timer Control Status Register 0

(low-order)

Timer Control Status Register 0

(high-order)

Timer Control Status Register 1

(low-order)

Timer Control Status Register 1

(high-order)

Input Capture Control Status

Register 0/1

Input Capture Control Status

Register 2/3

Input Capture Control Status

Register 4/5

TMCSR0 R/W

TMCSR0 R/W _ _ _ _ 0 0 0 0B

TMCSR1 R/W

TMCSR1 R/W _ _ _ _ 0 0 0 0B

ICS01 R/W Input Capture 0/1 0 0 0 0 0 0 0 0B

ICS23 R/W Input Capture 2/3 0 0 0 0 0 0 0 0B

ICS45 R/W Input Capture 4/5 0 0 0 0 0 0 0 0B
57H Reserved
58

59H

5AH

5BH

H

Output Compare Control Status

Register 0

Output Compare Control Status

Register 1

Output Compare Control Status

Register 2

Output Compare Control Status

Register 3

OCS0 R/W

OCS1 R/W _ _ _0 0 0 0 0B

OCS2 R/W

OCS3 R/W _ _ _ 0 0 0 0 0B

0 0 0 0 0 0 0 0B

16-bit Reload Timer 0

0 0 0 0 0 0 0 0B

16-bit Reload Timer 1

0 0 0 0 _ _ 0 0B

Output Compare 0/1

0 0 0 0 _ _ 0 0B

Output Compare 2/3

5CH

5DH
5EH

5FH

Output Compare Control Status

Register 4

Output Compare Control Status

Register 5

Sound Control Register (low-order)

Sound Control Register (high-order)

OCS4 R/W

0 0 0 0 _ _ 0 0B

Output Compare 4/5

OCS5 R/W _ _ _ 0 0 0 0 0B

SGCR R/W

0 0 0 0 0 0 0 0B

Sound Generator

SGCR R/W 0 _ _ _ _ _ _ 0B

(Continued)

21

MB90590/590G Series

Address Register Abbreviation Access Peripheral Initial value

60

H

Watch Timer Control Register

(low-order)

WTCR R/W

0 0 0 _ _ 0 0 0B

Watch Timer

61H

Watch Timer Control Register

(high-order)

62H PWM Control Register 0 PWC0 R/W

WTCR R/W 0 0 0 0 0 0 0 0B

Stepping Motor

Controller 0

0 0 0 0 0 _ _ 0B
63H Reserved
64

H PWM Control Register 1 PWC1 R/W

Stepping Motor

Controller 1

0 0 0 0 0 _ _ 0B
65H Reserved
66

H PWM Control Register 2 PWC2 R/W

Stepping Motor

Controller 2

0 0 0 0 0 _ _ 0B
67H Reserved
68H PWM Control Register 3 PWC3 R/W

Stepping Motor

Controller 3

0 0 0 0 0 _ _ 0B

69H to 6CH Reserved

6D

H Serial IO Prescaler Register CDCR R/W Prescaler (Serial IO) 0 XXX 1 1 1 1B

6EH Timer Control Status Register TCCS R/W I/O Timer 0 0 0 0 0 0 0 0B
6FH

ROM Mirror Function Select

Register

ROMM W ROM Mirror XXXXXXX1B

70H to 8FH Reserved for CAN Interface 0/1. Refer to section about CAN Controller

90

H to 9DH Reserved

9EH
9FH

A0H

Program Address Detection

Control Status Register

Delayed Interrupt/Release Register

Low Power Mode Control Register

PACSR R/W

DIRR R/W Delayed Interrupt _ _ _ _ _ _ _ 0B

LPMCR R/W Low Power Controller 0 0 0 1 1 0 0 0B

Address Match

Detection Function

0 0 0 0 0 0 0 0B

A1H Clock Selection Register CKSCR R/W Low Power Controller 1 1 1 1 1 1 0 0B

A2H to A7H Reserved

A8
A9H

H

Watchdog Timer Control Register

Time Base Timer Control Register

WDTC R/W Watchdog Timer XXXXX 1 1 1B

TBTC R/W Time Base Timer 1 - - 0 0 1 0 0B

AAH to ADH Reserved

Flash Memory Control Status

AE

H

Register

(Flash product only.

FMCS R/W Flash Memory 0 0 0 X 0 0 0 0

Otherwise reserved)

AFH Reserved

(Continued)

B

22

MB90590/590G Series

Address Register Abbreviation Access Peripheral Initial value

B0

H Interrupt Control Register 00 ICR00 R/W

B1H Interrupt Control Register 01 ICR01 R/W 0 0 0 0 0 1 1 1B
B2H Interrupt Control Register 02 ICR02 R/W 0 0 0 0 0 1 1 1B
B3H Interrupt Control Register 03 ICR03 R/W 0 0 0 0 0 1 1 1B
B4H Interrupt Control Register 04 ICR04 R/W 0 0 0 0 0 1 1 1B
B5H Interrupt Control Register 05 ICR05 R/W 0 0 0 0 0 1 1 1B
B6H Interrupt Control Register 06 ICR06 R/W 0 0 0 0 0 1 1 1B
B7H Interrupt Control Register 07 ICR07 R/W 0 0 0 0 0 1 1 1B

Interrupt controller

B8H Interrupt Control Register 08 ICR08 R/W 0 0 0 0 0 1 1 1B

B9H Interrupt Control Register 09 ICR09 R/W 0 0 0 0 0 1 1 1B
BAH Interrupt Control Register 10 ICR10 R/W 0 0 0 0 0 1 1 1B
BBH Interrupt Control Register 11 ICR11 R/W 0 0 0 0 0 1 1 1B
BCH Interrupt Control Register 12 ICR12 R/W 0 0 0 0 0 1 1 1B
BDH Interrupt Control Register 13 ICR13 R/W 0 0 0 0 0 1 1 1B

0 0 0 0 0 1 1 1B

BEH Interrupt Control Register 14 ICR14 R/W 0 0 0 0 0 1 1 1B

BFH Interrupt Control Register 15 ICR15 R/W 0 0 0 0 0 1 1 1B

C0H to

FF

H

1900

H Reload L Register PRLL0 R/W

1901H Reload H Register PRLH0 R/W XXXXXXXXB

Reserved

XXXXXXXXB

16-bit Programmable

Pulse

1902H Reload L Register PRLL1 R/W XXXXXXXXB

Generator 0/1

1903H Reload H Register PRLH1 R/W XXXXXXXXB
1904H Reload L Register PRLL2 R/W
1905H Reload H Register PRLH2 R/W XXXXXXXXB

16-bit Programmable

XXXXXXXXB

Pulse

1906H Reload L Register PRLL3 R/W XXXXXXXXB

Generator 2/3

1907H Reload H Register PRLH3 R/W XXXXXXXXB
1908H Reload L Register PRLL4 R/W
1909H Reload H Register PRLH4 R/W XXXXXXXXB

16-bit Programmable

XXXXXXXXB

Pulse

190AH Reload L Register PRLL5 R/W XXXXXXXXB

Generator 4/5

190BH Reload H Register PRLH5 R/W XXXXXXXXB
190CH Reload L Register PRLL6 R/W
190DH Reload H Register PRLH6 R/W XXXXXXXXB

16-bit Programmable

XXXXXXXX

Pulse

190EH Reload L Register PRLL7 R/W XXXXXXXXB

Generator 6/7

190FH Reload H Register PRLH7 R/W XXXXXXXXB

(Continued)

B

23

MB90590/590G Series

Address Register Abbreviation Access Peripheral Initial value

1910

H Reload L Register PRLL8 R/W

1911H Reload H Register PRLH8 R/W XXXXXXXXB

16-bit Programmable

XXXXXXXX

Pulse

1912H Reload L Register PRLL9 R/W XXXXXXXXB

Generator 8/9

1913H Reload H Register PRLH9 R/W XXXXXXXXB
1914H Reload L Register PRLLA R/W
1915H Reload H Register PRLHA R/W XXXXXXXXB

16-bit Programmable

XXXXXXXXB

Pulse

1916H Reload L Register PRLLB R/W XXXXXXXXB

Generator A/B

1917H Reload H Register PRLHB R/W XXXXXXXXB

1918H to 191FH Reserved

1920

1921H

H

Input Capture Register 0

(low-order)

Input Capture Register 0

(high-order)

IPCP0 R

XXXXXXXXB

IPCP0 R XXXXXXXXB

Input Capture 0/1

1922H

1923H

1924H

Input Capture Register 1

(low-order)

Input Capture Register 1

(high-order)

Input Capture Register 2

(low-order)

IPCP1 R XXXXXXXXB

IPCP1 R XXXXXXXXB

IPCP2 R

XXXXXXXXB

B

1925H

1926H

1927H

1928H

1929H

192AH

192BH

Input Capture Register 2

(high-order)

Input Capture Register 3

(low-order)

Input Capture Register 3

(high-order)

Input Capture Register 4

(low-order)

Input Capture Register 4

(high-order)

Input Capture Register 5

(low-order)

Input Capture Register 5

(high-order)

IPCP2 R XXXXXXXXB

IPCP3 R XXXXXXXXB

IPCP3 R XXXXXXXXB

IPCP4 R

IPCP4 R XXXXXXXXB

IPCP5 R XXXXXXXXB

IPCP5 R XXXXXXXXB

192CH to 192FH Reserved

Input Capture 2/3

XXXXXXXXB

Input Capture 4/5

(Continued)

24

MB90590/590G Series

Address Register Abbreviation Access Peripheral Initial value

1930

1931H

1932H

1933H

1934H

1935H

1936H

1937H

1938H

1939H

193AH

H

Output Compare Register 0

(low-order)

Output Compare Register 0

(high-order)

Output Compare Register 1

(low-order)

Output Compare Register 1

(high-order)

Output Compare Register 2

(low-order)

Output Compare Register 2

(high-order)

Output Compare Register 3

(low-order)

Output Compare Register 3

(high-order)

Output Compare Register 4

(low-order)

Output Compare Register 4

(high-order)

Output Compare Register 5

(low-order)

OCCP0 R/W

XXXXXXXXB

OCCP0 R/W XXXXXXXXB

Output Compare

0/1

OCCP1 R/W XXXXXXXXB

OCCP1 R/W XXXXXXXXB

OCCP2 R/W

XXXXXXXXB

OCCP2 R/W XXXXXXXXB

Output Compare

2/3

OCCP3 R/W XXXXXXXXB

OCCP3 R/W XXXXXXXXB

OCCP4 R/W

XXXXXXXXB

OCCP4 R/W XXXXXXXXB

Output Compare

4/5

OCCP5 R/W XXXXXXXXB

193BH

Output Compare Register 5

(high-order)

OCCP5 R/W XXXXXXXXB

193CH to 193FH Reserved

1940

1941H

1942H

1943H

H

Timer 0/Reload Register 0

(low-order)

Timer 0/Reload Register 0

(high-order)

Timer 1/Reload Register 1

(low-order)

Timer 1/Reload Register 1

(high-order)

1944H Timer Data Register (low-order) TCDT R/W

TMR0/

TMRLR0

TMR0/

TMRLR0

TMR1/

TMRLR1

TMR1/

TMRLR1

R/W

XXXXXXXX

16-bit Reload

Timer 0

R/W XXXXXXXXB

R/W

XXXXXXXXB

16-bit Reload

Timer 1

R/W XXXXXXXXB

0 0 0 0 0 0 0 0 B

IO Timer

1945H Timer Data Register (high-order) TCDT R/W 0 0 0 0 0 0 0 0 B
1946H Frequency Data Register SGFR R/W

XXXXXXXXB

1947H Amplitude Data Register SGAR R/W XXXXXXXXB

Sound Generator

1948H Decrement Grade Register SGDR R/W XXXXXXXXB
1949H Tone Count Register SGTR R/W XXXXXXXXB

B

(Continued)

25

MB90590/590G Series

Address Register Abbreviation Access Peripheral Initial value

194A

194BH

194CH

H

Sub-second Data Register

(low-order)

Sub-second Data Register

(middle-order)

Sub-second Data Register

(high-order)

WTBR R/W

XXXXXXXXB

WTBR R/W XXXXXXXXB

Watch Timer

WTBR R/W _ _ _ XXXXXB

194DH Second Data Register WTSR R/W _ _ 0 0 0 0 0 0 B
194E

H Minute Data Register WTMR R/W

_ _ 0 0 0 0 0 0 B

Watch Timer

194FH Hour Data Register WTHR R/W _ _ _ 0 0 0 0 0 B
1950H PWM1 Compare Register 0 PWC10 R/W
1951H PWM2 Compare Register 0 PWC20 R/W XXXXXXXXB
1952H PWM1 Select Register 0 PWS10 R/W _ _ 0 0 0 0 0 0 B

Stepping Motor

Controller 0

XXXXXXXXB

1953H PWM2 Select Register 0 PWS20 R/W _ 0 0 0 0 0 0 0 B
1954H PWM1 Compare Register 1 PWC11 R/W
1955H PWM2 Compare Register 1 PWC21 R/W XXXXXXXXB
1956H PWM1 Select Register 1 PWS11 R/W _ _ 0 0 0 0 0 0 B

Stepping Motor

Controller 1

XXXXXXXXB

1957H PWM2 Select Register 1 PWS21 R/W _ 0 0 0 0 0 0 0 B
1958H PWM1 Compare Register 2 PWC12 R/W

XXXXXXXXB
1959H PWM2 Compare Register 2 PWC22 R/W XXXXXXXXB
195AH PWM1 Select Register 2 PWS12 R/W _ _ 0 0 0 0 0 0 B

Stepping Motor

Controller 2

195BH PWM2 Select Register 2 PWS22 R/W _ 0 0 0 0 0 0 0 B
195CH PWM1 Compare Register 3 PWC13 R/W
195DH PWM2 Compare Register 3 PWC23 R/W XXXXXXXXB
195EH PWM1 Select Register 3 PWS13 R/W _ _ 0 0 0 0 0 0 B

Stepping Motor

Controller 3

XXXXXXXXB

195FH PWM2 Select Register 3 PWS23 R/W _0 0 0 0 0 0 0 B

1960H to 19FFH Reserved

1A00

H to 1AFFH Reserved for CAN Interface 0. Refer to section about CAN Controller

1B00H to 1BFFH Reserved for CAN Interface 1. Refer to section about CAN Controller

1C00

H to 1CFFH Reserved for CAN Interface 0. Refer to section about CAN Controller

1D00

H to 1DFFH Reserved for CAN Interface 1. Refer to section about CAN Controller

1E00H to 1EFFH Reserved

(Continued)

26

MB90590/590G Series

(Continued)

Address Register Abbreviation Access Peripheral Initial value

1FF0

H

1FF1H

1FF2H

1FF3H

1FF4H

1FF5H

1FF6H to 1FFFH Reserved

Note: Initial value of “_” represents unused bit; “X” represents unknown value.

Addresses in the rage 0000
of the MCU. A read access to these reserved addresses results in reading “X”, and any write access should
not be performed.

Program Address Detection

Register 0 (low-order)

Program Address Detection

Register 0 (middle-order)

Program Address Detection

Register 0 (high-order)

Program Address Detection

Register 1 (low-order)

Program Address Detection

Register 1 (middle-order)

Program Address Detection

Register 1 (high-order)

H to 00FFH, which are not listed in the table, are reserved f or the primary functions

PADR0 R/W

PADR0 R/W XXXXXXXX B

PADR0 R/W XXXXXXXX B

PADR1 R/W XXXXXXXX B

PADR1 R/W XXXXXXXX B

PADR1 R/W XXXXXXXX B

XXXXXXXX B

Address Match

Detection

Function

27

MB90590/590G Series

CAN CONTROLLERS

■■■■

The CAN controller has the following features:

• Conforms to CAN Specification Version 2.0 Part A and B

- Supports transmission/reception in standard frame and extended frame formats

• Supports transmission of data frames by receiving remote frames

• 16 transmitting/receiving message buffers

- 29-bit ID and 8-byte data

- Multi-level message buffer configuration

• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as 1D acceptance mask

- Two acceptance mask registers in either standard frame format or extended frame formats

• Bit rate programmable from 10 kbit/s to 2 Mbit/s (when input clock is at 16 MHz)

List of Control Registers

Address

CAN0 CAN1

Register Abbreviation Access Initial Value

000070
000071H 000081H
000072H 000082H
000073H 000083H
000074H 000084H
000075H 000085H
000076H 000086H
000077H 000087H
000078H 000088H

000079H 000089H
00007AH 00008AH
00007BH 00008BH

00007CH 00008CH
00007DH 00008DH

00007EH 00008EH
00007FH 00008FH

H 000080H

Message buffer valid register BVALR R/W 00000000 00000000B

Transmit request register TREQR R/W 00000000 00000000B

Transmit cancel register TCANR W 00000000 00000000B

Transmit complete register TCR R/W 00000000 00000000B

Receive complete register RCR R/W 00000000 00000000B

Remote request receiving register RRTRR R/W 00000000 00000000B

Receive overrun register ROVRR R/W 00000000 00000000B

Receive interrupt enable register RIER R/W 00000000 00000000B

28

Address

CAN0 CAN1

MB90590/590G Series

List of Control Registers

Register Abbreviation Access Initial Value

001C00

H 001D00H

001C01H 001D01H
001C02H 001D02H
001C03H 001D03H
001C04H 001D04H
001C05H 001D05H
001C06H 001D06H
001C07H 001D07H
001C08H 001D08H

001C09H 001D09H
001C0AH 001D0AH
001C0BH 001D0BH
001C0CH 001D0CH
001C0DH 001D0DH
001C0EH 001D0EH

001C0FH 001D0FH

001C10H 001D10H

001C11H 001D11H

001C12H 001D12H

001C13H 001D13H

Control status register CSR R/W, R 00---000 0----0-1B

Last event indicator register LEIR R/W -------- 000-0000B

Receive/transmit error counter RTEC R 00000000 00000000B

Bit timing register BTR R/W -1111111 11111111B

IDE register IDER R/W

XXXXXXXX

XXXXXXXXB

Transmit RTR register TRTRR R/W 00000000 00000000B

Remote frame receive waiting register RFWTR R/W

XXXXXXXX

XXXXXXXXB

Transmit interrupt enable register TIER R/W 00000000 00000000B

XXXXXXXX

XXXXXXXXB

Acceptance mask select register AMSR R/W

XXXXXXXX

XXXXXXXX

B

001C14H 001D14H

001C15H 001D15H

001C16H 001D16H

001C17H 001D17H

001C18H 001D18H

001C19H 001D19H
001C1AH 001D1AH
001C1BH 001D1BH

Acceptance mask register 0 AMR0 R/W

Acceptance mask register 1 AMR1 R/W

XXXXXXXX

XXXXXXXX

B

XXXXX--- XXXXXXXXB

XXXXXXXX

XXXXXXXX

B

XXXXX--- XXXXXXXXB

29

MB90590/590G Series

List of Message Buffers (ID Registers)

Address

CAN0 CAN1

Register Abbreviation Access Initial Value

001A20

H 001B20H

001A21H 001B21H
001A22H 001B22H
001A23H 001B23H
001A24H 001B24H
001A25H 001B25H
001A26H 001B26H
001A27H 001B27H
001A28H 001B28H

001A29H 001B29H
001A2AH 001B2AH
001A2BH 001B2BH
001A2CH 001B2CH
001A2DH 001B2DH
001A2EH 001B2EH
001A2FH 001B2FH

001A30H 001B30H

001A31H 001B31H

001A32H 001B32H

001A33H 001B33H

ID register 0 IDR0 R/W

ID register 1 IDR1 R/W

ID register 2 IDR2 R/W

ID register 3 IDR3 R/W

ID register 4 IDR4 R/W

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXXB

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXXB

XXXXX--- XXXXXXXXB

B

B

B

001A34H 001B34H

001A35H 001B35H

001A36H 001B36H

001A37H 001B37H

001A38H 001B38H

001A39H 001B39H
001A3AH 001B3AH
001A3BH 001B3BH
001A3CH 001B3CH
001A3DH 001B3DH
001A3EH 001B3EH
001A3FH 001B3FH

30

ID register 5 IDR5 R/W

ID register 6 IDR6 R/W

ID register 7 IDR7 R/W

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXXB

XXXXX--- XXXXXXXXB

(Continued)

B

B

(Continued)

Address

CAN0 CAN1

MB90590/590G Series

Register Abbreviation Access I nitial Value

001A40

H 001B40H

001A41H 001B41H

001A42H 001B42H

001A43FH 001B43H

001A44H 001B44H

001A45H 001B45H

001A46H 001B46H

001A47H 001B47H

001A48H 001B48H

001A49H 001B49H
001A4AH 001B4AH
001A4BH 001B4BH
001A4CH 001B4CH
001A4DH 001B4DH
001A4EH 001B4EH
001A4FH 001B4FH

001A50H 001B50H

001A51H 001B51H

001A52H 001B52H

001A53H 001B53H

ID register 8 IDR8 R/W

ID register 9 IDR9 R/W

ID register 10 IDR10 R/W

ID register 11 IDR11 R/W

ID register 12 IDR12 R/W

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXXB

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXXB

XXXXX--- XXXXXXXXB

B

B

B

001A54H 001B54H

001A55H 001B55H

001A56H 001B56H

001A57H 001B57H

001A58H 001B58H

001A59H 001B59H
001A5AH 001B5AH
001A5BH 001B5BH
001A5CH 001B5CH
001A5DH 001B5DH
001A5EH 001B5EH
001A5FH 001B5FH

ID register 13 IDR13 R/W

ID register 14 IDR14 R/W

ID register 15 IDR15 R/W

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXXB

XXXXX--- XXXXXXXXB

B

B

31

MB90590/590G Series

List of Message Buffers (DLC Registers and Data Registers)

Address

CAN0 CAN1

Register Abbreviation Access Initial Value

001A60

H 001B60H

001A61H 001B61H

001A62H 001B62H

001A63H 001B63H

001A64H 001B64H

001A65H 001B65H

001A66H 001B66H

001A67H 001B67H

001A68H 001B68H

001A69H 001B69H
001A6AH 001B6AH
001A6BH 001B6BH
001A6CH 001B6CH
001A6DH 001B6DH
001A6EH 001B6EH
001A6FH 001B6FH

001A70H 001B70H

001A71

H 001B71H

DLC register 0 DLCR0 R/W ----XXXXB

DLC register 1 DLCR1 R/W ----XXXXB

DLC register 2 DLCR2 R/W ----XXXXB

DLC register 3 DLCR3 R/W ----XXXXB

DLC register 4 DLCR4 R/W ----XXXXB

DLC register 5 DLCR5 R/W ----XXXXB

DLC register 6 DLCR6 R/W ----XXXXB

DLC register 7 DLCR7 R/W ----XXXXB

DLC register 8 DLCR8 R/W ----XXXX

001A72H 001B72H

001A73H 001B73H

001A74H 001B74H

001A75H 001B75H

001A76H 001B76H

001A77H 001B77H

001A78H 001B78H

001A79H 001B79H
001A7AH 001B7AH
001A7BH 001B7BH
001A7CH 001B7CH
001A7DH 001B7DH
001A7EH 001B7EH
001A7FH 001B7FH

001A80H

to

001A87

H

001B80H

to

001B87

DLC register 9 DLCR9 R/W ----XXXXB

DLC register 10 DLCR10 R/W ----XXXXB

DLC register 11 DLCR11 R/W ----XXXXB

DLC register 12 DLCR12 R/W ----XXXXB

DLC register 13 DLCR13 R/W ----XXXXB

DLC register 14 DLCR14 R/W ----XXXXB

DLC register 15 DLCR15 R/W ----XXXXB

XXXXXXXX

Data register 0 (8 bytes) DTR0 R/W

H

XXXXXXXX

B

to

B

(Continued)

32

(Continued)

Address

CAN0 CAN1

001A88

H

001B88H

to

001A8F

001A90H

H

001B8F
001B90H

to

001A97

001A98H

H

001B97
001B98H

to

001A9F
001AA0H

H

001B9F

001BA0H

to

001AA7
001AA8H

H

001BA7
001BA8H

to

001AAF
001AB0H

H

001BAF
001BB0H

to

001AB7
001AB8H

H

001BB7
001BB8H

to

001ABF
001AC0H

H

001BBF
001BC0H

to

001AC7
001AC8H

H

001BC7
001BC8H

to

001ACF
001AD0H

H

001BCF
001BD0H

to

001AD7
001AD8H

H

001BD7
001BD8H

to

001ADF
001AE0H

H

001BDF
001BE0H

to

001AE7
001AE8H

H

001BE7
001BE8H

to

001AEF
001AF0H

H

001BEF
001BF0H

to

001AF7
001AF8H

H

001BF7
001BF8H

to

001AFF

H

001BFF

to

to

to

to

to

to

to

to

to

to

to

to

to

to

to

MB90590/590G Series

Register Abbreviation Access Initial Value

Data register 1 (8 bytes) DTR1 R/W

H

Data register 2 (8 bytes) DTR2 R/W

H

Data register 3 (8 bytes) DTR3 R/W

H

Data register 4 (8 bytes) DTR4 R/W

H

Data register 5 (8 bytes) DTR5 R/W

H

Data register 6 (8 bytes) DTR6 R/W

H

Data register 7 (8 bytes) DTR7 R/W

H

Data register 8 (8 bytes) DTR8 R/W

H

Data register 9 (8 bytes) DTR9 R/W

H

Data register 10 (8 bytes) DTR10 R/W

H

Data register 11 (8 bytes) DTR11 R/W

H

Data register 12 (8 bytes) DTR12 R/W

H

Data register 13 (8 bytes) DTR13 R/W

H

Data register 14 (8 bytes) DTR14 R/W

H

Data register 15 (8 bytes) DTR15 R/W

H

XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

33

MB90590/590G Series

INTERRUPT MAP

■■■■

Interrupt cause

2

OS

I

clear

Interrupt vector Interrupt control register

Number Address Number Address

Reset N/A # 08 FFFFDC
INT9 instruction N/A # 09 FFFFD8
Exception N/A # 10 FFFFD4
Time Base Timer N/A # 11 FFFFD0H
External Interrupt (INT0 to INT7) *1 # 12 FFFFCCH
CAN 0 RX N/A # 13 FFFFC8H
CAN 0 TX/NS N/A # 14 FFFFC4H
CAN 1 RX N/A # 15 FFFFC0H
CAN 1 TX/NS N/A # 16 FFFFBCH
8/16 bit PPG 0/1 N/A # 17 FFFFB8H
8/16 bit PPG 2/3 N/A # 18 FFFFB4H
8/16 bit PPG 4/5 N/A # 19 FFFFB0H
8/16 bit PPG 6/7 N/A # 20 FFFFACH
8/16 bit PPG 8/9 N/A # 21 FFFFA8H
8/16 bit PPG A/B N/A # 22 FFFFA4H
16-bit Reload Timer 0 *1 # 23 FFFFA0H
16-bit Reload Timer 1 *1 # 24 FFFF9CH

H 
H 
H 

ICR00 0000B0H

ICR01 0000B1H

ICR02 0000B2H

ICR03 0000B3H

ICR04 0000B4H

ICR05 0000B5H

ICR06 0000B6H

Input Capture 0/1 *1 # 25 FFFF98H
Output compare 0/1 *1 # 26 FFFF94H
Input Capture 2/3 *1 # 27 FFFF90H
Output Compare 2/3 *1 # 28 FFFF8CH
Input Capture 4/5 *1 # 29 FFFF88H
Output Compare 4/5 *1 # 30 FFFF84H
8/10 bit A/D Converter *1 # 31 FFFF80H
I/O Timer/Watch Timer N/A # 32 FFFF7CH
Serial I/O *1 # 33 FFFF78H
Sound Generator N/A # 34 FFFF74H
UART 0 RX *2 # 35 FFFF70H
UART 0 TX *1 # 36 FFFF6CH
UART 1 RX *2 # 37 FFFF68H
UART 1 TX *1 # 38 FFFF64H
UART 2 RX *2 # 39 FFFF60H
UART 2 TX *1 # 40 FFFF5CH
Flash Memory N/A # 41 FFFF58H
Delayed interrupt N/A # 42 FFFF54 H

ICR07 0000B7H

ICR08 0000B8H

ICR09 0000B9H

ICR10 0000BAH

ICR11 0000BBH

ICR12 0000BCH

ICR13 0000BDH

ICR14 0000BEH

ICR15 0000BFH

34

2

*1:The interrupt request flag is cleared by the I
*2:The interrupt request flag is cleared by the I

OS interrupt clear signal.

2

OS interrupt clear signal. A stop request is available.

N/A:The interrupt request flag is not cleared by the I

MB90590/590G Series

2

OS interrupt clear signal.

Note:• For a peripheral module with two interrupt for a single interrupt number, both interrupt request flags are

cleared by the I

• At the end of I
terrupt number. If one interrupt flag starts the I
hardware event, the later event is lost because the flag is cleared by the I
first event. So it is recommended not to use the I

2

• If I

OS is enabled, I2OS is initiated when one of the two interrupt signals in the same interrupt control register
(ICR) is asserted. This means that different interrupt sources share the same I
be unique for each interrupt source. For this reason, when one interrupt source uses the I

2

OS interrupt clear signal.

2

OS, the I2OS clear signal will be asserted for all the interrupt flags assigned to the same in-

2

OS and in the meantime another interrupt flag is set by a

2

OS for this interrupt number.

2

OS clear signal caused by the

2

OS Descriptor which should

2

OS, the other

interrupt should be disabled.

35

MB90590/590G Series

ELECTRICAL CHARACTERISTICS

■■■■

1. Absolute Maximum Ratings

(VSS = AVSS = 0 V)

Parameter Symbol

V

CC VSS − 0.3 VSS + 6.0 V

AV

CC VSS − 0.3 VSS + 6.0 V VCC = AVCC *

Power supply voltage

AVRH,

AVRL

DVCC VSS − 0.3 VSS + 6.0 V VCC ≥ DVCC
Input voltage VI VSS − 0.3 VSS + 6.0 V *
Output voltage VO VSS − 0.3 VSS + 6.0 V *
Clamp Current ICLAMP −2.0 2.0 mA
"L" level max. output current I

OL1 — 15 mA Normal output *

"L" level avg. output current IOLAV1 — 4 mA Normal output, average value *
"L" level max. output current IOL2 — 40 mA High current output *
"L" level avg. output current

"L" level max. overall output current
"L" level max. overall output current
"L" level avg. overall output current
"L" level avg. overall output current

"H" level max. output current
"H" level avg. output current
"H" level max. output current
"H" level avg. output current

"H" level max. overall output current
"H" level max. overall output current
"H" level avg. overall output current
"H" level avg. overall output current

Power consumption
Operating temperature

Storage temperature

IOLAV2

∑I
∑I

∑I

OLAV1

∑I

OLAV2

IOH1

IOHAV1

IOH2

IOHAV2

∑I
∑I

∑I

OHAV1

∑I

OHAV2

PD

TA

TSTG

OL1
OL2

OH1
OH2

Rating

Min. Max.

Unit Remarks

VSS − 0.3 VSS + 6.0 V AVCC ≥ AVRH/L, AVRH ≥ AVRL *

— 30 mA High current output, average value *
— 100 mA Total normal output

330 mA Total high current output

— 50 mA Total normal output, average value *

250 mA

Total high current output, average value

— –15 mA Normal output *
— –4 mA Normal output, average value *
— –40 mA High current output *
— –30 mA High current output, average value *
— -100 mA Total normal output
— -330 mA Total high current output
— -50 mA Total normal output, average value *
—-250mA
— 500 mW

Total high current output, average value
MB90F594A, MB90F591A, MB90F594G

— 400 mW MB90594, MB90591, MB90594G
–40 +85 °C
–55 +150 °C

1

1

2
2

3

4
3
4

5
5

*

3
4
3
4

5

5

*

*1:AV

CC, AVRL and AVRL should not exceed VCC and AVRL should not exceed AVRH.

*2:VI and VO should not exceed VCC + 0.3V. VI should not exceed the specified ratings. However if the maximum

current to/from an input is limited by some means with external components, the I
V

I rating.

CLAMP rating supercedes the

*3:The maximum output current is a peak value for a corresponding pin.
*4:Average output current is an average current value observed for a 100 ms period for a corresponding pin.
*5:Total average current is an average current value observed for a 100 ms period for all corresponding pins.

Note: Average output current = operating current × operating efficiency

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

36

2. Recommended Conditions

Parameter

Power supply voltage

Input H voltage

Input L voltage

Symbol

V

CC

AVCC

V

IHS 0.8 VCC —VCC +0.3 V CMOS hysteresis input pin

V

IHM VCC – 0.3 — VCC +0.3 V MD input pin

ILS VSS – 0.3 — 0.6VCC V CMOS hysteresis input pin

V

VILM VSS – 0.3 — VSS + 0.3 V MD input pin

MB90590/590G Series

Value

Min. Typ. Max.

4.5 5.0 5.5 V Under normal operation

3.0 — 5.5 V

4.75 5.0 5.25 V Under normal operation

3.0 — 5.25 V

Unit Remarks

Maintains RAM data in
stop mode

Maintains RAM data in
stop mode

(VSS = AVSS = 0 V)

MB90V590A
MB90V590G
MB90F594A
MB90F594G
MB90594
MB90594G

MB90F591A
MB90591

Smooth capacitor C
Operating temperature T

S 0.022 0.1 1.0 µF*

A –40 — +85 °C

*: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to

be connected to the V

CC pin must have a capacitance value higher than CS.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

•

C Pin Connection Diagram

C

S

C

37

MB90590/590G Series

3. DC Characteristics

(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G:

(MB90F591A, MB90591: V

Parameter

Output H
voltage

Output L
voltage

Input leak
current

Analog in­put leak cur­rent

Power
supply
current *

Input
capacity

Symbol

V

V

V

V

I

I

ICCS

ICTS

ICCH

CIN

Pin name Condition

Normal

OH1

output
High cur-

OH2

rent output
Normal

OL1

output
High cur-

OL2

rent output

I

IL —

IAL AN0 to AN7

VCC = 4.5 V,
I

OH1 = –4.0 mA

VCC = 4.5 V,
I

OH2 = –30.0 mA

VCC = 4.5 V,
I

OL1 = 4.0 mA

VCC = 4.5 V,
I

OL2 = 30.0 mA

VCC = 5.5 V,
V

VCC = 5.5 V,
AV

VCC = 5.0 V±10%,

CC

Internal frequency:

VCC = 5.0 V±10%,
Internal frequency:

VCC

VCC = 5.0 V±1%,
Internal frequency:

VCC = 5.0 V±10%,
At Stop mode,
T

Other than C,
AV

CC, AVSS,

AVRH, AVRL,
V

CC, VSS,

DV

CC, DVSS,

P70 to P87
P70 to P87

SS < VI < VCC

SS < VI < AVCC

16 MHz,
At normal operation.

16 MHz,
At Sleep mode.

2 MHz,
At Timer mode

A = 25°C

——515pF

— — 15 30 pF

V

CC = 5.0 V±10 %, VSS = AVSS = 0V, TA = −40 °C to +85 °C)

CC = 5.0 V±5 %, VSS = AVSS = 0V, TA = −40 °C to +85 °C)

Value

Unit Remarks

Min. Ty p. Max.

VCC – 0.5 — — V

VCC – 0.5 — — V

——0.4V

——0.5V

–5 — 5 µA

–1 — 1 µA

—3760mA
—5080mA
—5080mA
—4560mA
—1320mA
—1523mA
—1523mA
—1523mA
—0.30.6mA
— 0.35 0.6 mA
— 0.35 0.6 mA
— 0.35 0.6 mA
—520µA
—520µA
—520µA
—520µA

MB90594/594G
MB90F594A/F594G
MB90F591A
MB90591
MB90594/594G
MB90F594A/F594G
MB90F591A
MB90591
MB90594/594G
MB90F594A/F594G
MB90F591A
MB90591
MB90594/594G
MB90F594A/F594G
MB90F591A
MB90591

*: Current values are tentative and subject to change without notice according to improvements in the character-

istics. The power supply current testing conditions are when using the external clock.

38

4. AC Characteristics

(1) Clock Timing

(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G:

(MB90F591A, MB90591: V

Parameter Symbol

Oscillation frequency f

Pin

name

C X0, X1

MB90590/590G Series

V

CC = 5.0 V±10 %, VSS = AVSS = 0V, TA = −40 °C to +85 °C)

CC = 5.0 V±5 %, VSS = AVSS = 0V, TA = −40 °C to +85 °C)

Value

Min. Typ. Max.

3 — 5 MHz When using an oscillation circuit.
3 — 16 MHz When using an external clock.

Unit Remarks

Oscillation cycle time t

CYL X0, X1

62.5 — 333 ns When using an external clock.

200 — 333 ns When using an oscillation circuit.

Frequency deviation with PLL*

Input clock pulse width P

∆f———5%

WH, PWL X0 10 — — ns Duty ratio is about 30 to 70%.

Input clock rise and fall time tCR, tCF X0 — — 5 ns When using external clock
Machine clock frequency f
Machine clock cycle time t

CP —1.5—16MHz
CP — 62.5 — 666 ns

Flash read cycle time tCYCFL —— 2 tCP — ns When Flash is accessed by CPU

*: Frequency deviation indicates the maximum frequency difference from the target frequency when using a multi-

plied clock.

+

α

------

∆f

•

Clock Timing

fo

α

100%×=

ent

C

equen

r

f

al

r

O

f

y

c

α

−

tCYL

0.8 VCC

X0

0.2 VCC

Example of Oscillation circuit

PWH

tCF

X0 X1

C1

PWL

tCR

R

C2

39

MB90590/590G Series

• Guaranteed operation range

Guaranteed operation range (MB90F591A, MB90591)

Guaranteed operation range (MB90V590A, MB90F594A, MB90594,

5.5

5.25

4.75

4.5

Power supply voltage
V

CC (V)

3.0

1.5 8 16

Guaranteed PLL operation range
(MB90V590A, MB90F594A, MB90594,
MB90V590G, MB90F594G, MB90594G)

Machine clock fCP (MHz)

• External clock frequency and machine clock frequency

MB90V590G, MB90F594G, MB90594G)

Guaranteed PLL operation range
(MB90F591A, MB90591)

16

×4 ×3 ×2

12

Machine clock

f

CP (MHz)

9
8

4

3 4 8 16

External clock f

C (MHz)*

*: When using the oscillation circuit, the maximum oscillation clock frequency is 5 MHz.

×1

×1/2

(PLL off)

40

MB90590/590G Series

(2) Reset and Hardware Standby Input

(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G:

V

CC = 5.0 V±10 %, VSS = AVSS = 0V, TA = −40 °C to +85 °C)

(MB90F591A, MB90591: V

Parameter

Reset input time t

Hardware standby input time t

*1:“t

cp” represents one cycle time of the machine clock.

Symbol

RSTL RST

HSTL HST

Pin name

No reset can fully initialize the Flash Memory if it is performing the automatic algorithm.

*2:Oscillation time of oscillator is time that the amplitude reached the 90%.

In the crystal oscillator, the oscillation time is between se v er al ms to tens of ms. In FAR / ceramic oscillator, the
oscillation time is between hundreds of µs to several ms. In the external clock, the oscillation time is 0 ms.

CC = 5.0 V±5 %, VSS = AVSS = 0V, TA = −40 °C to +85 °C)

Value

Unit Remarks

Min. Max.

1

16 tCP*

Oscillation time of

oscillator*

2

+ 16 tCP*

16 tCP*

1

Oscillation time of

oscillator*

2

+ 16 tCP*

— ns Under normal operation
— ms In stop mode

1

— ns Under normal operation
— ms In stop mode

1

Under Normal Operation

RST
HST

In Stop Mode

Internal operation clock

RST
HST

X0

0.6 VCC

tRSTL, tHSTL

0.6VCC 0.6VCC

90% of
amplitude

16 t

Oscillation time of

oscillator

Oscillation setting time

tRSTL, tHSTL

0.6 VCC

CP

Internal reset

Instruction execution

41

MB90590/590G Series

(3) Power On Reset

(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G:

(MB90F591A, MB90591: V

Parameter Symbol Pin name Condition

Power on rise time t
Power off time t

R VCC

OFF VCC 50 — ms Due to repetitive operation

V

CC = 5.0 V±10 %, VSS = AVSS = 0V, TA = −40 °C to +85 °C)

CC = 5.0 V±5 %, VSS = AVSS = 0V, TA = −40 °C to +85 °C)

Value

Unit Remarks

Min. Max.

0.05 30 ms

—

Note • V

• The above values are used for creating a power-on reset.

• Some registers in the device are initialized only upon a po wer-on reset. To initialize these register , turn on

the power supply using the above values.

.

CC must be kept lower than 0.2 V before power-on.

tR

CC

V

Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to
raise the voltage smoothly to suppress fluctuations as shown below.
In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1
V or fewer per second, however, you can use the PLL clock.

3.5 V

VCC

3V

RAM data being held

VSS

0.2 V

0.2 V0.2 V

tOFF

It is recommended to keep the
rising speed of the supply voltage
at 50 mV/ms or slower.

42

(4) UART0/1/2, Serial I/O

(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G:

(MB90F591A, MB90591: V

Parameter Symbol Pin name Condition

Serial clock cycle time t

SCYC SCK0 to SCK3

MB90590/590G Series

V

CC = 5.0 V±10 %, VSS = AVSS = 0V, TA = −40 °C to +85 °C)

CC = 5.0 V±5 %, VSS = AVSS = 0V, TA = −40 °C to +85 °C)

Value

Min. Max.

8 t

CP*— ns

Unit Remarks

SCK ↓ ⇒ SOT delay time t

Valid SIN ⇒ SCK ↑ t

SCK ↑ ⇒ Valid SIN hold time t
Serial clock "H" pulse width t

Serial clock "L" pulse width t

SLOV

IVSH

SHIX

SHSL SCK0 to SCK3
SLSH SCK0 to SCK3 4 tCP —ns

SCK ↓ ⇒ SOT delay time tSLOV

Valid SIN ⇒ SCK ↑ t

SCK ↑ ⇒ Valid SIN hold time t

*: t

CP is the machine cycle (Unit: ns)

IVSH

SHIX

SCK0 to SCK3,
SOT0 to SOT3

SCK0 to SCK3,
SIN0 to SIN3

SCK0 to SCK3,
SIN0 to SIN3

SCK0 to SCK3,
SOT0 to SOT3

SCK0 to SCK3,
SIN0 to SIN3

SCK0 to SCK3,
SIN0 to SIN3

Notes: • AC characteristic in CLK synchronized mode.

• C

L is load capacity value of pins when testing.

• Internal Shift Clock Mode

Internal clock opera­tion output pins are

L = 80 pF + 1 TTL.

C

External clock oper­ation output pins are
C

L = 80 pF + 1 TTL.

–80 80 ns

100 — ns

60 — ns

CP —ns

4 t

— 150 ns

60 — ns

60 — ns

SCK

SOT

SIN

0.8 V
tSLOV

2.4 V

0.8 V
tIVSH

0.8 VCC

0.6 VCC

tSCYC

2.4 V

0.8 V

tSHIX

0.8 VCC

0.6 VCC

43

MB90590/590G Series

• External Shift Clock Mode

tSLSH

tSHSL

SCK

0.6 VCC
tSLOV

SOT

SIN

(5)Timer Input Timing

(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G:

(MB90F591A, MB90591: V

Parameter Symbol Pin name Condition

TIWH TIN0

t

Input pulse width

tTIWL IN0 to IN5 1 — µs In stop mode

0.8 VCC

0.8 VCC

0.6 VCC

2.4 V

0.8 V
tIVSH

0.8 VCC

0.6 VCC

V

CC = 5.0 V±10 %, VSS = AVSS = 0V, TA = −40 °C to +85 °C)

CC = 5.0 V±5 %, VSS = AVSS = 0V, TA = −40 °C to +85 °C)

tSHIX

0.8 VCC

0.6 VCC

Value

Unit Remarks

Min. Max.

4 tCP — ns Under normal operation

—

44

•

Timer Input Timing

0.8 VCC

tTIWH

0.8 VCC

0.6 VCC

0.6 VCC

tTIWL

(6)Trigger Input Timing

(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G:

(MB90F591A, MB90591: V

Parameter Symbol Pin name Condition

Input pulse width

TRGH

t
tTRGL

INT0 to

INT7, ADTG

• Trigger Input Timing

MB90590/590G Series

V

CC = 5.0 V±10 %, VSS = AVSS = 0V, TA = −40 °C to +85 °C)

CC = 5.0 V±5 %, VSS = AVSS = 0V, TA = −40 °C to +85 °C)

Value

Min. Max.

—5 tCP —ns

Unit Remarks

0.8 VCC

tTRGH

0.8 VCC

0.6 VCC

0.6 VCC

tTRGL

(7) Slew Rate High Current Outputs (MB90F591A, MB90591, MB90594G and MB90F594G only)

(MB90F594G, MB90594G: V

(MB90F591A, MB90591: V

CC = 5.0 V±10 %, VSS = AVSS = 0V, TA = −40 °C to +85 °C)

CC = 5.0 V±5 %, VSS = AVSS = 0V, TA = −40 °C to +85 °C)

Value

Parameter Symbol Pin name Condition

Unit Remarks

Min. Max.

Output Rise/Fall time

R2

tF2

Port P70 to P77,

Port P80 to P87

—1540ns

t

• Slew Rate Output Timing

H

V

L

V

R2

t

H

V

L

V

F2

t

VH = VOL2 + 0.1 × (VOH2 − VOL2)
V

L = VOL2 + 0.9 × (VOH2 − VOL2)

45

MB90590/590G Series

5. A/D Converter

(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G:

V

CC = AVCC = 5.0 V±10 %, VSS = AVSS = 0V, 3.0 V ≤ AVR+ − AVR-, TA = −40 °C to +85 °C)

(MB90F591A, MB90591: VCC = AVCC = 5.0 V±5 %, VSS = AVSS = 0V, 3.0 V ≤ AVR+ − AVR-, TA = −40 °C to +85 °C)

Parameter Symbol Pin name

Min. Typ. Max.

Resolution — — — — 10 bit
Conversion error — — — — ±5.0 LSB
Nonlinearity error — — — — ±2.5 LSB

Value

Unit Remarks

Differential linearity
error

Zero transition voltage V
Full scale transition voltage V
Conversion time — — — 352t

—— — —±1.9 LSB

OT AN0 to AN7 AVRL – 3.5 AVRL +0.5 AVRL + 4.5 mV

FST AN0 to AN7 AVRH – 6.5 AVRH –1.5 AVRH + 1.5 mV

CP —ns

Sampling time — — — 64tCP —ns
Analog port input current I
Analog input voltage range V

AIN AN0 to AN7 -1 — +1 µA

AIN AN0 to AN7 AVRL — AVRH V

— AVRH AVRL + 2.7 — AVCC V

Reference voltage range

— AVRL 0 — AVRH – 2.7 V

A AVCC —5—mA

I

Power supply current

I

AH AVCC —— 5µA*

MB90594
MB90V590A
MB90V590G
MB90F594A
MB90F594G
MB90F591A

MB90594G
MB90591

Reference voltage current

R AVRH

I

— 400 600 µA

— 140 600 µA

I

RH AVRH — — 5 µA*

Offset between input
channels

— AN0 to AN7 — — 4 LSB

*: When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) when the CPU is stopped.

46

MB90590/590G Series

6. A/D Converter Glossary

Resolution: Analog changes that are identifiable with the A/D converter
Linearity error: The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00

0000 0001”) with the full-scale transition point (“11 1111 1110” ↔
conversion characteristics

Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the

theoretical value

Total error :The total error is defined as a difference between the actual value and the theoretical value, which

includes zero-transition error/full-scale transition error and linearity error.

Total error

3FF

“11 1111 1111”) from actual

3FE

3FD

t

u

p

t

u

o

l

004

a

t

i

g

i

D

003

002

001

1 LSB = (Theoretical value)

VOT (Theoretical value) = AVRL + 0.5 LSB[V]

FST

V

(Theoretical value) = AVRH – 1.5 LSB[V]

AVRH – AVRL

Actual conversion
value

1024

{1 LSB × (N – 1) + 0.5 LSB}

(measured value)

Actual conversion
characteristics

Theoretical
characteristics

0.5 LSB

Analog inputAVRL AVRH

[V]

Total error for digital output N

VNT: Voltage at a transition of digital output from (N – 1) to N

V

NT

0.5 LSB

=

NT

– {1 LSB × (N – 1) + 0.5 LSB}

V

1 LSB

[LSB]

(Continued)

47

MB90590/590G Series

(Continued)

Linearity error

3FF

3FE

3FD

t

u

p

t

u

o

l

004

a

t

i

g

i
D

003

002

001

Linearity error of
digital output N

Differential linearity error
of digital N

1 LSB

OT:

Voltage at transition of digital output from “000H” to “001H”

V

FST

: Voltage at transition of digital output from “3FEH” to “3FFH”

V

Actual conversion
value

{1 LSB × (N – 1)+ VOT}

Theoretical
characteristics

OT

(measured value)

V

Analog inputAVRL AVRH Analog inputAVRL AVRH

NT

V

– {1 LSB × (N – 1) + VOT}

=

=

FST

OT

V

– V

=

1022

[V]

(measured value)

Actual conversion
characteristics

1 LSB

(N + 1)T

– V

V

1 LSB

FST

V

(measured value)

NT

V

NT

– 1 LSB [LSB]

[LSB]

N + 1

t

u

p

t

u

o

l

a

t

i

g

i
D

N – 1

N – 2

Differential linearity error

Actual conversion value

N

Theoretical characteristics

(N + 1)T

V
(measured value)

NT

V

(measured value)

Actual conversion
value

7. Notes on Using A/D Converter

Select the output impedance value for the e xternal circuit of analog input according to the f ollowing conditions, :

• Output impedance values of the external circuit of 15 kΩ or lower are recommended.

• When capacitors are connected to external pins, the capacitance of several thousand times the internal
capacitor value is recommended to minimized the eff ect of v oltage distribution between the e xternal capacitor
and internal capacitor.

When the output impedance of the external circuit is too high, the sampling period for analog voltages may not
be sufficient (sampling period = 4.00 µs @machine clock of 16 MHz).

• Equipment of analog input circuit model

Analog input

Comparator

3.2 kΩ Max.
30 pF Max.

Note: Listed values must be considered as standards.

•Error

The smaller the | AVRH − AVRL |, the greater the error would become relatively.

48

MB90590/590G Series

ORDERING INFORMATION

■■■■

Part number Package Remarks

MB90594PF
MB90591PF
MB90594GPF
MB90F594GPF
MB90F594APF
MB90F591APF

MB90V590ACR
MB90V590GCR

100-pin

256-pin

Plastic QFP

(FPT-100P-M06)

Ceramic PGA

(PGA-256C-A01)

For evaluation

49

MB90590/590G Series

PACKA GE DIMENSION

■■■■

100-pin plastic QFP

(FPT-100P-M06)

23.90±0.40(.941±.016)

20.00±0.20(.787±.008)

81

INDEX

100

LEAD No.

C

2000 FUJITSU LIMITED F100008-3C-3

1

0.65(.0256)TYP 0.30±0.10

18.85(.742)REF

22.30±0.40(.878±.016)

(.012±.004)

0.10(.004)

"A"

0.13(.005)

5180

50

(.551±.008) (.705±.016)

31

30

M

"B"

17.90±0.4014.00±0.20

Details of "A" part

0.25(.010)

0.30(.012)

0.18(.007)MAX

0.53(.021)MAX

3.35(.132)MAX

(Mounting height)

0.05(.002)MIN
(STAND OFF)

12.35(.486)
REF

0.15±0.05(.006±.002)

Details of "B" part

16.30±0.40
(.642±.016)

0 10°

0.80±0.20

(.031±.008)

Dimensions in mm (inches)

50

MB90590/590G Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: [phone]
Fax: [phone]

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: [phone]
Fax: [phone]

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: [phone]
Fax: [phone]

http://www.fujitsumicro.com/

Europe

FUJITSU MICROELECTRONICS EUR OPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: [phone]
Fax: [phone]

http://www.fujitsu-fme.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: [phone]
Fax: [phone]

http://www.fmap.com.sg/

Korea

FUJITSU MICROELECTRONICS K OREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: [phone]
Fax: [phone]

All Rights Reserved.

The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.

The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.

The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.

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applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
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where extremely high levels of reliability are demanded (such as
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are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.

Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.

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technologies subject to certain restrictions on export under the
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F0101

 FUJITSU LIMITED Printed in Japan