FUJITSU MB90570A DATA SHEET

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FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13701-4E

16-bit Proprietary Microcontroller

CMOS

F2MC-16LX MB90570/A Series

MB90573/574/F574/V570/574A/F574A/V570A

DESCRIPTION

■

The MB90570/A series is a general-purpose 16-bit microcontroller developed and designed by Fujitsu for
process control applications in consumer products that require high-speed real time processing. It contains an

2C*2

I

bus interface that allows inter-equipment communication to be implemented readily. This product is well

adapted to car audio equipment, VTR systems, and other equipment and systems.

2

The instruction set of F
sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and
enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word
data.

MC-16LX CPU core inherits AT architecture of F2MC*1 family with additional instruction

The MB90570/A series has peripheral resources of an 8/10-bit A/D converter, an 8-bit D/A converter, UART
(SCI), an extended I/O serial interface, an 8/16-bit up/down counter/timer, an 8/16-bit PPG timer, I/O timer (a
16-bit free run timer, an input capture (ICU), an output compare (OCU)).

2

*1: F

MC stands for FUJITSU Flexible Microcontroller.

*2: Purchase of Fujitsu I

components in an I
defined by Philips.

PACKAGE

■

120-pin plastic LQFP

2

C components conveys a license under the Philips I2C Patent Rights to use these

2

C system, provided that the system conforms to the I2C Standard Specification as

120-pin plastic QFP

120-pin plastic LQFP

(FPT-120P-M05)

(FPT-120P-M13)

(FPT-120P-M21)

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MB90570/A Series

FEATURES

■

•Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from 1/2 to 4× oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz).
Minimum instruction ex ecution time : 62.5 ns (at oscillation of 4 MHz, 4× PLL clock, operation at V

• Maximum memory space
16 Mbytes

• Instruction set optimized for controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
Enhanced signed multiplication/division instruction and RETI instruction functions
Enhanced precision calculation realized by the 32-bit accumulator

• Instruction set designed for high level language (C) and multi-task operations
Adoption of system stack pointer

Enhanced pointer indirect instructions
Barrel shift instructions

• Program patch function (for two address pointers)

• Enhanced execution speed
4-byte instruction queue

• Enhanced interrupt function
8 levels, 34 factors

• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI

• Embedded ROM size and types
Mask ROM: 128 Kbytes/256 Kbytes

Flash ROM: 256 Kbytes
Embedded RAM size: 6 Kbytes/10 Kbytes (mask ROM)

10 Kbytes (flash memory)
10 Kbytes (evaluation device)

• Low-power consumption (standby) mode
Sleep mode (mode in which CPU operating clock is stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Hardware standby mode

•Process
CMOS technology

• I/O port
General-purpose I/O ports (CMOS): 63 ports

General-purpose I/O ports (with pull-up resistors): 24 ports
General-purpose I/O ports (open-drain): 10 ports
Total: 97 ports

2

OS): Up to 16 channels

of 5.0 V)

CC

(Continued)

2

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MB90570/A Series

(Continued)

•Timer
Timebase timer/watchdog timer: 1 channel
8/16-bit PPG timer: 8-bit × 2 channels or 16-bit × 1 channel

• 8/16-bit up/down counter/timer: 1 channel (8-bit × 2 channels)

• 16-bit I/O timer
16-bit free run timer: 1 channel
Input capture (ICU): Generates an interrupt request by latching a 16-bit free run timer counter value upon

detection of an edge input to the pin.

Output compare (OCU): Generates an interrupt request and re verse the output lev el upon detection of a match

between the 16-bit free run timer counter value and the compare setting value.

• Extended I/O serial interface: 3 channels

2

•I

C interface (1 channel)

Serial I/O port for supporting Inter IC BUS

• UART0 (SCI), UART1 (SCI)
With full-duplex double buffer
Clock asynchronized or clock synchronized transmission can be selectively used.

• DTP/external interrupt circuit (8 channels)
A module for starting extended intelligent I/O service (EI

by an external input.

• Delayed interrupt generation module
Generates an interrupt request for switching tasks.

• 8/10-bit A/D converter (8 channels)
8/10-bit resolution
Starting by an external trigger input.
Conversion time: 26.3 µs

• 8-bit D/A converter (based on the R-2R system)
8-bit resolution: 2 channels (independent)

Setup time: 12.5 µs

• Clock timer: 1 channel

• Chip select output (8 channels)
An active level can be set.

• Clock output function

2

OS) and generating an external interrupt triggered

3

MB90570/A Series

PRODUCT LINEUP

■

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Part number

Item

Classification Mask ROM products Flash ROM products Evaluation product
ROM size 128 Kbytes 256 Kbytes None
RAM size 6 Kbytes 10 Kbytes

CPU functions

Ports

UART0 (SCI), UART1 (SCI)

8/10-bit A/D converter

MB90573

Minimum execution time: 62.5 ns (at machine clock of 16 MHz)

Interrupt processing time: 1.5 µs (at machine clock of 16 MHz, minimum value)

General-purpose I/O ports (with pull-up resistor): 24

General-purpose I/O ports (N-ch open-drain output): 10

Clock synchronized transmission (62.5 kbps to 1 Mbps)

Clock asynchronized transmission (1202 bps to 9615 bps)
Transmission can be performed by bi-directional serial transmission or by
master/slave connection.

One-shot conversion mode (converts selected channel only once)

Scan conversion mode (converts two or more successive channels and can

Continuous conversion mode (converts selected channel continuously)

Stop conversion mode (converts selected channel and stop operation repeatedly)

MB90574/A MB90F574/A MB90V570/A

The number of instructions: 340
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1 bit, 8 bits, 16 bits

General-purpose I/O ports (CMOS output): 63

Total: 97

Resolution: 8/10-bit
Number of inputs: 8

program up to 8 channels.)

8/16-bit PPG timer

8/16-bit up/down counter/
timer

16-bit
free run timer

16-bit
I/O timer

4

Output
compare
(OCU)

Input capture
(ICU)

Number of channels: 1 (or 8-bit × 2 channels)

PPG operation of 8-bit or 16-bit

A pulse wave of given intervals and given duty ratios can be output.

Pulse interval: 62.5 ns to 1 µs (at oscillation of 4 MHz, machine clock of 16 MHz)

Number of channels: 1 (or 8-bit × 2 channels)

Event input: 6 channels

8-bit up/down counter/timer used: 2 channels

8-bit re-load/compare function supported: 1 channel

Number of channel: 1

Overflow interrupts

Number of channels: 4

Pin input factor: A match signal of compare register

Number of channels: 2

Rewriting a register value upon a pin input (rising, falling, or both edges)

(Continued)

(Continued)

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MB90570/A Series

Part number

Item

DTP/external interrupt circuit

Delayed interrupt generation
module

Extended I/O serial interface

2

C interface

I

Timebase timer

8-bit D/A converter

Watchdog timer

Low-power consumption
(standby) mode

MB90573

Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.

External interrupt circuit or extended intelligent I/O service (EI

An interrupt generation module for switching tasks used in real time operating

Clock synchronized transmission (3125 bps to 1 Mbps)

Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms

Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms

Sleep/stop/CPU intermittent operation/clock timer/hardware standby

MB90574/A MB90F574/A MB90V570/A

Number of inputs: 8

2

OS) can be used.

systems.

LSB first/MSB first

Serial I/O port for supporting Inter IC BUS

18-bit counter

(at oscillation of 4 MHz)

8-bit resolution

Number of channels: 2 channels

Based on the R-2R system

(at oscillation of 4 MHz, minimum value)

Process CMOS
Power supply voltage for

operation*

* :Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)

Assurance for the MB90V570/A is given only for operation with a tool at a power voltage of 4.5 V to 5.5 V, an
operating temperature of 0 to +25°C, and an operating frequency of 1 MHz to 16 MHz.

PACKAGE AND CORRESPONDING PRODUCTS

■

Package MB90573 MB90574 MB90F574/A MB90574A

FPT-120P-M05 ×
FPT-120P-M13
FPT-120P-M21 × ×

: Available × : Not available

Note: For more inf ormation about each package, see section “■ Pac kage Dimensions.”

4.5 V to 5.5 V

5

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MB90570/A Series

DIFFERENCES AMONG PRODUCTS

■

Memory Size

In evaluation with an evaluation product, note the difference between the evaluation product and the product
actually used. The following items must be taken into consideration.

• The MB90V570/A does not have an internal ROM, however, operations equivalent to chips with an internal
ROM can be ev aluated b y using a dedicated development tool, enabling selection of ROM size b y settings of
the development tool.

• In the MB90V570/A, images from FF4000
mapped to bank FE and FF only. (This setting can be changed by configuring the deveolpment tool.)

• In the MB90F574/574/573/F574A/574A, images from FF4000
FF0000

• The products designated with /A are different from those without /A in that they are DTP/externally-interrupted
types which return from standby mode at the ch.0 to ch.1 edge request.

to FF3FFFH to bank FF only.

H

to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to

H

to FFFFFFH are mapped to bank 00, and

H

6

PIN ASSIGNMENT

■

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MB90570/A Series

(Top view)

P31/RD
P32/WRL
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
V

CC

P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT1
P45/SCK1
P46/PPG0
P47/PPG1
P50/SIN2
P51/SOT2
P52/SCK2
P53/SIN3
P54/SOT3
P55/SCK3
P56/IN0
P57/IN1
P60/SIN4
P61/SOT4
P62/SCK4
P63/CKOT
P64/OUT0
P65/OUT1

P30/ALE

VSSP27/A23

P26/A22

P25/A21

P24/A20

P23/A19

P22/A18

P21/A17

P20/A16

P17/AD15

P16/AD14

P15/AD13

P14/AD12

P13/AD11

P12/AD10

P11/AD09

P10/AD08

P07/AD07

P06/AD06

P05/AD05

P04/AD04

P03/AD03

P02/AD02

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

3132333435363738394041424344454647484950515253545556575859

1009998979695949392

P01/AD01

P00/AD00

VCCX1X0V

SS

91

60

90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61

RST
MD0
MD1
MD2
HST
PC3
PC2
PC1
PC0
PB7
PB6/ADTG
PB5/IRQ5
PB4/IRQ4
PB3/IRQ3
PB2/IRQ2
PB1/IRQ1
X0A
X1A
PB0/IRQ0
PA7/SCL
PA6/SDA
PA5/ZIN1
PA4/BIN1
PA3/AIN1/IRQ7
PA2/ZIN0
PA1/BIN0
PA0/AIN0/IRQ6
V

SS

P97/CS7
P96/CS6

P66/OUT2

P67/OUT3

VSSC

P70

P71

P72

DVCCDVSSP73/DA0

P74/DA1

AVCCAVRH

AVRL

(FPT-120P-M05)
(FPT-120P-M13)
(FPT-120P-M21)

AVSSP80/AN0

P81/AN1

P82/AN2

P83/AN3

P84/AN4

P85/AN5

P86/AN6

P87/AN7

VCCP90/CS0

P91/CS1

P92/CS2

P93/CS3

P94/CS4

P95/CS5

7

MB90570/A Series

PIN DESCRIPTION

■

Pin no.

Pin name Circuit type Function

LQFP-120 *

QFP-120 *

92,93 X0,X1 A
74,73 X0A,X1A B

89 to 87 MD0 to MD2 C

90 RST C
86 HST C

95 to 102 P00 to P07 D

103 to 110 P10 to P17 D

111 to 118 P20 to P27 E

120 P30 E

1

2

AD00 to AD07

AD08 to AD15

A16 to A23

ALE

1P31 E

RD

2P32 E

WRL

3P33 E

WRH

4P34 E

HRQ

5P35 E

HAK

6P36 E

RDY

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High speed oscillator input pins
Low speed oscillator input pins
These are input pins used to designate the operating mode. They should

be connected directly to Vcc or Vss.
Reset input pin
Hardware standby input pin
In single chip mode, these are general purpose I/O pins. When set for

input, they can be set by the pull-up resistance setting register (RDR0).
When set for output, this setting will be invalid.

In external bus mode, these pins function as address low output/data low
I/O pins.

In single chip mode, these are general purpose I/O pins. When set for
input, they can be set by the pull-up resistance setting register (RDR1).
When set for output, the setting will be invalid.

In external bus mode, these pins function as address middle output/data
high I/O pins.

In single chip mode this is a general-purpose I/O port.
In external bus mode, these pins function as address high output pins.
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the address latch enable signal

output pin.
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the read strobe signal output

pin.
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the data bus lower 8-bit write

strobe signal output pin.
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the data bus upper 8-bit write

strobe signal output pin.
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the hold request signal input

pin.
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the hold acknowledge signal

output pin.
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the ready signal input pin.

.

*1: FPT-120P-M05
*2: FPT-120P-M13

8

FPT-120P-M21

,

(Continued)

Pin no.

Pin name Circuit type Function

LQFP-120 *

QFP-120 *

1

2

7P37 E

CLK

9P40 F

SIN0

10 P41 F

SOT0

11 P42 F

SCK0

12 P43 F

SIN1

13 P44 F

SOT1

14 P45 F

SCK1

15,16 P46,P47 F

PPG0,PPG1

17 P50 E

SIN2

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MB90570/A Series

In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the clock (CLK) signal output

pin.
In single chip mode this is a general-purpose I/O port. It can be set to open

drain by the ODR4 register.
This is also the UART ch.0 serial data input pin. While UART ch.0 is in

input operation, this input signal is in continuous use, and therefore the
output function should only be used when needed. If shared by output
from other functions, this pin should be output disabled during SIN
operation.

In single chip mode this is a general-purpose I/O port. It can be set to open
drain by the ODR4 register.

This is also the UART ch.0 serial data output pin. This function is valid
when UART ch.0 is enabled for data output.

In single chip mode this is a general-purpose I/O port. It can be set to open
drain by the ODR4 register.

This is also the UART ch.0 serial clock I/O pin. This function is valid when
UART ch.0 is enabled for clock output.

In single chip mode this is a general-purpose I/O port. It can be set to
open-drain by the ODR4 register.

This is also the UART ch.1 serial data input pin. While UART ch.1 is in
input operation, this input signal is in continuous use, and therefore the
output function should only be used when needed. If shared by output
from other functions, this pin should be output disabled during SIN
operation.

In single chip mode this is a general-purpose I/O port. It can be set to
opendrain by the ODR4 register.

This is also the UART ch.1 serial data output pin. This function is valid
when UART ch.1 is enabled for data output.

In single chip mode this is a general-purpose I/O port. It can be set to open
drain by the ODR4 register.

This is also the UART ch.1 serial clock I/O pin. This function is valid when
UART ch.1 is enabled for clock output.

In single chip mode this is a general-purpose I/O port. It can be set to open
drain by the ODR4 register.

These are also the PPG0, 1 output pins. This function is valid when PPG0,
1 output is enabled.

In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.0 data input pin. During serial data input, this

input signal is in continuous use, and therefore the output function should
only be used when needed.

*1: FPT-120P-M05
*2: FPT-120P-M13

FPT-120P-M21

,

(Continued)

9

MB90570/A Series

Pin no.

Pin name Circuit type Function

LQFP-120 *

QFP-120 *

18 P51 E

19 P52 E

20 P53 E

21 P54 E

22 P55 E

23,24 P56,P57 E

25 P60 F

26 P61 F

27 P62 F

28 P63 F

*1: FPT-120P-M05
*2: FPT-120P-M13

1

2

SOT2

SCK2

SIN3

SOT3

SCK3

IN0,IN1

SIN4

SOT4

SCK4

CKOT

FPT-120P-M21

,

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In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.0 data output pin. This function is valid when

serial ch.0 is enabled for serial data output.
In single chip mode this is a general-purpose I/O port .
This is also the I/O serial ch.0 clock I/O pin. This function is valid when

serial ch.0 is enabled for serial data output.
In single chip mode this is a general-purpose I/O port.

This is also the I/O serial ch.1 data input pin. During serial data input, this
input signal is in continuous use, and therefore the output function should
only be used when needed.

In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.1 data output pin. This function is valid when

serial ch.1 is enabled for serial data output.
In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.1 clock I/O pin. This function is valid when

serial ch.1 is enabled for serial data output.
In single chip mode this is a general-purpose I/O port.

These are also the input capture ch.0/1 trigger input pins. During input
capture signal input on ch.0/1 this function is in continuous use, and
therefore the output function should only be used when needed.

In single chip mode this is a general-purpose I/O port. When set for input
it can be set by the pull-up resistance register (RDR6). When set for
output this setting will be invalid.

This is also the I/O serial ch.2 data input pin. During serial data input this
function is in continuous use, and therefore the output function should
only be used when needed.

In single chip mode this is a general-purpose I/O port. When set for input
it can be set by the pull-up resistance register (RDR6). When set for
output this setting will be invalid.

This is also the I/O serial ch.2 data output pin. This function is valid when
serial ch.2 is enabled for serial data output.

In single chip mode this is a general-purpose I/O port. When set for input
it can be set by the pull-up resistance register (RDR6). When set for
output this setting will be invalid.

This is also the I/O serial ch.2 serial clock I/O pin. This function is valid
when serial ch.2 is enabled for serial data output.

In single chip mode this is a general-purpose I/O port. When set for input
it can be set by the pull-up resistance register (RDR6). When set for
output this setting will be invalid.

This is also the clock monitor output pin. This function is valid when cloc k
monitor output is enabled.

(Continued)

10

Pin no.

Pin name Circuit type Function

LQFP-120 *

QFP-120 *

1

2

29 to 32 P64 to P67 F

OUT0 to
OUT3

35 to 37 P70 to P72 E

40,41 P73,P74 I

DA0,DA1

46 to 53 P80 to P87 K

AN0 to AN7

55 to 62 P90 to P97 E

CS0 to CS7

34 C G

64 PA0 E

AIN0
IRQ6

65 PA1 E

BIN0

66 PA2 E

ZIN0

67 PA3 E

AIN1
IRQ7

68 PA4 E

BIN1

69 PA5 E

ZIN1

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MB90570/A Series

In single chip mode these are general-purpose I/O ports. When set for
input they can be set by the pull-up resistance register (RDR6). When set
for output this setting will be invalid.

These are also the output compare ch.0 to ch.3 event output pins. This
function is valid when the respective channel(s) are enabled for output.

These are general purpose I/O ports.
These are general purpose I/O ports.
These are also the D/A converter ch.0,1 analog signal output pins.
These are general purpose I/O ports.
These are also A/D converter analog input pins. This function is valid

when analog input is enabled.
These are general purpose I/O ports.

These are also chip select signal output pins. This function is valid when
chip select signal output is enabled.

This is the power supply stabilization capacitor pin. It should be
connected externally to an 0.1 µF ceramic capacitor. Note that this is
not required on the FLASH model (MB90F574/A) and MB90574A.

This is a general purpose I/O port.
This pin is also used as count clock A input for 8/16-bit up-down counter

ch.0.
This pin can also be used as interrupt request input ch. 6.

This is a general purpose I/O port.
This pin is also used as count clock B input for 8/16-bit up-down counter

ch.0.
This is a general purpose I/O port.
This pin is also used as count clock Z input for 8/16-bit up-down counter

ch.0.
This is a general purpose I/O port.
This pin is also used as count clock A input for 8/16-bit up-down counter

ch.1.
This pin can also be used as interrupt request input ch.7.
This is a general purpose I/O port.
This pin is also used as count clock B input for 8/16-bit up-down counter

ch.1.
This is a general purpose I/O port.

This pin is also used as count clock Z input for 8/16-bit up-down counter
ch.1.

*1: FPT-120P-M05
*2: FPT-120P-M13

FPT-120P-M21

,

(Continued)

11

MB90570/A Series

(Continued)

Pin no.

Pin name Circuit type Function

LQFP-120 *

QFP-120 *

70 PA6 L

71 PA7 L

72,

75 to 79

80 PB6 E

81 PB7 E

82 to 85 PC0 to PC3 E

8,54,94 V

33,63,

91,119

42 AV
43 AVRH J

44 AVRL H
45 AV

38 DV
39 DV

1

2

SDA

SCL

PB0,
PB1 to PB5

IRQ0,
IRQ1 to IRQ5

ADTG

CC

V

SS

CC

SS

CC

SS

Power
supply

Power
supply

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This is a general purpose I/O port.
This pin is also used as the data I/O pin for the 12C interface. This

function is valid when the 1

2

the 1

C interface is operating this port's output level should be set to

Hi-Z level (high impedance setting: PDRA=1).
This is a general purpose I/O port.

This pin is also used as the clock I/O pin for the 12C interface. This
function is valid when the 1

2

the 1

C interface is operating this port's output level should be set to

Hi-Z level (high impedance setting: PDRA=1).

E

H

H
H

H

These are general-purpose I/O ports.

These pins are also the external interrupt input pins. IRQ0, 1 are
enabled for both rising and falling edge detection, and therefore cannot
be used for recovery from STOP status for MB90V570, MB90F574,
MB90573 and MB90574. However, IRQ0, 1 can be used for recovery
from STOP status for MB90V570A, MB90F574A and MB90574A.

This is a general purpose I/O port.
This is also the A/D converter external trigger input pin. While the A/D

converter is in input operation, this input signal is in continuous use, and
therefore the output function should only be used when needed.

This is a general purpose I/O port.
These are general purpose I/O ports.
These are power supply (5V) input pins.

These are power supply (0V) input pins.

This is the analog macro (D/A, A/D etc.) Vcc power supply input pin.
This is the A/D converter Vref+ input pin. The input voltage should not

exceed Vcc.
This is the A/D converter Vref-input pin. The input voltage should not

belower than Vss.
This is the analog macro (D/A, A/D etc.) Vss power supply input pin.

This is the D/A converter Vref input pin. The input voltage should not
exceed Vcc..

This is the D/A converter GND power supply pin. It should be set to Vss
equivalent potential.

2

C interface is enabled for operation. While

2

C interface is enabled for operation. While

*1: FPT-120P-M05
*2: FPT-120P-M13

12

FPT-120P-M21

,

MB90570/A Series

I/O CIRCUIT TYPE

■

Type Circuit Remarks

A • Oscillator circuit

X1

X0

Standby control signal

B • Oscillator circuit

X1A

Oscillator recovery resistance for high
speed= approx. 1M

Oscillator recovery resistancer for low
speed =approx. 1MΩ

To Top / Lineup / Index

Ω

X0A

Standby control signal

C • Hysteresis input pin

Resistance value=approx. 50kΩ(typ.)

R

Hysteresis input

D • CMOS hystersis input pin with input pull-

V

CC

V

P-ch

Selective signal either
with a pull-up resistor or

CC

without it.

P-ch

up control

• CMOS level output.

• CMOS hystersis input
(Includes input shutoff standby control
function)

= 4 mA

I

OL

N-ch

R

Standby control for input interruption

Hysteresis input

• Pull-up resistance value=
approx.50kΩ(typ.)
I

= 4mA

OL

(Continued)

13

MB90570/A Series

Type Circuit Remarks

E • CMOS hysteresis input/output pin.

IOL = 4 mA

V

CC

P-ch

N-ch

R

Standby control for input interruption

Hysteresis input

• CMOS level output

• CMOS hysteresis input
(Includes input shutoff standby control
function)
I

= 4mA

OL

To Top / Lineup / Index

F • CMOS hysteresis input/output pin.

V

CC

P-ch

• CMOS level output

• CMOS hysteresis input
(Includes input shutoff standby control
function)

= 10mA (Large current port)

I

N-ch

R

= 10 mA

I

OL

G • C pin output

V

Standby control for input interruption

CC

Hysteresis input

OL

(capacitance connector pin).

P-ch

N-ch

H • Analog power supply protector

V

CC

On the MB90F574 this pin is not
connected (NC).

circuit.

P-ch

AVP

N-ch

14

I • CMOS hysteresis input/output

V

CC

P-ch

• Analog output/CMOS output
dual-function pin ( CMOS output is not
available during analog output.)
(Analog output priority : DAE = 1)

= 4 mA

I

OL

N-ch

R

Standby control for input interruption

Hysteresis input

DAO

• Includes input shutoff standby control
function.
I

= 4mA

OL

(Continued)

To Top / Lineup / Index

MB90570/A Series

Type Circuit Remarks

J • A/D converter ref+ power supply input

V

CC

P-ch

N-ch

ANE
AVR
ANE

P-ch
N-ch

pin(AVRH), with power supply
protector circuit.

K • CMOS hysteresis input /analog input

V

CC

P-ch

dual-function pin.

• CMOS output

• Includes input shutoff function at input

N-ch

R

Standby control for input interruption

I

= 4 mA

OL

L • Hysteresis input

V

CC

Hysteresis input

Analog input

N-ch

shutoff standby.

• N-ch open-drain output

• Includes input shutoff standby control
function.
I

= 4mA

OL

= 4 mA

I

OL

N-ch

R

Hysteresis input

Standby control for input interruption

15

To Top / Lineup / Index

MB90570/A Series

HANDLING DEVICES

■

1. Make Sure that the Voltage not Exceed the Maximum Rating (to Avoid a Latch-up).

In CMOS ICs, a latch-up phenomenon is caused when an voltage exceeding VCC or an voltage below VSS is
applied to input or output pins or a voltage exceeding the rating is applied across V

When a latch-up is caused, the power supply current may be dramatically increased causing resultant thermal
break-down of devices. To avoid the latch-up, make sure that the voltage not exceed the maximum rating.

and VSS.

CC

In turning on/turning off the analog power supply, make sure the analog power voltage (AV
analog input voltages not exceed the digital voltage (V

CC

).

, AVRH, DVCC) and

CC

2. Connection of Unused Pins

Leaving unused pins open may result in abnormal operations. Clamp the pin level by connecting it to a pull-up
or a pull-down resistor.

3. Notes on Using External Clock

In using the external clock, drive X0 pin only and leave X1 pin unconnected.

Using external clock

•

X0

Open

X1

MB90570/A series

4. Power Supply Pins

In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to
avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to
lower the electro-magnetic emission level and abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total current rating.

Make sure to connect V
It is recommended to provide a bypass capacitor of around 0.1 µF between V

5. Crystal Oscillator Circuit

Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.

It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand
area for stabilizing the operation.

16

and VSS pins via lowest impedance to power lines.

CC

and VSS pin near the device.

CC

To Top / Lineup / Index

MB90570/A Series

6. Turning-on Sequence of Power Supply to A/D Conv erter and Analog Inputs

Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVRL, DVCC,
DV

) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC).

SS

Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage not exceed AVRH or AV
is acceptable).

7. Connection of Unused Pins of A/D Converter

Connect unused pins of A/D converter and those of D/A converter to AVCC = VCC, AVSS = AVRH = DVCC = VSS.

8. N.C. Pin

The N.C. (internally connected) pin must be opened for use.

9. Notes on Energization

(turning on/off the analog and digital power supplies simultaneously

CC

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
or more µs (0.2 V to 2.7 V).

10. Initialization

In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers
turning on the power again.

17

MB90570/A Series

BLOCK DIAGRAM

■

To Top / Lineup / Index

X0, X1
X0A, X1A
RST
HST

P00/AD00 to P07/AD07
P10/AD08 to P17/AD15
P20/A16 to P27/A23

P30/ALE
P31/RD
P32/WRL

P33/WRH
P34/HRQ

P35/HAK
P36/RDY

P37/CLK

P40/SIN0
P41/SOT0
P42/SCK0

P43/SIN1
P44/SOT1
P45/SCK1
P46/PPG0
P47/PPG1

P50/SIN2
P51/SOT2
P52/SCK2
P53/SIN3
P54/SOT3
P55/SCK3

P56/IN0
P57/IN1

Main clock
Sub clock

2

F

MC–16LX

CPU

Clock control

block

(including timebase

timer)

8
8

8

Port 0, 1, 2

16

8

2

External bus

interface

6

Port 3

Port 4

2

UART0

2

UART1

2

8/16-bit

PPG timer

Port 5

2
2

SIO × 2 ch

2

2

Input capture

Internal data bus

(SCI),

(SCI)

ch.0

(ICU)

Interrupt controller

Port 7

8-bit

D/A

converter

×

2 ch.

Port 9

Chip select

output

Port A

8/16-bit up/down

counter/timer

I2C bus

DTP/
external
interrupt

circuit

8 ch.

×

Port B

8/10-bit

A/D converter

×

8 ch.

Port 8

Port C

3

P70 to P72

2

6

2

6

8

P73/DA0
P74/DA1

DV

CC

DV

SS

88

P90/CS0 to P97/CS7

PA1/BIN0
PA2/ZIN0
PA3/AIN1/IRQ7
PA4/BIN1
PA5/ZIN1

PA6/SDA
PA7/SCL

PA0/AIN0/IRQ6

6

PB0/IRQ0 to
PB5/IRQ5

PB7

PB6/ADTG
AVRL

AVRH
AV

CC

AV

SS

8

P80/AN0 to
P87/AN7

4

PC0 to PC3

18

P64/OUT0 to P67/OUT3

P60/SIN4
P61/SOT4
P62/SCK4

P63/SKOT

Other pins

MD0 to MD2,

, V

C, V

CC

SS

16-bit free run timer

4

4

Output

compare

(OCU)

SIO × 1 ch.

Port 6

Clock output

RAM

ROM

P00 to P07 (8 ports): Provided with a register optional input pull-up resistor
P10 to P17 (8 ports): Provided with a register optional input pull-up resistor
P40 to P47 (8 ports): Heavy-current (I
P60 to P67 (8 ports): Provided with a register optional input pull-up resistor

= 10 mA) por

OL

MEMORY MAP

■

FFFFFF

H

Address #1

FC0000

H

010000

H

Address #2

004000

H

Internal ROM

Single chip mode
A mirror function is
supported.

ROM area ROM area

ROM area

(image of
bank FF)

external bus mode
A mirror function
is supported.

ROM area

(image of
bank FF)

To Top / Lineup / Index

MB90570/A Series

External ROM
external bus mode

Address #3

000100
0000C0
000000

Register

RAM RAM RAM

H

H

H

Register

PeripheralPeripheral Peripheral

Register

Part number Address #1* Address #2 * Address #3 *

MB90573 FE0000
MB90574/A FC0000
MB90F574/A FC0000

: Internal access memory
: External access memory
: Inhibited area

*: Addresses #1, #2 and #3 are unique to the product type.

H

H

H

004000
004000
004000

H

H

H

001800
002900
002900

H

H

H

Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effectiv e use of the C compiler

small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 is assigned to the same address ,
enabling reference of the table on the ROM without stating “far”.

For example, if an attempt has been made to access 00C000

, the contents of the ROM at FFC000H are

H

accessed actually . Since the ROM area of the FF bank exceeds 48 Kb ytes, the whole area cannot be reflected
in the image for the 00 bank. The ROM data at FF4000
for 00400
to FFFFFF

to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H

H

.

H

to FFFFFFH looks, therefore, as if it w ere the image

H

19

MB90570/A Series

2

F

MC-16LX CPU PROGRAMMING MODEL

■

• Dedicated registers

To Top / Lineup / Index

AH AL

USP

SSP

PS

PC

DPR

PCB

DTB

USB

: Accumlator (A)

Dual 16-bit register used for storing results of calculation etc. The two 16-bit
registers can be combined to be used as a 32-bit register.

: User stack pointer (USP)

The 16-bit pointer indicating a user stack address.

: System stack pointer (SSP)

The 16-bit pointer indicating the status of the system stack address.

: Processor status (PS)

The 16-bit register indicating the system status.

: Program counter (PC)

The 16-bit register indicating storing location of the current instruction code.

: Direct page register (DPR)

The 8-bit register indicating bit 8 through 15 of the operand address in the short
direct addressing mode.

: Program bank register (PCB)

The 8-bit register indicating the program space.

: Data bank register (DTB)

The 8-bit register indicating the data space.

: User stack bank register (USB)

The 8-bit register indicating the user stack space.

32-bit

16-bit

SSB

ADB

8-bit

: System stack bank register (SSB)

The 8-bit register indicating the system stack space.

: Additional data bank register (ADB)

The 8-bit register indicating the additional data space.

20

• General-purpose registers

To Top / Lineup / Index

MB90570/A Series

Maximum of 32 banks

+ (RP × 10H )

000180

H

• Processor status (PS)

ILM RP CCR

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

PS

ILM2 B4ILM1 ILM0 B3 B2 B1 B0 — I S T N Z V C

R7
R5

R3
R1

RW3
RW2
RW1
RW0

16-bit

R6
R4

R2
R0

RW7

RL3

RW6
RW5

RL2

RW4

RL1

RL0

Initial value

— : Reserved
X : Undefined

00 000000 10XXXXX

—

21

MB90570/A Series

I/O MAP

■

To Top / Lineup / Index

Address

000000
000001
000002
000003
000004
000005
000006
000007
000008

000009
00000A
00000B

00000C
00000D

to

00000F
000010
000011
000012
000013
000014
000015
000016
000017
000018
000019
00001A
00001B

00001C
00001D

00001E

00001F
000020
000021

Abbreviated

register

Register name

name

PDR0 Port 0 data register R/W Port 0 X X XXXXXX

H

PDR1 Port 1 data register R/W Port 1 X X XXXXXX

H

PDR2 Port 2 data register R/W Port 2 X X XXXXXX

H

PDR3 Port 3 data register R/W Port 3 X X XXXXXX

H

PDR4 Port 4 data register R/W Port 4 X X XXXXXX

H

PDR5 Port 5 data register R/W Port 5 X X XXXXXX

H

PDR6 Port 6 data register R/W Port 6 X X XXXXXX

H

PDR7 Port 7 data register R/W Port 7 – – –XXXXX

H

PDR8 Port 8 data register R/W Port 8 X X XXXXXX

H

PDR9 Port 9 data register R/W Port 9 X X XXXXXX

H

PDRA Port A data register R/W Port A XXXXX X X X

H

PDRB Port B data register R/W Port B XXXXX X X X

H

PDRC Port C data register R/W Port C XXXXXX X X

H

H

Read/

write

Resource name Initial value

(Disabled)

H

DDR0 Port 0 direction register R/W Port 0 0 0 0 0 0 0 0 0

H

DDR1 Port 1 direction register R/W Port 1 0 0 0 0 0 0 0 0

H

DDR2 Port 2 direction register R/W Port 2 0 0 0 0 0 0 0 0

H

DDR3 Port 3 direction register R/W Port 3 0 0 0 0 0 0 0 0

H

DDR4 Port 4 direction register R/W Port 4 0 0 0 0 0 0 0 0

H

DDR5 Port 5 direction register R/W Port 5 0 0 0 0 0 0 0 0

H

DDR6 Port 6 direction register R/W Port 6 0 0 0 0 0 0 0 0

H

DDR7 Port 7 direction register R/W Port 7 – – – 0 0 0 0 0

H

DDR8 Port 8 direction register R/W Port 8 0 0 0 0 0 0 0 0

H

DDR9 Port 9 direction register R/W Port 9 0 0 0 0 0 0 0 0

H

DDRA Port A direction register R/W Port A 0 0 0 0 0 0 0 0

H

DDRB Port B direction register R/W Port B 0 0 0 0 0 0 0 0

H

DDRC Port C direction register R/W Port C 0 0 0 0 0 0 0 0

H

ODR4 Port 4 output pin register R/W Port 4 0 0 0 0 0 0 0 0

H

Port 8,

ADER Analog input enable register R/W

H

8/10-bit

11111111

A/D converter

H

SMR0 Serial mode register 0 R/W

H

SCR0 Serial control register 0 R/W 0 0 0 0 0 1 0 0

H

(Disabled)

UART0

(SCI)

00000000

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

22

(Continued)

To Top / Lineup / Index

MB90570/A Series

Address

000022
000023

000024
000025

000026
000027

000028

000029

00002A

00002B

to

00002F
000030
000031
000032
000033
000034
000035

000036

000037
000038

000039
00003A
00003B

00003C
00003D

00003E
00003F

000040
000041

Abbreviated

register

name

SIDR0/

H

SODR0

Register name

Serial input data register 0/
serial output data register 0

Read/

write

R/W

Resource name Initial value

UART0

XXXXXXXX

(SCI)

SSR0 Serial status register 0 R/W 00001–00

H

SMR1 Serial mode register 1 R/W

H

SCR1 Serial control register 1 R/W 00000100

H

00000000

UART1

SIDR1/

H

SODR1

SSR1 Serial status register 1 R/W 00001–00

H

CDCR0

H

H

CDCR1

H

H

Serial input data register 1/
serial output data register 1

Communications prescaler control
register 0

(Disabled)

Communications prescaler control
register 1

R/W XXXXXXXX

(SCI)

Communications

R/W

prescaler

0–––1111

register 0

Communications

R/W

prescaler

0–––1111

register 0

(Disabled)

H

H

H

H

ENIR DTP/interrupt enable register R/W
EIRR DTP/interrupt factor register R/W XXXXXXXX

DTP/external

interrupt circuit

00000000

00000000

ELVR Request level setting register R/W

H

H

00000000

(Disabled)

H

ADCS1

H

ADCS2

H

ADCR1 A/D data register lower digits R XXXXX X X X

H

ADCR2 A/D data register upper digits R 0 0 0 0 1 – XX

H

DADR0 D/A converter data register ch.0 R/W

H

DADR1 D/A converter data register ch.1 R/W XXXXX X X X

H

DACR0 D/A control register 0 R/W –––––––0

H

DACR1 D/A control register 1 R/W –––––––0

H

CLKR Clock output enable register R/W

H

H

PRLL0 PPG0 reload register L ch.0 R/W

H

PRLH0 PPG0 reload register H ch.0 R/W XXXXX X X X

H

A/D control status register lower
digits

A/D control status register upper
digits

(Disabled)

R/W

R/W 00000000

8/10-bit A/D

00000000

converter

XXXXXXXX

8-bit D/A

converter

Clock monitor

function

8/16-bit PPG

––––0000

XXXXXXXX

timer 0

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

(Continued)

23

MB90570/A Series

To Top / Lineup / Index

Address

000042
000043

000044

000045

000046
000047
000048

000049
00004A

00004B

00004C

00004D

00004E
00004F
000050
000051
000052
000053
000054
000055
000056
000057
000058
000059
00005A
00005B

00005C
00005D

00005E
00005F

Abbreviated

register

Register name

name

PRLL1 PPG1 reload register L ch.1 R/W

H

PRLH1 PPG1 reload register H ch.1 R/W XXXXX X X X

H

PPGC0

H

PPGC1

H

PPGOE

H

H

SMCSL0

H

SMCSH0

H

SDR0 Serial data register 0 R/W XXXX X X X X

H

H

SMCSL1

H

SMCSH1

H

SDR1 Serial data register 1 R/W XXXX X X X X

H

H

H

PPG0 operating mode control
register ch.0

PPG1 operating mode control
register ch.1

PPG0 and 1 output control registers
ch.0 and ch.1

(Disabled)

Serial mode control lower status
register 0

Serial mode control upper status
register 0

(Disabled)

Serial mode control lower status
register 1

Serial mode control upper status
register 1

(Disabled)

Read/

write

Resource name Initial value

8/16-bit PPG

XXXXXXXX

timer 1

R/W

R/W

R/W

R/W

8/16-bit PPG

timer 0

8/16-bit PPG

timer 1

8/16-bit PPG

timer 0, 1

0X000XX1

0X000001

000000XX

––––0000

Extended I/O

R/W 00000010

R/W

serial interface 0

––––0000

Extended I/O

R/W 00000010

serial interface 1

XXXXXXXX

IPCP0 ICU data register ch.0 R

H

H

IPCP1 ICU data register ch.1 R

H

ICS01 ICU control status register R/W 0 0 0 0 0 0 0 0

H

H

H

(Disabled)

TCDT Free run timer data register R/W

H

TCCS Free run timer control status register R/W 0 0 0 0 0 0 0 0

H

H

H

(Disabled)

16-bit I/O timer

(input capture
(ICU) section)

16-bit I/O timer
(16-bit free run

timer section)

XXXXXXXX
XXXXXXXX
XXXXXXXX

00000000
00000000

XXXXXXXX

OCCP0 OCU compare register ch.0 R/W

H

H

OCCP1 OCU compare register ch.1 R/W

H

H

16-bit I/O timer

(output compare

(OCU) section)

XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX

OCCP2 OCU compare register ch.2 R/W

H

XXXXXXXX

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

24

(Continued)

To Top / Lineup / Index

MB90570/A Series

Address

000060
000061
000062
000063
000064
000065
000066
000067
000068
000069
00006A
00006B

00006C
00006D

00006E

00006F

000070
000071
000072
000073
000074
000075
000076
000077
000078
000079
00007A
00007B

00007C

00007D

00007E
00007F

Abbreviated

register

name

H

Register name

Read/

write

Resource name Initial value

XXXXXXXX

OCCP3 OCU compare register ch.3 R/W

H

OCS0 OCU control status register ch.0 R/W 0 0 0 0 – – 0 0

H

16-bit I/O timer

XXXXXXXX

(output compare

OCS1 OCU control status register ch.1 R/W – – – 0 0 0 0 0

H

OCS2 OCU control status register ch.2 R/W 0 0 0 0 – – 0 0

H

OCS3 OCU control status register ch.3 R/W – – – 0 0 0 0 0

H

H

(OCU) section)

(Disabled)

H

H

H

H

H

IBSR
IBCR
ICCR
IADR
IDAR

H

H

2

I

C bus status register

2

I

C bus control register

2

I

C bus clock control register

2

I

C bus address register

2

I

C bus data register

R/W
R/W 00000000
R/W ––0XXXXX

2

C interface

I
R/W –XXXXXXX
R/W XXXXXXXX

00000000

(Disabled)

H

ROMM

H

UDCR0 Up/down count register 0 R

H

UDCR1 Up/down count register 1 R 0 0 0 0 0 0 0 0

H

RCR0 Reload compare register 0 W 0 0 0 0 0 0 0 0

H

RCR1 Reload compare register 1 W 0 0 0 0 0 0 0 0

H

CSR0 Counter status register 0 R/W 0 0 0 0 0 0 0 0

H

H

CCRL0

H

ROM mirroring function selection
register

(Reserved area)*

W

Counter control register 0 R/W

CCRH0 00000000

H

CSR1 Counter status register 1 R/W 0 0 0 0 0 0 0 0

H

H

CCRL1

H

(Reserved area)*

Counter control register 1 R/W

CCRH1 –0000000

H

SMCSL2

H

SMCSH2

H

SDR2 Serial data register 2 R/W XXXX X X X X

H

H

Serial mode control lower status
register 2

Serial mode control higher status
register 2

(Disabled)

R/W

R/W 00000010

ROM mirroring

function

selection module

8/16-bit up/down

counter/timer

3

8/16-bit up/down

counter/timer

3

8/16-bit up/down

counter/timer

Extended I/O

serial interface 2

–––––––1

00000000

–0000000

–0000000

––––0000

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

(Continued)

25

MB90570/A Series

To Top / Lineup / Index

Address

000080
000081
000082
000083
000084
000085
000086
000087

to

00008B

00008C

00008D

00008E
00008F

to

00009D

00009E

00009F

0000A0
0000A1

0000A2

to

0000A4
0000A5
0000A6

0000A7
0000A8
0000A9

0000AA

Abbreviated

register

Register name

name

CSCR0 Chip selection control register 0 R/W

H

CSCR1 Chip selection control register 1 R/W – – – – 0 0 0 0

H

CSCR2 Chip selection control register 2 R/W – – – – 0 0 0 0

H

CSCR3 Chip selection control register 3 R/W – – – – 0 0 0 0

H

CSCR4 Chip selection control register 4 R/W – – – – 0 0 0 0

H

CSCR5 Chip selection control register 5 R/W – – – – 0 0 0 0

H

CSCR6 Chip selection control register 6 R/W – – – – 0 0 0 0

H

H

Read/

write

Resource name Initial value

––––0000

Chip select

output

(Disabled)

H

RDR0

H

RDR1

H

RDR6

H

H

Port 0 input pull-up resistor setup
register

Port 1 input pull-up resistor setup
register

Port 6 input pull-up resistor setup
register

R/W Port 0 00000000

R/W Port 1 00000000

R/W Port 6 00000000

(Disabled)

H

Address match

detection

function

00000000

H

PACSR

Program address detection control
status register

R/W

Delayed

H

DIRR

Delayed interrupt factor generation/
cancellation register

R/W

interrupt

generation

–––––––0

module

LPMCR

H

CKSCR Clock select register R/W 11111100

H

H

Low-power consumption mode
control register

R/W

Low-power

consumption

(standby) mode

00011000

(Disabled)

H

ARSR

H

HACR Upper address control register W 0 0 0 0 0 0 0 0

H

ECSR Bus control signal select register W 0 0 0 0 0 0 0 0

H

WDTC Watchdog timer control register R/W Watchdog timer X XXXXXXX

H

TBTC Timebase timer control register R/W Timebase timer 1 – – 0 0 1 0 0

H

WTC Clock timer control register R/W Clock timer 1 X 0 0 0 0 0 0

H

Automatic ready function select
register

W

0011––00

External bus pin

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

26

(Continued)

(Continued)

To Top / Lineup / Index

MB90570/A Series

Address

0000AB

to

0000AD

0000AE
0000AF

0000B0
0000B1
0000B2
0000B3
0000B4
0000B5
0000B6
0000B7
0000B8

0000B9
0000BA
0000BB

0000BC
0000BD

0000BE
0000BF
0000C0

to

0000FF

000100

to

00####

00####

to

001FEF

001FF0

001FF1

001FF2

001FF3

001FF4

001FF5

001FF6

to

001FFF

Abbreviated

register

name

H

Register name

Read/

write

Resource name Initial value

(Disabled)

H

FMCS Flash control register R/W Flash interface 0 0 0 X 0 XX 0

H

H

ICR00 Interrupt control register 00 R/W

H

ICR01 Interrupt control register 01 R/W 0 0 0 0 0 1 1 1

H

ICR02 Interrupt control register 02 R/W 0 0 0 0 0 1 1 1

H

ICR03 Interrupt control register 03 R/W 0 0 0 0 0 1 1 1

H

ICR04 Interrupt control register 04 R/W 0 0 0 0 0 1 1 1

H

ICR05 Interrupt control register 05 R/W 0 0 0 0 0 1 1 1

H

ICR06 Interrupt control register 06 R/W 0 0 0 0 0 1 1 1

H

ICR07 Interrupt control register 07 R/W 0 0 0 0 0 1 1 1

H

ICR08 Interrupt control register 08 R/W 0 0 0 0 0 1 1 1

H

ICR09 Interrupt control register 09 R/W 0 0 0 0 0 1 1 1

H

ICR10 Interrupt control register 10 R/W 0 0 0 0 0 1 1 1

H

ICR11 Interrupt control register 11 R/W 0 0 0 0 0 1 1 1

H

ICR12 Interrupt control register 12 R/W 0 0 0 0 0 1 1 1

H

ICR13 Interrupt control register 13 R/W 0 0 0 0 0 1 1 1

H

ICR14 Interrupt control register 14 R/W 0 0 0 0 0 1 1 1

H

ICR15 Interrupt control register 15 R/W 0 0 0 0 0 1 1 1

H

H

H

H

H

H

H

H

H

H

H

H

H

H

PADR0

PADR1

Program address detection register 0 R/W
Program address detection register 1 R/W XXXXX X X X
Program address detection register 2 R/W XXXXX X X X
Program address detection register 3 R/W XXXXX X X X
Program address detection register 4 R/W XXXXX X X X
Program address detection register 5 R/W XXXXX X X X

(Disabled)

(External area)*

(RAM area)*

2

(Reserved area)*

00000111

Interrupt

controller

1

3

XXXXXXXX

Program patch

processing

(Reserved area)

H

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

27

MB90570/A Series

Descriptions for read/write

R/W: Readable and writable
R: Read only
W: Write only

Descriptions for initial value

0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
– : This bit is unused. The initial value is undefined.

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*1: This area is the only external access area having an address of 0000FF

area is handled as that to external I/O area.
*2: For details of the RAM area, see “■ MEMORY MAP”.
*3: The reserved area is disabled because it is used in the system.

Notes: • For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an

initial value. Note that the values are different from reading results.
For LPMCR/CKSCR/WDTC , there are cases where initialization is performed or not performed, depending
on the types of the reset. However initial value for resets that initializes the value are listed.

• The addresses following 0000FF

• Boundary ####

between the RAM area and the reserved area varies with the product model.

H

are reserved. No external bus access signal is generated.

H

or lower . An access oper ation to this

H

28

To Top / Lineup / Index

MB90570/A Series

INTERRUPT FA CTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

■

Interrupt source

2

OS

EI

support

Interrupt vector Interrupt control register

Number Address ICR Address

Reset × # 08 FFFFDC
INT9 instruction × # 09 FFFFD8
Exception × # 10 FFFFD4
8/10-bit A/D converter # 11 FFFFD0

Input capture 0 (ICU) include # 12 FFFFCC
DTP0 (external interrupt 0) # 13 FFFFC8
Input capture 1 (ICU) include # 14 FFFFC4
Output compare 0 (OCU) match # 15 FFFFC0
Output compare 1 (OCU) match # 16 FFFFBC
Output compare 2 (OCU) match # 17 FFFFB8
Output compare 3 (OCU) match # 18 FFFFB4
Extended I/O serial interface 0 # 19 FFFFB0

16-bit free run timer × # 20 FFFFAC
Extended I/O serial interface 1 # 21 FFFFA8
Clock timer × # 22 FFFFA4

Priority

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

——High
——
——

ICR00 0000B0

ICR01 0000B1

ICR02 0000B2

ICR03 0000B3

ICR04 0000B4

ICR05 0000B5

H

H

H

H

H

H

Extended I/O serial interface 2 # 23 FFFFA0
DTP1 (external interrupt 1) # 24 FFFF9C

DTP2/DTP3 (external interrupt 2/
external interrupt 3)

8/16-bit PPG timer 0 counter
borrow

DTP4/DTP5 (external interrupt 4/
external interrupt 5)

8/16-bit PPG timer 1 counter
borrow

8/16-bit up/down counter/timer 0
borrow/overflow/inversion

8/16-bit up/down counter/timer 0
compare match

8/16-bit up/down counter/timer 1
borrow/overflow/inversion

8/16-bit up/down counter/timer 1
compare match

× # 26 FFFF94

× # 28 FFFF8C

# 25 FFFF98

# 27 FFFF90

# 29 FFFF88

# 30 FFFF84

# 31 FFFF80

# 32 FFFF7C

DTP6 (external interrupt 6) # 33 FFFF78
Timebase timer × # 34 FFFF74

H

H

H

H

H

H

H

H

H

ICR06 0000B6

ICR07 0000B7

ICR08 0000B8

ICR09 0000B9

0000BA

H

H

H

H

H

ICR10

H

H

ICR11 0000BB

H

0000BA

H

H

Low

(Continued)

29

MB90570/A Series

(Continued)

To Top / Lineup / Index

Interrupt source

2

OS

EI

support

Interrupt vector Interrupt control register

Number Address ICR Address

DTP7 (external interrupt 7) # 35 FFFF70

2

C interface

I

× # 36 FFFF6C
UART1 (SCI) reception complete # 37 FFFF68
UART1 (SCI) transmission

complete

# 38 FFFF64

UART0 (SCI) reception complete # 39 FFFF60
UART0 (SCI) transmission

complete

# 40 FFFF5C

Flash memory × # 41 FFFF58
Delayed interrupt generation

module

× # 42 FFFF54

: Can be used

×

: Can not be used
: Can be used. With EI

2

OS stop function.

Priority

H

H

H

H

H

H

H

H

ICR12 0000BC

ICR13 0000BD

ICR14 0000BE

ICR15 0000BF

H

High

H

H

H

Low

30