The MB90570 series is a general-purpose 16-bit microcontroller developed and designed by Fujitsu for process
control applications in consumer products that require high-speed real time processing. It contains an I
interface that allows inter-equipment communication to be implemented readily. This product is well adapted to
car audio equipment, VTR systems, and other equipment and systems.
2
The instruction set of F
sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and
enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word
data.
MC-16LX CPU core inherits AT architecture of F2MC*1 family with additional instruction
2C*2
bus
The MB90570 series has peripheral resources of an 8/10-bit A/D converter, an 8-bit D/A converter, UART (SCI),
an extended I/O serial interface, an 8/16-bit up/down counter/timer, an 8/16-bit PPG timer, I/O timer (a 16-bit
free run timer, an input capture (ICU), an output compare (OCU)).
2
MC stands for FUJITSU Flexible Microcontroller.
*1: F
*2: Purchase of Fujitsu I
components in an I
defined by Philips.
PACKAGE
■
120-pin plastic LQFP
(FPT-120P-M05)
2
C components conveys a license under the Philips I2C Patent Rights to use these
2
C system, provided that the system conforms to the I2C Standard Specification as
120-pin plastic QFP
(FPT-120P-M13)
120-pin plastic LQFP
(FPT-120P-M21)
MB90570 Series
FEATURES
■
•Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from 1/2 to 4× oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz).
Minimum instruction execution time: 62.5 ns (at oscillation of 4 MHz, 4 × PLL clock, operation at V
• Maximum memory space
16 Mbytes
• Instruction set optimized for controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
Enhanced signed multiplication/division instruction and RETI instruction functions
Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C) and multi-task operations
Adoption of system stack pointer
• Low-power consumption (standby) mode
Sleep mode (mode in which CPU operating clock is stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Hardware standby mode
•Process
CMOS technology
• I/O port
General-purpose I/O ports (CMOS): 63 ports
• 16-bit I/O timer
16-bit free run timer: 1 channel
Input capture (ICU): Generates an interrupt request by latching a 16-bit free run timer counter value upon
detection of an edge input to the pin.
Output compare (OCU): Generates an interrupt request and re verse the output lev el upon detection of a match
between the 16-bit free run timer counter value and the compare setting value.
• Extended I/O serial interface: 3 channels
2
•I
C interface (1 channel)
Serial I/O port for supporting Inter IC BUS
• UART0 (SCI), UART1 (SCI)
With full-duplex double buffer
Clock asynchronized or clock synchronized transmission can be selectively used.
• DTP/external interrupt circuit (8 channels)
A module for starting extended intelligent I/O service (EI
by an external input.
• Delayed interrupt generation module
Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels)
8/10-bit resolution
Starting by an external trigger input.
Conversion time: 26.3 µs
• 8-bit D/A converter (based on the R-2R system)
8-bit resolution: 2 channels (independent)
Setup time: 12.5 µs
• Clock timer: 1 channel
• Chip select output (8 channels)
An active level can be set.
• Clock output function
2
OS) and generating an external interrupt triggered
3
MB90570 Series
PRODUCT LINEUP
■
Part number
Item
ClassificationMask ROM productsFlash ROM products Evaluation product
ROM size128 kbytes256 kbytesNone
RAM size6 kbytes10 kbytes
Clock synchronized transmission (62.5 kbps to 1 Mbps)
Clock asynchronized transmission (1202 bps to 9615 bps)
Transmission can be performed by bi-directional serial transmission or by
master/slave connection.
One-shot conversion mode (converts selected channel only once)
Scan conversion mode (converts two or more successive channels and can
* :Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)
Assurance for the MB90V570/A is given only for operation with a tool at a power voltage of 4.5 V to 5.5 V, an
operating temperature of 0 to +25°C, and an operating frequency of 1 MHz to 16 MHz.
PACKAGE AND CORRESPONDING PRODUCTS
■
PackageMB90573MB90574MB90F574/AMB90574C
FPT-120P-M05×
FPT-120P-M13
FPT-120P-M21× ×
: Available ×: Not available
Note: For more inf ormation about each package, see section “■ Package Dimensions.”
4.5 V to 5.5 V
5
MB90570 Series
DIFFERENCES AMONG PRODUCTS
■
Memory Size
In evaluation with an evaluation product, note the difference between the evaluation product and the product
actually used. The following items must be taken into consideration.
• The MB90V570/A does not have an internal ROM, however, operations equivalent to chips with an internal
ROM can be ev aluated b y using a dedicated development tool, enabling selection of ROM size b y settings of
the development tool.
• In the MB90V570/A, images from FF4000
mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.)
• In the MB90F574/574/573/F574A/574C, images from FF4000H to FFFFFFH are mapped to bank 00, and
FF0000
• The products designated with /A or /C are different from those without /A or /C in that they are DTP/externallyinterrupted types which return from standby mode at the ch.0 to ch.1 edge request.
H to FF3FFFH to bank FF only.
H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to
High speed oscillator input pins
Low speed oscillator input pins
These are input pins used to designate the operating mode. They should
be connected directly to Vcc or Vss.
Reset input pin
Hardware standby input pin
In single chip mode, these are general purpose I/O pins. When set for
input, they can be set by the pull-up resistance setting register (RDR0).
When set for output, this setting will be invalid.
In external bus mode, these pins function as address low output/data low
I/O pins.
In single chip mode, these are general purpose I/O pins. When set for
input, they can be set by the pull-up resistance setting register (RDR1).
When set for output, the setting will be invalid.
In external bus mode, these pins function as address middle output/data
high I/O pins.
In single chip mode this is a general-purpose I/O port.
In external bus mode, these pins function as address high output pins.
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the address latch enable signal
output pin.
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the read strobe signal output
pin.
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the data bus lower 8-bit write
strobe signal output pin.
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the data bus upper 8-bit write
strobe signal output pin.
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the hold request signal input
pin.
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the hold acknowledge signal
output pin.
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the ready signal input pin.
*1: FPT-120P-M05
*2: FPT-120P-M13
8
(Continued)
,FPT-120P-M21
Pin no.
Pin nameCircuit typeFunction
LQFP-120 *
QFP-120 *
1
2
7P37 E
CLK
9P40F
SIN0
10P41F
SOT0
11P42F
SCK0
12P43F
SIN1
13P44F
SOT1
14P45F
SCK1
15,16P46,P47F
PPG0,PPG1
17P50E
SIN2
MB90570 Series
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the clock (CLK) signal output
pin.
In single chip mode this is a general-purpose I/O port. It can be set to open
drain by the ODR4 register.
This is also the UART ch.0 serial data input pin. While UART ch.0 is in
input operation, this input signal is in continuous use, and therefore the
output function should only be used when needed. If shared by output
from other functions, this pin should be output disabled during SIN
operation.
In single chip mode this is a general-purpose I/O port. It can be set to open
drain by the ODR4 register.
This is also the UART ch.0 serial data output pin. This function is valid
when UART ch.0 is enabled for data output.
In single chip mode this is a general-purpose I/O port. It can be set to open
drain by the ODR4 register.
This is also the UART ch.0 serial clock I/O pin. This function is valid when
UART ch.0 is enabled for clock output.
In single chip mode this is a general-purpose I/O port. It can be set to
open-drain by the ODR4 register.
This is also the UART ch.1 serial data input pin. While UART ch.1 is in
input operation, this input signal is in continuous use, and therefore the
output function should only be used when needed. If shared by output
from other functions, this pin should be output disabled during SIN
operation.
In single chip mode this is a general-purpose I/O port. It can be set to
opendrain by the ODR4 register.
This is also the UART ch.1 serial data output pin. This function is valid
when UART ch.1 is enabled for data output.
In single chip mode this is a general-purpose I/O port. It can be set to open
drain by the ODR4 register.
This is also the UART ch.1 serial clock I/O pin. This function is valid when
UART ch.1 is enabled for clock output.
In single chip mode this is a general-purpose I/O port. It can be set to open
drain by the ODR4 register.
These are also the PPG0, 1 output pins. This function is valid when PPG0,
1 output is enabled.
In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.0 data input pin. During serial data input, this
input signal is in continuous use, and therefore the output function should
only be used when needed.
*1: FPT-120P-M05
*2: FPT-120P-M13
(Continued)
,FPT-120P-M21
9
MB90570 Series
Pin no.
Pin nameCircuit typeFunction
LQFP-120 *
QFP-120 *
18P51E
19P52E
20P53E
21P54E
22P55E
23,24P56,P57E
25P60F
26P61F
27P62F
28P63F
*1: FPT-120P-M05
*2: FPT-120P-M13
1
2
SOT2
SCK2
SIN3
SOT3
SCK3
IN0,IN1
SIN4
SOT4
SCK4
CKOT
,FPT-120P-M21
In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.0 data output pin. This function is valid when
serial ch.0 is enabled for serial data output.
In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.0 clock I/O pin. This function is valid when
serial ch.0 is enabled for serial data output.
In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.1 data input pin. During serial data input, this
input signal is in continuous use, and therefore the output function should
only be used when needed.
In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.1 data output pin. This function is valid when
serial ch.1 is enabled for serial data output.
In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.1 clock I/O pin. This function is valid when
serial ch.1 is enabled for serial data output.
In single chip mode this is a general-purpose I/O port.
These are also the input capture ch.0/1 trigger input pins. During input
capture signal input on ch.0/1 this function is in continuous use, and
therefore the output function should only be used when needed.
In single chip mode this is a general-purpose I/O port. When set for input
it can be set by the pull-up resistance register (RDR6). When set for
output this setting will be invalid.
This is also the I/O serial ch.2 data input pin. During serial data input this
function is in continuous use, and therefore the output function should
only be used when needed.
In single chip mode this is a general-purpose I/O port. When set for input
it can be set by the pull-up resistance register (RDR6). When set for
output this setting will be invalid.
This is also the I/O serial ch.2 data output pin. This function is valid when
serial ch.2 is enabled for serial data output.
In single chip mode this is a general-purpose I/O port. When set for input
it can be set by the pull-up resistance register (RDR6). When set for
output this setting will be invalid.
This is also the I/O serial ch.2 serial clock I/O pin. This function is valid
when serial ch.2 is enabled for serial data output.
In single chip mode this is a general-purpose I/O port. When set for input
it can be set by the pull-up resistance register (RDR6). When set for
output this setting will be invalid.
This is also the clock monitor output pin. This function is valid when cloc k
monitor output is enabled.
(Continued)
10
Pin no.
1
LQFP-120 *
QFP-120 *
Pin nameCircuit typeFunction
2
29 to 32P64 to P67F
OUT0 to
OUT3
35 to 37P70 to P72E
40,41P73,P74I
DA0,DA1
46 to 53P80 to P87K
AN0 to AN7
55 to 62P90 to P97E
CS0 to CS7
34CG
64PA0E
AIN0
IRQ6
65PA1E
BIN0
66PA2E
ZIN0
67PA3E
AIN1
IRQ7
68PA4E
BIN1
69PA5E
ZIN1
MB90570 Series
In single chip mode these are general-purpose I/O ports. When set for
input they can be set by the pull-up resistance register (RDR6). When set
for output this setting will be invalid.
These are also the output compare ch.0 to ch.3 event output pins. This
function is valid when the respective channel(s) are enabled for output.
These are general purpose I/O ports.
These are general purpose I/O ports.
These are also the D/A converter ch.0,1 analog signal output pins.
These are general purpose I/O ports.
These are also A/D converter analog input pins. This function is valid
when analog input is enabled.
These are general purpose I/O ports.
These are also chip select signal output pins. This function is valid when
chip select signal output is enabled.
This is the power supply stabilization capacitor pin. It should be
connected externally to an 0.1 µF ceramic capacitor. Note that this is
not required on the FLASH model (MB90F574/A) and MB90574C.
This is a general purpose I/O port.
This pin is also used as count clock A input for 8/16-bit up-down counter
ch.0.
This pin can also be used as interrupt request input ch. 6.
This is a general purpose I/O port.
This pin is also used as count clock B input for 8/16-bit up-down counter
ch.0.
This is a general purpose I/O port.
This pin is also used as count clock Z input for 8/16-bit up-down counter
ch.0.
This is a general purpose I/O port.
This pin is also used as count clock A input for 8/16-bit up-down counter
ch.1.
This pin can also be used as interrupt request input ch.7.
This is a general purpose I/O port.
This pin is also used as count clock B input for 8/16-bit up-down counter
ch.1.
This is a general purpose I/O port.
This pin is also used as count clock Z input for 8/16-bit up-down counter
ch.1.
*1: FPT-120P-M05
*2: FPT-120P-M13
(Continued)
,FPT-120P-M21
11
MB90570 Series
(Continued)
Pin no.
Pin nameCircuit typeFunction
LQFP-120 *
QFP-120 *
70PA6L
71PA7L
72,
75 to 79
80PB6E
81PB7E
82 to 85PC0 to PC3E
8,54,94VCCPower
33,63,
91,119
42AVCCH
43AVRHJ
44AVRLH
45AVSSH
38DVCCH
39DVSSH
1
2
SDA
SCL
PB0,
PB1 to PB5
IRQ0,
IRQ1 to IRQ5
ADTG
VSSPower
E
supply
supply
This is a general purpose I/O port.
This pin is also used as the data I/O pin for the I2C interface. This
function is valid when the I
2
I
C interface is operating, this port should be set to the input level
(DDRA: bit6 = 0).
This is a general purpose I/O port.
This pin is also used as the clock I/O pin for the I2C interface. This
function is valid when the I
2
I
C interface is operating, this port should be set to the input level
(DDRA: bit7 = 0).
These are general-purpose I/O ports.
These pins are also the external interrupt input pins. IRQ0, 1 are
enabled for both rising and falling edge detection, and therefore cannot
be used for recovery from STOP status for MB90V570, MB90F574,
MB90573 and MB90574. However, IRQ0, 1 can be used for recovery
from STOP status for MB90V570A, MB90F574A and MB90574C.
This is a general purpose I/O port.
This is also the A/D converter external trigger input pin. While the A/D
converter is in input operation, this input signal is in continuous use, and
therefore the output function should only be used when needed.
This is a general purpose I/O port.
These are general purpose I/O ports.
These are power supply (5V) input pins.
These are power supply (0V) input pins.
This is the analog macro (D/A, A/D etc.) Vcc power supply input pin.
This is the A/D converter Vref+ input pin. The input voltage should not
exceed Vcc.
This is the A/D converter Vref-input pin. The input voltage should not
less than Vss.
This is the analog macro (D/A, A/D etc.) Vss power supply input pin.
This is the D/A converter Vref input pin. The input voltage should not
exceed Vcc.
This is the D/A converter GND power supply pin. It should be set to Vss
equivalent potential.
2
C interface is enabled f or operation. While the
2
C interface is enabled f or operation. While the
*1: FPT-120P-M05
*2: FPT-120P-M13
12
,FPT-120P-M21
MB90570 Series
I/O CIRCUIT TYPE
■
TypeCircuitRemarks
A• Oscillator circuit
X1
X0
Standby control signal
B• Oscillator circuit
X1A
X0A
Oscillator recovery resistance for high
speed = approx. 1 M
Oscillator recovery resistance for low
speed = approx. 1 MΩ
Ω
Standby control signal
C• Hysteresis input pin
Resistance value = approx. 50 kΩ (typ.)
R
Hysteresis input
D• CMOS hysteresis input pin with input pull-
CC
V
V
P-ch
Selective signal either
with a pull-up resistor or
CC
without it.
P-ch
up control
• CMOS level output.
• CMOS hysteresis input
(Includes input shut down standby control
function)
OL
= 4 mA
I
N-ch
R
Standby control for input interruption
Hysteresis input
• Pull-up resistance value =
approx. 50 kΩ(typ.)
I
OL = 4mA
(Continued)
13
MB90570 Series
TypeCircuitRemarks
E• CMOS hysteresis input/output pin.
R
IOL = 4 mA
CC
V
P-ch
N-ch
Hysteresis input
Standby control for input interruption
• CMOS level output
• CMOS hysteresis input
(Includes input shut down standby control
function)
I
OL = 4 mA
F• CMOS hysteresis input/output pin.
CC
V
P-ch
• CMOS level output
• CMOS hysteresis input
(Includes input shut down standby control
function)
OL = 10 mA (Large current port)
N-ch
R
OL
= 10 mA
I
G• C pin output
V
Standby control for input interruption
CC
Hysteresis input
I
(capacitance connector pin).
P-ch
N-ch
H• Analog power supply protector
CC
V
On the MB90F574 this pin is not
connected (NC).
circuit.
P-ch
AVP
N-ch
14
I• CMOS hysteresis input/output
CC
V
P-ch
• Analog output/CMOS output
dual-function pin (CMOS output is not
available during analog output.)
(Analog output priority: DAE = 1)
OL
= 4 mA
I
N-ch
R
Standby control for input interruption
Hysteresis input
DAO
• Includes input shout down standby
control function.
I
OL = 4mA
(Continued)
MB90570 Series
TypeCircuitRemarks
J• A/D converter ref+ power supply input
CC
V
P-ch
N-ch
ANE
AVR
ANE
P-ch
N-ch
pin(AVRH), with power supply
protector circuit.
K• CMOS hysteresis input /analog input
CC
V
P-ch
dual-function pin.
• CMOS output
• Includes input shut down function at input
N-ch
R
Standby control for input interruption
OL
I
= 4 mA
L• Hysteresis input
CC
V
Hysteresis input
Analog input
N-ch
shut down standby.
• N-ch open-drain output
• Includes input shut down standby control
function.
I
OL= 4mA
OL
= 4 mA
I
N-ch
R
Hysteresis input
Standby control for input interruption
15
MB90570 Series
HANDLING DEVICES
■
1.Preventing Latchup
CMOS ICs may cause latchup in the following situations:
• When a voltage higher than Vcc or lower than Vss is applied to input or output pins.
• When a voltage exceeding the rating is applied between Vcc and Vss.
• When AVcc power is supplied prior to the Vcc voltage.
In turning on/turning off the analog power supply , mak e sure the analog po wer v oltage (AV
analog input voltages not exceed the digital voltage (V
CC).
CC, AVRH, D VCC)and
2.Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefor they must be tied to V
more than 2 k<Symbol>W.
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
CC or Ground through resistors. In this case those resistors should be
3.Notes on Using External Clock
In using the external clock, drive X0 pin only and leave X1 pin unconnected.
• Using external clock
MB90570 series
X0
Open
X1
4. Unused Sub Clock Mode
If sub clock modes are not used, the oscillator should be connected to the X01A pin and X1A pin
5.Power Supply Pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to
avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to
lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise
in the ground level, and to conform to the total current rating.
Make sure to connect V
16
CC and VSS pins via lowest impedance to power lines.
MB90570 Series
It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pin near the device.
Using
•
power supply pins
VCC
VSS
VCC
VSS
MB90570 series
VCC
VSS
VSS
VCC
VSS
VCC
6.Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand
area for stabilizing the operation.
7.Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVR H, AVRL ,
DV
CC,DVSS) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage does not exceed AVRH or AVCC (tur ning on/off the analog and digital power supplies simultaneously is acceptable).
8.Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = DVCC = VSS.
9.N.C. Pins
The N.C. (internally connected) pins must be opened for use.
10. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
or more µs (0.2 V to 2.7 V).
11. Indeterminate outputs from ports 0 and 1
The outputs from ports 0 and 1 become indeterminate during oscillation setting time of step-down circuit (during
a power-on reset) after the power is turned on. (MB90573, MB90574, MB90V570, MB90V570A)
17
MB90570 Series
The series without built-in step-down circuit have no oscillation setting time of step-down circuit, so outputs
should not become indeterminate. (MB90F574,MB90F574A,MB90574C)
Timing chart of indeterminate outputs from ports 0 and 1
Oscillation setting time *
Step-down circuit setting time *
VCC (power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operating clock A) signal
KB (internal operating clock B) signal
PORT (port output) signal
*1: Step-down circuit setting time 217/oscillation clock frequency (oscillation clock frequency of 16 MHz: 8.19 ms)
*2: Oscillation setting time2
18
/oscillation clock frequency (oscillation clock frequency of 16 MHz: 16.38 ms)
Period of indeterminate
1
2
12. Initialization
In the device, there are internal registers which are initialized only by a po wer-on reset. Turn on the power again
to initialize these registers.
13. Return from standby state
If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may
fail to return from the standby state. In this case, reset the de vice via the external reset pin to return to the normal
state.
14. Precautions for Use of ’DIV A, Ri,’ and ’DIVW A, Ri’ Instructions
The signed multiplication-division instructions ’DIV A, Ri,’ and ’DIVW A, RWi’ should be used when the corresponding bank registers (DTB, ADB, USB , SSB) are set to value ’00h.’ If the corresponding bank registers (DTB,
ADB, USB, SSB) are set to a value other than ’00h,’ then the remainder obtained after the execution of the
instruction will not be placed in the instruction operand register.
15. Precautions for Use of REALOS
Extended intelligent I/O service (EI2OS) cannot be used, when REALOS is used.
18
BLOCK DIAGRAM
■
MB90570 Series
X0, X1
X0A, X1A
RST
HST
P00/AD00 to P07/AD07
P10/AD08 to P17/AD15
P20/A16 to P27/A23
P00 to P07 (8 ports): Provided with a register optional input pull-up resistor
P10 to P17 (8 ports): Provided with a register optional input pull-up resistor
OL
P40 to P47 (8 ports): Heavy-current (I
P60 to P67 (8 ports): Provided with a register optional input pull-up resistor
*: Addresses #1, #2 and #3 are unique to the product type.
Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effectiv e use of the C compiler
small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 is assigned to the same address ,
enabling reference of the table on the ROM without stating “far”.
For example, if an attempt has been made to access 00C000
H, the contents of the ROM at FFC000H are
accessed actually . Since the ROM area of the FF bank e xceeds 48 kbytes, the whole area cannot be reflected
in the image for the 00 bank. The ROM data at FF4000
for 00400
to FFFFFF
H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H
H.
H to FFFFFFH looks, therefore , as if it were the image
20
2
F
MC-16LX CPU PROGRAMMING MODEL
■
• Dedicated registers
MB90570 Series
AHAL
USP
SSP
PS
PC
DPR
PCB
DTB
USB
: Accumulator (A)
Dual 16-bit register used for storing results of calculation etc. The two 16-bit
registers can be combined to be used as a 32-bit register.
: User stack pointer (USP)
The 16-bit pointer indicating a user stack address.
: System stack pointer (SSP)
The 16-bit pointer indicating the status of the system stack address.
: Processor status (PS)
The 16-bit register indicating the system status.
: Program counter (PC)
The 16-bit register indicating storing location of the current instruction code.
: Direct page register (DPR)
The 8-bit register indicating bit 8 through 15 of the operand address in the short
direct addressing mode.
: Program bank register (PCB)
The 8-bit register indicating the program space.
: Data bank register (DTB)
The 8-bit register indicating the data space.
: User stack bank register (USB)
The 8-bit register indicating the user stack space.
32-bit
16-bit
SSB
ADB
8-bit
: System stack bank register (SSB)
The 8-bit register indicating the system stack space.
: Additional data bank register (ADB)
The 8-bit register indicating the additional data space.
21
MB90570 Series
• General-purpose registers
Maximum of 32 banks
H
000180
• Processor status (PS)
ILMRPCCR
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PS
ILM2B4ILM1 ILM0B3B2B1B0—ISTNZVC
+ (RP × 10H)
R7
R5
R3
R1
RW3
RW2
RW1
RW0
16-bit
R6
R4
R2
R0
RW7
RL3
RW6
RW5
RL2
RW4
RL1
RL0
22
Initial value
—: Reserved
X : Undefined
00 00000010XXXXX
—
I/O MAP
■
MB90570 Series
Address
000000
Abbreviated
register
Register name
name
HPDR0Port 0 data register R/WPort 0X X XXXXXX B
Read/
write
Resource nameInitial value
000001HPDR1Port 1 data register R/WPort 1X X XXXXXX B
000002HPDR2Port 2 data register R/WPort 2X X XXXXXX B
000003HPDR3Port 3 data register R/WPort 3X X XXXXXX B
000004HPDR4Port 4 data register R/WPort 4X X XXXXXX B
000005HPDR5Port 5 data register R/WPort 5X X XXXXXX B
000006HPDR6Port 6 data register R/WPort 6X X XXXXXX B
000007HPDR7Port 7 data register R/WPort 7X X XXXXXX B
000008HPDR8Port 8 data register R/WPort 8X X XXXXXX B
000009HPDR9Port 9 data register R/WPort 9X X XXXXXX B
00000AHPDRAPort A data register R/WPort AXXXXX X X X B
00000BHPDRBPort B data register R/WPort BXXXXX X X X B
00000CHPDRCPort C data registerR/WPort CXXX X X X X X B
00000DH
to
00000F
000010
H
HDDR0Port 0 direction registerR/WPort 00 0 0 0 0 0 0 0 B
(Disabled)
000011HDDR1Port 1 direction registerR/WPort 10 0 0 0 0 0 0 0 B
000012HDDR2Port 2 direction registerR/WPort 20 0 0 0 0 0 0 0 B
000013HDDR3Port 3 direction registerR/WPort 30 0 0 0 0 0 0 0 B
000014HDDR4Port 4 direction registerR/WPort 40 0 0 0 0 0 0 0 B
000015HDDR5Port 5 direction registerR/WPort 50 0 0 0 0 0 0 0 B
000016HDDR6Port 6 direction registerR/WPort 60 0 0 0 0 0 0 0 B
000017HDDR7Port 7 direction registerR/WPort 7– – – 0 0 0 0 0 B
000018HDDR8Port 8 direction registerR/WPort 80 0 0 0 0 0 0 0 B
000019HDDR9Port 9 direction registerR/WPort 90 0 0 0 0 0 0 0 B
00001AHDDRAPort A direction registerR/WPort A0 0 0 0 0 0 0 0 B
00001BHDDRBPort B direction registerR/WPort B0 0 0 0 0 0 0 0 B
00001CHDDRCPort C direction registerR/WPort C0 0 0 0 0 0 0 0 B
00001DHODR4Port 4 output pin registerR/WPort 40 0 0 0 0 0 0 0 B
Port 8,
00001EHADERAnalog input enable registerR/W
8/10-bit
11111111B
A/D converter
00001FH(Disabled)
000020
000021HSCR0Serial control register 0R/W0 0 0 0 0 1 0 0 B
HSMR0Serial mode register 0R/W
UART0
(SCI)
00000000B
(Continued)
23
MB90570 Series
Address
000022
Abbreviated
register
name
SIDR0/
H
SODR0
Register name
Serial input data register 0/
serial output data register 0
Read/
write
R/W
Resource
name
UART0
Initial value
XXXXXXXX
(SCI)
000023HSSR0Serial status register 0R/W0 0 0 0 1 – 0 0 B
000024HSMR1Serial mode register 1R/W
00000000B
000025HSCR1Serial control register 1R/W0 0 0 0 0 1 0 0 B
UART1
000026H
SIDR1/
SODR1
Serial input data register 1/
serial output data register 1
R/WXXXXXXXX
(SCI)
000027HSSR1Serial status register 1R/W0 0 0 0 1 – 0 0 B
Communica-
000028HCDCR0
Communications prescaler control
register 0
R/W
tions
prescaler
0–––1111
register 0
000029H(Disabled)
Communica-
00002A
HCDCR1
Communications prescaler control
register 1
R/W
tions
prescaler
0–––1111B
register 0
00002BH
to
(Disabled)
00002FH
000030
000031HEIRRDTP/interrupt factor registerR/WXXXXXXXX B
HENIRDTP/interrupt enable registerR/W
00000000B
DTP/external
interrupt cir-
000032H
ELVRRequest level setting registerR/W
cuit
00000000
000033H00000000B
000034H
(Disabled)
000035
000036HADCS1
000037HADCS2
H
A/D control status register lower
digits
A/D control status register upper
digits
R/W
R/W or W00000000
8/10-bit A/D
00000000B
converter
000038HADCR1A/D data register lower digitsRXX X X X X X X B
000039HADCR2A/D data register upper digitsW0 0 0 0 1 – X X B
00003AHDADR0D/A converter data register ch.0R/W
00003BHDADR1D/A converter data register ch.1R/WXXXX X X X X B
00003CHDACR0D/A control register 0R/W–––––––0B
8-bit D/A
converter
XXXXXXXX
00003DHDACR1D/A control register 1R/W–––––––0B
00003EHCLKRClock output enable registerR/W
Clock monitor
function
––––0000
00003FH(Disabled)
000040
000041HPRLH0PPG0 reload register H ch.0R/WXXXX X X X X B
HPRLL0PPG0 reload register L ch.0R/W
8/16-bit PPG
timer 0
XXXXXXXXB
(Continued)
B
B
B
B
B
B
B
24
MB90570 Series
Address
register
Register name
name
Abbreviated
000042
HPRLL1PPG1 reload register L ch.1R/W
000043HPRLH1PPG1 reload register H ch.1R/WXX X X X X XX B
000044HPPGC0
000045HPPGC1
000046HPPGOE
PPG0 operating mode control
register ch.0
PPG1 operating mode control
register ch.1
PPG0 and 1 output control registers
ch.0 and ch.1
000047H(Disabled)
000048
HSMCSL0
000049HSMCSH0
Serial mode control lower status
register 0
Serial mode control upper status
register 0
00004AHSDR0Serial data register 0R/WXXXXXXXX B
00004BH(Disabled)
00004C
HSMCSL1
00004DHSMCSH1
Serial mode control lower status
register 1
Serial mode control upper status
register 1
00004EHSDR1Serial data register 1R/WXXXXXXXX B
00004FH(Disabled)
000050
H
IPCP0ICU data register ch.0R
000051HXXXXXXXXB
000052H
IPCP1ICU data register ch.1R
000053HXXXXXXXXB
000054HICS01ICU control status registerR/W0 0 0 0 0 0 0 0 B
000055H(Disabled)
000056
H
TCDTFree run timer data registerR/W
000057H00000000B
000058HTCCSFree run timer control status registerR/W0 0 0 0 0 0 0 0 B
000059H(Disabled)
00005A
H
OCCP0OCU compare register ch.0R/W
00005BHXXXXXXXXB
00005CH
OCCP1OCU compare register ch.1R/W
00005DHXXXXXXXXB
00005EH
OCCP2OCU compare register ch.2R/W
00005FHXXXXXXXXB
Read/
write
Resource nameInitial value
8/16-bit PPG
XXXXXXXXB
timer 1
R/W
R/W
R/W
R/W
8/16-bit PPG
timer 0
8/16-bit PPG
timer 1
8/16-bit PPG
timer 0, 1
0X000XX1B
0X000001
000000XXB
––––0000B
Extended I/O
R/W00000010
R/W
serial interface 0
––––0000B
Extended I/O
R/W00000010B
serial interface 1
XXXXXXXX
16-bit I/O timer
(input capture
XXXXXXXX
(ICU) section)
16-bit I/O timer
00000000
(16-bit free run
timer section)
XXXXXXXX
16-bit I/O timer
XXXXXXXX
(output compare
(OCU) section)
XXXXXXXX
(Continued)
B
B
B
B
B
B
B
B
25
MB90570 Series
Address
register
Register name
name
Abbreviated
000060
H
OCCP3OCU compare register ch.3R/W
000061HXXXXXXXXB
000062HOCS0OCU control status register ch.0R/W0 0 0 0 – – 0 0 B
000063HOCS1OCU control status register ch.1R/W– – – 0 0 0 0 0 B
000064HOCS2OCU control status register ch.2R/W0 0 0 0 – – 0 0 B
000065HOCS3OCU control status register ch.3R/W– – – 0 0 0 0 0 B
000066H
control register
0000A1HCKSCRClock select registerR/W1 1 1 1 1 1 0 0 B
0000A2H
to
0000A4
0000A5
H
HARSR
Automatic ready function select
register
(Disabled)
0000A6HHACRUpper address control registerW0 0 0 0 0 0 0 0 B
0000A7HECSRBus control signal select registerW0 0 0 0 0 0 0 0 B
0000A8HWDTCWatchdog timer control registerR/WWatchdog timerX X X XXXXX B
0000A9HTBTCTimebase timer control registerR/WTimebase timer1 – – 0 0 1 0 0 B
0000AAHWTCClock timer control registerR/WClock timer1 X 0 0 0 0 0 0 B
Read/
write
Resource nameInitial value
––––0000B
Chip select
output
R/WPort 000000000
R/WPort 100000000B
R/WPort 600000000B
Address match
R/W
detection
00000000
function
Delayed
R/W
interrupt
generation
–––––––0B
module
R/W
Low-power
00011000B
consumption
(standby) mode
W
0011––00B
External bus pin
(Continued)
B
B
27
MB90570 Series
(Continued)
Address
0000AB
to
0000AD
0000AE
Abbreviated
register
Register name
name
H
(Disabled)
H
HFMCSFlash control registerR/WFlash interface0 0 0 X 0 XX 0 B
Read/
write
Resource nameInitial value
0000AFH(Disabled)
0000B0
HICR00Interrupt control register 00R/W
00000111B
0000B1HICR01Interrupt control register 01R/W0 0 0 0 0 1 1 1 B
0000B2HICR02Interrupt control register 02R/W0 0 0 0 0 1 1 1 B
0000B3HICR03Interrupt control register 03R/W0 0 0 0 0 1 1 1 B
0000B4HICR04Interrupt control register 04R/W0 0 0 0 0 1 1 1 B
0000B5HICR05Interrupt control register 05R/W0 0 0 0 0 1 1 1 B
0000B6HICR06Interrupt control register 06R/W0 0 0 0 0 1 1 1 B
0000B7HICR07Interrupt control register 07R/W0 0 0 0 0 1 1 1 B
0000B8HICR08Interrupt control register 08R/W0 0 0 0 0 1 1 1 B
Interrupt
controller
0000B9HICR09Interrupt control register 09R/W0 0 0 0 0 1 1 1 B
0000BAHICR10Interrupt control register 10R/W0 0 0 0 0 1 1 1 B
0000BBHICR11Interrupt control register 11R/W0 0 0 0 0 1 1 1 B
0000BCHICR12Interrupt control register 12R/W0 0 0 0 0 1 1 1 B
0000BDHICR13Interrupt control register 13R/W0 0 0 0 0 1 1 1 B
0000BEHICR14Interrupt control register 14R/W0 0 0 0 0 1 1 1 B
0000BFHICR15Interrupt control register 15R/W0 0 0 0 0 1 1 1 B
0000C0H
to
0000FF
(External area)*
H
1
000100H
to
000###
(RAM area)*
H
2
000###H
to
(Reserved area)*
3
001FEFH
001FF0H
001FF1HProgram address detection register 1R/WXXXXX X X X B
PADR0
001FF2HProgram address detection register 2R/WXXXXX X X X B
Program address detection register 0R/W
Address match
XXXXXXXX
detection
001FF3H
001FF4HProgram address detection register 4R/WXXXXX X X X B
PADR1
Program address detection register 3R/WX X X X X XXX
function
001FF5HProgram address detection register 5R/WXXXXX X X X B
001FF6H
to
001FFF
H
(Reserved area)
B
B
28
Descriptions for read/write
R/W: Readable and writable
R: Read only
W: Write only
Descriptions for initial value
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
– : This bit is unused. The initial value is undefined.
MB90570 Series
*1: This area is the only external access area having an address of 0000FF
area is handled as that to external I/O area.
*2: For details of the RAM area, see “■ MEMORY MAP”.
*3: The reserved area is disabled because it is used in the system.
Notes: • For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an
initial value. Note that the values are different from reading results.
For LPMCR/CKSCR/WDTC , there are cases where initialization is performed or not performed, depending
on the types of the reset. However initial value for resets that initializes the value are listed.
• The addresses following 0000FF
• Boundary ####H between the RAM area and the reserved area varies with the product model.
H are reserved. No external bus access signal is generated.
H or lower . An access oper ation to this
29
MB90570 Series
INTERRUPT FA CTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Port 0 through 4, 6, 8, A and B are general-purpose I/O ports having a combined function as an external bus
pin and a resource input. Port 0 to Port 3 have a general-purpose I/O ports function only in the single-chip mode.
• Operation as output port
The pin is configured as an output port by setting the corresponding bit of the DDR register to “1”.
Writing data to PDR register when the port is configured as output, the data is retained in the output latch in
the PDR and directly output to the pin.
The value of the pin (the same value retained in the output latch of PDR) can be read out b y reading the PDR
register.
Note: When a read-modify-write instruction (e.g. bit set instruction) is performed to the port data register, the
destination bit of the operation is set to the specified value, not affecting the bits configured by the DDR
register for output, howe ver , v alues of bits configured by the DDR register as inputs are changed because
input values to the pins are written into the output latch. To avoid this situation, configure the pins by the
DDR register as output after writing output data to the PDR register when configuring the bit used as
input as outputs.
• Operation as input port
The pin is configured as an input by setting the corresponding bit of the DDR register to “0”.
When the pin is configured as an input, the output buffer is turned-off and the pin is put into a high-impedance
status.
When a data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs
are unaffected.
Reading the PDR register reads out the pin level (“0” or “1”).
32
(2) Register Configuration
• Port 0 data register (PDR0)
Address
000000
............
bit 15 bit 8
H
(PDR1)
• Port 1 data register (PDR1)
Address
P17P16P15P14P13P12P11P10
H
000001
R/WR/WR/WR/WR/WR/WR/WR/W
• Port 2 data register (PDR2)
Address
000002
............
bit 15 bit 8
H
MB90570 Series
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
P07P06P05P04P03P02P01P00
R/WR/WR/WR/WR/WR/WR/WR/W
............
bit 7 bit 0bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
(PDR0)
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
P27P26P25P24P23P22P21P20(PDR3)
R/WR/WR/WR/WR/WR/WR/WR/W
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
B
B
B
• Port 3 data register (PDR3)
Address
P37P36P35P34P33P32P31P30
H
000003
R/WR/WR/WR/WR/WR/WR/WR/W
• Port 4 data register (PDR4)
Address
000004
............
bit 15 bit 8
H
• Port 5 data register (PDR5)
Address
H
000005
P57P56P55P54P53P52P51P50
R/WR/WR/WR/WR/WR/WR/WR/W
• Port 6 data register (PDR6)
Address
000006
............
bit 15 bit 8
H
• Port 7 data register (PDR7)
Address
———P74P73P72P71P70
H
000007
———R/WR/WR/WR/WR/W
• Port 8 data register (PDR8)
Address
000008
............
bit 15 bit 8
H
............
bit 7 bit 0bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
(PDR2)
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
P47P46P45P44P43P42P41P40(PDR5)
R/WR/WR/WR/WR/WR/WR/WR/W
............
bit 7 bit 0bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
(PDR4)
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
P67P66P65P64P63P62P61P60(PDR7)
R/WR/WR/WR/WR/WR/WR/WR/W
............
bit 7 bit 0bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
(PDR6)
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
P87P86P85P84P83P82P81P80(PDR9)
R/WR/WR/WR/WR/WR/WR/WR/W
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
- - -XXXXX
Initial value
XXXXXXXX
B
B
B
B
B
B
(Continued)
33
MB90570 Series
• Port 9 data register (PDR9)
Address
H
000009
P97P96P95P94P93P92P91P90
R/WR/WR/WR/WR/WR/WR/WR/W
• Port A data register (PDRA)
Address
00000A
............
bit 15 bit 8
H
(PDRB)
• Port B data register (PDRB)
Address
00000B
............
bit 15 bit 8
H
(PDRA)
• Port C data register (PDRC)
Address
00000C
............
bit 15 bit 8
H
(Disabled)
• Port 0 direction register (DDR0)
Address
000010
............
bit 15 bit 8
H
(DDR1)
• Port 1 direction register (DDR1)
Address
H
000011
D17D16D15D14D13D12D11D10
R/WR/WR/WR/WR/WR/WR/WR/W
• Port 2 direction register (DDR2)
Address
000012
............
bit 15 bit 8
H
(DDR3)
............
bit 7 bit 0bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
(PDR8)
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
PA7PA6PA5PA4PA3PA2PA1PA0
R/WR/WR/WR/WR/WR/WR/WR/W
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
PB7PB6PB5PB4PB3PB2PB1PB0
R/WR/WR/WR/WR/WR/WR/WR/W
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
————PC3PC2PC1PC0
————R/WR/WR/WR/W
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
D07D06D05D04D03D02D01D00
R/WR/WR/WR/WR/WR/WR/WR/W
............
bit 7 bit 0bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
(DDR0)
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
D27D26D25D24D23D22D21D20
R/WR/WR/WR/WR/WR/WR/WR/W
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
00000000
Initial value
00000000
Initial value
00000000
B
B
B
B
B
B
B
34
• Port 3 direction register (DDR3)
Address
H
000013
D37D36D35D34D33D32D31D30
R/WR/WR/WR/WR/WR/WR/WR/W
• Port 4 direction register (DDR4)
Address
000014
............
bit 15 bit 8
H
(DDR5)
............
bit 7 bit 0bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
(DDR2)
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
D47D46D45D44D43D42D41D40
R/WR/WR/WR/WR/WR/WR/WR/W
Initial value
00000000
Initial value
00000000
(Continued)
B
B
MB90570 Series
• Port 5 direction register (DDR5)
Address
D57D56D55D54D53D52D51D50
H
000015
R/WR/WR/WR/WR/WR/WR/WR/W
• Port 6 direction register (DDR6)
Address
000016
............
bit 15 bit 8
H
(DDR7)
• Port 7 direction register (DDR7)
Address
———D74D73D72D71D70
H
000017
———R/WR/WR/WR/WR/W
• Port 8 direction register (DDR8)
Address
000018
............
bit 15 bit 8
H
(DDR9)
• Port 9 direction register (DDR9)
Address
H
000019
D97D96D95D94D93D92D91D90
R/WR/WR/WR/WR/WR/WR/WR/W
• Port A direction register (DDRA)
Address
00001A
............
bit 15 bit 8
H
(DDRB)
• Port B direction register (DDRB)
............
Address
00001B
bit 15 bit 8
H
............
bit 7 bit 0bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
(DDR4)
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
D67D66D65D64D63D62D61D60
R/WR/WR/WR/WR/WR/WR/WR/W
............
bit 7 bit 0bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
(DDR6)
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
D87D86D85D84D83D82D81D80
R/WR/WR/WR/WR/WR/WR/WR/W
............
bit 7 bit 0bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
(DDR8)
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
DA7DA6DA5DA4DA3DA2DA1DA0
R/WR/WR/WR/WR/WR/WR/WR/W
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
DB7DB6DB5DB4DB3DB2DB1DB0(DDRA)
R/WR/WR/WR/WR/WR/WR/WR/W
Initial value
00000000
Initial value
00000000
Initial value
- -- 00000
Initial value
00000000
Initial value
00000000
Initial value
00000000
Initial value
00000000
B
B
B
B
B
B
B
• Port C direction register (DDRC)
Address
00001C
............
bit 15 bit 8
H
(ODR4)
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
————DC3DC2DC1DC0
————R/WR/WR/WR/W
• Port 4 output pin register (ODR4)
Address
00001D
............
bit 15 bit 8
H
(DDRC)
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40
R/WR/WR/WR/WR/WR/WR/WR/W
• Port 0 input pull-up resistor setup register (RDR0)
bit 15 bit 8 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
H
—:Reserved
X :Undefined
(Disabled)
ADE7
ADE6
R/WR/WR/WR/WR/WR/WR/WR/W
ADE5
ADE4 ADE3
bit 7 bit 0bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
ADE2
............
(RDR0)
ADE0
ADE1
Initial value
00000000
Initial value
00000000
Initial value
11111111
B
B
B
36
(3) Block Diagram
• Input/output port
MB90570 Series
PDR (port data register)
PDR read
PDR write
DDR (port direction register)
Internal data bus
DDR write
DDR read
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
• Output pin register (ODR)
PDR (port data register)
PDR read
Output latch
PDR write
DDR (port direction register)
Direction latch
DDR write
Output latch
Direction latch
To resource input
P-ch
Pin
N-ch
Standby control (SPL=1)
From resource output
Resource output enable
P-ch
Pin
N-ch
Internal data bus
DDR read
ODR (output pin register)
ODR latch
ODR write
ODR read
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
Standby control
(SPL=1)
37
MB90570 Series
• Input pull-up resistor setup register (RDR)
PDR (port data register)
PDR read
Output latch
PDR write
DDR (port direction register)
Direction latch
DDR write
Internal data bus
Standby control: Stop, timebase timer mode and SPL=1
DDR read
RDR latch
RDR write
RDR read
To resource input
P-ch
N-ch
Standby control
(SPL=1)
RDR
(input pull-up resistor setup register)
Pull-up resistor
About 5.0 kΩ
(5.0 V)
P-ch
Pin
• Analog input enable register (ADER)
ADER (analog input enable register)
ADER read
ADER latch
ADER write
PDR (port data register)
PDR read
Internal data bus
Output latch
PDR write
DDR (port direction register)
Direction latch
DDR write
DDR read
To analog input
RMW
(read-modify-write
type instruction)
P-ch
Pin
N-ch
Standby control
(SPL=1)
38
Standby control: Stop, timebase timer mode and SPL=1
MB90570 Series
2. Timebase Timer
The timebase timer is a 18-bit free run counter (timebase counter) for counting up in synchronization to the
internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from
four types of 2
The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation
stabilization time or the watchdog timer etc.
(1) Register Configuration
• Timebase timer control register (TBTC)
12
/HCLK, 214/HCLK, 216/HCLK, and 219/HCLK.
Address
0000A9
R/W: Readable and writable
W : Write only
— : Unused
RESV: Reserved bit
bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8 bit 7bit 0
To oscillation stabilization
time selector of clock control block
Initial value
1--00100
18
B
Power-on reset
Start stop mode
CKSCR: MCS = 1→0*
Timebase timer control register
(TBTC)
OF: Overflow
HCLK: Oscillation clock
*1: Switch machine clock from oscillation clock to PLL clock
*2: Interrupt signal
1
Timebase timer
interrupt signal
2
#34*
Counter
clear circuit
RESV
timer selector
Clear TBOF
——
Interval
Set TBOF
TBIETBRTBOFTBC1 TBC0
39
MB90570 Series
3. Watchdog Timer
The watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the CPU when
the counter is not cleared for a preset period of time.
(1) Register Configuration
• Watchdog timer control register (WDTC)
Address
0000A8
bit 15 bit 8
H
R: Read only
W: Write only
X : Indeterminate
(2) Block Diagram
Watchdog timer
Start sleep mode
Start hold status
Start stop mode
............
Watchdog timer control register (WDTC)
PONR STBR WRST ERST SRST WTE WT1 WT0
Counter clear
control circuit
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
PONR STBR WRST ERST SRST WTEWT1WT0(TBTC)
RRRRRWWW
2
CLR and start
Count clock
selector
CLR
counter
2-bit
Overflow
CLR
Watchdog timer
reset generation
circuit
Initial value
XXXXXXXX
To internal reset
generation circuit
B
40
Clear
(Timebase timer counter)
Divided-by-2
of HCLK
HCLK: Oscillation clock
× 2
4
1
× 2
2
...
8
× 29× 210× 211× 212× 213× 214× 215× 216× 217× 2
× 2
18
MB90570 Series
4. 8/16-bit PPG Timer
The 8/16-bit PPG timer is a 2-CH reload timer module for outputting pulse having given frequencies/duty ratios.
The two modules performs the following operation by combining functions.
• 8-bit PPG output 2-CH independent operation mode
This is a mode for operating independent 2-CH 8-bit PPG timer, in which PPG0 and PPG1 pins correspond
to outputs from PPG0 and PPG1 respectively.
• 16-bit PPG timer output operation mode
In this mode, PPG0 and PPG1 are combined to be operated as a 1-CH 8/16-bit PPG timer operating as a 16-
bit timer. Because PPG0 and PPG1 outputs are reversed by an underflow from PPG1 outputting the same
output pulses from PPG0 and PPG1 pins.
• 8 + 8-bit PPG timer output operation mode
In this mode, PPG0 is operated as an 8-bit communications prescaler, in which an underflow output of PPG0
is used as a clock source for PPG1. A toggle output of PPG0 and PPG output of PPG1 are output from PPG0
and PPG1 respectively.
• PPG output operation
A pulse wave with any period/duty ratio is output. The module can also be used as a D/A converter with an
external add-on circuit.
41
MB90570 Series
(1) Register Configuration
• PPG0 operating mode control register ch.0 (PPGC0)
Address
000044
• PPG1 operating mode control register ch.1 (PPGC1)
Address
000045
• PPG0, 1 output control register ch.0, ch.1(PPGOE)
Address
000046
• PPG0 reload register H ch.0 (PRLH0)
Address
000041
• PPG1 reload register H ch.1 (PRLH1)
Address
000043
• PPG0 reload register L ch.0 (PRLL0)
Address
000040
• PPG1 reload register L ch.1 (PRLL1)
Address
000042
............
bit 15 bit 8 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
H
PEN0—PE00 PIE0PUF0——RESV(PPGC1)
R/W—R/WR/WR/W———
PEN1—PEI0PIE1PUF1 MD1MD0 RESV
H
R/WR/WR/WR/WR/WR/WR/WR/W
............
bit 15 bit 8
H
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0——(Disabled)
R/WR/WR/WR/WR/WR/W——
H
R/WR/WR/WR/WR/WR/WR/WR/W
H
R/WR/WR/WR/WR/WR/WR/WR/W
............
bit 15 bit 8 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
H
(PRLH0)
R/WR/WR/WR/WR/WR/WR/WR/W
............
bit 15 bit 8 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
H
(PRLH1)
R/WR/WR/WR/WR/WR/WR/WR/W
............
bit 7 bit 0bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
(PPGC0)
............
bit 7 bit 0bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
(PRLL0)
............
bit 7 bit 0bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
The 16-bit I/O timer module consists of one 16-bit free run timer, two input capture circuits, and four output
comparators. This module allows two independent waveforms to be output on the basis of the 16-bit free run
timer. Input pulse width and external clock periods can, therefore, be measured.
•Block Diagram
Internal data bus
Input capture
Dedicated
bus
16-bit
free run timer
Dedicated
bus
Output compare
45
MB90570 Series
(1) 16-bit free run Timer
The 16-bit free run timer consists of a 16-bit up counter, a control register, and a communications prescaler
register. The value output from the timer counter is used as basic timer (base timer) for input capture (ICU) and
output compare (OCU).
• A counter operation clock can be selected from four internal clocks (φ/4, φ/16, φ/32 and φ/64).
• An interrupt can be generated by o verflow of counter value or compare match with OCU compare register 0.
(Compare match requires mode setup.)
• The counter value can be initialized to “0000
register 0.
• Register Configuration
• free run timer data register (TCDT)
H” by a reset, software clear or compare match with OCU compare
Address
000056
000057
bit 15
bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
The input capture (ICU) generates an interrupt request to the CPU simultaneously with a storing operation of
current counter value of the 16-bit free run timer to the ICU data register (IPCP) upon an input of a trigger edge
to the external pin.
There are four sets (four channels) of the input capture external pins and ICU data registers, enabling
measurements of maximum of four events.
• The input capture has two sets of external input pins (IN0, IN1) and ICU registers (IPCP), enabling
measurements of maximum of four events.
• A trigger edge direction can be selected from rising/falling/both edges.
• The input capture can be set to generate an interrupt request at the storage timing of the counter value of the
16-bit free run timer to the ICU data register (IPCP).
• The input compare conforms to the extended intelligent I/O service (EI
• The input capture (ICU) function is suited for measurements of intervals (frequencies) and pulse widths.
• Register Configuration
2
OS).
• ICU data register ch.0, ch.1 (IPCP0, IPCP1)
IPCP0(high):
IPCP1(high):
IPCP0(low):
IPCP1(low):
Note: This register holds a 16-bit free run timer value when the valid edge of the corresponding external pin input wav ef orm is
AddressInitial value
000051
000053
Address
000050
000052
detected. (You can word-access this register, but you cannot program it.)
bit 15 bit 14bit 13 bit 12 bit 11 bit 10bit 9bit 8 bit 7 bit 0
H
CP15 CP14CP13 CP12 CP11 CP10CP09 CP08
H
RR RRRR RR
............
H
(IPCP0 high, IPCP1 high)
H
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0bit 15 bit 8
CP07 CP06CP05 CP04 CP03 CP02CP01 CP00
• ICU control status register (ICS01)
Address
H
000054
R/W: Readable and writable
R :Read only
X:Undefined
............
(Disabled)
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0bit 15 bit 8
ICP1ICP0ICE1ICE0 EG11 EG10EG01 EG00
R/WR/WR/WR/WR/WR/WR/WR/W
.............
(IPCP0 low, IPCP1 low)
RR RRRR RR
XXXXXXXX
Initial value
XXXXXXXX
Initial value
00000000
B
B
B
47
MB90570 Series
•Block Diagram
Edge detection circuit
P56/IN0
Pin
P57/IN1
Pin
ICU control status register (ICS01)
ICP1
Internal data bus
Latch
signal
Output latch
Data latch signal
2
2
ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
IPCP0HIPCP0L
IPCP1HIPCP1L
ICU data register (IPCP)
16
16-bit free run
16
timer
* : Interrupt number
Interrupt request
#12*
Interrupt request
#14*
48
MB90570 Series
(3) Output Compare (OCU)
The output compare (OCU) is two sets of compare units consisting of four-channel OCU compare registers, a
comparator and a control register.
An interrupt request can be generated for each channel upon a match detection by performing time-division
comparison between the OCU compare data register setting value and the counter value of the 16-bit free run
timer.
The OUT pin can be used as a waveform output pin for reversing output upon a match detection or a generalpurpose output port for directly outputting the setting value of the CMOD bit.
• Register Configuration
• OCU control status register ch.1, ch.3 (OCS1, OCS3)
AddressInitial value
000063
000065
bit 15 bit 14 bit 13bit 12 bit 11 bit 10bit 9bit 8 bit 7 bit 0
H
———CMOD OTE1 OTE0 OTD1 OTD0(OCS0, OCS2)
H
———R/WR/WR/WR/WR/W
• OCU control status register ch.0, ch.2 (OCS0, OCS2)
Address
000062
000064
............
H
H
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0bit 15 bit 8
ICP1ICP0ICE1ICE0——CST1 CST0(OCS1, OCS3)
R/WR/WR/WR/W——R/WR/W
• OCU compare register ch.0 to ch.3 (OCCP0 to OCCP3)
OCCP0 (high order address): 00005B
Address
OCCP1 (high order address): 00005D
OCCP2 (high order address): 00005F
OCCP3 (high order address): 000061
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10bit 9bit 8
H
C15C14C13C12C11C10C09C08
H
H
R/WR/WR/WR/WR/WR/WR/WR/W
H
.............
- --00000
Initial value
0000 - -00
Initial value
XXXXXXXX
B
B
B
OCCP0 (low order address): 00005A
OCCP1 (low order address): 00005C
OCCP2 (low order address): 00005E
OCCP3 (low order address): 000060
The 8/16-bit up/down counter/timer consists of six event input pins, two 8-bit up/down counters, two 8-bit
reload compare registers, and their controllers.
(1) Register configuration
• Up/down count register 0 (UDCR0)
Address
H
000070
............
bit 15 bit 8
(UDCR1)
bit 7bit 6bit 5bit 4
D06D07
RRRRRRRR
• Up/down count register 1 (UDCR1)
Address
000071
• Reload compare register 0 (RCR0)
Address
000072
bit 15bit 14 bit 13 bit 12 bit 11 bit 10bit 9bit 8
D17D16D15D14D13D12D11D10
H
RRRRRRRR
............
bit 15 bit 8
H
(RCR1)
bit 7bit 6bit 5bit 4
D06D07
WWWWWWWW
• Reload compare register 1 (RCR1)
Address
000073
• Counter status register 0, 1 (CSR0, CSR1)
Address
000074
000078
• Counter control register 0, 1 (CCRL0, CCRL1)
Address
000076
00007A
bit 15bit 14 bit 13 bit 12 bit 11 bit 10bit 9bit 8
D17D16D15D14D13D12D11D10
H
WWWWWWWW
............
bit 15 bit 8
H
(Reserved area)
H
bit 7bit 6bit 5bit 4
CITECSTR
R/WR/WR/WR/WR/WR/WRR
............
bit 15 bit 8
H
(CCRH0, CCRH1)
H
bit 7bit 6bit 5bit 4
CTUT
—
R/WR/WR/WR/WR/WR/WR/W
—
• Counter control register 0 (CCRH0)
Address
000077
bit 15bit 14 bit 13 bit 12 bit 11 bit 10bit 9bit 8
H
M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
R/WR/WR/WR/WR/WR/WR/WR/W
• Counter control register 1 (CCRH1)
Address
00007B
bit 15bit 14 bit 13 bit 12 bit 11 bit 10bit 9bit 8
CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
—
H
R/WR/WR/WR/WR/WR/WR/W
—
bit 3bit 2bit 1bit 0
D04D05D02D03D00D01
.............
bit 7 bit 0
(UDCR0)
bit 3bit 2bit 1bit 0
D04D05D02D03D00D01
.............
bit 7 bit 0
(RCR0)
bit 3bit 2bit 1bit 0
CMPFUDIEUDFFOVFFUDF0UDF1
bit 3bit 2bit 1bit 0
RLDEUCRECGSCUDCCCGE0CGE1
.............
bit 7 bit 0
(CCRL0)
.............
bit 7 bit 0
(CCRL1)
Initial value
00000000
Initial value
00000000
Initial value
00000000
Initial value
00000000
Initial value
00000000
Initial value
- 0000000
Initial value
00000000
Initial value
- 0000000
B
B
B
B
B
B
B
B
R/W: Readable and writable
R :Read only
W : Write only
— : Undefined
51
MB90570 Series
(2) Block Diagram
• Block diagram of 8/16-bit up/down counter/timer 0
Internal data bus
RCR0
Reload compare register 0
UDCR0
Up/down count register 0
Counter control
register 0 (CCRL0)
Re-load
control
circuit
CARRY/
BORRW
(to channel 1)
—
CTUT
PA2/ZIN0
Pin
PA0/AIN0/IRQ6
Pin
Pin
PA1/BIN0
M16E
* : Interrupt number
Edge/level
detection circuit
φ
Prescaler
CDCFCES1 CES0CFIECMS1CLKSCMS0
Counter control register 0 (CCRH0)
φ: Machine clock frequency
CGE1 CGE0UCREUDCCRLDECGSC
Counter clear
UP/down count
clock selector
circuit
Count clock
Counter status
register 0 (CSR0)
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
Overflow
control circuit
Underflow
Compare
Interrupt request
#29*
Interrupt request
#30*
M16E
(to channel 1)
52
MB90570 Series
• Block diagram of 8/16-bit up/down counter/timer 1
Internal data bus
RCR1
Reload compare register 1
UDCR1
Up/down count register 1
Counter control
register 1 (CCRL1)
CTUTCGE1 CGE0UCREUDCCRLDECGSC
—
PA5/ZIN1
Pin
CARRY/BORRW
(from channel 0)
PA3/AIN1/IRQ7
Pin
Edge/level
detection circuit
φ
Prescaler
UP/down count
clock selector
Counter clear
circuit
Count clock
Counter status
register 1 (CSR1)
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
Re-load
control
circuit
Compare
Overflow
control circuit
Underflow
Pin
PA4/BIN1
M16E
(from channel 1)
—
Counter control register 1 (CCRH1)
* : Interrupt number
φ: Machine clock frequency
CDCFCES1 CES0CFIECMS1CLKSCMS0
Interrupt request
#31*
Interrupt request
#32*
53
MB90570 Series
7. Extended I/O serial interface
The extended I/O serial interface transfers data using a clock synchronization system having an 8-bit x 1 channel
configuration.
For data transfer, you can select LSB first/MSB first.
(1) Register Configuration
• Serial mode control upper status register 0 to 2 (SMCSH0 to SMCSH2)
SMCSH0: 000049
Address
SMCSH1: 00004D
SMCSH2: 00007D
• Serial mode control lower status register 0 to 2 (SMCSL0 to SMCSL2)
SMCSL0: 000048
SMCSL1: 00004C
SMCSL2: 00007C
Address
• Serial data register 0 to 2 (SDR0 to SDR2)
Address
SDR0: 00004A
SDR1: 00004E
SDR2: 00007E
R/W: Readable and writable
R :Read only
—:Reserved
X : Undefined
bit 15bit 14 bit 13 bit 12 bit 11 bit 10bit 9bit 8
bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8 bit 7bit 0
H
—A6A5A4 A3A2A1A0
—R/WR/WR/WR/WR/WR/WR/W
. . . . . . . . . . . .
bit 15
H
(Disabled)D7
. . . . . . . . . . . .
(IBSR)
bit 8 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
——ENCS4CS3CS2CS1CS0
——R/W
bit 8 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
D6D5D4D3D2D1D0
R/WR/WR/WR/WR/W
R/WR/WR/WR/WR/W
R/WR/WR/W
. . . . . . . . . . . .
(ICCR)
Initial value
00000000
Initial value
--0XXXXX
Initial value
-XXXXXXX
Initial value
XXXXXXXX
B
B
B
B
56
R/W : Readable and writable
R: Read only
—: Reserved
X: Indeterminate
(2) Block Diagram
2
C bus control register
I
(IBCR)
MB90570 Series
Internal data bus
I2C bus status register
(IBSR)
BER BEIE SCC MSS ACK
Error
Number of
interrupt
request
generated
2
C enable
I
Start
Start stop condition
IDAR register
Slave address
comparison circuit
GCAA INTE
Master
ACK enable
GC-ACK enable
generation circuit
INTBB RSC AL LRB TRX AAS GCA FBT
Interrupt enable
Transmission
complete flag
Bus busy
Repeat start
Start stop condition
detection circuit
Arbitration lost
detection circuit
Last bit
SDA line
SCL line
Slave
Transmit/receive
General call
Detection of first byte
Interrupt request signal
#36*
Pin
PA6/SDA
Pin
PA7/SCL
IADR register
Clock
divider 1
φ
(1/5 to
1/8)
2
C enable
I
——EN CS4 CS3 CS2 CS1 CS0
2
C bus clock control register
I
(ICCR)
φ: Machine clock frequency
* : Interrupt number
4
selector 1
Count
clock
Clock
divider 2
Clock control block
Count
8
clock
selector 2
Sync
Shift clock
generation
circuit
57
MB90570 Series
9. UART0 (SCI), UART1 (SCI)
UART0 (SCI) and UART1 (SCI) are general-purpose serial data communication interfaces for performing
synchronous or asynchronous communication (start-stop synchronization system).
• Data buffer: Full-duplex double buffer
• Transfer mode: Clock synchronized (with start and stop bit)
Clock asynchronized (start-stop synchronization system)
DTP (Data Transfer Peripheral), which is located between the peripheral circuit outside the device and the
2
F
MC-16LX CPU, receives an interrupt request or DMA request generated by the external peripheral circuit*
for transmission to the F
As request levels for IRQ2 to IRQ7, two types of “H” and “L” can be selected for the intelligent I/O service. Rising
and falling edges as well as “H” and “L” can be selected for an external interrupt request. For IRQ0 and IRQ1,
a request by a level cannot be entered, but both edges can be entered.
* :The external peripheral circuit is connected outside the MB90570/A series device.
Note: IRQ0 and IRQ1 cannot be used for the intelligent I/O service and return from an interrupt.
(1) Register Configuration
• DTP/interrupt factor register (EIRR)
Address
000031
• DTP/interrupt enable register (ENIR)
Address
000030
2
MC-16LX CPU. DTP is used to activate the intelligent I/O service or interrupt processing.
............
bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
The delayed interrupt generation module generates interrupts for switching tasks for development on a realtime operating system (REALOS series). The module can be used to generate softwarewise generates hardware
interrupt requests to the CPU and cancel the interrupts.
2
This module does not conform to the extended intelligent I/O service (EI
bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
H
———————R0
———————R/W
—:Reserved
OS).
............
bit 7 bit 0
(PACSR)
Initial value
-------0
B
The DIRR is the register used to control delay interrupt request generation/cancellation. Programming this
register with “1” generates a delay interrupt request. Programming this register with “0” cancels a delay interrupt
request. Upon a reset, an interrupt is canceled. The reserved bit area can be programmed with either “0” or “1”.
For future extension, however, it is recommended that bit set and clear instructions be used to access this
register.
The 8/10-bit A/D converter has a function of converting analog voltage input to the analog input pins (input
voltage) to digital values (A/D conversion) and has the following features.
• Minimum conversion time: 26.3 µs (at machine clock of 16 MHz, including sampling time)
• Compare time: 176/352 machine cycles per channel (176 machine cycles are used for a machine clock below
8 MHz.)
• Conversion method: RC successive approximation method with a sample and hold circuit.
• 8-bit or 10-bit resolution
• Analog input pins: Selectable from eight channels by software
Single conversion mode: Selects and converts one channel.
Scan conv ersion mode:Converts two or more successive channels. Up to eight channels can be programmed.
Continuous conversion mode: Repeatedly converts specified channels.
Stop conversion mode:Stops conversion after completing a conversion for one channel and wait for the next
activation (conversion can be started synchronously.)
• Interrupt requests can be generated and the e xtended intelligent I/O service (EI
end of A/D conversion. Furthermore, A/D conversion result data can be transferred to the memory, enabling
efficient continuous processing.
• When interrupts are enabled, there is no loss of data even in continuous operations because the conversion
data protection function is in effect.
• Starting factors for conversion: Selected from software activation, and external trigger (falling edge).
2
OS) can be started after the
65
MB90570 Series
(1) Register Configuration
• A/D control status register upper digits (ADCS2)
Address
000037
• A/D control status register lower digits (ADCS1)
Address
000036
• A/D data register upper digits (ADCR2)
Address
000039
• A/D data register lower digits (ADCR1)
Address
000038
bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
The 8-bit D/A converter, which is based on the R-2R system, supports 8-bit resolution mode. It contains two
channels each of which can be controlled in terms of output by the D/A control register.
(1) Register Configuration
• D/A converter data register ch.0 (DADR0)
Address
H
00003A
• D/A converter data register ch.1 (DADR1)
Address
H
00003B
• D/A control register 0 (DACR0)
Address
H
00003C
............
bit 15 bit 8 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00(DADR1)
R/WR/WR/WR/WR/WR/WR/WR/W
............
bit 7 bit 0bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10(DADR0)
R/WR/WR/WR/WR/WR/WR/WR/W
............
bit 15 bit 8 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
———————DAE0(DACR1)
———————R/W
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
-------0
B
B
B
• D/A control register 1 (DACR1)
Address
H
00003D
R/W: Readable and writable
—:Reserved
X : Undefined
———————DAE1 (DACR0)
———————R/W
............
bit 7 bit 0bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
Initial value
-------0
B
68
(2) Block Diagram
Internal data bus
D/A converter data register ch.1 (DADR1)D/A converter data register ch.0 (DADR0)
To sub-clock oscillation stabilization
time controller
70
MB90570 Series
15. Chip Select Output
This module generates a chip select signal for facilitating a memory and I/O unit, and is provided with eight chip
select output pins. When access to an address is detected with a hardware-set area set for each pin register,
a select signal is output from the pin.
H to FFFFFFH1 MbyteBecomes active when the program ROM
H to FFFFFFH512 kbyte
Number of
area bytes
Remarks
area or the program vector is fetched.
10FE0000H to FFFFFFH128 kbyte
11—Disabled
00E00000
01F00000
H to EFFFFFH1 MbyteAdapted to the data ROM and RAM areas,
H to F7FFFFH512 kbyte
and external circuit connection
applications.
10FC0000H to FDFFFFH128 kbyte
1168FF80
00003000
01FA0000H to FBFFFFH128 kbyte
1068FF80
1168FF00
H to 68FFFFH128 byte
H to 003FFFH4 kbyteAdapted to the data ROM and RAM areas,
and external circuit connection
applications.
H to 68FFFFH128 byte
H to 68FF7FH128 byte
00F80000H to F9FFFFH128 kbyteAdapted to the data ROM and RAM areas,
0168FF00
1068FE80
H to 68FF7FH128 byte
H to 68FEFFH128 byte
and external circuit connection
applications.
11—Disabled
00002800
0168FE80
CS4
H to 002FFFH2 kbyteAdapted to the data ROM and RAM areas,
H to 68FEFFH128 byte
and external circuit connection
applications.
10—Disabled
11—Disabled
0068FF80
01—Disabled
CS5
H to 68FFFFH128 byteAdapted to the data ROM and RAM areas,
and external circuit connection
applications.
10—Disabled
11—Disabled
0068FF00
01—Disabled
CS6
H to 68FF7FH128 byteAdapted to the data ROM and RAM areas,
and external circuit connection
applications.
10—Disabled
11—Disabled
CS7———DisabledDisabled
73
MB90570 Series
16. Communications Prescaler Register
This register controls machine clock division.
Output from the communications prescaler register is used for UART0 (SCI), UART1 (SCI), and extended I/O
serial interface.
The communications prescaler register is so designed that a constant baud rate may be acquired for various
machine clocks.
(1) Register Configuration
• Communications prescaler control register 0,1 (CDCR0, CDCR1)
Address
H
000028
H
00002A
R/W: Readable and writable
—:Reserved
............
bit 15 bit 8
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
MD———DIV3DIV2DIV1DIV0(Disabled)
R/W———R/WR/WR/WR/W
Initial value
0 - -- 1111
B
74
MB90570 Series
17. Address Match Detection Function
When the address is equal to a value set in the address detection register, the instruction code loaded into the
CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set
instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program
patching function to be implemented.
Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value
set in the address detection register matches an address and if the interrupt enable bit is set at “1”, the instruction
code loaded into the CPU is replaced forcibly with the INT9 instruction code.
(1) Register Configuration
• Program address detection register 0 to 2 (PADR0)
Address
PADR0 (Low order address): 001FF0
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
H
R/WR/WR/WR/WR/WR/WR/WR/W
Address
PADR0 (Middle order address): 001FF1
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
H
R/WR/WR/WR/WR/WR/WR/WR/W
Address
PADR0 (High order address): 001FF2
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
H
R/WR/WR/WR/WR/WR/WR/WR/W
• Program address detection register 3 to 5 (PADR1)
Address
PADR1 (Low order address): 001FF3
Address
PADR1 (Middle order address): 001FF4
Address
PADR1 (High order address): 001FF5
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
H
R/WR/WR/WR/WR/WR/WR/WR/W
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
H
R/WR/WR/WR/WR/WR/WR/WR/W
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
H
R/WR/WR/WR/WR/WR/WR/WR/W
• Program address detection control status register (PACSR)
Address
00009E
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
RESV RESV RESV RESV AD1E RESV AD0E RESV
H
R/WR/WR/WR/WR/WR/WR/WR/W
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
00000000
B
B
B
B
B
B
B
R/W: Readable and writable
X : Undefined
RESV: Reserved bit
75
MB90570 Series
(2) Block Diagram
Address latch
Address detection
Enable bit
Internal data bus
register
Compare
INT9
instruction
2
F
MC-16LX
CPU core
76
MB90570 Series
18. ROM Mirroring Function Selection Module
The ROM mirroring function selection module can select what the FF bank allocated the ROM sees through the
00 bank according to register settings.
(1) Register Configuration
• ROM mirroring function selection register (ROMM)
Address
00006F
W : Write only
—:Reserved
bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
H
———————MI
———————W
............
bit 7 bit 0
(Disabled)
Initial value
-------1
B
Note: Do not access this register during operation at addresses 004000
(2) Block Diagram
ROM mirroring function selection
register (ROMM)
Address area
Address
Internal data bus
Data
FF bank00 bank
ROM
H to 00FFFFH.
77
MB90570 Series
19. Low-power Consumption (Standb y) Mode
The F2MC-16LX has the following CPU operating mode configured by selection of an operating clock and clock
operation control.
•Clock mode
PLL clock mode: A mode in which the CPU and peripheral equipment are driven b y PLL-multiplied oscillation
clock (HCLK).
Main clock mode: A mode in which the CPU and peripheral equipment are driven by divided-by-2 of the
oscillation clock (HCLK).
The PLL multiplication circuits stops in the main clock mode.
• CPU intermittent operation mode
The CPU intermittent operation mode is a mode for reducing power consumption by operating the CPU
intermittently while external bus and peripheral functions are operated at a high-speed.
• Hardware standby mode
The hardware standby mode is a mode f or reducing pow er consumption by stopping cloc k supply to the CPU
by the low-power consumption control circuit, stopping clock supplies to the CPU and peripheral functions
(timebase timer mode), and stopping oscillation clock (stop mode, hardware standb y mode). Of these modes,
modes other than the PLL clock mode are power consumption modes.
(1) Register Configuration
• Clock select register (CKSCR)
Address
0000A1
bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
H
SCMMCMWS1WS0SCSMCSCS1CS0
RRR/WR/WR/WR/WR/WR/W
• Low-power consumption mode control register (LPMCR)
............
Address
0000A0
bit 15 bit 8
H
R/W: Readable and writable
R : Read only
W : Write only
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
STPSLPSPLRSTTMDCG1CG0SSR(CKSCR)
WWR/WWR/WWR/WR/W
............
bit 7 bit 0
(LPMCR)
Initial value
11111100
Initial value
00011000
B
B
78
(2) Block Diagram
Standby control circuit
Low-power consumption mode control register
(LPMCR)
STP
SLP SPL RST TMD CG1 CG0 SSR
CPU intermittent
operation cycle
selector
2
Clock mode
Sleep signal
Stop signal
MB90570 Series
CPU clock
control circuit
CPU operation
clock
Hardware
standby
Reset
Interrupt
PinX0
X1
Pin
Clock selector
Clock oscillator
SQ
R
SQ
R
PLL multiplication
circuit
Oscillation
clock
SQ
R
SQ
R
SCM
MCM WS1 WS0 SCS MCS CS1 CS0
Clock select register (CKSCR)
1/2
Main
clock
1/2048
Timebase timer
Peripheral clock
control circuit
Peripheral function
operation clock
Machine clock
2
Oscillation
stabilization
time selector
2
1/4
1/4
1/8
To watchdog timer
PinX0A
X1A
Pin
S: Set
R: Reset
Q: Output
Sub-clock oscillator
Oscillation
sub-clock
1/1024
Clock timer
1/81/2
1/2
79
MB90570 Series
ELECTRICAL CHARACTERISTICS
■
1. Absolute Maximum Ratings
Parameter
Power supply voltage
(AVSS = VSS = 0.0 V)
Value
Symbol
UnitRemarks
Min.Max.
V
CCVSS – 0.3VSS + 6.0V
AV
CCVSS – 0.3VSS + 6.0V*1
AVRH,
AVRL
SS – 0.3VSS + 6.0V*1
V
SS – 0.3VSS + 6.0V*1
Input voltage V
DVRHV
IVSS – 0.3VSS + 6.0V*2
Output voltageVOVSS – 0.3VSS + 6.0V*2
“L” level maximum output current I
“L” level average output current I
OL15mA*3
OLAV4mA*4
“L” level total maximum output currentΣIOL100mA
“L” level total average output currentΣI
“H” level maximum output currentI
OLAV50mA*5
OH–15mA*3
“H” level average output currentIOHAV–4mA*4
“H” level total maximum output current ΣI
“H” level total average output currentΣI
Power consumptionP
OH–100mA
OHAV–50mA*5
300mW
D
500mWMB90574C
MB90573/4
MB90V570/A
800mWMB90F574/A
Operating temperatureT
A–40+85°C
Storage temperatureTstg–55+150°C
*1: AV
CC, AVRH, AVRL, and DVRH shall never exceed VCC. AVRL shall never exceed AVRH.
*2: V
I and VO shall never exceed VCC + 0.3 V.
*3: The maximum output current is a peak value for a corresponding pin.
*4: Average output current is an average current value observed for a 100 ms period for a corresponding pin.
*5: Total average current is an average current value observed for a 100 ms period for all corresponding pins.
Note: Average output current = operating × operating efficiency
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
80
2. Recommended Operating Conditions
Parameter
Power supply voltage
Smoothing capacitorC
Symbol
Min.Max.
V
CC3.05.5VNormal operation (MB90574/C)
VCC4.55.5VNormal operation (MB90F574/A)
CC3.05.5V
V
S0.11.0µF*
MB90570 Series
(AVSS = VSS = 0.0 V)
Value
UnitRemarks
Retains status at the time of
operation stop
Operating temperatureT
A–40+85°C
* : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be
connected to the V
CC pin must have a capacitance value higher than CS.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
• C pin connection circuit
C
S
C
81
MB90570 Series
3. DC Characteristics
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
CL is a load capacitance connected to a pin under test.
L
Capacitors of C
be connected to address data bus (AD15 to AD00), RD, WRL, and WRH pins.
= 30 pF must be connected to CLK and ALE pins, while CL of 80 pF must
0.2 V
RSTL
HSTL
t
, t
CC
0.2 V
CC
84
(2) Specification for Power-on Reset
Parameter
Power supply rising timet
Power supply cut-off timet
* :V
CC must be kept lower than 0.2 V before power-on.
Symbol Pin name Condition
RVCC
OFFVCC4—ms
—
Notes: • The above ratings are values for causing a power-on reset.
• There are internal registers which can be initialized only by a power-on reset.
Apply power according to this rating to ensure initialization of the registers.
R
t
MB90570 Series
(AV
SS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Min.Max.
0.0530ms*
UnitRemarks
Due to repeated
operations
0.2 V
2.7 V
0.2 V0.2 V
OFF
t
It is recommended to keep the rising
speed of the supply voltage at 50 mV/ms
or slower.
CC
V
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to raise the voltage
smoothly to suppress fluctuations as shown below.
In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 mV or fewer per
second, however, you can use the PLL clock.
CC
V
3.0 V
SS
V
85
MB90570 Series
(3) Clock Timings
Parameter
Clock frequency
Clock cycle time
Input clock pulse width
Input clock rising/falling time
Internal operating clock
frequency
Internal operating clock cycle
time
Frequency fluctuation rate
locked
Symbol Pin name Condition
F
CX0, X1
F
CLX0A, X1A—32.768—kHz
t
HCYLX0, X162.5—333ns
t
LCYLX0A, X1A—30.5—µs
WH,
P
PWL
P
WLH,
P
WLL
CR,
t
tCF
CP—1.5—16MHz
f
LCP——8.192—kHz
f
t
CP—62.5—333ns
LCP——122.1—µs
t
∆f———5%*
(AV
CC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Min.Typ.Max.
UnitRemarks
3—16MHz
Recommend
X010——ns
duty ratio of
30% to 70%
X0A—15.2—µs
X0, X0A——5ns
—
External clock
operation
Main clock
operation
Subclock
operation
External clock
operation
Subclock
operation
* : The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied
PLL signal is locked.
+
+ α
| α |
∆f = × 100 (%)
O
f
Center frequency
O
f
– α
–
The PLL frequency deviation changes periodically from the preset frequency “(about CLK × (1CYC to 50 CYC)”,
thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with
long intervals).
86
• X0, X1 clock timing
HCYL
t
MB90570 Series
0.8 V
X0
• X0A, X1A clock timing
0.8 V
X0A
• PLL operation guarantee range
Relationship between internal operating clock
frequency and power supply voltage
(V)
C
C
V
5.5
e
g
a
t
l
o
4.5
v
y
l
p
p
u
s
3.3
r
e
3.0
w
o
P
1.5381216
Relationship between oscillating frequency, internal
(MHz)
operating clock frequency, and power supply voltage
Multiplied-
16
by-4
CC
WH
P
CC
WLH
P
PLL operation
guarantee range
Internal clock f
Multipliedby-3
CC
0.8 V
LCYL
t
0.8 V
0.2 V
CC
0.2 V
CC
CF
t
CC
CF
t
0.2 V
WL
P
0.2 V
WLL
P
0.8 V
CC
0.8 V
CC
Operation guarantee range (MB90F574/A)
Operation guarantee range MB90574C
(MHz)
CP
Multiplied-by-2
Multiplied-by-1
CC
CR
t
CC
CR
t
Operation guarantee range
MB90V570/A
Operation guarantee range
MB90573/4
12
P
C
f
k
c
o
l
c
l
a
n
r
e
t
n
I
1.5
9
8
Not multiplied
6
4
3
2
34816
612
Oscillation clock F
C
(MHz)
87
MB90570 Series
The AC ratings are measured for the following measurement reference voltages.