FUJITSU MB90570 DATA SHEET

查询MB90573供应商
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13701-7E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90570 Series
DESCRIPTION
The MB90570 series is a general-purpose 16-bit microcontroller developed and designed by Fujitsu for process control applications in consumer products that require high-speed real time processing. It contains an I interface that allows inter-equipment communication to be implemented readily. This product is well adapted to car audio equipment, VTR systems, and other equipment and systems.
2
The instruction set of F sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data.
MC-16LX CPU core inherits AT architecture of F2MC*1 family with additional instruction
2C*2
bus
The MB90570 series has peripheral resources of an 8/10-bit A/D converter, an 8-bit D/A converter, UART (SCI), an extended I/O serial interface, an 8/16-bit up/down counter/timer, an 8/16-bit PPG timer, I/O timer (a 16-bit free run timer, an input capture (ICU), an output compare (OCU)).
2
MC stands for FUJITSU Flexible Microcontroller.
*1: F *2: Purchase of Fujitsu I
components in an I defined by Philips.
PACKAGE
120-pin plastic LQFP
(FPT-120P-M05)
2
C components conveys a license under the Philips I2C Patent Rights to use these
2
C system, provided that the system conforms to the I2C Standard Specification as
120-pin plastic QFP
(FPT-120P-M13)
120-pin plastic LQFP
(FPT-120P-M21)
MB90570 Series
FEATURES
•Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from 1/2 to 4× oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz). Minimum instruction execution time: 62.5 ns (at oscillation of 4 MHz, 4 × PLL clock, operation at V
• Maximum memory space 16 Mbytes
• Instruction set optimized for controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C) and multi-task operations Adoption of system stack pointer
Enhanced pointer indirect instructions Barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed 4-byte instruction queue
• Enhanced interrupt function 8 levels, 34 factors
• Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI
• Embedded ROM size and types Mask ROM: 128 kbytes/256 kbytes
Flash ROM: 256 kbytes Embedded RAM size: 6 kbytes/10 kbytes (mask ROM)
10 kbytes (flash memory) 10 kbytes (evaluation device)
• Low-power consumption (standby) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) CPU intermittent operation mode Hardware standby mode
•Process CMOS technology
• I/O port General-purpose I/O ports (CMOS): 63 ports
General-purpose I/O ports (with pull-up resistors): 24 ports General-purpose I/O ports (open-drain): 10 ports Total: 97 ports
2
OS): Up to 16 channels
CC of 5.0 V)
(Continued)
2
MB90570 Series
(Continued)
•Timer Timebase timer/watchdog timer: 1 channel 8/16-bit PPG timer: 8-bit × 2 channels or 16-bit × 1 channel
• 8/16-bit up/down counter/timer: 1 channel (8-bit × 2 channels)
• 16-bit I/O timer 16-bit free run timer: 1 channel Input capture (ICU): Generates an interrupt request by latching a 16-bit free run timer counter value upon
detection of an edge input to the pin.
Output compare (OCU): Generates an interrupt request and re verse the output lev el upon detection of a match
between the 16-bit free run timer counter value and the compare setting value.
• Extended I/O serial interface: 3 channels
2
•I
C interface (1 channel)
Serial I/O port for supporting Inter IC BUS
• UART0 (SCI), UART1 (SCI) With full-duplex double buffer Clock asynchronized or clock synchronized transmission can be selectively used.
• DTP/external interrupt circuit (8 channels) A module for starting extended intelligent I/O service (EI
by an external input.
• Delayed interrupt generation module Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels) 8/10-bit resolution Starting by an external trigger input. Conversion time: 26.3 µs
• 8-bit D/A converter (based on the R-2R system) 8-bit resolution: 2 channels (independent)
Setup time: 12.5 µs
• Clock timer: 1 channel
• Chip select output (8 channels) An active level can be set.
• Clock output function
2
OS) and generating an external interrupt triggered
3
MB90570 Series
PRODUCT LINEUP
Part number
Item
Classification Mask ROM products Flash ROM products Evaluation product ROM size 128 kbytes 256 kbytes None RAM size 6 kbytes 10 kbytes
CPU functions
Ports
UART0 (SCI), UART1 (SCI)
8/10-bit A/D converter
MB90573
Minimum execution time: 62.5 ns (at machine clock of 16 MHz)
Interrupt processing time: 1.5 µs (at machine clock of 16 MHz, minimum value)
General-purpose I/O ports (with pull-up resistor): 24
General-purpose I/O ports (N-ch open-drain output): 10
Clock synchronized transmission (62.5 kbps to 1 Mbps)
Clock asynchronized transmission (1202 bps to 9615 bps) Transmission can be performed by bi-directional serial transmission or by master/slave connection.
One-shot conversion mode (converts selected channel only once)
Scan conversion mode (converts two or more successive channels and can
Continuous conversion mode (converts selected channel continuously)
Stop conversion mode (converts selected channel and stop operation repeatedly)
MB90574/C MB90F574/A MB90V570/A
The number of instructions: 340 Instruction bit length: 8 bits, 16 bits Instruction length: 1 byte to 7 bytes Data bit length: 1 bit, 8 bits, 16 bits
General-purpose I/O ports (CMOS output): 63
Total: 97
Resolution: 8/10-bit Number of inputs: 8
program up to 8 channels.)
8/16-bit PPG timer
8/16-bit up/down counter/ timer
16-bit free run timer
16-bit I/O timer
4
Output compare (OCU)
Input capture (ICU)
Number of channels: 1 (or 8-bit × 2 channels)
PPG operation of 8-bit or 16-bit
A pulse wave of given intervals and given duty ratios can be output.
Pulse interval: 62.5 ns to 1 µs (at oscillation of 4 MHz, machine clock of 16 MHz)
Number of channels: 1 (or 8-bit × 2 channels)
Event input: 6 channels
8-bit up/down counter/timer used: 2 channels
8-bit re-load/compare function supported: 1 channel
Number of channel: 1
Overflow interrupts
Number of channels: 4
Pin input factor: A match signal of compare register
Number of channels: 2
Rewriting a register value upon a pin input (rising, falling, or both edges)
(Continued)
(Continued)
MB90570 Series
Part number
Item
DTP/external interrupt circuit
Delayed interrupt generation module
Extended I/O serial interface
2
C interface
I
Timebase timer
8-bit D/A converter
Watchdog timer
Low-power consumption (standby) mode
MB90573
Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.
External interrupt circuit or extended intelligent I/O service (EI
An interrupt generation module for switching tasks used in real time operating
Clock synchronized transmission (3125 bps to 1 Mbps)
Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms
Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
Sleep/stop/CPU intermittent operation/clock timer/hardware standby
MB90574/C MB90F574/A MB90V570/A
Number of inputs: 8
2
OS) can be used.
systems.
LSB first/MSB first
Serial I/O port for supporting Inter IC BUS
18-bit counter
(at oscillation of 4 MHz)
8-bit resolution
Number of channels: 2 channels
Based on the R-2R system
(at oscillation of 4 MHz, minimum value)
Process CMOS Power supply voltage for
operation*
* :Varies with conditions such as the operating frequency. (See section “ Electrical Characteristics.”)
Assurance for the MB90V570/A is given only for operation with a tool at a power voltage of 4.5 V to 5.5 V, an operating temperature of 0 to +25°C, and an operating frequency of 1 MHz to 16 MHz.
PACKAGE AND CORRESPONDING PRODUCTS
Package MB90573 MB90574 MB90F574/A MB90574C
FPT-120P-M05 × FPT-120P-M13 FPT-120P-M21 × ×
: Available ×: Not available
Note: For more inf ormation about each package, see section “ Package Dimensions.”
4.5 V to 5.5 V
5
MB90570 Series
DIFFERENCES AMONG PRODUCTS
Memory Size
In evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. The following items must be taken into consideration.
• The MB90V570/A does not have an internal ROM, however, operations equivalent to chips with an internal ROM can be ev aluated b y using a dedicated development tool, enabling selection of ROM size b y settings of the development tool.
• In the MB90V570/A, images from FF4000 mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.)
• In the MB90F574/574/573/F574A/574C, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000
• The products designated with /A or /C are different from those without /A or /C in that they are DTP/externally­interrupted types which return from standby mode at the ch.0 to ch.1 edge request.
H to FF3FFFH to bank FF only.
H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to
6
PIN ASSIGNMENT
MB90570 Series
(Top view)
P31/RD P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK
CC
V P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN1 P44/SOT1 P45/SCK1 P46/PPG0 P47/PPG1 P50/SIN2 P51/SOT2 P52/SCK2 P53/SIN3 P54/SOT3 P55/SCK3 P56/IN0 P57/IN1 P60/SIN4 P61/SOT4 P62/SCK4 P63/CKOT P64/OUT0 P65/OUT1
P30/ALE
VSSP27/A23
P26/A22
P25/A21
P24/A20
P23/A19
P22/A18
P21/A17
P20/A16
P17/AD15
P16/AD14
P15/AD13
P14/AD12
P13/AD11
P12/AD10
P11/AD09
P10/AD08
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
3132333435363738394041424344454647484950515253545556575859
1009998979695949392
P01/AD01
P00/AD00
VCCX1X0V
SS
91
60
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RST MD0 MD1 MD2 HST PC3 PC2 PC1 PC0 PB7 PB6/ADTG PB5/IRQ5 PB4/IRQ4 PB3/IRQ3 PB2/IRQ2 PB1/IRQ1 X0A X1A PB0/IRQ0 PA7/SCL PA6/SDA PA5/ZIN1 PA4/BIN1 PA3/AIN1/IRQ7 PA2/ZIN0 PA1/BIN0 PA0/AIN0/IRQ6
SS
V P97/CS7 P96/CS6
P66/OUT2
P67/OUT3
VSSC
P70
P71
P72
DVCCDVSSP73/DA0
P74/DA1
AVCCAVRH
AVRL
(FPT-120P-M05) (FPT-120P-M13) (FPT-120P-M21)
AVSSP80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
VCCP90/CS0
P91/CS1
P92/CS2
P93/CS3
P94/CS4
P95/CS5
7
MB90570 Series
PIN DESCRIPTION
Pin no.
Pin name Circuit type Function
LQFP-120 *
QFP-120 *
92,93 X0,X1 A 74,73 X0A,X1A B
89 to 87 MD0 to MD2 C
90 RST C 86 HST C
95 to 102 P00 to P07 D
103 to 110 P10 to P17 D
111 to 118 P20 to P27 E
120 P30 E
1
2
AD00 to AD07
AD08 to AD15
A16 to A23
ALE
1P31 E
RD
2P32 E
WRL
3P33 E
WRH
4P34 E
HRQ
5P35 E
HAK
6P36 E
RDY
High speed oscillator input pins Low speed oscillator input pins These are input pins used to designate the operating mode. They should
be connected directly to Vcc or Vss. Reset input pin Hardware standby input pin In single chip mode, these are general purpose I/O pins. When set for
input, they can be set by the pull-up resistance setting register (RDR0). When set for output, this setting will be invalid.
In external bus mode, these pins function as address low output/data low I/O pins.
In single chip mode, these are general purpose I/O pins. When set for input, they can be set by the pull-up resistance setting register (RDR1). When set for output, the setting will be invalid.
In external bus mode, these pins function as address middle output/data high I/O pins.
In single chip mode this is a general-purpose I/O port. In external bus mode, these pins function as address high output pins. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the address latch enable signal
output pin. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the read strobe signal output
pin. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the data bus lower 8-bit write
strobe signal output pin. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the data bus upper 8-bit write
strobe signal output pin. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the hold request signal input
pin. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the hold acknowledge signal
output pin. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the ready signal input pin.
*1: FPT-120P-M05 *2: FPT-120P-M13
8
(Continued)
,FPT-120P-M21
Pin no.
Pin name Circuit type Function
LQFP-120 *
QFP-120 *
1
2
7P37 E
CLK
9P40 F
SIN0
10 P41 F
SOT0
11 P42 F
SCK0
12 P43 F
SIN1
13 P44 F
SOT1
14 P45 F
SCK1
15,16 P46,P47 F
PPG0,PPG1
17 P50 E
SIN2
MB90570 Series
In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the clock (CLK) signal output
pin. In single chip mode this is a general-purpose I/O port. It can be set to open
drain by the ODR4 register. This is also the UART ch.0 serial data input pin. While UART ch.0 is in
input operation, this input signal is in continuous use, and therefore the output function should only be used when needed. If shared by output from other functions, this pin should be output disabled during SIN operation.
In single chip mode this is a general-purpose I/O port. It can be set to open drain by the ODR4 register.
This is also the UART ch.0 serial data output pin. This function is valid when UART ch.0 is enabled for data output.
In single chip mode this is a general-purpose I/O port. It can be set to open drain by the ODR4 register.
This is also the UART ch.0 serial clock I/O pin. This function is valid when UART ch.0 is enabled for clock output.
In single chip mode this is a general-purpose I/O port. It can be set to open-drain by the ODR4 register.
This is also the UART ch.1 serial data input pin. While UART ch.1 is in input operation, this input signal is in continuous use, and therefore the output function should only be used when needed. If shared by output from other functions, this pin should be output disabled during SIN operation.
In single chip mode this is a general-purpose I/O port. It can be set to opendrain by the ODR4 register.
This is also the UART ch.1 serial data output pin. This function is valid when UART ch.1 is enabled for data output.
In single chip mode this is a general-purpose I/O port. It can be set to open drain by the ODR4 register.
This is also the UART ch.1 serial clock I/O pin. This function is valid when UART ch.1 is enabled for clock output.
In single chip mode this is a general-purpose I/O port. It can be set to open drain by the ODR4 register.
These are also the PPG0, 1 output pins. This function is valid when PPG0, 1 output is enabled.
In single chip mode this is a general-purpose I/O port. This is also the I/O serial ch.0 data input pin. During serial data input, this
input signal is in continuous use, and therefore the output function should only be used when needed.
*1: FPT-120P-M05 *2: FPT-120P-M13
(Continued)
,FPT-120P-M21
9
MB90570 Series
Pin no.
Pin name Circuit type Function
LQFP-120 *
QFP-120 *
18 P51 E
19 P52 E
20 P53 E
21 P54 E
22 P55 E
23,24 P56,P57 E
25 P60 F
26 P61 F
27 P62 F
28 P63 F
*1: FPT-120P-M05 *2: FPT-120P-M13
1
2
SOT2
SCK2
SIN3
SOT3
SCK3
IN0,IN1
SIN4
SOT4
SCK4
CKOT
,FPT-120P-M21
In single chip mode this is a general-purpose I/O port. This is also the I/O serial ch.0 data output pin. This function is valid when
serial ch.0 is enabled for serial data output. In single chip mode this is a general-purpose I/O port. This is also the I/O serial ch.0 clock I/O pin. This function is valid when
serial ch.0 is enabled for serial data output. In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.1 data input pin. During serial data input, this input signal is in continuous use, and therefore the output function should only be used when needed.
In single chip mode this is a general-purpose I/O port. This is also the I/O serial ch.1 data output pin. This function is valid when
serial ch.1 is enabled for serial data output. In single chip mode this is a general-purpose I/O port. This is also the I/O serial ch.1 clock I/O pin. This function is valid when
serial ch.1 is enabled for serial data output. In single chip mode this is a general-purpose I/O port.
These are also the input capture ch.0/1 trigger input pins. During input capture signal input on ch.0/1 this function is in continuous use, and therefore the output function should only be used when needed.
In single chip mode this is a general-purpose I/O port. When set for input it can be set by the pull-up resistance register (RDR6). When set for output this setting will be invalid.
This is also the I/O serial ch.2 data input pin. During serial data input this function is in continuous use, and therefore the output function should only be used when needed.
In single chip mode this is a general-purpose I/O port. When set for input it can be set by the pull-up resistance register (RDR6). When set for output this setting will be invalid.
This is also the I/O serial ch.2 data output pin. This function is valid when serial ch.2 is enabled for serial data output.
In single chip mode this is a general-purpose I/O port. When set for input it can be set by the pull-up resistance register (RDR6). When set for output this setting will be invalid.
This is also the I/O serial ch.2 serial clock I/O pin. This function is valid when serial ch.2 is enabled for serial data output.
In single chip mode this is a general-purpose I/O port. When set for input it can be set by the pull-up resistance register (RDR6). When set for output this setting will be invalid.
This is also the clock monitor output pin. This function is valid when cloc k monitor output is enabled.
(Continued)
10
Pin no.
1
LQFP-120 *
QFP-120 *
Pin name Circuit type Function
2
29 to 32 P64 to P67 F
OUT0 to OUT3
35 to 37 P70 to P72 E
40,41 P73,P74 I
DA0,DA1
46 to 53 P80 to P87 K
AN0 to AN7
55 to 62 P90 to P97 E
CS0 to CS7
34 C G
64 PA0 E
AIN0 IRQ6
65 PA1 E
BIN0
66 PA2 E
ZIN0
67 PA3 E
AIN1 IRQ7
68 PA4 E
BIN1
69 PA5 E
ZIN1
MB90570 Series
In single chip mode these are general-purpose I/O ports. When set for input they can be set by the pull-up resistance register (RDR6). When set for output this setting will be invalid.
These are also the output compare ch.0 to ch.3 event output pins. This function is valid when the respective channel(s) are enabled for output.
These are general purpose I/O ports. These are general purpose I/O ports. These are also the D/A converter ch.0,1 analog signal output pins. These are general purpose I/O ports. These are also A/D converter analog input pins. This function is valid
when analog input is enabled. These are general purpose I/O ports.
These are also chip select signal output pins. This function is valid when chip select signal output is enabled.
This is the power supply stabilization capacitor pin. It should be connected externally to an 0.1 µF ceramic capacitor. Note that this is not required on the FLASH model (MB90F574/A) and MB90574C.
This is a general purpose I/O port. This pin is also used as count clock A input for 8/16-bit up-down counter
ch.0. This pin can also be used as interrupt request input ch. 6.
This is a general purpose I/O port. This pin is also used as count clock B input for 8/16-bit up-down counter
ch.0. This is a general purpose I/O port. This pin is also used as count clock Z input for 8/16-bit up-down counter
ch.0. This is a general purpose I/O port. This pin is also used as count clock A input for 8/16-bit up-down counter
ch.1. This pin can also be used as interrupt request input ch.7. This is a general purpose I/O port. This pin is also used as count clock B input for 8/16-bit up-down counter
ch.1. This is a general purpose I/O port.
This pin is also used as count clock Z input for 8/16-bit up-down counter ch.1.
*1: FPT-120P-M05 *2: FPT-120P-M13
(Continued)
,FPT-120P-M21
11
MB90570 Series
(Continued)
Pin no.
Pin name Circuit type Function
LQFP-120 *
QFP-120 *
70 PA6 L
71 PA7 L
72,
75 to 79
80 PB6 E
81 PB7 E
82 to 85 PC0 to PC3 E
8,54,94 VCC Power
33,63,
91,119
42 AVCC H 43 AVRH J
44 AVRL H 45 AVSS H
38 DVCC H 39 DVSS H
1
2
SDA
SCL
PB0, PB1 to PB5
IRQ0, IRQ1 to IRQ5
ADTG
VSS Power
E
supply
supply
This is a general purpose I/O port. This pin is also used as the data I/O pin for the I2C interface. This
function is valid when the I
2
I
C interface is operating, this port should be set to the input level
(DDRA: bit6 = 0). This is a general purpose I/O port.
This pin is also used as the clock I/O pin for the I2C interface. This function is valid when the I
2
I
C interface is operating, this port should be set to the input level
(DDRA: bit7 = 0). These are general-purpose I/O ports.
These pins are also the external interrupt input pins. IRQ0, 1 are enabled for both rising and falling edge detection, and therefore cannot be used for recovery from STOP status for MB90V570, MB90F574, MB90573 and MB90574. However, IRQ0, 1 can be used for recovery from STOP status for MB90V570A, MB90F574A and MB90574C.
This is a general purpose I/O port. This is also the A/D converter external trigger input pin. While the A/D
converter is in input operation, this input signal is in continuous use, and therefore the output function should only be used when needed.
This is a general purpose I/O port. These are general purpose I/O ports. These are power supply (5V) input pins.
These are power supply (0V) input pins.
This is the analog macro (D/A, A/D etc.) Vcc power supply input pin. This is the A/D converter Vref+ input pin. The input voltage should not
exceed Vcc. This is the A/D converter Vref-input pin. The input voltage should not
less than Vss. This is the analog macro (D/A, A/D etc.) Vss power supply input pin.
This is the D/A converter Vref input pin. The input voltage should not exceed Vcc.
This is the D/A converter GND power supply pin. It should be set to Vss equivalent potential.
2
C interface is enabled f or operation. While the
2
C interface is enabled f or operation. While the
*1: FPT-120P-M05 *2: FPT-120P-M13
12
,FPT-120P-M21
MB90570 Series
I/O CIRCUIT TYPE
Type Circuit Remarks
A • Oscillator circuit
X1
X0
Standby control signal
B • Oscillator circuit
X1A
X0A
Oscillator recovery resistance for high speed = approx. 1 M
Oscillator recovery resistance for low speed = approx. 1 M
Standby control signal
C • Hysteresis input pin
Resistance value = approx. 50 k(typ.)
R
Hysteresis input
D • CMOS hysteresis input pin with input pull-
CC
V
V
P-ch
Selective signal either with a pull-up resistor or
CC
without it.
P-ch
up control
• CMOS level output.
• CMOS hysteresis input (Includes input shut down standby control function)
OL
= 4 mA
I
N-ch
R
Standby control for input interruption
Hysteresis input
• Pull-up resistance value = approx. 50 kΩ(typ.) I
OL = 4mA
(Continued)
13
MB90570 Series
Type Circuit Remarks
E • CMOS hysteresis input/output pin.
R
IOL = 4 mA
CC
V
P-ch
N-ch
Hysteresis input
Standby control for input interruption
• CMOS level output
• CMOS hysteresis input (Includes input shut down standby control function) I
OL = 4 mA
F • CMOS hysteresis input/output pin.
CC
V
P-ch
• CMOS level output
• CMOS hysteresis input (Includes input shut down standby control function)
OL = 10 mA (Large current port)
N-ch
R
OL
= 10 mA
I
G • C pin output
V
Standby control for input interruption
CC
Hysteresis input
I
(capacitance connector pin).
P-ch
N-ch
H • Analog power supply protector
CC
V
On the MB90F574 this pin is not connected (NC).
circuit.
P-ch
AVP
N-ch
14
I • CMOS hysteresis input/output
CC
V
P-ch
• Analog output/CMOS output dual-function pin (CMOS output is not available during analog output.) (Analog output priority: DAE = 1)
OL
= 4 mA
I
N-ch
R
Standby control for input interruption
Hysteresis input
DAO
• Includes input shout down standby control function. I
OL = 4mA
(Continued)
MB90570 Series
Type Circuit Remarks
J • A/D converter ref+ power supply input
CC
V
P-ch
N-ch
ANE AVR ANE
P-ch N-ch
pin(AVRH), with power supply protector circuit.
K • CMOS hysteresis input /analog input
CC
V
P-ch
dual-function pin.
• CMOS output
• Includes input shut down function at input
N-ch
R
Standby control for input interruption
OL
I
= 4 mA
L • Hysteresis input
CC
V
Hysteresis input
Analog input
N-ch
shut down standby.
• N-ch open-drain output
• Includes input shut down standby control function. I
OL= 4mA
OL
= 4 mA
I
N-ch
R
Hysteresis input
Standby control for input interruption
15
MB90570 Series
HANDLING DEVICES
1. Preventing Latchup
CMOS ICs may cause latchup in the following situations:
• When a voltage higher than Vcc or lower than Vss is applied to input or output pins.
• When a voltage exceeding the rating is applied between Vcc and Vss.
• When AVcc power is supplied prior to the Vcc voltage. In turning on/turning off the analog power supply , mak e sure the analog po wer v oltage (AV
analog input voltages not exceed the digital voltage (V
CC).
CC, AVRH, D VCC)and
2. Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefor they must be tied to V more than 2 k<Symbol>W. Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection.
CC or Ground through resistors. In this case those resistors should be
3. Notes on Using External Clock
In using the external clock, drive X0 pin only and leave X1 pin unconnected.
• Using external clock
MB90570 series
X0
Open
X1
4. Unused Sub Clock Mode
If sub clock modes are not used, the oscillator should be connected to the X01A pin and X1A pin
5. Power Supply Pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating.
Make sure to connect V
16
CC and VSS pins via lowest impedance to power lines.
MB90570 Series
It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pin near the device.
Using
power supply pins
VCC VSS
VCC
VSS
MB90570 series
VCC
VSS
VSS
VCC
VSS
VCC
6. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand area for stabilizing the operation.
7. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVR H, AVRL , DV
CC,DVSS) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does not exceed AVRH or AVCC (tur ning on/off the analog and digital power supplies simulta­neously is acceptable).
8. Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = DVCC = VSS.
9. N.C. Pins
The N.C. (internally connected) pins must be opened for use.
10. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 or more µs (0.2 V to 2.7 V).
11. Indeterminate outputs from ports 0 and 1
The outputs from ports 0 and 1 become indeterminate during oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on. (MB90573, MB90574, MB90V570, MB90V570A)
17
MB90570 Series
The series without built-in step-down circuit have no oscillation setting time of step-down circuit, so outputs should not become indeterminate. (MB90F574,MB90F574A,MB90574C)
Timing chart of indeterminate outputs from ports 0 and 1
Oscillation setting time *
Step-down circuit setting time *
VCC (power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal KA (internal operating clock A) signal KB (internal operating clock B) signal
PORT (port output) signal
*1: Step-down circuit setting time 217/oscillation clock frequency (oscillation clock frequency of 16 MHz: 8.19 ms) *2: Oscillation setting time 2
18
/oscillation clock frequency (oscillation clock frequency of 16 MHz: 16.38 ms)
Period of indeterminate
1
2
12. Initialization
In the device, there are internal registers which are initialized only by a po wer-on reset. Turn on the power again to initialize these registers.
13. Return from standby state
If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may fail to return from the standby state. In this case, reset the de vice via the external reset pin to return to the normal state.
14. Precautions for Use of ’DIV A, Ri,’ and ’DIVW A, Ri’ Instructions
The signed multiplication-division instructions ’DIV A, Ri,’ and ’DIVW A, RWi’ should be used when the corre­sponding bank registers (DTB, ADB, USB , SSB) are set to value ’00h.’ If the corresponding bank registers (DTB, ADB, USB, SSB) are set to a value other than ’00h,’ then the remainder obtained after the execution of the instruction will not be placed in the instruction operand register.
15. Precautions for Use of REALOS
Extended intelligent I/O service (EI2OS) cannot be used, when REALOS is used.
18
BLOCK DIAGRAM
MB90570 Series
X0, X1 X0A, X1A RST HST
P00/AD00 to P07/AD07 P10/AD08 to P17/AD15 P20/A16 to P27/A23
P30/ALE P31/RD P32/WRL
P33/WRH P34/HRQ
P35/HAK P36/RDY
P37/CLK
P40/SIN0 P41/SOT0 P42/SCK0
P43/SIN1 P44/SOT1 P45/SCK1 P46/PPG0 P47/PPG1
P50/SIN2 P51/SOT2 P52/SCK2 P53/SIN3 P54/SOT3 P55/SCK3
P56/IN0 P57/IN1
Main clock Sub clock
2
F
MC–16LX
CPU
Clock control
block
(including timebase
timer)
8 8
8
Port 0, 1, 2
16
8
2
External bus
interface
6
Port 3
Port 4
2
UART0
2
UART1
2
8/16-bit
PPG timer
Port 5
2 2
SIO × 2 ch
2
2
Input capture
Internal data bus
(SCI),
(SCI)
ch.0
(ICU)
Interrupt controller
Port 7
8-bit
D/A
converter
2 ch.
×
Port 9
Chip select
output
Port A
8/16-bit up/down
counter/timer
I2C bus
DTP/ external interrupt
circuit
8 ch.
×
Port B
8/10-bit
A/D converter
× 8 ch.
Port 8
Port C
3
P70 to P72
2
6
2
6
8
P73/DA0 P74/DA1
DV
CC
DV
SS
88
P90/CS0 to P97/CS7
PA1/BIN0 PA2/ZIN0 PA3/AIN1/IRQ7 PA4/BIN1 PA5/ZIN1
PA6/SDA PA7/SCL
PA0/AIN0/IRQ6
6
PB0/IRQ0 to PB5/IRQ5
PB7
PB6/ADTG AVRL
AVRH AV
CC
AV
SS
8
P80/AN0 to P87/AN7
4
PC0 to PC3
P64/OUT0 to P67/OUT3
P60/SIN4 P61/SOT4 P62/SCK4
P63/CKOT
Other pins
MD0 to MD2,
CC
SS
, V
C, V
16-bit free run timer
4
4
Output
compare
(OCU)
SIO × 1 ch.
Port 6
Clock output
RAM
ROM
P00 to P07 (8 ports): Provided with a register optional input pull-up resistor P10 to P17 (8 ports): Provided with a register optional input pull-up resistor
OL
P40 to P47 (8 ports): Heavy-current (I P60 to P67 (8 ports): Provided with a register optional input pull-up resistor
= 10 mA) port
19
MB90570 Series
MEMORY MAP
H
FFFFFF
Address #1
H
FC0000
H
010000
Address #2
H
004000
Address #3
H
000100
H
0000C0
H
000000
Internal ROM
Single chip mode A mirror function is supported.
ROM area ROM area
ROM area
(image of bank FF)
Register
RAM RAM RAM
external bus mode A mirror function is supported.
ROM area
(image of bank FF)
Register
PeripheralPeripheral Peripheral
External ROM external bus mode
Register
Part number Address #1* Address #2 * Address #3 *
MB90573 FE0000
H 004000H 001800H
MB90574/C FC0000H 004000H 002900H MB90F574/A FC0000H 004000H 002900H
: Internal access memory : External access memory : Inhibited area
*: Addresses #1, #2 and #3 are unique to the product type.
Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effectiv e use of the C compiler
small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 is assigned to the same address , enabling reference of the table on the ROM without stating “far”.
For example, if an attempt has been made to access 00C000
H, the contents of the ROM at FFC000H are
accessed actually . Since the ROM area of the FF bank e xceeds 48 kbytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000 for 00400 to FFFFFF
H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H
H.
H to FFFFFFH looks, therefore , as if it were the image
20
2
F
MC-16LX CPU PROGRAMMING MODEL
• Dedicated registers
MB90570 Series
AH AL
USP
SSP
PS
PC
DPR
PCB
DTB
USB
: Accumulator (A)
Dual 16-bit register used for storing results of calculation etc. The two 16-bit registers can be combined to be used as a 32-bit register.
: User stack pointer (USP)
The 16-bit pointer indicating a user stack address.
: System stack pointer (SSP)
The 16-bit pointer indicating the status of the system stack address.
: Processor status (PS)
The 16-bit register indicating the system status.
: Program counter (PC)
The 16-bit register indicating storing location of the current instruction code.
: Direct page register (DPR)
The 8-bit register indicating bit 8 through 15 of the operand address in the short direct addressing mode.
: Program bank register (PCB)
The 8-bit register indicating the program space.
: Data bank register (DTB)
The 8-bit register indicating the data space.
: User stack bank register (USB)
The 8-bit register indicating the user stack space.
32-bit
16-bit
SSB
ADB
8-bit
: System stack bank register (SSB)
The 8-bit register indicating the system stack space.
: Additional data bank register (ADB)
The 8-bit register indicating the additional data space.
21
MB90570 Series
• General-purpose registers
Maximum of 32 banks
H
000180
• Processor status (PS)
ILM RP CCR
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PS
ILM2 B4ILM1 ILM0 B3 B2 B1 B0 I S T N Z V C
+ (RP × 10H)
R7 R5
R3 R1
RW3 RW2 RW1 RW0
16-bit
R6 R4
R2 R0
RW7
RL3
RW6 RW5
RL2
RW4
RL1
RL0
22
Initial value
—: Reserved X : Undefined
00 000000 10XXXXX
I/O MAP
MB90570 Series
Address
000000
Abbreviated
register
Register name
name
H PDR0 Port 0 data register R/W Port 0 X X XXXXXX B
Read/
write
Resource name Initial value
000001H PDR1 Port 1 data register R/W Port 1 X X XXXXXX B 000002H PDR2 Port 2 data register R/W Port 2 X X XXXXXX B 000003H PDR3 Port 3 data register R/W Port 3 X X XXXXXX B 000004H PDR4 Port 4 data register R/W Port 4 X X XXXXXX B 000005H PDR5 Port 5 data register R/W Port 5 X X XXXXXX B 000006H PDR6 Port 6 data register R/W Port 6 X X XXXXXX B 000007H PDR7 Port 7 data register R/W Port 7 X X XXXXXX B 000008H PDR8 Port 8 data register R/W Port 8 X X XXXXXX B
000009H PDR9 Port 9 data register R/W Port 9 X X XXXXXX B 00000AH PDRA Port A data register R/W Port A XXXXX X X X B 00000BH PDRB Port B data register R/W Port B XXXXX X X X B
00000CH PDRC Port C data register R/W Port C XXX X X X X X B 00000DH
to
00000F 000010
H
H DDR0 Port 0 direction register R/W Port 0 0 0 0 0 0 0 0 0 B
(Disabled)
000011H DDR1 Port 1 direction register R/W Port 1 0 0 0 0 0 0 0 0 B 000012H DDR2 Port 2 direction register R/W Port 2 0 0 0 0 0 0 0 0 B 000013H DDR3 Port 3 direction register R/W Port 3 0 0 0 0 0 0 0 0 B 000014H DDR4 Port 4 direction register R/W Port 4 0 0 0 0 0 0 0 0 B 000015H DDR5 Port 5 direction register R/W Port 5 0 0 0 0 0 0 0 0 B 000016H DDR6 Port 6 direction register R/W Port 6 0 0 0 0 0 0 0 0 B 000017H DDR7 Port 7 direction register R/W Port 7 – – – 0 0 0 0 0 B 000018H DDR8 Port 8 direction register R/W Port 8 0 0 0 0 0 0 0 0 B 000019H DDR9 Port 9 direction register R/W Port 9 0 0 0 0 0 0 0 0 B 00001AH DDRA Port A direction register R/W Port A 0 0 0 0 0 0 0 0 B 00001BH DDRB Port B direction register R/W Port B 0 0 0 0 0 0 0 0 B
00001CH DDRC Port C direction register R/W Port C 0 0 0 0 0 0 0 0 B 00001DH ODR4 Port 4 output pin register R/W Port 4 0 0 0 0 0 0 0 0 B
Port 8,
00001EH ADER Analog input enable register R/W
8/10-bit
11111111B
A/D converter 00001FH (Disabled) 000020 000021H SCR0 Serial control register 0 R/W 0 0 0 0 0 1 0 0 B
H SMR0 Serial mode register 0 R/W
UART0
(SCI)
00000000B
(Continued)
23
MB90570 Series
Address
000022
Abbreviated
register
name
SIDR0/
H
SODR0
Register name
Serial input data register 0/ serial output data register 0
Read/
write
R/W
Resource
name
UART0
Initial value
XXXXXXXX
(SCI)
000023H SSR0 Serial status register 0 R/W 0 0 0 0 1 – 0 0 B 000024H SMR1 Serial mode register 1 R/W
00000000B
000025H SCR1 Serial control register 1 R/W 0 0 0 0 0 1 0 0 B
UART1
000026H
SIDR1/
SODR1
Serial input data register 1/ serial output data register 1
R/W XXXXXXXX
(SCI)
000027H SSR1 Serial status register 1 R/W 0 0 0 0 1 – 0 0 B
Communica-
000028H CDCR0
Communications prescaler control register 0
R/W
tions
prescaler
0–––1111
register 0
000029H (Disabled)
Communica-
00002A
H CDCR1
Communications prescaler control register 1
R/W
tions
prescaler
0–––1111B
register 0
00002BH
to
(Disabled)
00002FH 000030 000031H EIRR DTP/interrupt factor register R/W XXXXXXXX B
H ENIR DTP/interrupt enable register R/W
00000000B
DTP/external
interrupt cir-
000032H
ELVR Request level setting register R/W
cuit
00000000 000033H 00000000B 000034H
(Disabled)
000035 000036H ADCS1
000037H ADCS2
H
A/D control status register lower digits
A/D control status register upper digits
R/W
R/W or W 00000000
8/10-bit A/D
00000000B
converter
000038H ADCR1 A/D data register lower digits R XX X X X X X X B 000039H ADCR2 A/D data register upper digits W 0 0 0 0 1 – X X B
00003AH DADR0 D/A converter data register ch.0 R/W 00003BH DADR1 D/A converter data register ch.1 R/W XXXX X X X X B 00003CH DACR0 D/A control register 0 R/W –––––––0B
8-bit D/A
converter
XXXXXXXX
00003DH DACR1 D/A control register 1 R/W –––––––0B 00003EH CLKR Clock output enable register R/W
Clock monitor
function
––––0000 00003FH (Disabled)
000040 000041H PRLH0 PPG0 reload register H ch.0 R/W XXXX X X X X B
H PRLL0 PPG0 reload register L ch.0 R/W
8/16-bit PPG
timer 0
XXXXXXXXB
(Continued)
B
B
B
B
B
B
B
24
MB90570 Series
Address
register
Register name
name
Abbreviated
000042
H PRLL1 PPG1 reload register L ch.1 R/W
000043H PRLH1 PPG1 reload register H ch.1 R/W XX X X X X XX B 000044H PPGC0
000045H PPGC1
000046H PPGOE
PPG0 operating mode control register ch.0
PPG1 operating mode control register ch.1
PPG0 and 1 output control registers ch.0 and ch.1
000047H (Disabled) 000048
H SMCSL0
000049H SMCSH0
Serial mode control lower status register 0
Serial mode control upper status
register 0 00004AH SDR0 Serial data register 0 R/W XXXXXXXX B 00004BH (Disabled)
00004C
H SMCSL1
00004DH SMCSH1
Serial mode control lower status
register 1
Serial mode control upper status
register 1 00004EH SDR1 Serial data register 1 R/W XXXXXXXX B 00004FH (Disabled) 000050
H
IPCP0 ICU data register ch.0 R
000051H XXXXXXXXB 000052H
IPCP1 ICU data register ch.1 R
000053H XXXXXXXXB 000054H ICS01 ICU control status register R/W 0 0 0 0 0 0 0 0 B 000055H (Disabled) 000056
H
TCDT Free run timer data register R/W
000057H 00000000B 000058H TCCS Free run timer control status register R/W 0 0 0 0 0 0 0 0 B 000059H (Disabled) 00005A
H
OCCP0 OCU compare register ch.0 R/W
00005BH XXXXXXXXB
00005CH
OCCP1 OCU compare register ch.1 R/W
00005DH XXXXXXXXB
00005EH
OCCP2 OCU compare register ch.2 R/W
00005FH XXXXXXXXB
Read/
write
Resource name Initial value
8/16-bit PPG
XXXXXXXXB
timer 1
R/W
R/W
R/W
R/W
8/16-bit PPG
timer 0
8/16-bit PPG
timer 1
8/16-bit PPG
timer 0, 1
0X000XX1B
0X000001
000000XXB
––––0000B
Extended I/O
R/W 00000010
R/W
serial interface 0
––––0000B
Extended I/O
R/W 00000010B
serial interface 1
XXXXXXXX
16-bit I/O timer
(input capture
XXXXXXXX
(ICU) section)
16-bit I/O timer
00000000
(16-bit free run
timer section)
XXXXXXXX
16-bit I/O timer
XXXXXXXX
(output compare
(OCU) section)
XXXXXXXX
(Continued)
B
B
B
B
B
B
B
B
25
MB90570 Series
Address
register
Register name
name
Abbreviated
000060
H
OCCP3 OCU compare register ch.3 R/W
000061H XXXXXXXXB 000062H OCS0 OCU control status register ch.0 R/W 0 0 0 0 – – 0 0 B 000063H OCS1 OCU control status register ch.1 R/W – – – 0 0 0 0 0 B 000064H OCS2 OCU control status register ch.2 R/W 0 0 0 0 – – 0 0 B 000065H OCS3 OCU control status register ch.3 R/W – – – 0 0 0 0 0 B 000066H
(Disabled)
000067 000068H IBSR 000069H IBCR 00006AH ICCR 00006BH IADR
00006CH IDAR
H
2
I
C bus status register
2
I
C bus control register
2
I
C bus clock control register
2
I
C bus address register
2
I
C bus data register
00006DH
(Disabled)
00006E
00006FH ROMM
H
ROM mirroring function selection
register 000070H UDCR0 Up/down count register 0 R
000071H UDCR1 Up/down count register 1 R 0 0 0 0 0 0 0 0 B 000072H RCR0 Reload compare register 0 W 0 0 0 0 0 0 0 0 B 000073H RCR1 Reload compare register 1 W 0 0 0 0 0 0 0 0 B 000074H CSR0 Counter status register 0 R/W 0 0 0 0 0 0 0 0 B 000075H
(Reserved area)*
000076H CCRL0
Counter control register 0 R/W 000077H CCRH0 0 0 0 0 0 0 0 0 B
000078H CSR1 Counter status register 1 R/W 0 0 0 0 0 0 0 0 B 000079H
(Reserved area)*
00007AH CCRL1
Counter control register 1 R/W 00007BH CCRH1 – 0 0 0 0 0 0 0 B
00007CH SMCSL2
00007DH SMCSH2
Serial mode control lower status
register 2
Serial mode control higher status
register 2 00007EH SDR2 Serial data register 2 R/W XXXXXXXX B 00007FH (Disabled)
Read/
write
Resource name Initial value
XXXXXXXX
16-bit I/O timer
(output compare
(OCU) section)
R
00000000 R/W 00000000 R/W ––0XXXXX
2
C interface
I R/W –XXXXXXX R/W XXXXXXXX
ROM mirroring
W
function
–––––––1
selection module
00000000B
8/16-bit up/down
counter/timer
3
–0000000B
8/16-bit up/down
counter/timer
3
8/16-bit up/down
–0000000B
counter/timer
R/W
––––0000B
Extended I/O
R/W 00000010
serial interface 2
(Continued)
B
B
B
B
B
B
B
B
26
MB90570 Series
Address
register
Register name
name
Abbreviated
000080
H CSCR0 Chip selection control register 0 R/W
000081H CSCR1 Chip selection control register 1 R/W – – – – 0 0 0 0 B 000082H CSCR2 Chip selection control register 2 R/W – – – – 0 0 0 0 B 000083H CSCR3 Chip selection control register 3 R/W – – – – 0 0 0 0 B 000084H CSCR4 Chip selection control register 4 R/W – – – – 0 0 0 0 B 000085H CSCR5 Chip selection control register 5 R/W – – – – 0 0 0 0 B 000086H CSCR6 Chip selection control register 6 R/W – – – – 0 0 0 0 B 000087H
to
00008B
00008C
H
H RDR0
00008DH RDR1
00008EH RDR6
Port 0 input pull-up resistor setup register
Port 1 input pull-up resistor setup register
Port 6 input pull-up resistor setup register
(Disabled)
00008FH
to
(Disabled)
00009DH
00009E
H PACSR
00009FH DIRR
0000A0H LPMCR
Program address detection control status register
Delayed interrupt factor generation/ cancellation register
Low-power consumption mode
control register 0000A1H CKSCR Clock select register R/W 1 1 1 1 1 1 0 0 B 0000A2H
to
0000A4 0000A5
H
H ARSR
Automatic ready function select
register
(Disabled)
0000A6H HACR Upper address control register W 0 0 0 0 0 0 0 0 B 0000A7H ECSR Bus control signal select register W 0 0 0 0 0 0 0 0 B 0000A8H WDTC Watchdog timer control register R/W Watchdog timer X X X XXXXX B 0000A9H TBTC Timebase timer control register R/W Timebase timer 1 – – 0 0 1 0 0 B
0000AAH WTC Clock timer control register R/W Clock timer 1 X 0 0 0 0 0 0 B
Read/
write
Resource name Initial value
––––0000B
Chip select
output
R/W Port 0 00000000
R/W Port 1 00000000B
R/W Port 6 00000000B
Address match
R/W
detection
00000000
function Delayed
R/W
interrupt
generation
–––––––0B
module
R/W
Low-power
00011000B
consumption
(standby) mode
W
0011––00B
External bus pin
(Continued)
B
B
27
MB90570 Series
(Continued)
Address
0000AB
to
0000AD
0000AE
Abbreviated
register
Register name
name
H
(Disabled)
H
H FMCS Flash control register R/W Flash interface 0 0 0 X 0 XX 0 B
Read/
write
Resource name Initial value
0000AFH (Disabled)
0000B0
H ICR00 Interrupt control register 00 R/W
00000111B 0000B1H ICR01 Interrupt control register 01 R/W 0 0 0 0 0 1 1 1 B 0000B2H ICR02 Interrupt control register 02 R/W 0 0 0 0 0 1 1 1 B 0000B3H ICR03 Interrupt control register 03 R/W 0 0 0 0 0 1 1 1 B 0000B4H ICR04 Interrupt control register 04 R/W 0 0 0 0 0 1 1 1 B 0000B5H ICR05 Interrupt control register 05 R/W 0 0 0 0 0 1 1 1 B 0000B6H ICR06 Interrupt control register 06 R/W 0 0 0 0 0 1 1 1 B 0000B7H ICR07 Interrupt control register 07 R/W 0 0 0 0 0 1 1 1 B 0000B8H ICR08 Interrupt control register 08 R/W 0 0 0 0 0 1 1 1 B
Interrupt
controller
0000B9H ICR09 Interrupt control register 09 R/W 0 0 0 0 0 1 1 1 B
0000BAH ICR10 Interrupt control register 10 R/W 0 0 0 0 0 1 1 1 B
0000BBH ICR11 Interrupt control register 11 R/W 0 0 0 0 0 1 1 1 B 0000BCH ICR12 Interrupt control register 12 R/W 0 0 0 0 0 1 1 1 B 0000BDH ICR13 Interrupt control register 13 R/W 0 0 0 0 0 1 1 1 B
0000BEH ICR14 Interrupt control register 14 R/W 0 0 0 0 0 1 1 1 B
0000BFH ICR15 Interrupt control register 15 R/W 0 0 0 0 0 1 1 1 B
0000C0H
to
0000FF
(External area)*
H
1
000100H
to
000###
(RAM area)*
H
2
000###H
to
(Reserved area)*
3
001FEFH
001FF0H 001FF1H Program address detection register 1 R/W XXXXX X X X B
PADR0
001FF2H Program address detection register 2 R/W XXXXX X X X B
Program address detection register 0 R/W
Address match
XXXXXXXX
detection
001FF3H 001FF4H Program address detection register 4 R/W XXXXX X X X B
PADR1
Program address detection register 3 R/W X X X X X XXX
function
001FF5H Program address detection register 5 R/W XXXXX X X X B 001FF6H
to
001FFF
H
(Reserved area)
B
B
28
Descriptions for read/write
R/W: Readable and writable R: Read only W: Write only
Descriptions for initial value
0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. – : This bit is unused. The initial value is undefined.
MB90570 Series
*1: This area is the only external access area having an address of 0000FF
area is handled as that to external I/O area. *2: For details of the RAM area, see “ MEMORY MAP”. *3: The reserved area is disabled because it is used in the system.
Notes: • For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an
initial value. Note that the values are different from reading results. For LPMCR/CKSCR/WDTC , there are cases where initialization is performed or not performed, depending on the types of the reset. However initial value for resets that initializes the value are listed.
• The addresses following 0000FF
• Boundary ####H between the RAM area and the reserved area varies with the product model.
H are reserved. No external bus access signal is generated.
H or lower . An access oper ation to this
29
MB90570 Series
INTERRUPT FA CTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt source
2
OS
EI
support
Interrupt vector Interrupt control register
Number Address ICR Address
Reset × # 08 FFFFDC INT9 instruction × # 09 FFFFD8 Exception × # 10 FFFFD4 8/10-bit A/D converter # 11 FFFFD0
Input capture 0 (ICU) include # 12 FFFFCCH DTP0 (external interrupt 0) # 13 FFFFC8H Input capture 1 (ICU) include # 14 FFFFC4H Output compare 0 (OCU) match # 15 FFFFC0H Output compare 1 (OCU) match # 16 FFFFBCH Output compare 2 (OCU) match # 17 FFFFB8H Output compare 3 (OCU) match # 18 FFFFB4H Extended I/O serial interface 0 # 19 FFFFB0H
16-bit free run timer × # 20 FFFFACH Extended I/O serial interface 1 # 21 FFFFA8H Clock timer × # 22 FFFFA4H
Priority
H ——High H —— H ——
H
ICR00 0000B0H
ICR01 0000B1H
ICR02 0000B2H
ICR03 0000B3H
ICR04 0000B4H
ICR05 0000B5H
Extended I/O serial interface 2 # 23 FFFFA0H
ICR06 0000B6H
DTP1 (external interrupt 1) # 24 FFFF9CH DTP2/DTP3 (external interrupt 2/
external interrupt 3)
# 25 FFFF98
H
ICR07 0000B7H
8/16-bit PPG timer 0 counter borrow
DTP4/DTP5 (external interrupt 4/ external interrupt 5)
× # 26 FFFF94
# 27 FFFF90
H
H
ICR08 0000B8H
8/16-bit PPG timer 1 counter borrow
8/16-bit up/down counter/timer 0 borrow/overflow/inversion
× # 28 FFFF8C
# 29 FFFF88
H
H
ICR09 0000B9H
8/16-bit up/down counter/timer 0 compare match
8/16-bit up/down counter/timer 1 borrow/overflow/inversion
# 30 FFFF84
# 31 FFFF80
H
H
0000BAH
ICR10
8/16-bit up/down counter/timer 1 compare match
# 32 FFFF7C
H 0000BAH
DTP6 (external interrupt 6) # 33 FFFF78H
ICR11 0000BBH
Timebase timer × # 34 FFFF74H Low
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(Continued)
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