The MB90550A/550B series is a line of general-purpose, high-performance, 16-bit microcontrollers designed for
applications which require high-speed real-time processing, such as industrial machines, OA equipment, and
process control systems.
While inheriting the AT architecture of the F
incorporates additional instructions for high-level languages , supports extended addressing modes, and contains
enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation
instructions. In addition, the MB90550A/550B has an on-chip 32-bit accumulator which enables processing of
long-word data.
MB90552B and MB90553B are radiation noise decreased type. There are no change in the functional specification.
2
*: F
MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
2
MC*-8 family, the instruction set for the MB90550A/550B series
FEATURES
■■■■
• Minimum instruction execution time: 62.5 ns (at oscillation of 4 MHz, × four times the PLL clock)
• Maximum memory space: 16 Mbytes
• Instruction set optimized for controller applications
Supported data types: Bit, byte, word and long word
Typical addressing mode: 23 types
Enhanced precision calculation realized by 32-bit accumulator
Enhanced signed multiplication/division instruction and RETI instruction functions
PACKAGES
■■■■
100-pin plastic QFP100-pin plastic LQFP
(FPT-100P-M06)(FPT-100P-M05)
(Continued)
MB90550A/550B Series
(Continued)
• Instruction set designed for high level language (C) and multi-task operations
Adoption of system stack pointer
Symmetrical instruction set and barrel shift instructions
• Integrated address match detection function (for two address pointers)
(at oscillation of 4 MHz, minimum value)
ProcessCMOS
Power supply volt-
age for operation*
4.5 V to 5.5 V
*:Varies with conditions such as the operating frequency. (See section “■ ELECTRICAL CHARA CTERISTICS”)
Assurance for the MB90V550A is given only for operation with a tool at a power voltage of 4.5 V to 5.5 V, an
operating temperature of 0°C to +25°C, and an operating frequency of 1 MHz to 16 MHz.
PACKAGE AND CORRESPONDING PRODUCTS
■■■■
Package
MB90552A
MB90552B
MB90553A
MB90553B
MB90F553AMB90P553A
FPT-100P-M05×
FPT-100P-M06
: Available ×: Not available
Note:For more info rmation about each package, see section “■ PACKAGE DIMENSIONS”
DIFFERENCES AMONG PRODUCTS
■■■■
Memory Size
In evaluation with an evaluation product, note the difference between the evaluation product and the product
actually used. The following items must be taken into consideration.
• The MB90V550A does not have an internal ROM. However, operations equivalent to those performed by a
chip with an internal ROM can be evaluated b y using a dedicated dev elopment tool, enabling selection of ROM
size by setting the development tool.
• In the MB90V550A, images from FF4000
H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH
are mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.)
• In the MB90F553A/553A/553B/552A/552B, images from FF4000
A pull-up resistor can be added (RD07 to RD00 = 1) by using
the pull-up resistor setting register (RDR0).
D07 to D00 = 1: Disabled when the port is set for output.
Serve as lower data I/O/lower address output (AD00 to AD07)
pins in the external bus mode.
General-purpose I/O ports.
A pull-up resistor can be added (RD17 to RD10 = 1) by using the
pull-up resistor setting register (RDR1).
D17 to D10 = 1: Disabled when the port is set for output.
Serve as upper data I/O/middle address output (AD08 to AD15)
pins in the 16-bit bus-width, external bus mode.
General-purpose I/O ports.
This function is enabled either in single-chip mode or with the
external address output control register set to “Port”.
External address bus A16 to A23 output pins.
This function is enabled in an external-bus enabled mode with
the external address output register set to “Address”.
General-purpose I/O port.
This function is enabled in single-chip mode.
Address latch enable output pin.
This function is enabled in an external-bus enabled mode.
108
1210
1311
P31
RD
P32
WRL
P33
WRH
E
(CMOS)
E
(CMOS)
E
(CMOS)
General-purpose I/O port.
This function is enabled in single-chip mode.
Read strobe output pin for the data bus.
This function is enabled in an external-bus enabled mode.
General-purpose I/O port.
This function is enabled in single-chip mode.
Write strobe output pin for the lower eight bits of the data bus.
This function is enabled in an external-bus enabled mode.
General-purpose I/O port.
This function is enabled in single-chip mode.
Write strobe output pin for the upper eight bits of the data bus.
This function is enabled in an external-bus enabled mode.
(Continued)
7
MB90550A/550B Series
Pin no.
QFPLQFP
1412
1513
1614
1715
1816
Pin nameCircuit typeFunction
P34
E
(CMOS)
HRQ
P35
E
(CMOS)
HAK
P36
E
(CMOS)
RDY
P37
E
(CMOS)
CLK
P40
F
(CMOS/H)
SCK
General-purpose I/O port.
This function is enabled in single-chip mode
Hold request input pin.
This function is enabled in an external-bus enabled mode.
General-purpose I/O port.
This function is enabled in single-chip mode.
Hold acknowledge output pin.
This function is enabled in an external-bus enabled mode.
General-purpose I/O port.
This function is enabled in single-chip mode.
Ready signal input pin.
This function is enabled in an external-bus enabled mode.
General-purpose I/O port.
This function is enabled in single-chip mode.
CLK output pin.
This function is enabled in an external-bus enabled mode.
General-purpose I/O port.
Serves as an open-drain output port (OD40 = 1) depending on the
setting of the open-drain control setting register (ODR4).
(D40 = 0: Disabled when the port is set for input.)
UART serial clock I/O pin.
This function is enabled with the UART clock output enabled.
1917
2018
2119
P41
SOT
P42
SIN
P43
SCK1
F
(CMOS/H)
F
(CMOS/H)
F
(CMOS/H)
General-purpose I/O port.
Serves as an open-drain output port (OD41 = 1) depending on the
setting of the open-drain control setting register (ODR4).
(D41 = 0: Disabled when the port is set for input.)
UART serial data output pin.
This function is enabled with the UART serial data output enabled.
General-purpose I/O port.
Serves as an open-drain output port (OD42 = 1) depending on the
setting of the open-drain control setting register (ODR4).
(D42 = 0: Disabled when the port is set for input.)
UART serial data input pin. Since this input is used as required while
the UART is operating for input, the output by any other function
must be off unless used intentionally.
General-purpose I/O port.
Serves as an open-drain output port (OD43 = 1) depending on the
setting of the open-drain control setting register (ODR4).
(D43 = 0: Disabled when the port is set for input.)
Extended I/O serial clock I/O pin. This function is enabled with the
extended I/O serial clock output enabled.
(Continued)
8
MB90550A/550B Series
Pin no.
QFPLQFP
2220
2422
2523
Pin nameCircuit typeFunction
General-purpose I/O port.
P44
F
Serves as an open-drain output port (OD44 = 1) depending on
the setting of the open-drain control setting register (ODR4).
(D44 = 0: Disabled when the port is set for input.)
(CMOS/H)
Extended I/O serial data output pin.
SOT1
This function is enabled with the extended I/O serial data output
enabled.
General-purpose I/O port.
P45
F
(CMOS/H)
SIN1
Serves as an open-drain output port (OD45 = 1) depending on
the setting of the open-drain control setting register (ODR4).
(D45 = 0: Disabled when the port is set for input.)
Extended I/O serial data input pin.
Since this input is used as required while the extended I/O serial
interface is operating for input, the output by any other function
must be off unless used intentionally.
General-purpose I/O port.
P46
F
(CMOS/H)
ADTG
Serves as an open-drain output port (OD46 = 1) depending on
the setting of the open-drain control setting register (ODR4).
(D46 = 0: Disabled when the port is set for input.)
A/D converter external trigger input pin.
Since this input is used as required while the A/D converter is operating for input, the output by any other function must be off unless used intentionally.
P47
2624
F
(CMOS/H)
SCK0
2725C—
P50
SDA0
2826
G
(NchOD/H)
SOT0
General-purpose I/O port.
Serves as an open-drain output port (OD47 = 1) depending on
the setting of the open-drain control setting register (ODR4).
D47 = 0: Disabled when the port is set for input.
Extended I/O serial clock I/O pin. This function is enabled with
the extended I/O serial clock output enabled.
Capacitance pin for regulating the power supply.
Connect an external ceramic capacitor of about 0.1 µF.
N-channel open-drain I/O port.
2
I
C interface data I/O pin.
This function is enabled with the I
2
C interface enabled for
operation.
While the I
2
C interface is operating, place the port output in the
Hi-Z state (PDR = 1).
Extended I/O serial data output pin.
This function is enabled with the extended I/O serial data output
enabled.
(Continued)
9
MB90550A/550B Series
Pin no.
QFPLQFP
2927
30,3228,30
31,3329,31
38 to 41,
43 to 46
36 to 39,
41 to 44
Pin nameCircuit typeFunction
P51
SCL0
G
(NchOD/H)
N-channel open-drain I/O port.
2
I
C interface clock I/O pin. This function is enabled with the
2
I
C interface enabled for operation.
While the I
2
C interface is operating, place the port output in
the Hi-Z state (PDR = 1).
Extended I/O serial data input pin.
SIN0
Since this input is used as required while the extended I/O
serial interface is operating for input, the output by any other
function must be off unless used intentionally.
P52,P54
SDA1,SDA2
G
(NchOD/H)
N-channel open-drain I/O ports.
2
C interface data I/O pins. This function is enabled with the
I
2
I
C interface enabled for operation.
While the I
2
C interface is operating, place the port output in
the Hi-Z state (PDR = 1).
P53,P55
SCL1,SCL2
G
(NchOD/H)
N-channel open-drain I/O ports.
2
C interface clock I/O pins. This function is enabled with the
I
2
I
C interface enabled for operation.
While the I
2
C interface is operating, place the port output in
the Hi-Z state (PDR = 1).
P60 to P67
AN0 to AN7
H
(CMOS/H)
General-purpose I/O ports.
A/D converter analog input pin. This function is enabled with
Since this input is used as required while the reload timer is
operating for input, the output by any other function must be
off unless used intentionally.
P82,P83
General-purpose I/O ports.
J
TOT0,TOT1
P84 to P87
IN0 to IN3
(CMOS/H)
J
(CMOS/H)
Reload timer output pins.This function is enabled with reroad
timer output enabled.
Since this input is used as required while the input capture
unit is operating for input, the output by any other function
must be off unless used intentionally.
P90,P91
OUT0,OUT1Output compare event output pins.
J
(CMOS/H)
General-purpose I/O ports.
(Continued)
10
(Continued)
Pin no.
QFPLQFP
MB90550A/550B Series
Pin nameCircuit typeFunction
P92 to P97
69 to 74 67 to 72
PPG0 to
PPG5
PA0,PA1
75,7673,74
OUT2,OUT3Output compare event output pins.
78,7976,77PA2,PA3
PA4
8078
CKOTServes as the CKOT output while the CKOT is operating.
3432AV
J
(CMOS/H)
J
(CMOS/H)
J
(CMOS/H)
J
(CMOS/H)
CCA/D converter power-supply pin.
General-purpose I/O ports.
PPG output pins. This function is enabled with the PPG output
3533AVRHA/D converter external reference voltage source pin.
3634AVRLA/D converter external reference voltage source pin.
3735AV
49,5047,48MD0,MD1C
SSA/D converter power-supply pin.
Operation mode setting input pins.
Connect these pins directly to Vcc or Vss.
Operation mode setting input pin.
K
5149MD2
C
Connect this pin directly to Vcc or Vss. (MB90552A/552B/553A/
553B/V550A)
Operation mode setting input pin.
Connect this pin directly to Vcc or Vss. (MB90P553A/F553A)
23,8421,82V
11,42,819,40,
79
CCPower (5 V) input pins.
V
SSPower (0 V) input pins.
11
MB90550A/550B Series
I/O CIRCUIT TYPE
■■■■
TypeCircuitRemarks
Clock input
X1
• 3 MHz to 32 MHz
• Oscillator recovery resistor approx. 1MΩ
A
X0
HARD,SOFT
STANDBY
CONTROL
• CMOS level hysteresis input
• Pull-up resistor provided
Resistor: About 50 kΩ
B
• CMOS level hysteresis input
C
Pull-up resistor control
• CMOS level output
• CMOS level input
• Standby control provided
Digital output
• Input pull-up resistor control provided
Resistor: About 50 kΩ
12
Digital output
D
Digital input
HARD,SOFT
STANDBY
CONTROL
(Continued)
MB90550A/550B Series
TypeCircuitRemarks
• CMOS level output
Digital output
Digital output
E
Digital input
HARD,SOFT
STANDBY
CONTROL
• CMOS level input
• Standby control provided
Open- drain
control
signal
Digital input
• CMOS level output
• CMOS level hysteresis input
• Open-drain control provided
F
Digital input
HARD,SOFT
STANDBY
CONTROL
• N-channel open-drain output
• CMOS level hysteresis input
Digital output
• Standby control provided
Note: Unlike normal CMOS I/O pins, this
pin is not provided with any P-channel
G
Digital input
transistor. Therefore the pin does not allow
a current to flow to the Vcc side even when
applied with a voltage from an external
HARD,SOFT
STANDBY
CONTROL
device with the IC’s power supply left off.
• CMOS level output
Digital output
• CMOS level hysteresis input
• Standby control provided
• Analog input
Digital output
H
HARD,SOFT
STANDBY
CONTROL
A/D
DISABLE
Analog input
Digital input
(Continued)
13
MB90550A/550B Series
(Continued)
TypeCircuitRemarks
• CMOS level output
Digital output
Digital output
I
Digital input
HARD
STANDBY
CONTROL
Digital output
• CMOS level hysteresis input
• Standby control provided
• CMOS level output
• CMOS level hysteresis input
• Standby control provided
Digital output
J
Digital input
HARD,SOFT
STANDBY
CONTROL
• CMOS level hysteresis input
• Pull-up resistor provided
Resistor: About 50 kΩ
K
14
MB90550A/550B Series
HANDLING DEVICES
■■■■
1.Preventing Latchup
CMOS ICs may cause latchup in the following situations:
• When a voltage higher than Vcc or lower than Vss is applied to input or output pins.
• When a voltage exceeding the rating is applied between Vcc and Vss.
• When AVcc power is supplied prior to the Vcc voltage.
If latchup occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the
device. Use meticulous care not to let it occur.
For the same reason, also be careful not to let the analog power-supply v oltage e xceed the digital pow er-supply
voltage.
2.Handling unused input pins
Leaving unused input pins open ma y cause a malfunction or latch-up which leads to fatal damage to the de vice .
Therefore they must be pulled up or pulled down through at least 2 kΩ resistance. Also, unused input/output
pins should be left open in output state or handled in the same way as unused input pins.
3.Notes on Using External Clock
In using the external clock, drive X0 pin only and leave X1 pin unconnected.
Using external clock
•
MB90550A/550B series
X0
Open
X1
4.Power Supply Pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to
avoid abnormal operations including latch-up. However, the pins should be connected to external power and
ground lines to lower the electro-magnetic emission level and abnormal operation of strobe signals caused by
the rise in the ground level, and to conform to the total current rating.
Make sure to connect V
It is recommended that a bypass capacitor of around 0.1 µF be placed between the V
device.
Using
•
power supply pins
CC and VSS pins via lowest impedance to power lines.
V
CC
V
SS
V
SS
MB90550A/550B
V
V
CC
series
CC
CC and VSS pins near the
V
CC
V
SS
V
SS
V
V
SS
CC
15
MB90550A/550B Series
5.Crystal Oscillator Circuit
Noises around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via
shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure
that lines of oscillation circuit not cross the lines of other circuits.
A printed circuit board artwor k surrounding the X0 and X1 pins with grand area for stabilizing the operation is
highly recommended.
6.Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVRL) and
analog inputs (AN0 to AN7) after turning-on the digital power supply (V
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage does not exceed AVRH or AV
CC (turning on/off the analog and digital power supplies simulta-
neously is acceptable).
7.Connection of Unused Pins of A/D Converter
Connect unused pin of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.
8.N.C. Pin
The N.C. (internally connected) pin must be opened for use.
CC).
9.Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
µs or more.
10. Indeterminate outputs from ports 0 and 1
The outputs from ports 0 and 1 become indeterminate during oscillation setting time of step-down circuit (during
a power-on reset) after the power is turned on. (MB90552A, MB90552B, MB90553A, MB90553B , MB90F553A,
MB90V550A)
The series without built-in step-down circuit has no oscillation setting time of step-down circuit, so outputs should
not become indeterminate. (MB90P553A)
Timing chart of indeterminate outputs from ports 0 and 1
2
VCC (power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
Oscillation setting time *
Step-down circuit setting time *
1
KA (internal operating clock A) signal
KB (internal operating clock B) signal
PORT (port output) signal
Period of indeterminate
*1: Step-down circuit setting time 217/oscillation clock frequency (oscillation clock frequency of 16 MHz: 8.19 ms)
*2: Oscillation setting time2
18
/oscillation clock frequency (oscillation clock frequency of 16 MHz: 16.38 ms)
16
MB90550A/550B Series
11. Initialization
In the device, there are internal registers which is initialized only by a po wer-on reset. To initialize these registers
turning on the power again.
12. Return from standby state
If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may
fail to return from the standby state. In this case, reset the de vice via the external reset pin to return to the normal
state.
13. Precautions for Use of ’DIV A, Ri,’ and ’DIVW A, Ri’ Instructions
The signed multiplication-division instructions ’DIV A, Ri,’ and ’DIVW A, RWi’ should be used when the corresponding bank registers (DTB, ADB, USB , SSB) are set to value ’00h.’ If the corresponding bank registers (DTB,
ADB, USB, SSB) are set to a v alue other than ’00h,’ the remainder obtained after the ex ecution of the instruction
will not be placed in the instruction operand register.
14. Using of REALOS
The use of EI2OS is not possible the REALOS real time operating system.
17
MB90550A/550B Series
BLOCK DIAGRAM
■■■■
X0, X1
RST
HST
P00 to P07/
AD00 to AD07
P10 to P17/
AD08 to AD15
P20 to P27/
A16 to A23
P30/ALE
P31/RD
P32/WRL
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SCK
P41/SOT
P42/SIN
Clock control
4
circuit*
RAM
ROM
Port 0
Port 1
Port 2
Port 3
Port 4
Communication prescaler
UART
CPU
Core of F2MC-16LX
family
F
F
M
C
16
L
X
B
U
S
Interrupt controller
Port A
Clock monitor function
Port 9
8/16 PPG × 3c h
I/O timer
16-bit output compare
unit x 4 channels
16-bit input capture
unit x 4 channels
16-bit free-run timer
16-bit reload timer
x 2 channels
Port 8
CKOT/PA4
PA2, A3
OUT2, OUT3/
PA0, A1
PPG5/P97
PPG4/P96
PPG3/P95
PPG2/P94
PPG1/P93
PPG0/P92
OUT0, OUT1/
P90, P91
IN0 to IN3/
P84 to P87
TOT0, TOT1/
P82, P83
TIN0, TIN1/
P80, P81
18
P43/SCK1
P44/SOT1
P45/SIN1
P46/ADTG
P47/SCK0
P50/SDA0/SOT0
P51/SCL0/SIN0
P52/SDA1
P53/SCL1
P54/SDA2
P55/SCL2
Extended I/O
serial interface 1
Extended I/O
serial interface 0
I2C interface 0
2
C interface 1
I
Port 5
Port 7
External interrupt
A/D converter
(8/10 bits)
IRQ0 to IRQ7/
P70 to P77
AV
AVRH, AVRL
AV
AN0 to AN7/
P60 to P67
Port 6
pecifications of evaluation model
*: S
(MB90V550A)
Contains no internal ROM.
Contains 6 KB of internal RAM.
Contains the same internal resources as the
other products in the MB90550A/550B series.
CC
SS
MB90550A/550B Series
Note: The clock control circuit contains a watchdog timer, time-base timer, and a low power consumption control
circuit.
P00 to P07 (8 pins): Input pull-up resistor setting register provided
P10 to P17 (8 pins): Input pull-up resistor setting register provided
P40 to P47 (8 pins): Open-drain control setting register provided
P50 to P55 (6 pins): N-channel open drain
Ports 0, 1, 2, 3, 4, 6, 7, 8, 9, and A are CMOS level input/output ports.
19
MB90550A/550B Series
MEMORY MAP
■■■■
The ROM data of bank FF is reflected in the upper address of bank 00, realizing effectiv e use of the C compiler
small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 are assigned to the same address,
enabling reference of the table on the ROM without stating “far”.
For e xample, if an attempt has been made to access 00C000
H, the contents of the ROM at FFC000H are accessed.
Since the ROM area of the FF bank exceeds 48 Kb ytes , the whole area cannot be reflected in the image f or the
00 bank. The ROM data at FF4000
Thus, it is recommended that the ROM data table be stored in the area of FF4000
H to FFFFFFH looks, therefore , as if it were the image for 004000H to 00FFFFH.
Dual 16-bit register used for storing results of calculation, etc. The two 16-bit
registers can be combined and used as a 32-bit register.
: User stack pointer (USP)
The 16-bit pointer indicating a user stack address.
: System stack pointer (SSP)
The 16-bit pointer indicating the status of the system stack address.
: Processor status (PS)
The 16-bit register indicating the system status.
: Program counter (PC)
The 16-bit register indicating storing location of the current instruction code.
: Direct page register (DPR)
The 8-bit register indicating bits 8 through 15 of the operand address in the short
direct addressing mode.
: Program bank register (PCB)
The 8-bit register indicating the program space.
: Data bank register (DTB)
The 8-bit register indicating the data space.
: User stack bank register (USB)
The 8-bit register indicating the user stack space.
32 bit
16 bit
SSB
ADB
8 bit
: System stack bank register (SSB)
The 8-bit register indicating the system stack space.
: Additional data bank register (ADB)
The 8-bit register indicating the additional data space.
21
MB90550A/550B Series
I/O MAP
■■■■
AddressRegister name
00
HPort 0 data register PDR0R/WPort 0
Abbreviated
register name
Read/writeResource nameInitial value
01HPort 1 data register PDR1R/WPort 1
02HPort 2 data register PDR2R/WPort 2
03HPort 3 data register PDR3R/WPort 3
04HPort 4 data register PDR4R/WPort 4
05HPort 5 data register PDR5R/WPort 5
06HPort 6 data register PDR6R/WPort 6
07HPort 7 data register PDR7R/WPort 7
08HPort 8 data register PDR8R/WPort 8
09HPort 9 data register PDR9R/WPort 9
0AHPort A data register PDRAR/WPort A
0BH to
0F
H
10
HPort 0 direction registerDDR0R/WPort 0
(Disabled)
11HPort 1 direction registerDDR1R/WPort 1
12HPort 2 direction registerDDR2R/WPort 2
13HPort 3 direction registerDDR3R/WPort 3
14HPort 4 direction registerDDR4R/WPort 4
15H
16
HPort 6 direction registerDDR6R/WPort 6
(Disabled)
17HPort 7 direction registerDDR7R/WPort 7
18HPort 8 direction registerDDR8R/WPort 8
19HPort 9 direction registerDDR9R/WPort 9
1AHPort A direction registerDDRAR/WPort A
Serial input data register /
serial output data register
SIDR/SODRR/W
23HSerial status registerSSRR/W
Port 6,
A/D converter
UART
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 10 0
XXXXXXXX
0 0 0 0 1 _ 0 0
(Continued)
MB90550A/550B Series
AddressRegister name
24
Serial mode control status
H
register 0
Abbreviated
register name
Read/writeResource nameInitial value
SMCS0
25H
Serial mode control status
register 0
26HSerial data register 0SDR0R/W
27H
28H
Clock frequency-divider control
register
Serial mode control status
register 1
CDCRR/W
SMCS1
29H
Serial mode control status
register 1
2AHSerial data register 1SDR1R/W
2BH
2C
HI
2
C bus status register 0IBSR0R
(Disabled)
2DHI2C bus control register 0IBCR0R/W
2EHI2C bus clock select register 0ICCR0R/W
2FHI2C bus address register 0IADR0R/W
30HI2C bus data register 0IDAR0R/W
31H
32
HI
2
C bus status register 1IBSR1R
(Disabled)
33HI2C bus control register 1IBCR1R/W
34HI2C bus clock select register 1ICCR1R/W
35HI2C bus address register 1IADR1R/W
36HI2C bus data register 1IDAR1R/W
37HI2C bus port select registerISELR/W
38HInterrupt/DTP enable registerENIRR/W
39HInterrupt/DTP factor registerEIRRR/W
3AH
B1HInterrupt control register 01ICR01R/W!
B2HInterrupt control register 02ICR02R/W!
B3HInterrupt control register 03ICR03R/W!
B4HInterrupt control register 04ICR04R/W!
B5HInterrupt control register 05ICR05R/W!
B6HInterrupt control register 06ICR06R/W!
B7HInterrupt control register 07ICR07R/W!
B8HInterrupt control register 08ICR08R/W!
B9HInterrupt control register 09ICR09R/W!
BAHInterrupt control register 10ICR10R/W!
BBHInterrupt control register 11ICR11R/W!
BCHInterrupt control register 12ICR12R/W!
BDHInterrupt control register 13ICR13R/W!
BEHInterrupt control register 14ICR14R/W!
BFHInterrupt control register 15ICR15R/W!
• Initial value representations
0: Initial value of 0
1: Initial value of 1
X: Initial value undefined
_: Initial value undefined (none)
• Addresses that follow 00FFH are a reserved area.
• The boundary #
H between the RAM and reserved areas is different depending on each product.
PADR0
PADR1
(Reserved area)
R/W
R/W
R/W
R/W
R/W
R/W
Address match
detection function
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Note : For writable bits, the initial value column contains the initial value to which the bit is initialized at a reset.
Notice that it is not the value read from the bit.
The LPMCR, CKSCR, and WDTC registers may be initialized or not at a reset, depending on the type of the
reset. Their initial values in the above list are those to which the registers are initialized, of course.
“R/W!” in the access column indicates that the register contains read-only or write-only bits.
If a read-modify-write instruction (such as a bit setting instruction) is used to access a register marked “R/
W!” “R/W*”, or “W” in the access column, the bit focused on by the instruction is set to the desired v alue but
a malfunction occurs if the other bits contains a write-only bit. Do not use such instructions to access those
registers.
:The interrupt request flag is cleared by the EI
:The interrupt request flag is cleared by the EI
×
::The interrupt request flag is not cleared by the EI
2
2
Interrupt vectorsInterrupt control registers
NumberAddressICRAddress
OS interrupt clear signal. The stop request is available.
OS interrupt clear signal.
2
OS interrupt clear signal.
H——
H——
H——
H
ICR000000B0H
ICR010000B1H
ICR020000B2H
ICR030000B3H
ICR040000B4H
ICR050000B5H
ICR060000B6H
ICR070000B7H
ICR080000B8H
ICR090000B9H
ICR100000BAH
ICR110000BBH
ICR120000BCH
H
H
ICR130000BDH
ICR140000BEH
ICR150000BFH
29
MB90550A/550B Series
2
Note: On using the EI
OS Function with Extended I/O Serial Interface 2
If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags
are cleared by the EI
interrupt sources, therefore, the other interrupt function cannot be used. Set the interrupt request enable
bit for the relevant resource to “0” for software polling processing.
Interrupt sourceInterrupt No.Interrupt control registerResource interrupt request
Extended I/O serial interface 1# 23
16-bit free-run timer
(I/O timer) overflow
2
OS interrupt clear signal. When the EI2OS function is used for one of the two
# 24Disabled
Enabled
ICR06
30
MB90550A/550B Series
ELECTRICAL CHARACTERISTICS
■■■■
1.Absolute Maximum Ratings
(VSS = AVSS = 0.0 V)
Parameter
Symbol
Min.Max.
V
CCVSS− 0.3VSS+ 6.0V
AVCCVSS− 0.3VSS+ 6.0VVCC≥ AVCC *
Power supply voltage
AVRHVSS− 0.3VSS+ 6.0V
AVRLV
SS− 0.3VSS+ 6.0V
Input voltage VIVSS− 0.3VSS+ 6.0V*
Output voltageVOVSS− 0.3VSS+ 6.0V*
Value
UnitRemarks
AV
CC≥ AVRH ≥ AVRL
1
5
5
“L” level maximum output current *
2
IOL110mAOther than P20 to P27
IOL220mAP20 to P27
OLAV14mAOther than P20 to P27
I
“L” level average output current
I
OLAV212mAP20 to P27
“L” level total maximum output current∑IOL150mA
“L” level total average output current∑I
“H” level maximum output current
“H” level average output current *
2
*
3
“H” level total maximum output current∑I
“H” level total average output current
*1 : Be careful not to let AVcc exceed Vcc, for example, when the power supply is turned on.
*2 : The maximum output current is a peak value for a corresponding pin.
*3 : Average output current is an average current value observed for a 100 ms period for a corresponding pin.
*4 : Total average current is an average current value observed for a 100 ms period for all corresponding pins.
I and VO should not exceed VCC + 0.3V.
*5 : V
Note: Average output current = operating current × operating efficiency
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
31
MB90550A/550B Series
2.Recommended Operating Conditions
Parameter
Symbol
Value
Min.Max.
(VSS = AVSS = 0.0 V)
UnitRemarks
Normal operation (MB90F553A,
MB90P553A, MB90V550A)
Normal operation (MB90553A, MB90553B,
MB90552A, MB90552B)
Power supply voltage
V
CC
AVCC
4.55.5V
3.55.5V
3.55.5VRetains status at the time of operation stop
Smoothing capacitorC
Operating temperatureT
S0.11.0µF
A–40+85°C
*
* : Use a ceramic capacitor or a capacitor with equivqlent frequency characteristics. The smoothing capacitor to
be connected to the V
For connecting smoothing capacitor C
CC pin must have a capacitance value higher than CS.
S, see the diagram below:
• C pin connection circuit
C
C
S
VSS
AVSS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
32
3.DC Characteristics
(VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = –40 °C to +85 °C)
ParameterSymbolPin nameCondition
“H” level input
voltage
“L” level input
voltage
Open-drain output
pin voltage
“H” level output
voltage
“L” level output
voltage 1
“L” level output
voltage 2
Input leakage
current
Power supply
current *
4
Input
capacitance
Open-drain output
leakage current
Pull-up
resistance
V
IHCMOS input pin*
VIHS
V
CMOS hysteresys input pin
IHMMD pin input*
VILCMOS input pin*
VILS
V
CMOS hysteresys input pin
ILMMD pin input*
VDP50 to P55—VSS – 0.3—VSS + 6.0 V
OH
OL1
Other than
P50 to P55
Other than
P20 to P27
V
V
VOL2P20 to P27
IILAll output pins
ICC
VCC
ICCS
ICCH
Other than AVCC,
CIN
AV
SS, C, VCC and VSS
I
leakP50 to P55——0.15µA
P00 to P07 and P10
R
to P17 (In pull-up
UP
setting),RST
1
2
*
3
1
2
*
3
VCC = 4.5V,
I
OH = −4.0mA
VCC = 4.5V,
I
OL = 4.0mA
VCC = 4.5V,
I
OL = 12.0mA
VCC = 5.5V,
V
SS < VI < VCC
Internal
operation at 16
MHz
V
CC = 5.5 V
Normal operation
When data written in flash
mode
*1 : P00 to P07, P10 to P17, P20 to P27, P30 to P37
*2 : X0, HST
, RST, P40 to P47, P50 to P55, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA 0 to PA4
*3 : MD0, MD1 and MD2
*4 : The current value is preliminary value and may be subject to change for enhanced characteristics without
previous notice. The power supply current is measured with an external clock.
33
MB90550A/550B Series
4.AC Characteristics
(1) Clock Timing
Parameter
SymbolPin name
(V
CC= 5.0 V±10%, VSS= AVSS= 0.0 V, TA=−40 °C to +85 °C)
* :The frequency fluctuation rate is the maximum deviation r ate of the preset center frequency when the multiplied
PLL signal is locked.
+
α
∆f = × 100 (%)
fo
Center frequency
+α
fo
−α
−
• X0, X1 clock timing
34
X0
HCYL
t
0.8 VCC0.8 VCC
0.2 VCC
PWHPWL
tCF
0.8 VCC
0.2 VCC
tCR
• PLL operation guarantee range
Relationship between internal operating clock frequency and power supply voltage
)
5.5
V
(
C
C
V
4.5
e
g
a
t
l
o
v
3.5
y
l
p
p
u
s
r
e
w
o
P
MB90550A/550B Series
Operation guarantee range
MB90F553A, MB90P553A,
MB90V550A
PLL Operation guarantee
range
Operation guarantee range MB90553A/553B,
MB90552A/552B
1.5
381216
Internal operating clock frequency FCP (MHz)
Relationship between oscillation clock frequency and internal operating clock frequency
16
12
1.5
Multipliedby-4
9
8
4
348
Multipliedby-3
Multiplied-by-2
Oscillation clock frequency F
Multiplied-by-1
C (MHz)
Internal operating clock frequency FCP (MHz)
The AC ratings are measured for the following measurement reference voltages.
• Input signal waveform
• Output signal waveform
Not multiplied
16
Hystheresis input pin
0.8 VCC
0.2 VCC
Pins other than hystheresis input / MD input
0.7 V
CC
0.3 VCC
Output pin
2.4 V
0.8 V
35
MB90550A/550B Series
(2) Clock Output Timing
Parameter
SymbolPin name
(V
CC= 5.0 V ±10%, VSS= AVSS= 0.0 V, TA=−40 °C to +85 °C)
Value
UnitRemarks
Min.Max.
Cycle timet
CLK ↑ → CLK ↓ timet
CLK
CYC
CHCLtCP/2 − 20tCP/2+20ns
CHCL
t
2.4 V2.4 V
(3) Reset, Hardware Standby Input Timing
Parameter
Reset input timet
Hardware standby input timet
SymbolPin name
RSTLRST16 tCP—ns
HSTLHST16 tCP—ns
CLK
62.5—ns
tCYC
0.8 V
(VCC= 5.0 V ±10%, VSS= AVSS= 0.0 V, TA=−40 °C to +85 °C)
Value
UnitRemarks
Min.Max.
36
RST
HST
0.2 VCC
tRSTL, tHSTL
0.2 VCC
(4) Specification for Power-on Reset
ParameterSymbolPin name
MB90550A/550B Series
(V
CC = 5.0 V ± 10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Min.Max.
UnitRemarks
Power supply rising timet
R
0.0530ms
Power-supply start voltageVOFF—0.2V
VCC
Power-supply end voltageV
Power supply cut-off timet
Note• V
CC must be kept lower than 0.2 V before power-on.
ON2.7—V
OFF4—msDue to repeated operations
• The above values are used for creating a power-on reset.
• Some registers in the device are initialized only upon a po wer-on reset. To initialize these register , turn on
the power supply using the above values.
tR
2.7 V
VCC
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to
raise the voltage smoothly to suppress fluctuations as shown below.
In this case, change the supply voltage with the PLL clock not used. If the voltage drop is
1 V or fewer per second, however, you can use the PLL clock.
0.2 V
0.2 V
0.2 V
t
OFF
5.0 V
3.0 V
0 V
VCC
V
SS
It is recommended to keep the rising speed of
the supply voltage at 50 mV/ms or slower.
RAM data being held
37
MB90550A/550B Series
(5) Bus Read Timing
ParameterSymbolPin name
(V
CC= 5.0 V±10%, VSS= AVSS= 0.0 V, TA=−40 °C to +85 °C)
Value
UnitRemarks
Min.Max.
ALE pulse widtht
Effective address → ALE ↓ timet
ALE ↓ → address effective timet
Effective address → RD ↓ timetAVRL
Effective address → valid data
input
RD
pulse widthtRLRHRD3 tCP/2 − 20—ns
LHLLALEtCP/2 − 20—ns
ALE, A23 to A16,
AVLL
AD15 to AD00
LLAXALE, AD15 to AD00tCP/2 − 15—ns
A23 to A16,
AD15 to AD00, RD
AVDV
t
A23 to A16,
AD15 to AD00
tCP/2 − 20—ns
tCP− 15—ns
—5 tCP/2 − 60ns
RD ↓→ valid data inputtRLDVRD, AD15 to AD00—3 tCP/2 − 60ns
RD
SMP = 64 × tCP” or “tCMP = 352 × tCP” is selected when FCP =
µA
LSB
16 MHz.
*3: Specifies the power-supply current (Vcc = AVcc = AVRH = 5.0 V) when the A/D converter is inactive and the
CPU has been stopped.
Notes: • The error becomes larger relatively as |AVRH-AVRL| becomes smaller.
• Use the output impedance r
External circuit output impedance r
S of the external circuit for analog input under the following condition:
S = 10 kΩ Max.
• If the output impedance of the external circuit is too high, the analog voltage sampling time may be
insufficient.
• If you insert a DC-blocking capacitor between the e xternal circuit and the input pin, select a capacitance
that is about several thousands times the sampling capacitance C
capacity potential division with C
SH.
SH in the chip to suppress the effect of
46
MB90550A/550B Series
• Analog input circuit model
Microcontroller internal circuit
Input pin AN0
rS
RSH
CSH
Comparator
Input pin AN7
VS
External circuit
to
S/H circuit
Analog channel selector
<Recommended/reference values for device parameters>
r
S = 10 kΩor less
SH = About 3 kΩ
R
C
SH = About 25 pF
Note: Device parameter values are provided as reference values for design purposes; they
are not guaranteed.
47
MB90550A/550B Series
(2) Definitions of Terms
• Resolution: Analog transition identifiable by the A/D converter.
Analog voltage can be divided into 1024 (2
• Total error: Difference between actual and logical values. This error is the sum of an offset error, gain error,
non-linearity error and an error caused by noise.
• Linearity error: Deviation of the straight line drawn between the zero transition point (00 0000 0000 <-> 00
0000 0001) and the full-scale transition point (11 1111 1110 <-> 11 1111 1111) of the device
from actual conversion characteristics
• Differential linearity error: Deviation from the ideal input voltage required to shift output code by one LSB
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3347
Fax: +81-3-5322-3386
http://edevice.fujitsu.com/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
Korea
FUJITSU MICROELECTRONICS K OREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
FUJITSU semiconductor devices are intended for use in standard
applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.
F0101
FUJITSU LIMITED Printed in Japan
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