FUJITSU MB90540, MB90540G, MB90545, MB90545G DATA SHEET

查询MB90548供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13703-5E

16-bit Proprietary Microcontroller

CMOS

F2MC-16LX MB90540/G/545/G Series

MB90F543/F549/V540
MB90F543G(S)/F546G(S)/F548G(S)/F549G(S)/549G(S)/V540G
MB90543G(S)/547G(S)/548G(S)/F548GL(S)

DESCRIPTION

■■■■

The MB90540/545 series with FULL-CAN*1 and FLASH ROM is specially designed for automotiv e and industrial
applications. Its main features are two on board CAN Interfaces (one for MB90V545 series) , which conform to
V2.0 Part A and Part B, supporting very flexible message buffer
normal full CAN approach. The instruction set by F
family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplica­tion/division instructions, and enhanced bit manipulation instructions.The micro controller has a 32-bit accumulator
for processing long word data.The MB90540/545 series has peripheral resources of 8/10-bit A/D conver ters,
UAR T (SCI) , extended I/O serial interfaces, 8/16-bit timer, I/O timer (input capture (ICU) , output compare (OCU) ) .

2

MC-16LX CPU core inherits an AT architecture of the F2MC*

scheme and so offering more functions than a

2

*1 : Controller Area Network (CAN) -License of Robert Bosch GmbH.

2

*2 : F

MC stands for FUJITSU Flexible Microcontroller.

FEATURES

■■■■

•Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from : divided-b y-2 of oscillation or one to f our times the oscillation
Minimum instruction ex ecution time : 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock)
Subsystem Clock : 32 kHz

PACKAGES

■■■■

100-pin Plastic QFP 100-pin Plastic LQFP

(FPT-100P-M06) (FPT-100P-M05)

(Continued)

(Continued)

MB90540/540G/545/545G Series

• Instruction set to optimize controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
Enhanced signed multiplication/division instruction and RETI instruction functions
Enhanced precision calculation realized by the 32-bit accumulator

• Instruction set designed for high level language (C language) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions

• Program patch function (for two address pointers)

• Enhanced execution speed : 4-byte Instruction queue

• Enhanced interrupt function : 8 levels, 34 factors

• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI

• Embedded ROM size and types
Mask ROM : 256 Kbytes / 64 Kbytes / 128 Kbytes
Flash ROM : 128 Kbytes/256 Kbytes
Embedded RAM size : 2 Kbytes/4 Kbytes/6 Kbytes/8 Kbytes (evaluation chip)

•Flash ROM
Supports automatic programming, Embedded Algorithm TM*
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory
Erase can be performed on each block
Block protection with external programming voltage

• Low-power consumption (stand-by) mode
Sleep mode (mode in which CPU operating clock is stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Clock mode
Hardware stand-by mode

•Process

0.5 µm CMOS technology

• I/O port
General-purpose I/O ports : 81 ports

•Timer
Watchdog timer : 1 channel
8/16-bit PPG timer : 8/16-bit × 4 channels
16-bit re-load timer : 2 channels

• 16-bit I/O timer
16-bit free-run timer : 1 channel
Input capture : 8 channels
Output compare : 4 channels

• Extended I/O serial interface : 1 channel

•UART 0
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used.

2

OS)

(Continued)

2

MB90540/540G/545/545G Series

(Continued)

•UART 1
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized serial (extended I/O serial) can be used.

• External interrupt circuit (8 channels)
A module for starting an extended intelligent I/O service (EI
is triggered by an external input.

• Delayed interrupt generation module
Generates an interrupt request for switching tasks.

• 8/10-bit A/D converter (8 channels)
8/10-bit resolution can be selectively used.
Starting by an external trigger input.
Conversion time : 26.3 µs

• FULL-CAN interfaces
MB90540 series : 2 channel
MB90545 series : 1 channel
Conforming to Version 2.0 Part A and Part B
Flexible message buffering (mailbox and FIFO buffering can be mixed)

• External bus interface : Maximum address space 16 Mbytes

• Package: QFP-100, LQFP-100

2

OS) and generating an external interrupt which

* : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.

3

MB90540/540G/545/545G Series

PRODUCT LINEUP

■■■■

MB90F543/F549

Features

MB90F543G (S) /F548G (S)
MB90F549G (S) /F546G (S)

MB90F548GL(S)

CPU F
System clock

ROM

RAM

Clocks

Flash memory
MB90F543/F543G(S)/
F548G(S) / F548GL(S) :
128 K
MB90F549/F549G(S)/
F546G(S) : 256 K

MB90F548G(S)/F548GL(S):
4 Kbytes
MB90F543/F549/F543G (S) /
F549G(S) : 6 Kbytes
MB90F546G(S) : 8 Kbytes

MB90F543/F549/F543G/
F548G/F549G/F546G/F548GL
: Two clocks system
MB90F543GS/F548GS/
F549GS/F546GS/F548GLS
: One clock system

On-chip PLL clock multiplier (×1, ×2, ×3, ×4, 1/2 when PLL stop)

Minimum instruction exection time : 62.5 ns (4 MHz osc. PLL × 4)

Mask ROM :
MB90547G(S): 64 K
MB90543G(S)/548G(S):
128 K
MB90549G(S): 256 K

MB90547G(S): 2 Kbytes
MB90548G(S): 4 Kbytes
MB90543G(S)/549G(S):
6 Kbytes

MB90543G/547G/548G/
549G : Two clocks system
MB90543GS/547GS/
548GS/549GS
: One clock system

Operating voltage
range

Temperature range

MB90F543/F549: −40 °C to 85 °C

Other than MB90F543/F549: −40 °C to 105 °C

MB90543G (S) *
MB90547G (S) *

MB90548G (S)
MB90549G (S)

2

MC-16LX CPU

*5

1
1

MB90V540/V540G

External

8 Kbytes

Two clocks system*

Package QFP100, LQFP100 PGA-256
Emulator-specify

power supply

*3

 None

Full duplex double buffer

UART0

Support asynchronous/synchronous (with start/stop bit) transfer
Baud rate : 4808/5208/9615/10417/19230/38460/62500/500000 bps (asynchronous)

500 K/1 M/2 Mbps (synchronous) at System clock = 16 MHz

Full duplex double buffer
UART1
(SCI)

Asynchronous (start-stop synchronized) and CLK-synchronous communication

Baud rate : 1202/2404/4808/9615/19230/31250/38460/62500 bps (asynchronous)

62.5 K/125 K/250 K/500 K/1 M/2 Mbps (synchronous) at 6, 8, 10, 12, 16 MHz

Transfer can be started from MSB or LSB
Serial I/O

Supports internal clock synchronized transfer and external clock synchronized transfer

Supports positive-edge and nagative-edge clock synchronization

Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock = 16 MHz

10-bit or 8-bit resolution
A/D Converter

8 input channels

Conversion time : 26.3 µs (per one channel)

2

(Continued)

4

MB90540/540G/545/545G Series

(Continued)

MB90543G (S) *
MB90547G (S) *

MB90548G (S)
MB90549G (S)

1

, fsys/23, fsys/25 (fsys = System clock frequency)

2

, fsys/24, fsys/26, fsys/28 (fsys = System clock freq.)

Features

16-bit Reload Timer
(2 channels)

16-bit I/O Timer

16-bit Output Compare
(4 channels)

16-bit Input Capture
(8 channels)

MB90F543/F549
MB90F543G (S) /F548G (S)
MB90F549G (S) /F546G (S)

MB90F548GL(S)

Operation clock frequency : fsys/2
Supports External Event Count function
Signals an interrupt when overflow

Supports Timer Clear when a match with Output Compare (Channel 0)
Operation clock freq. : fsys/2

Signals an interrupt when a match with 16-bit I/O Timer
Four 16-bit compare registers
A pair of compare registers can be used to generate an output signal

Rising edge, falling edge or rising & falling edge sensitive
Four 16-bit Capture registers
Signals an interrupt upon external event

Supports 8-bit and 16-bit operation modes
Eight 8-bit reload counters

8/16-bit
Programmable
Pulse Generator
(4 channels)

Eight 8-bit reload registers for L pulse width
Eight 8-bit reload registers for H pulse width
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit
prescaler plus 8-bit reload counter
4 output pins
Operation clock freq. : fsys, fsys/2

1

, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz

(fsys = System clock frequency, fosc = Oscillation clock frequency)
Conforms to CAN Specification Version 2.0 Part A and B

CAN Interface
MB90540 series
: 2 channels
MB90545 series
: 1 channel

Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 massage buffers for data and ID’s supports multipe massages
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps

32 kHz Sub-clock Sub-clock for low power operation
External Interrupt

(8 channels)
External bus

interface

Can be programmed edge sensitive or level sensitive
External access using the selectable 8-bit or 16-bit bus is enabled

(external bus mode.)
Virtually all external pins can be used as general purpose I/O

I/O Ports

All push-pull outputs and schmitt trigger inputs
Bit-wise programmable as input/output or peripheral signal
Sub-clock for 32 kHz Sub clock low power operation

Supports automatic programming, Embeded Algorithm TM
Write/Erase/Erase-Suspend/Erase-Resume commands
A flag indicating completion of the algorithm

Flash Memory

Number of erase cycles : 10,000 times
Data retention time : 10 years
Boot block configuration
Erase can be performed on each block
Block protection by externally programmed voltage

*1 : Under development
*2 : If the one clock system is used, equip X0A and X1A with clocks from the tool side.

1
1

*4

MB90V540

MB90V540G

5

MB90540/540G/545/545G Series

*3 : It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.Please refer to the MB2145-507

hardware manual (2.7 Emulator-specific Power Pin) about details.
*4 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
*5 : OPERATING VOLTAGE RANGE

Products Operation guarantee range

MB90F543/F549/F543G(S)/F546G(S)/F548G(S)/
MB90549G(S)/F549G(S)/V540/V540G

MB90F548GL(S)/543G(S)*

1

/547G(S)*1/548G(S) 3.5 V to 5.5 V

4.5 V to 5.5 V

6

PIN ASSIGNMENT

■■■■

MB90540/540G/545/545G Series

(TOP VIEW)

P20/A16
P21/A17
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23

P30/ALE

P31/RD

V

SS

P32/WRL/WR

P33/WRH

P34/HRQ

P35/HAK
P36/RDY

P37/CLK
P40/SOT0
P41/SCK0

P42/SIN0
P43/SIN1

P44/SCK1

V

CC

P45/SOT1
P46/SOT2
P47/SCK2

P50/SIN2
P51/INT4
P52/INT5

P17/AD15

P16/AD14

P15/AD13

P14/AD12

P13/AD11

P12/AD10

P11/AD09

P10/AD08

P07/AD07

P06/AD06

P05/AD05

P04/AD04

P03/AD03

P02/AD02

99989796959493929190898887868584838281

100

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

C

28
29
30

31323334353637383940414243444546474849

CC

P01/AD01

P00/AD00

V

X1X0V

SS

50

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

X0A
X1A
PA0
RST
P97/RX1
P96/TX1
P95/RX0
P94/TX0
P93/INT3
P92/INT2
P91/INT1
P90/INT0
P87/TOT1
P86/TIN1
P85/OUT1
P84/OUT0
P83/PPG3
P82/PPG2
P81/PPG1
P80/PPG0
P77/OUT3/IN7
P76/OUT2/IN6
P75/IN5
P74/IN4
P73/IN3
P72/IN2
P71/IN1
P70/IN0
HST
MD2

P53/INT6

P54/INT7

P55/ADTG

CC

AV

SS

AV

AVRL

AVRH

P60/AN0

P61/AN1

(FPT-100P-M06)

SS

V

P62/AN2

P63/AN3

P64/AN4

P65/AN5

P66/AN6

P67/AN7

P56/TIN0

P57/TOT0

MD0

MD1

7

MB90540/540G/545/545G Series

(TOP VIEW)

P21/A17

P20/A16

P17/AD15

P16/AD14

P15/AD13

P14/AD12

P13/AD11

P12/AD10

P11/AD09

P10/AD08

P07/AD07

P06/AD06

P05/AD05

P04/AD04

P03/AD03

P02/AD02

P01/AD01

100999897969594939291908988878685848382818079787776

CC

X1X0VSSX0A

P00/AD00

V

X1A

PA0

P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23

P30/ALE

P31/RD

V

P32/WRL/WR

P33/WRH

P34/HRQ

P35/HAK

P36/RDY

P37/CLK
P40/SOT0
P41/SCK0

P42/SIN0
P43/SIN1

P44/SCK1

V
P45/SOT1
P46/SOT2
P47/SCK2

SS

CC

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

C

26272829303132333435363738394041424344454647484950

P51/INT4

P52/INT5

P50/SIN2

P53/INT6

P54/INT7

P55/ADTG

CC

AV

AVRL

AVRH

SS

AV

P60/AN0

P61/AN1

SS

V

P62/AN2

P63/AN3

P64/AN4

P65/AN5

P66/AN6

P67/AN7

P56/TIN0

P57/TOT0

MD0

MD1

MD2

HST

75

RST

74

P97/RX1

73

P96/TX1

72

P95/RX0

71

P94/TX0

70

P93/INT3

69

P92/INT2

68

P91/INT1

67

P90/INT0

66

P87/TOT1

65

P86/TIN1

64

P85/OUT1

63

P84/OUT0
P83/PPG3

62
61

P82/PPG2

60

P81/PPG1

59

P80/PPG0

58

P77/OUT3/IN7

57

P76/OUT2/IN6

56

P75/IN5

55

P74/IN4

54

P73/IN3

53

P72/IN2

52

P71/IN1

51

P70/IN0

(FPT-100P-M05)

8

PIN DESCRIPTION

■■■■

MB90540/540G/545/545G Series

Pin No.

*2

LQFP

80
81

78 80 X0A

77 79 X1A
75 77 RST

50 52 HST

83 to 90 85 to 92

91 to 98 93 to 100

99 to 6 1 to 8

QFP

82
83

*1

P00 to P07

AD00 to AD07

P10 to P17

AD08 to AD15

P20 to P27

A16 to A23

Pin name Circuit type Function

X0
X1

A

(Oscillation)

A

(Oscillation)

B External reset request input pin
C Hardware standby input pin

I

I

I

High speed crystal oscillator input pins
Low speed crystal oscillator input pins. For the one clock sys-

tem parts, perfom external pull-down processing.
Low speed crystal oscillator input pins. For the one clock sys-

tem parts, leave it open.

General I/O port with programmable pullup. This function is
enabled in the single-chip mode.

I/O pins for 8 lower bits of the external address/data bus. This
function is enabled when the external bus is enabled.

General I/O port with programmable pullup. This function is
enabled in the single-chip mode.

I/O pins for 8 higher bits of the external address/data bus. This
function is enabled when the external bus is enabled.

General I/O port with programmable pullup. In external bus
mode, this function is valid when the corresponding bits in the
external address output control resister (HACR) are set to “1”.

8-bit I/O pins for A16 to A23 at the external address/data bus.
In external bus mode, this function is valid when the corre­sponding bits in the external address output control resister
(HACR) are set to “0”.

79

810

10 12

P30

ALE

P31

RD

P32

WRL

WR

General I/O port with programmable pullup. This function is

I

I

I

enabled in the single-chip mode.
Address latch enable output pin. This function is enabled

when the external bus is enabled.
General I/O port with programmable pullup. This function is

enabled in the single-chip mode.
Read strobe output pin for the data bus. This function is en-

abled when the external bus is enabled.
General I/O port with programmable pullup. This function is

enabled in the single-chip mode or when the WR
put is disabled.

Write strobe output pin for the data bus. This function is en­abled when both the external bus and the WR
are enabled. WRL
of the data bus in 16-bit access. WR
for the 8 bits of the data bus in 8-bit access.

is write-strobe output pin for the lower 8 bits

is write-strobe output pin

/WRL pin out-

/WRL pin output

(Continued)

9

MB90540/540G/545/545G Series

Pin No.

*2

LQFP

11 13

12 14

13 15

14 16

15 17

QFP

*1

Pin name

P33

WRH

P34

HRQ

P35

HAK

P36

RDY

P37

CLK

Circuit

type

I

I

I

I

H

Function

General I/O port with programmable pullup. This function is
enabled in the single-chip mode, external bus 8-bit mode or
when WRH

Write strobe output pin for the 8 higher bits of the data bus.
This function is enabled when the external bus is enabled,
when the external bus 16-bit mode is selected, and when the
WRH

General I/O port with programmable pullup. This function is
enabled in the single-chip mode or when the hold function is
disabled.

Hold request input pin. This function is enabled when both the
external bus and the hold functions are enabled.

General I/O port with programmable pullup. This function is
enabled in the single-chip mode or when the hold function is
disabled.

Hold acknowledge output pin. This function is enabled when
both the external bus and the hold functions are enabled.

General I/O port with programmable pullup. This function is
enabled in the single-chip mode or when the external ready
function is disabled.

Ready input pin. This function is enabled when both the
external bus and the external ready functions are enabled.

General I/O port with programmable pullup. This function is
enabled in the single-chip mode or when the CLK output is dis­abled.

CLK output pin. This function is enabled when both the
external bus and CLK outputs are enabled.

pin output is disabled.

output pin is enabled.

10

16 18

17 19

18 20

19 21

P40

SOT0

P41

SCK0

P42

SIN0

P43

SIN1

General I/O port. This function is enabled when UART0

G

G

G

G

disables the serial data output.
Serial data output pin for UART0. This function is enabled

when UART0 enables the serial data output.
General I/O port. This function is enabled when UART0

disables serial clock output.
Serial clock I/O pin for UART0. This function is enabled when

UART0 enables the serial clock output.
General I/O port. This function is always enabled.
Serial data input pin for UART0. Set the corresponding Port

Direction Register to input if this function is used.
General I/O port. This function is always enabled.
Serial data input pin for UART1. Set the corresponding Port

Direction Register to input if this function is used.

(Continued)

MB90540/540G/545/545G Series

Pin No.

*2

LQFP

20 22

22 24

23 25

24 26

QFP

*1

Pin name

P44

SCK1

P45

SOT1

P46

SOT2

P47

SCK2

P50

Circuit

type

G

G

G

G

Function

General I/O port. This function is enabled when UART1
disables the clock output.

Serial clock pulse I/O pin for UART1. This function is
enabled when UART1 enables the serial clock output.

General I/O port. This function is enabled when UART1
disables the serial data output.

Serial data output pin for UART1. This function is enabled when
UART1 enables the serial data output.

General I/O port. This function is enabled when the Extended
I/O serial interface disables the serial data output.

Serial data output pin for the Extended I/O serial interface. This
function is enabled when the Extended I/O serial interface en­ables the serial data output.

General I/O port. This function is enabled when the Extended
I/O serial interface disables the clock output.

Serial clock pulse I/O pin for the Extended I/O serial interface .
This function is enabled when the Extended I/O serial interface
enables the Serial clock output.

General I/O port. This function is always enabled.

26 28

27 to 30 29 to 32

31 33

36 to 39 38 to 41

41 to 44 43 to 46

45 47

SIN2

P51 to P54

INT4 to INT7

P55

ADTG

P60 to P63

AN0 to AN3

P64 to P67

AN4 to AN7

P56

TIN0

D

D

D

E

E

D

Serial data input pin for the Extended I/O serial interface . Set
the corresponding Port Direction Register to input if this func­tion is used.

General I/O port. This function is always enabled.
External interrupt request input pins for INT4 to INT7. Set the

corresponding Port Direction Register to input if this function is
used.

General I/O port. This function is always enabled.
Trigger input pin for the A/D converter. Set the corresponding

Port Direction Register to input if this function is used.
General I/O port. This function is enabled when the analog

input enable register specifies a port.
Analog input pins for the 8/10-bit A/D converter. This function is

enabled when the analog input enable register specifies A/D.
General I/O port. The function is enabled when the analog

input enable register specifies a port.
Analog input pins for the 8/10-bit A/D converter. This function is

enabled when the analog input enable register specifies A/D.
General I/O port. This function is always enabled.
Event input pin for the 16-bit reload timers 0. Set the

corresponding Port Direction Register to input if this function is
used.

(Continued)

11

MB90540/540G/545/545G Series

Pin No.

*2

LQFP

46 48

51 to 56 53 to 58

57 , 58 59 , 60

59 , 62 61 to 64

QFP

*1

Pin name

P57

TOT0

P70 to P75

IN0 to IN5

P76 , P77

OUT2 , OUT3

IN6 , IN7

P80 to P83

PPG0 to

PPG3

Circuit

type

D

D

D

D

Function

General I/O port. This function is enabled when the 16-bit
reload timers 0 disables the output.

Output pin for the 16-bit reload timers 0. This function is
enabled when the 16-bit reload timers 0 enables the output.

General I/O ports. This function is always enabled.
Trigger input pins for input captures ICU0 to ICU5. Set the cor-

responding Port Direction Register to input if this
function is used.

General I/O ports. This function is enabled when the OCU
disables the waveform output.

Event output pins for output compares OCU2 and OCU3. This
function is enabled when the OCU enables the waveform out­put.

Trigger input pins for input captures ICU6 and ICU7. Set the
corresponding Port Direction Register to input and disable the
OCU waveform output if this function is used.

General I/O ports. This function is enabled when 8/16-bit PPG
disables the waveform output.

Output pins for 8/16-bit PPGs. This function is enabled when
8/16-bit PPG enables the waveform output.

63 , 64 65 , 66

65 67

66 68

67 to 70 69 to 72

71 73

P84 , P85

OUT0 , OUT1

P86

TIN1

P87

TOT1

P90 to P93

INT0 to INT3

P94

TX0

General I/O ports. This function is enabled when the OCU
disables the waveform output.

D

D

D

D

D

Waveform output pins for output compares OCU0 and OCU1.
This function is enabled when the OCU enables the waveform
output.

General I/O port. This function is always enabled.
Input pin for the 16-bit reload timers 1. Set the

corresponding Port Direction Register to input if this function is
used.

General I/O port. This function is enabled when the 16-bit
reload timers 0 disables the output.

Output pin for the 16-bit reload timers 1.This function is
enabled when the 16-bit reload timers 1 enables the output.

General I/O port. This function is always enabled.
External interrupt request input pins for INT0 to INT3. Set the

corresponding Port Direction Register to input if this function is
used.

General I/O port. This function is enabled when CAN0 disables
the output.

TX output pin for CAN0. This function is enabled when CAN0
enables the output.

(Continued)

12

(Continued)

Pin No.

*2

LQFP

QFP

*1

Pin name

MB90540/540G/545/545G Series

Circuit

type

Function

72 74

73 75

74 76

P95

D

RX0

P96

D

TX1
P97

D

RX1

General I/O port. This function is always enabled.
RX input pin for CAN0 Interface. When the CAN function is

used, output from the other functions must be stopped.
General I/O port. This function is enabled when CAN1 disables

the output.
TX output pin for CAN1. This function is enabled when CAN1

enables the output (only MB90540 series) .
General I/O port. This function is always enabled.
RX input pin for CAN1 Interface. When the CAN function is

used, output from the other functions must be stopped (only
MB90540 series) .

76 78 PA0 D General I/O port. This function is always enabled.

Power supply pin for the A/D Converter. This power supply
must be turned on or off while a voltage higher than or equal to
AV

CC is applied to VCC.

Power supply pin for the A/D Converter.
External reference voltage input pin for the A/D Converter.

This power supply must be turned on or off while a voltage
higher than or equal to AVRH is applied to AV

CC.

32 34 AV

CC

35 37 AVSS

33 35 AVRH

Power
supply

Power
supply

Power
supply

34 36 AVRL
47

48

49
50

MD0
MD1

49 51 MD2 F

25 27 C 

21, 82 23, 84 V

9, 40, 79

11, 42,

81

CC

V

SS

*1 : FPT-100P-M06
*2 : FPT-100P-M05

Power
supply

C

Power
supply

Power
supply

External reference voltage input pin for the A/D Converter.
Input pins for specifying the operating mode. The pins must be

directly connected to V

CC or VSS.

Input pin for specifying the operating mode. The pin must be
directly connected to V

CC or VSS.

Power supply stabilization capacitor pin. It should be connect­ed externally to an 0.1 µF ceramic capacitor.

Input pin for power supply (5.0 V) .

Input pin for power supply (0.0 V) .

13

MB90540/540G/545/545G Series

I/O CIRCUIT TYPE

■■■■

Circuit type Diagram Remarks

• High-speed oscillation feedback resistor

X1, X1A

X0, X0A

A

Standby control signal

: 1 MΩ approx.

• Low-speed oscillation feedbac k resistor
: 10 MΩ approx.

• Hysteresis input

• Pull-up resistor : 50 kΩ approx.

B

R (Pull-up)

R

HYS input

• Hysteresis input

C

R

HYS input

• CMOS level output

VCC

P-ch

D

R

N-ch

HYS input

• CMOS Hysteresis input

(Continued)

14

MB90540/540G/545/545G Series

Circuit type Diagram Remarks

• CMOS level output

CC

V

P-ch

N-ch

E

P-ch

Analog input

N-ch

R

R

HYS input

HYS input

• CMOS Hysteresis input

• Analog input

• Hysteresis input

• Pull-down Resistor : 50 kΩ approx.
(except FLASH devices)

F

R (Pull-down)

• CMOS level output

• CMOS Hysteresis input

• TTL level input (FLASH devices in

CC

V

P-ch

N-ch

FLASH writer mode only)

G

R

R

T

HYS input

TTL level input

(Continued)

15

MB90540/540G/545/545G Series

(Continued)

Circuit type Diagram Remarks

• CMOS level output

• CMOS Hysteresis input

• Programmable pull-up resistor :

VCC

H

VCC

CNTL

P-chP-ch

N-ch

50 kΩ approx.

R

HYS input

• CMOS level output

• CMOS Hysteresis input

• TTL level input (FLASH devices in

VCC

P-ch

I

R

R

CNTL

CC

V

P-ch

N-ch

T

FLASH writer mode only)

• Programmable pullup resistor :
50 kΩ approx.

HYS input

TTL level input

16

MB90540/540G/545/545G Series

HANDLING DEVICES

■■■■

(1) Preventing latch-up

CMOS IC chips may suffer latch-up under the following conditions :

• A voltage higher than V

• A voltage higher than the rated voltage is applied between V

• The AVcc power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.

For the same reason, care must also be tak en in not allowing the analog po wer-supply v oltage (AV
exceed the digital power-supply voltage.

(2) Handling unused pins

Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Theref or the y m ust be pulled up or pulled down through resistors . In this case those resistors should be
more than 2 kΩ.
Unused bi-directional pins should be set to the output state and can be left open, or the input state with the
above described connection.

(3) Using external clock

To use external clock, drive X0 pin only and leave X1 pin unconnected.
Below is a diagram of how to use external clock.

CC or lower than VSS is applied to an input or output pin.

CC and VSS.

CC, A VRH) to

MB90540/545 Series

X0

Open

X1

(4) Use of the sub-clock

Use one clock system parts when the sub-clock is not used. In that case, pull-down the pin X0A and leave the
pin X1A open. When using two clock system parts, a 32 kHz oscillator has to be connected to the X0A and X1A
pins.

CC/VSS

(5) Power supply pins (V

In products with multiple V

)

CC or VSS pins, the pins of a same potential are internally connected in the device to

avoid abnormal operations including latch-up. However you must connect the pins to an external power and a
ground line to lower the electro-magnetic emission le vel to pre v ent abnormal operation of strobe signals caused
by the rise in the ground level, and to conform to the total current rating.
Make sure to connect V
It is recommended to provide a bypass capacitor of around 0.1 µF between V

CC and VSS pins via the lowest impedance to power lines.

CC and VSS pins near the device.

VCC
VSS

VCC

VSS

VSS

VCC

VSS

MB90540/545

Series

VCC

VCC

VSS

17

MB90540/540G/545/545G Series

(6) Pull-up/down resistors

The MB90540/545 Series does not support internal pull-up/down resistors (except Port0 − Port3 : pull-up resis­tors) . Use external components where needed.

(7) Crystal Oscillator Circuit

Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via the shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines,
and make sure, to the utmost effort, that lines of oscillation circuits do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground
area for stabilizing the operation.

(8) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on the A/D converter power supply (A V
turning-on the digital power supply (V

CC) .

CC, A VRH, A VRL) and analog inputs (AN0 to AN7) after

Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage does not exceed AVRH or AV

CC (turning on/off the analog and digital power supplies simulta-

neously is acceptable) .

(9) Connection of Unused Pins of A/D Converter

Connect unused pins of A/D converter to AV

CC = VCC, AVSS = AVRH = VSS.

(10) N.C. Pin

The N.C. (internally connected) pin must be opened for use.

(11) Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 µs or more (0.2 V to 2.7 V) .

18

MB90540/540G/545/545G Series

(12) Indeterminate outputs from ports 0 and 1 (MB90F543/F549/V540/V540G only)

During oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the
outputs from ports 0 and 1 become following state.

•If RST

•If RST pin is “L”, the outputs become high-impedance.
Pay attention to the port output timing shown as follow.

•RST pin is “H”

pin is “H”, the outputs become indeterminate.

VCC (Power-supply pin)

PONR (power-on reset) signal

RST (external asynchronous reset) signal

RST (internal reset) signal

Oscillation clock signal

KA (internal operation clock A) signal

KB (internal operation clock B) signal

PORT (port output) signal

Oscillation setting time*

Power-on reset*

Period of indeterminated

2

1

*1 : Power-on reset time : Period of “clock frequency × 217” (Clock frequency of 16 MHz : 8.19 ms)
*2 : Oscillation setting time : Period of “clock frequency × 2

18

” (Clock frequency of 16 MHz : 16.38 ms)

19

MB90540/540G/545/545G Series

•RST pin is “L”

VCC (Power-supply pin)

PONR (power-on reset) signal

RST (external asynchronous reset) signal

RST (internal reset) signal

Oscillation clock signal

KA (internal operation clock A) signal

KB (internal operation clock B) signal

PORT (port output) signal

Oscillation setting time*

Power-on reset*

High-impedance

2

1

*1 : Power-on reset time : Period of “clock frequency × 217” (Clock frequency of 16 MHz : 8.19 ms)
*2 : Oscillation setting time : Period of “cloc k frequency × 2

18

” (Clock frequency of 16 MHz : 16.38 ms)

(13) Initialization

In the device, there are internal registers which are initialized only by a pow er-on reset. T o initialize these registers,
please turn on the power again.

(14) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions

In the Signed multiplication and division instructions (“DIV A, Ri” and “DIVW A, RWi”) , the value of the corre­sponding bank register (DTB, ADB, USB, SSB) is set in “00

H”.

If the values of the corresponding bank registers (DTB, ADB, USB, SSB) are set to other than “00H”, the remainder
by the execution result of the instruction is not stored in the register of the instruction operand.

(15) Using REALOS

The use of EI

2

OS is not possible with the REALOS real time operating system.

(16) Caution on Operations during PLL Clock Mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit ev en
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.

20

BLOCK DIAGRAM

■■■■

X0, X1
X0A, X1A

RST
HST

Clock

Controller

MB90540/540G/545/545G Series

F2MC 16LX

CPU

SOT0
SCK0

SIN0

SOT1
SCK1

SIN1

SOT2
SCK2

SIN2

AV

CC

AVSS
AN0 to AN7

AVRH
AVRL
ADTG

RAM

2 K/4 K/6 K/8 K

ROM/Flash

128 K/256 K/

64K(ROM only)

Prescaler

UART0

Prescaler

UART1

(SCI)

Prescaler

Serial I/O

10-bit A/D
Converter

8 ch.

FMC-16 Bus

16-bit I/O

Timer

16-bit Input

Capture

8 ch.

16-bit Output

Compare

4 ch.

8/16-bit

PPG

4 ch.

CAN

Controller

16-bit Reload

Timer 2 ch.

External

Bus

Interface

IN0 to IN5
IN6/OUT2,

IN7/OUT3
OUT0, OUT1

PPG0 to PPG3

RX0, RX1 *
TX0, TX1 *

TIN0, TIN1
TOT0, TOT1

AD00 to AD15
A16 to A23
ALE
RD
WRL
WRH

HRQ
HAK
RDY
CLK

* : Only the MB90540 series has two channels

External

Interrupt

8 ch.

INT0 to INT7

21

MB90540/540G/545/545G Series

MEMORY MAP

■■■■

The memory space of the MB90540/545 Series is shown below.

MB90V540G/F546G (S)

FFFFFF

H

FF0000H
FEFFFFH

FE0000H
FDFFFFH

FD0000H
FCFFFFH

FC0000H

00FFFFH

004000H
003FFFH

003900H

0020FFH
001FF5H

001FF0H

000100H

0000BFH
000000H

ROM correction

MB90V540

ROM

(FF bank)

ROM

(FE bank)

ROM

(FD bank)

ROM

(FC bank)

External

ROM

(Image of

FF bank)

Peripheral

External

RAM 8 K

External

Peripheral

MB90F543/F543G(S)

FFFFFF

H

FF0000H
FEFFFFH

FE0000H

00FFFFH

004000H
003FFFH

003900H

002000H

0018FFH

000100H

0000BFH
000000H

MB90543G(S)*

ROM

(FF bank)

ROM

(FE bank)

External

ROM

(Image of

FF bank)

Peripheral

External

RAM 6 K

External

Peripheral

2

FFFFFF

FF0000H
FEFFFFH

FE0000H

00FFFFH

004000H
003FFFH

003900H

002000H

0010FFH

000100H

0000BFH
000000H

MB90548G(S)

MB90F548GL(S)

MB90F548G (S)

H

ROM

(FF bank)

ROM

(FE bank)

External

ROM

(Image of

FF bank)

Peripheral

External

RAM 4 K

External

Peripheral

MB90549G (S) /F549G (S)

FFFFFFH

FF0000H
FEFFFFH

FE0000H
FDFFFFH

FD0000H
FCFFFFH

FC0000H

00FFFFH

004000H
003FFFH

003900H

002100H*1

H

0018FF

000100H

0000BFH
000000H

MB90F549

ROM

(FF bank)

ROM

(FE bank)

ROM

(FD bank)

ROM

(FC bank)

External

ROM

(Image of

FF bank)

Peripheral

External

RAM 6 K

External

Peripheral

FFFFFFH

FF0000H

00FFFFH

004000H

003FFFH

003900H

002000H

0008FFH

000100H
0000BFH

000000H

MB90547G (S)*2

ROM

(FF bank)

External

ROM

(Image of

FF bank)

Peripheral

External

RAM 2 K

External

Peripheral

*1 : 002000H for MB90F549
*2 : Under development

Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C

compiler effective. Since the low-order 16 bits address are the same, the table in ROM can be referenced
without using the “far” specification in the pointer declaration.
For e xample, an attempt to access 00C000

H accesses the value at FFC000H in ROM.The R OM area in bank

FF exceeds 48 Kbytes, and its entire image cannot be shown in bank 00.The image between FF4000
FFFFFF

H is visible in bank 00, while the image between FF0000H and FF3FFFH is visible only in bank FF.

22

H and

MB90540/540G/545/545G Series

I/O MAP

■■■■

Address Register Abbreviation Access Resource name Initial value

00

H Port 0 data register PDR0 R/W Port 0 XXXXXXXXB

01H Port 1 data register PDR1 R/W Port 1 XXXXXXXXB
02H Port 2 data register PDR2 R/W Port 2 XXXXXXXXB
03H Port 3 data register PDR3 R/W Port 3 XXXXXXXXB
04H Port 4 data register PDR4 R/W Port 4 XXXXXXXXB
05H Port 5 data register PDR5 R/W Port 5 XXXXXXXXB
06H Port 6 data register PDR6 R/W Port 6 XXXXXXXXB
07H Port 7 data register PDR7 R/W Port 7 XXXXXXXXB
08H Port 8 data register PDR8 R/W Port 8 XXXXXXXXB
09H Port 9 data register PDR9 R/W Port 9 XXXXXXXXB
0AH Port A data register PDRA R/W Port A _ _ _ _ _ _ _XB

0BH to 0FH Reserved

10

H Port 0 direction register DDR0 R/W Port 0 0 0 0 0 0 0 0 0B

11H Port 1 direction register DDR1 R/W Port 1 0 0 0 0 0 0 0 0B
12H Port 2 direction register DDR2 R/W Port 2 0 0 0 0 0 0 0 0B
13H Port 3 direction register DDR3 R/W Port 3 0 0 0 0 0 0 0 0B
14H Port 4 direction register DDR4 R/W Port 4 0 0 0 0 0 0 0 0B
15H Port 5 direction register DDR5 R/W Port 5 0 0 0 0 0 0 0 0B
16H Port 6 direction register DDR6 R/W Port 6 0 0 0 0 0 0 0 0B
17H Port 7 direction register DDR7 R/W Port 7 0 0 0 0 0 0 0 0B
18H Port 8 direction register DDR8 R/W Port 8 0 0 0 0 0 0 0 0B
19H Port 9 direction register DDR9 R/W Port 9 0 0 0 0 0 0 0 0B
1AH Port A direction register DDRA R/W Port A _ _ _ _ _ _ _0B

1BH Analog Input Enable register ADER R/W Port 6, A/D 1 1 1 1 1 1 1 1B
1CH Port 0 Pullup control register PUCR0 R/W Port 0 0 0 0 0 0 0 0 0B
1DH Port 1 Pullup control register PUCR1 R/W Port 1 0 0 0 0 0 0 0 0B
1EH Port 2 Pullup control register PUCR2 R/W Port 2 0 0 0 0 0 0 0 0B
1FH Port 3 Pullup control register PUCR3 R/W Port 3 0 0 0 0 0 0 0 0B

20H Serial Mode Control Register 0 UMC0 R/W

21H Serial Status Register 0 USR0 R/W 0 0 0 1 0 0 0 0B

22H

Serial input data register 0/

Serial output data register 0

UIDR0/

UODR0

R/W XXXXXXXXB

UART0

0 0 0 0 0 1 0 0B

23H Rate and data register 0 URD0 R/W 0 0 0 0 0 0 0XB

(Continued)

23

MB90540/540G/545/545G Series

Address Register

24

H Serial mode register 1 SMR1 R/W

Abbreviation

Access Resource name Initial value

0 0 0 0 0 0 0 0B

25H Serial control register 1 SCR1 R/W 0 0 0 0 0 1 0 0B
26H

Serial input data register 1/

Serial output data register 1

SIDR1/

SODR1

R/W XXXXXXXXB

UART1

27H Serial status register 1 SSR1 R/W 0 0 0 0 1_0 0B
28H UART1 prescaler control register CDCR R/W 0_ _ _1 1 1 1B
29H Serial Edge select register SES1 R/W _ _ _ _ _ _ _0B

2AH Prohibited

2B

H Serial I/O prescaler SCDCR R/W

0_ _ _1 1 1 1B
2CH Serial mode control register SMCS R/W _ _ _ _0 0 0 0B
2DH Serial mode control register SMCS R/W 0 0 0 0 0 0 1 0B

Extended I/O

Serial Interface

2EH Serial data register SDR R/W XXXXXXXXB
2FH Serial Edge select register SES2 R/W _ _ _ _ _ _ _0B
30H External interrupt enable register ENIR R/W

0 0 0 0 0 0 0 0B

31H External interrupt request register EIRR R/W XXXXXXXXB

External Interrupt

32H External interrupt level register ELVR R/W 0 0 0 0 0 0 0 0B
33H External interrupt level register ELVR R/W 0 0 0 0 0 0 0 0B
34H A/D control status register 0 ADCS0 R/W

0 0 0 0 0 0 0 0B

35H A/D control status register 1 ADCS1 R/W 0 0 0 0 0 0 0 0B

A/D Converter

36H A/D data register 0 ADCR0 R XXXXXXXXB
37H A/D data register 1 ADCR1 R/W 0 0 0 0 1 _ XXB
38H PPG0 operation mode control register PPGC0 R/W
39H PPG1 operation mode control register PPGC1 R/W 0 _ 0 0 0 0 0 1B
3AH PPG0/1 clock selection register PPG01 R/W 0 0 0 0 0 0 _ _B

16-bit Programmable

Pulse

Generator 0/1

0 _ 0 0 0 _ _ 1B

3BH Prohibited
3CH PPG2 operation mode control register PPGC2 R/W
3DH PPG3 operation mode control register PPGC3 R/W 0 _ 0 0 0 0 0 1B
3EH PPG2/3 Clock Selection Register PPG23 R/W 0 0 0 0 0 0 _ _B

16-bit Programmable

Pulse

Generator 2/3

0 _ 0 0 0 _ _1B

3FH Prohibited
40

H PPG4 operation mode control register PPGC4 R/W

41H PPG5 operation mode control register PPGC5 R/W 0 _ 0 0 0 0 0 1B
42H PPG4/5 clock selection register PPG45 R/W 0 0 0 0 0 0 _ _B

16-bit Programmable

Pulse

Generator 4/5

0 _ 0 0 0 _ _ 1B

43H Prohibited
44

H PPG6 operation mode control register PPGC6 R/W

45H PPG7 operation mode control register PPGC7 R/W 0 _ 0 0 0 0 0 1B
46H PPG6/7 clock selection register PPG67 R/W 0 0 0 0 0 0 _ _B

16-bit Programmable

Pulse

Generator 6/7

0 _ 0 0 0 _ _ 1B

(Continued)

24

MB90540/540G/545/545G Series

Address Register Abbreviation Access Resource name Initial value

47

H to 4BH Prohibited

4CH
4DH

4EH
4FH

Input capture control status register 0/1
Input capture control status register 2/3
Input capture control status register 4/5
Input capture control status register 6/7

50H Timer control status register 0 TMCSR0 R/W
51H Timer control status register 0 TMCSR0 R/W _ _ _ _ 0 0 0 0B

52H Timer register 0/reload register 0

53H Timer register 0/reload register 0

ICS01 R/W Input Capture 0/1 0 0 0 0 0 0 0 0B
ICS23 R/W Input Capture 2/3 0 0 0 0 0 0 0 0B
ICS45 R/W Input Capture 4/5 0 0 0 0 0 0 0 0B
ICS67 R/W Input Capture 6/7 0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0B

TMR0/

TMRLR0

TMR0/

TMRLR0

R/W XXXXXXXXB

R/W XXXXXXXXB

16-bit Reload

Timer 0

54H Timer control status register 1 TMCSR1 R/W

0 0 0 0 0 0 0 0B

55H Timer control status register 1 TMCSR1 R/W _ _ _ _ 0 0 0 0B
56H Timer register 1/reload register 1

57H Timer register 1/reload register 1
58H

59H
5AH
5BH

Output compare control status register 0
Output compare control status register 1
Output compare control status register 2
Output compare control status register 3

TMR1/

TMRLR1

TMR1/

TMRLR1

R/W XXXXXXXXB

R/W XXXXXXXXB

OCS0 R/W
OCS1 R/W _ _ _0 0 0 0 0B
OCS2 R/W
OCS3 R/W _ _ _ 0 0 0 0 0B

16-bit Reload

Timer 1

Output Compare

0/1

Output Compare

2/3

0 0 0 0 _ _ 0 0

0 0 0 0 _ _ 0 0B

5CH to 6BH Prohibited

6CH Timer Data register TCDT R/W
6DH Timer Data register TCDT R/W 0 0 0 0 0 0 0 0B

I/O Timer

0 0 0 0 0 0 0 0B

6EH Timer Control register TCCS R/W 0 0 0 0 0 0 0 0B
6FH

ROM mirror function

selection register

ROMM R/W ROM Mirror _ _ _ _ _ _ _ 1B

70H to 7FH Reserved for CAN 0 Interface.
80

H to 8FH Reserved for CAN 1 Interface.

90H to 9DH Prohibited

B

Address Match

Detection

Function

0 0 0 0 0 0 0 0B

9E

H

Program address detection

control status register

PACSR R/W

9FH Delayed interrupt/release register DIRR R/W Delayed Interrupt _ _ _ _ _ _ _ 0B
A0H Low-power mode control register LPMCR R/W

A1H Clock selection register CKSCR R/W

Low Power

Controller

Low Power

Controller

0 0 0 1 1 0 0 0B

1 1 1 1 1 1 0 0B

(Continued)

25

MB90540/540G/545/545G Series

(Continued)

Address Register Abbreviation Access Resource name Initial value

A2

H to A4H Prohibited

A5
A6H
A7H Bus control signal selection register ECSR W 0 0 0 0 0 0 0 _B
A8H Watchdog Timer control register WDTC R/W Watchdog Timer XXXXX 1 1 1B
A9H Time Base Timer Control register TBTC R/W Time Base Timer 1 - - 0 0 1 0 0B

AAH Watch timer control register WTC R/W Watch Timer 1 X 0 0 0 0 0 0B

ABH to ADH Prohibited

Automatic ready function select register

H

External address output control register

ARSR W
HACR W 0 0 0 0 0 0 0 0B

External Memory

Access

0 0 1 1 _ _ 0 0B

AE

Flash memory control status register

H

(Flash only, otherwise reserved)

FMCS R/W Flash Memory 0 0 0 X 0 0 0 0B

AFH Prohibited

B0H Interrupt control register 00 ICR00 R/W

0 0 0 0 0 1 1 1B
B1H Interrupt control register 01 ICR01 R/W 0 0 0 0 0 1 1 1B
B2H Interrupt control register 02 ICR02 R/W 0 0 0 0 0 1 1 1B
B3H Interrupt control register 03 ICR03 R/W 0 0 0 0 0 1 1 1B
B4H Interrupt control register 04 ICR04 R/W 0 0 0 0 0 1 1 1B
B5H Interrupt control register 05 ICR05 R/W 0 0 0 0 0 1 1 1B
B6H Interrupt control register 06 ICR06 R/W 0 0 0 0 0 1 1 1B
B7H Interrupt control register 07 ICR07 R/W 0 0 0 0 0 1 1 1B
B8H Interrupt control register 08 ICR08 R/W 0 0 0 0 0 1 1 1B

Interrupt

controller

B9H Interrupt control register 09 ICR09 R/W 0 0 0 0 0 1 1 1B

BAH Interrupt control register 10 ICR10 R/W 0 0 0 0 0 1 1 1B
BBH Interrupt control register 11 ICR11 R/W 0 0 0 0 0 1 1 1B
BCH Interrupt control register 12 ICR12 R/W 0 0 0 0 0 1 1 1B
BDH Interrupt control register 13 ICR13 R/W 0 0 0 0 0 1 1 1B
BEH Interrupt control register 14 ICR14 R/W 0 0 0 0 0 1 1 1B
BFH Interrupt control register 15 ICR15 R/W 0 0 0 0 0 1 1 1B

C0H to FFH External

Address Register Abbreviation Access Resource name Initial value

1FF0

H Program address detection register 0 PADR0 R/W

XXXXXXXXB
1FF1H Program address detection register 0 PADR0 R/W XXXXXXXXB
1FF2H Program address detection register 0 PADR0 R/W XXXXXXXXB
1FF3H Program address detection register 1 PADR1 R/W XXXXXXXXB

Address Match

Detection Function

1FF4H Program address detection register 1 PADR1 R/W XXXXXXXXB
1FF5H Program address detection register 1 PADR1 R/W XXXXXXXXB

26

(Continued)

Address Register

3900

H Reload L PRLL0 R/W

MB90540/540G/545/545G Series

Abbreviation

Access Resource name Initial value

XXXXXXXXB
3901H Reload H PRLH0 R/W XXXXXXXXB
3902H Reload L PRLL1 R/W XXXXXXXXB
3903H Reload H PRLH1 R/W XXXXXXXXB
3904H Reload L PRLL2 R/W
3905H Reload H PRLH2 R/W XXXXXXXXB
3906H Reload L PRLL3 R/W XXXXXXXXB
3907H Reload H PRLH3 R/W XXXXXXXXB
3908H Reload L PRLL4 R/W
3909H Reload H PRLH4 R/W XXXXXXXXB
390AH Reload L PRLL5 R/W XXXXXXXXB
390BH Reload H PRLH5 R/W XXXXXXXXB

390CH Reload L PRLL6 R/W
390DH Reload H PRLH6 R/W XXXXXXXXB

390EH Reload L PRLL7 R/W XXXXXXXXB
390FH Reload H PRLH7 R/W XXXXXXXXB

3910H to

3917

H

3918H Input Capture Register 0 IPCP0 R

Reserved

16-bit Programmable Pulse

Generator 0/1

XXXXXXXXB

16-bit Programmable Pulse

Generator 2/3

XXXXXXXXB

16-bit Programmable Pulse

Generator 4/5

XXXXXXXXB

16-bit Programmable Pulse

Generator 6/7

XXXXXXXXB
3919H Input Capture Register 0 IPCP0 R XXXXXXXXB
391AH Input Capture Register 1 IPCP1 R XXXXXXXXB
391BH Input Capture Register 1 IPCP1 R XXXXXXXXB

391CH Input Capture Register 2 IPCP2 R
391DH Input Capture Register 2 IPCP2 R XXXXXXXXB

391EH Input Capture Register 3 IPCP3 R XXXXXXXXB
391FH Input Capture Register 3 IPCP3 R XXXXXXXXB
3920H Input Capture Register 4 IPCP4 R
3921H Input Capture Register 4 IPCP4 R XXXXXXXXB
3922H Input Capture Register 5 IPCP5 R XXXXXXXXB
3923H Input Capture Register 5 IPCP5 R XXXXXXXXB
3924H Input Capture Register 6 IPCP6 R
3925H Input Capture Register 6 IPCP6 R XXXXXXXXB
3926H Input Capture Register 7 IPCP7 R XXXXXXXXB
3927H Input Capture Register 7 IPCP7 R XXXXXXXXB

Input Capture 0/1

XXXXXXXXB

Input Capture 2/3

XXXXXXXXB

Input Capture 4/5

XXXXXXXXB

Input Capture 6/7

(Continued)

27

MB90540/540G/545/545G Series

(Continued)

Address Register Abbreviation Access Resource name Initial value

3928

H Output Compare Register 0 OCCP0 R/W

3929H Output Compare Register 0 OCCP0 R/W XXXXXXXXB

Output Compare 0/1

392AH Output Compare Register 1 OCCP1 R/W XXXXXXXXB
392BH Output Compare Register 1 OCCP1 R/W XXXXXXXXB

XXXXXXXXB

392CH Output Compare Register 2 OCCP2 R/W

XXXXXXXXB

392DH Output Compare Register 2 OCCP2 R/W XXXXXXXXB

Output Compare 2/3

392EH Output Compare Register 3 OCCP3 R/W XXXXXXXXB
392FH Output Compare Register 3 OCCP3 R/W XXXXXXXXB

3930H to

39FF

H

3A00

H to

3AFF

H

3B00

H to

3BFF

H

3C00H to

3CFF

H

3D00

H to

3DFF

H

3E00

H to

3FFF

H

Reserved for CAN 0 Interface.

Reserved for CAN 0 Interface.

Reserved for CAN 1 Interface.

Reserved for CAN 1 Interface.

Reserved

Reserved

• Read/write notation
R/W : Reading and writing permitted

R : Read-only

W : Write-only

• Initial value notation

0 : Initial value is “0”.
1 : Initial value is “1”.

X : Initial value is undefined.

_ : Initial value is unused.

Note : Addresses in the range 0000

of the MCU. A read access to these reserved addresses results in an “X” reading and any write access should
not be performed.

28

H to 00FFH, which are not listed in the table, are reserved for the primary functions

MB90540/540G/545/545G Series

CAN CONTROLLER

■■■■

The MB90540 series contains two CAN controllers (CAN0 and CAN1) , the MB90545 series contains only one
(CAN0) . The Evaluation Chip MB90V540 also has two CAN controllers.
The CAN controller has the following features :

• Conforms to CAN Specification Version 2.0 Part A and B

- Supports transmission/reception in standard frame and extended frame formats

• Supports transmission of data frames by receiving remote frames

• 16 transmitting/receiving message buffers

- 29-bit ID and 8-byte data

- Multi-level message buffer configuration

• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message

buffer as ID acceptance mask

- Two acceptance mask registers in either standard frame format or extended frame formats

• Bit rate programmable from 10 Kbps to 1 Mbps (when input clock is at 16 MHz)

List of Control Registers

Address

CAN0 CAN1

Register Abbreviation Access Initial Value

000070
000071H 000081H
000072H 000082H
000073H 000083H
000074H 000084H
000075H 000085H
000076H 000086H
000077H 000087H
000078H 000088H
000079H 000089H
00007AH 00008AH
00007BH 00008BH
00007CH 00008CH
00007DH 00008DH
00007EH 00008EH
00007FH 00008FH

H 000080H

Message buffer valid register BVALR R/W 00000000 00000000B

Transmit request register TREQR R/W 00000000 00000000B

Transmit cancel register TCANR W 00000000 00000000B

Transmit complete register TCR R/W 00000000 00000000B

Receive complete register RCR R/W 00000000 00000000B

Remote request receiving register RRTRR R/W 00000000 00000000B

Receive overrun register ROVRR R/W 00000000 00000000B

Receive interrupt enable register RIER R/W 00000000 00000000B

(Continued)

29

MB90540/540G/545/545G Series

(Continued)

Address

CAN0 CAN1

003B00

H 003D00H

003B01H 003D01H

Control status register CSR R/W, R 00---000 0----0-1B

Register Abbreviation Access Initial Value

003B02H 003D02H
003B03H 003D03H
003B04H 003D04H
003B05H 003D05H
003B06H 003D06H
003B07H 003D07H
003B08H 003D08H

003B09H 003D09H
003B0AH 003D0AH
003B0BH 003D0BH
003B0CH 003D0CH
003B0DH 003D0DH
003B0EH 003D0EH

003B0FH 003D0FH

003B10H 003D10H

003B11H 003D11H

003B12H 003D12H

003B13H 003D13H

003B14H 003D14H

003B15H 003D15H

003B16H 003D16H

003B17H 003D17H

Last event indicator register LEIR R/W -------- 000-0000B

Receive/transmit error counter
register

RTEC R 00000000 00000000B

Bit timing register BTR R/W -1111111 11111111B

IDE register IDER R/W XXXXXXXX XXXXXXXXB

Transmit RTR register TRTRR R/W 00000000 00000000B

Remote frame receive waiting
register

Transmit request enable regis­ter

RFWTR R/W XXXXXXXX XXXXXXXXB

TIER R/W 00000000 00000000B

XXXXXXXX XXXXXXXX
Acceptance mask select regis­ter

AMSR R/W

XXXXXXXX XXXXXXXXB

XXXXXXXX XXXXXXXXB
Acceptance mask register 0 AMR0 R/W

XXXXX--- XXXXXXXXB

B

003B18H 003D18H

003B19H 003D19H
003B1AH 003D1AH
003B1BH 003D1BH

30

Acceptance mask register 1 AMR1 R/W

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

B

MB90540/540G/545/545G Series

Address

CAN0 CAN1

003A00

003A1F

to

H

H

003C00H

to

003C1F
003A20H 003C20H
003A21H 003C21H
003A22H 003C22H
003A23H 003C23H
003A24H 003C24H
003A25H 003C25H
003A26H 003C26H
003A27H 003C27H
003A28H 003C28H
003A29H 003C29H

003A2AH 003C2AH
003A2BH 003C2BH

List of Message Buffers (ID Registers

Register Abbreviation Access Initial Value

General-purpose RAM  R/W

H

ID register 0 IDR0 R/W

ID register 1 IDR1 R/W

ID register 2 IDR2 R/W

)

XXXXXXXX

B

to

XXXXXXXX

XXXXXXXX XXXXXXXX

B

B

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX

B

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXXB

XXXXX--- XXXXXXXXB

003A2CH 003C2CH
003A2DH 003C2DH
003A2EH 003C2EH

003A2FH 003C2FH
003A30H 003C30H
003A31H 003C31H
003A32H 003C32H
003A33H 003C33H
003A34H 003C34H
003A35H 003C35H
003A36H 003C36H
003A37H 003C37H
003A38H 003C38H
003A39H 003C39H

003A3AH 003C3AH
003A3BH 003C3BH

ID register 3 IDR3 R/W

ID register 4 IDR4 R/W

ID register 5 IDR5 R/W

ID register 6 IDR6 R/W

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXXB

XXXXX--- XXXXXXXXB

(Continued)

B

B

B

31

MB90540/540G/545/545G Series

(Continued)

Address

CAN0 CAN1

003A3C

H 003C3CH

003A3DH 003C3DH
003A3EH 003C3EH

003A3FH 003C3FH
003A40H 003C40H
003A41H 003C41H
003A42H 003C42H
003A43H 003C43H
003A44H 003C44H
003A45H 003C45H
003A46H 003C46H
003A47H 003C47H
003A48H 003C48H
003A49H 003C49H

003A4AH 003C4AH
003A4BH 003C4BH
003A4CH 003C4CH
003A4DH 003C4DH
003A4EH 003C4EH

003A4FH 003C4FH
003A50H 003C50H
003A51H 003C51H
003A52H 003C52H
003A53H 003C53H
003A54H 003C54H
003A55H 003C55H
003A56H 003C56H
003A57H 003C57H
003A58H 003C58H
003A59H 003C59H

003A5AH 003C5AH
003A5BH 003C5BH
003A5CH 003C5CH
003A5DH 003C5DH
003A5EH 003C5EH

003A5FH 003C5FH

ID register 7 IDR7 R/W

ID register 8 IDR8 R/W

ID register 9 IDR9 R/W

ID register 10 IDR10 R/W

ID register 11 IDR11 R/W

ID register 12 IDR12 R/W

ID register 13 IDR13 R/W

ID register 14 IDR14 R/W

ID register 15 IDR15 R/W

Register Abbreviation Access Initial Value

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

XXXXXXXX XXXXXXXX

XXXXX--- XXXXXXXXB

B

B

B

B

B

B

B

B

B

32

MB90540/540G/545/545G Series

Address

CAN0 CAN1

003A60

H 003C60H

003A61H 003C61H
003A62H 003C62H
003A63H 003C63H
003A64H 003C64H
003A65H 003C65H
003A66H 003C66H
003A67H 003C67H
003A68H 003C68H
003A69H 003C69H

003A6AH 003C6AH
003A6BH 003C6BH
003A6CH 003C6CH
003A6DH 003C6DH
003A6EH 003C6EH

003A6FH 003C6FH

List of Message Buffers (DLC Registers and Data Registers

)

Register Abbreviation Access Initial Value

DLC register 0 DLCR0 R/W ----XXXXB

DLC register 1 DLCR1 R/W ----XXXXB

DLC register 2 DLCR2 R/W ----XXXXB

DLC register 3 DLCR3 R/W ----XXXXB

DLC register 4 DLCR4 R/W ----XXXXB

DLC register 5 DLCR5 R/W ----XXXXB

DLC register 6 DLCR6 R/W ----XXXXB

DLC register 7 DLCR7 R/W ----XXXXB

003A70H 003C70H
003A71

H 003C71H

003A72H 003C72H
003A73H 003C73H
003A74H 003C74H
003A75H 003C75H
003A76H 003C76H
003A77H 003C77H
003A78H 003C78H
003A79H 003C79H

003A7AH 003C7AH
003A7BH 003C7BH
003A7CH 003C7CH
003A7DH 003C7DH
003A7EH 003C7EH

003A7FH 003C7FH
003A80H

to

003A87

H

003C80H

to

003C87

DLC register 8 DLCR8 R/W ----XXXX

DLC register 9 DLCR9 R/W ----XXXXB

DLC register 10 DLCR10 R/W ----XXXXB

DLC register 11 DLCR11 R/W ----XXXXB

DLC register 12 DLCR12 R/W ----XXXXB

DLC register 13 DLCR13 R/W ----XXXXB

DLC register 14 DLCR14 R/W ----XXXXB

DLC register 15 DLCR15 R/W ----XXXXB

XXXXXXXX

Data register 0 (8 bytes) DTR0 R/W

H

XXXXXXXX

B

to

B

(Continued)

33

MB90540/540G/545/545G Series

(Continued)

Address

CAN0 CAN1

003A88

H

003C88H

to

003A8F
003A90H

H

003C8F
003C90H

to

003A97
003A98H

H

003C97
003C98H

to

003A9F
003AA0H

H

003C9F

003CA0H

to

003AA7
003AA8H

H

003CA7
003CA8H

to

003AAF

003AB0H

H

003CAF
003CB0H

to

003AB7
003AB8H

H

003CB7
003CB8H

to

003ABF
003AC0H

H

003CBF
003CC0H

to

003AC7
003AC8H

H

003CC7
003CC8H

to

003ACF
003AD0H

H

003CCF
003CD0H

to

003AD7
003AD8H

H

003CD7
003CD8H

to

003ADF

003AE0H

H

003CDF
003CE0H

to

003AE7
003AE8H

H

003CE7
003CE8H

to

003AEF

003AF0H

H

003CEF

003CF0H

to

003AF7
003AF8H

H

003CF7
003CF8H

to

003AFF

H

003CFF

to

to

to

to

to

to

to

to

to

to

to

to

to

to

to

Data register 1 (8 bytes) DTR1 R/W

H

Data register 2 (8 bytes) DTR2 R/W

H

Data register 3 (8 bytes) DTR3 R/W

H

Data register 4 (8 bytes) DTR4 R/W

H

Data register 5 (8 bytes) DTR5 R/W

H

Data register 6 (8 bytes) DTR6 R/W

H

Data register 7 (8 bytes) DTR7 R/W

H

Data register 8 (8 bytes) DTR8 R/W

H

Data register 9 (8 bytes) DTR9 R/W

H

Data register 10 (8 bytes) DTR10 R/W

H

Data register 11 (8 bytes) DTR11 R/W

H

Data register 12 (8 bytes) DTR12 R/W

H

Data register 13 (8 bytes) DTR13 R/W

H

Data register 14 (8 bytes) DTR14 R/W

H

Data register 15 (8 bytes) DTR15 R/W

H

Register Abbreviation Access Initial Value

XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

34

INTERRUPT MAP

■■■■

MB90540/540G/545/545G Series

Interrupt cause

2

EI

clear

OS

Interrupt vector Interrupt control register

Number Address Number Address

Reset N/A #08 FFFFDC
INT9 instruction N/A #09 FFFFD8
Exception N/A #10 FFFFD4
CAN 0 RX N/A #11 FFFFD0H
CAN 0 TX/NS N/A #12 FFFFCCH
CAN 1 RX N/A #13 FFFFC8H
CAN 1 TX/NS N/A #14 FFFFC4H
External Interrupt INT0/INT1 *1 #15 FFFFC0H
Time Base Timer N/A #16 FFFFBCH
16-bit Reload Timer 0 *1 #17 FFFFB8H
8/10-bit A/D Converter *1 #18 FFFFB4H
I/O Timer N/A #19 FFFFB0H
External Interrupt INT2/INT3 *1 #20 FFFFACH
Serial I/O *1 #21 FFFFA8H
8/16-bit PPG 0/1 N/A #22 FFFFA4H
Input Capture 0 *1 #23 FFFFA0H
External Interrupt INT4/INT5 *1 #24 FFFF9CH

H 
H 
H 

ICR00 0000B0H

ICR01 0000B1H

ICR02 0000B2H

ICR03 0000B3H

ICR04 0000B4H

ICR05 0000B5H

ICR06 0000B6H

Input Capture 1 *1 #25 FFFF98H
8/16-bit PPG 2/3 N/A #26 FFFF94H
External Interrupt INT6/INT7 *1 #27 FFFF90H
Watch Timer N/A #28 FFFF8CH
8/16-bit PPG 4/5 N/A #29 FFFF88H
Input Capture 2/3 *1 #30 FFFF84H
8/16-bit PPG 6/7 N/A #31 FFFF80H
Output Compare 0 *1 #32 FFFF7CH
Output Compare 1 *1 #33 FFFF78H
Input Capture 4/5 *1 #34 FFFF74H
Output Compare 2/3 - Input Capture 6/7 *1 #35 FFFF70H
16-bit Reload Timer 1 *1 #36 FFFF6CH
UART 0 RX *2 #37 FFFF68H
UART 0 TX *1 #38 FFFF64H
UART 1 RX *2 #39 FFFF60H
UART 1 TX *1 #40 FFFF5CH
Flash Memory N/A #41 FFFF58H
Delayed interrupt N/A #42 FFFF54H

ICR07 0000B7H

ICR08 0000B8H

ICR09 0000B9H

ICR10 0000BAH

ICR11 0000BBH

ICR12 0000BCH

ICR13 0000BDH

ICR14 0000BEH

ICR15 0000BFH

35

MB90540/540G/545/545G Series

2

*1 : The interrupt request flag is cleared by the EI
*2 : The interrupt request flag is cleared by the EI

OS interrupt clear signal.

2

OS interrupt clear signal. A stop request is available.

Note :

• N/A : The interrupt request flag is not cleared by the EI

2

OS interrupt clear signal.

• For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags
are cleared by the EI

• At the end of EI
interrupt number. If one interrupt flag starts the EI
hardware ev ent, the later e v ent is lost because the flag is cleared by the EI
event. So it is recommended not to use the EI

2

•If EI

OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control register
(ICR) is asserted. This means that different interrupt sources share the same EI
be unique for each interrupt source. For this reason, when one interr upt source uses the EI

2

OS interrupt clear signal.

2

OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same

2

OS and in the meantime another interrupt flag is set by a

2

OS clear signal caused by the first

2

OS for this interrupt number.

2

OS Descriptor which should

2

OS, the other

interrupt should be disabled.

36

ELECTRICAL CHARACTERISTICS

■■■■

MB90540/540G/545/545G Series

1. Absolute Maximum Ratings

Parameter Symbol

Power supply voltage

Input voltage V
Output voltage V

AVRH,

AVRL

Value

Min Max

V

CC VSS − 0.3 VSS + 6.0 V

AV

CC VSS − 0.3 VSS + 6.0 V VCC = AVCC *1

VSS − 0.3 VSS + 6.0 V

I VSS − 0.3 VSS + 6.0 V *2

O VSS − 0.3 VSS + 6.0 V *2

Units Remarks

AVCC ≥ AVRH/AVRL,
AVRH ≥ AVRL *1

(VSS = AVSS = 0.0 V)

Maximum clamp current ICLAMP − 2.0 + 2.0 mA *6
Total maximum clamp current ∑| I
“L” level max output current I

CLAMP |  20 mA *6

OL  15 mA *3

“L” level avg. output current IOLAV  4mA *4
“L” level max overall output current ∑I
“L” level avg. overall output current ∑I

OL  100 mA

OLAV  50 mA *5

“H” level max output current IOH −15 mA *3
“H” level avg. output current I
“H” level max overall output current ∑I

OHAV −4mA *4

OH −100 mA

“H” level avg. overall output current ∑IOHAV −50 mA *5
Power consumption P

Operating temperature T

D

A

 500 mW Flash device
 400 mW Mask ROM

−40 +85 °C MB90F543/F549

−40 +105 °C

Other than MB90F543/F549

Storage temperature TSTG −55 +150 °C

*1 : AV

CC, AVRH, AVRL should not exceed VCC. Also, AVRH, AVRL should not exceed AVCC, and AVRL does not

exceed AVRH.

*2 : V

I and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum

current to/from an input is limited by some means with external components, the I
V

I rating.

CLAMP rating supercedes the

*3 : The maximum output current is a peak value for a corresponding pin.
*4 : Average output current is an average current value observed for a 100 ms period for a corresponding pin.
*5 : Total average current is an average current value observed for a 100 ms period for all corresponding pins.
*6 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77,

P80 to P87, P90 to P97, PA0

• Use within recommended operating conditions.

• Use at DC voltage (current) .

• The +B signal should always be applied with a limiting resistance placed between the +B signal and the

microcontroller.

• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the V

CC pin, and this may affect

other devices.

• Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is
provided from the pins, so that incomplete operation may result.

• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on result.

(Continued)

37

MB90540/540G/545/545G Series

(Continued)

• Care must be taken not to leave the +B input pin open.

• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input
pins, etc.) cannot accept +B signal input.

• Sample recommended circuits :

• Input/Output Equivalent circuits

Protective diode

VCC

Limiting

resistance

+B input (0 V to 16 V)

R

Note : Average output current = operating current × operating efficiency
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

P-ch

N-ch

38

MB90540/540G/545/545G Series

2. Recommended Conditions

Parameter Symbol

Value

Min Typ Max

Units Remarks

(VSS = AVSS = 0.0 V)

Under normal operation : Other than

Power supply voltage

V

AV

CC,

CC

4.5 5.0 5.5 V

3.5 5.0 5.5 V

MB90F548GL(S)/543G(S)/547G(S)/
548G(S)

Under normal operation :
MB90F548GL(S)/543G(S)/547G(S)/
548G(S)

3.0  5.5 V Maintain RAM data in stop mode

Smooth capacitor C
Operating temperature T

S 0.022 0.1 1.0 µF*

A

−40 +85 °C MB90F543/F549

−40 +105 °C Other than MB90F543/F549

*: Use a ceramic capacitor or a capacitor of better 4. AC characteristics. The b ypass capacitor should be g reater

than this capacitor.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

• C Pin Connection Diagram

C

C

S

39

MB90540/540G/545/545G Series

3. DC Characteristics

(MB90F543/F549: VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S):

V

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Parameter

Input H
voltage

Input L
voltage

Output H
voltage

Output L
voltage

Input
leak cur­rent

Pull-up
resis­tance

Pull­down
resis­tance

Sym-

Pin name Condition

bol

Min Typ Max

CMOS

IHS

V

hysteresis

 0.8 V

input pin
TTL input

V

V

IHM

IH

pin
MD input

pin

 2.0 V

 VCC − 0.3  VCC + 0.3 V

CMOS

ILS

V

hysteresis

 V

CC − 0.3  0.2 VCC V

input pin
TTL input

V

IL

pin
MD input

V

ILM

pin
All output

V

OH

pins
All output

V

OL

pins

I

IL 

VCC = 4.5 V,
I

OH = −4.0 mA

VCC = 4.5 V,
I

OL = 4.0 mA

VCC = 5.5 V,
V

SS < VI < VCC

0.8 V

 VSS − 0.3  VCC + 0.3 V

VCC − 0.5 V

0.4 V

−5  5 µA

P00 to
P07,
P10 to
P17,

R

P20 to

UP

 25 50 100 kΩ
P27,
P30 to
P37,
RST

R

DO

MD2  25 50 100 kΩ

WN

Value

CC  VCC + 0.3 V

Units Remarks

(Continued)

40

MB90540/540G/545/545G Series

(Continued)

(MB90F543/F549: VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

(MB90543G(S)/547G(S)/548G(S)/F548GL(S): V

(Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S):

Parameter

Power
supply
current*

Input
capacity

Sym-

Pin name Condition

bol

Internal frequency : 16 MHz,
At normal operating

I

CC

Internal frequency : 16 MHz,
At Flash programming/eras­ing

I

CCS

Internal frequency : 16 MHz,
At sleep mode

VCC = 5.0 V ± 1%,

I

CTS

Internal frequency : 2 MHz,
At pseudo timer mode

VCC

CCL

I

CCLS

I

I

CCT

I

CCH1 At stop, TA = 25 °C  520µA

I

CCH2

Other than
AV

CC, AVSS,

AVRH,

IN

C

AVRL, C,
V

CC, VSS

Internal frequency : 8 kHz,
At sub operation, T

Internal frequency : 8 kHz,
At sub sleep, T

A = 25 °C

Internal frequency : 8 kHz,
At timer mode, T

At hardware standby mode,
T

A = 25 °C

515pF

CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

V

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Min Typ Max

Units Remarks

 40 55 mA

 50 70 mA Flash device

 12 20 mA
 300 600 µA

 600 1100 µA MB90F548GL (S) only
 200 400 µA

MB90543G(S)/
547G(S)/548(S) only

 400 750 µA MB90F548GL only

A = 25 °C

 50 100 µAMask ROM
 150 300 µA Flash device

 15 40 µA

A = 25 °C

 725µA

 50 100 µA

* : The power supply current testing conditions are when using the external clock.

41

MB90540/540G/545/545G Series

4. AC Characteristics

(1) Clock Timing

(MB90F543/F549: V

(MB90543G(S)/547G(S)/548G(S)/F548GL(S): V

(Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S):

Parameter Symb ol Pin name

C X0, X1

f

Oscillation frequency

f

CL X0A, X1A  32.768  kHz

CYL X0, X1

t

Oscillation cycle time

t

LCYL X0A, X1A  30.5 µs

PWH, PWL X0 10 ns

Input clock pulse width

P

WLH, PWLL X0A  15.2 µs

CC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

V

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Min Typ Max

3  16 MHz V
3  5MHz

62.5  333 ns V
200  333 ns

Units Remarks

CC = 5.0 V±10%

V

CC<4.5 (MB90F548GL(S)/

543G(S)/547G(S)/548G(S))

CC = 5.0 V±10%

V

CC<4.5 (MB90F548GL(S)/

543G(S)/547G(S)/548G(S))

Duty ratio is about 30% to
70%.

Input clock rise and fall
time

Machine clock frequency

Machine clock cycle time

• Clock Timing

X0A

t

CR, tCF X0  5 ns When using external clock

CP  1.5  16 MHz When using main clock

f

fLCP 8.192  kHz When using sub-clock

CP  62.5  666 ns When using main clock

t

t

LCP 122.1 µs When using sub-clock

tCYL

X0

PWH PWL

tCF tCR

tLCYL

PWLH PWLL

tCF tCR

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

42

• Guaranteed PLL operation range

5.5

MB90540/540G/545/545G Series

Guaranteed operation range
(Other than MB90F548GL(S)/543G(S)/547G(S)/548G(S))

Guaranteed operation range
(MB90F548GL(S)/543G(S)/547G(S)/548G(S))

Power supply voltage

CC

V

(V)

4.5

3.5

Guaranteed PLL operation range
( Other than MB90F548GL(S)/543G(S)/547G(S)/548G(S))

1.5

Machine clock f

• External clock frequency and Machine clock frequency

×4 ×3 ×2 ×1

Machine clock

CP

(MHz)

f

16

12

9
8

Guaranteed PLL operation range
(MB90F548GL(S)/543G(S)/547G(S)/548G(S))

816

CP

(MHz)

×1/2

(PLL off)

4

34 8

External clock f

C

(MHz)

16

43

MB90540/540G/545/545G Series

AC characteristics are set to the measured reference voltage values below.

• Input signal waveform

Hysteresis Input Pin

0.8 VCC

0.2 VCC

TTL Input Pin

2.0 V

0.8 V

• Output signal waveform

Output Pin

2.4 V

0.8 V

44

MB90540/540G/545/545G Series

(2) Clock Output Timing

(MB90F543/F549 : V

(MB90543G(S)/547G(S)/548G(S)/F548GL(S): V

(Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S):

Parameter Symbol Pin name Condition

Cycle time t
CLK↑ →CLK↓ t

CYC

CHCL 20  ns

CHCL

t

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

V

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, T A = −40 °C to +105 °C)

Value

Units Remarks

Min Max

62.5  ns

CLK VCC = 5 V ± 10%

tCYC

CLK

2.4 V 2.4 V

0.8 V

(3) Reset and Hardware Standby Input Timing

(MB90F543/F549 : VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S):

V

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, T A = −40 °C to +105 °C)

Parameter Symbol

Pin

name

Value

Units Remarks

Min Max

4 tCP  ns Under normal operation

Oscillation time of
oscillator + 4 t

CP

 ms In stop mode

In pseudo timer mode

Reset input time t

100 µs

RSTL RST

(MB90543G (S) /547G (S) /
548G (S) )

In pseudo timer mode

4 t

CP  ns

(Other than MB90543G (S) /
547G (S) /548G (S) )

In sub-clock mode,

2 t

CP µs

sub-sleep mode,
timer mode

Hardware standby input time t

HSTL HST 4 tCP  ns Under normal operation

Note : “t

cp” represents one cycle time of the machine clock.

Oscillation time of oscillator is time that amplitude reached the 90%. In the crystal oscillator, the oscillation
time is between sev eral ms to tens of ms. In F AR/ceramic oscillator, the oscillation time is betw een handreds
of µs to several ms. In the external clock, the oscillation time is 0 ns.
Any reset can not fully initialize the Flash Memory if it is performing the automatic algorithm.

45

MB90540/540G/545/545G Series

• In under normal operation, pseudo timer mode, sub-clock mode, sub-sleep mode, timer mode

tRSTL, tHSTL

RST

• In stop mode

HST

RST

X0

90% of
amplitude

0.2 VCC

tRSTL

0.2 VCC 0.2 VCC

0.2 VCC

Internal operation clock

Internal reset

Oscillation time of
oscillator

4 tCP

Oscillation setting time

Instruction execution

46

MB90540/540G/545/545G Series

(4) Power On Reset

(MB90F543/F549 : V

(MB90543G(S)/547G(S)/548G(S)/F548GL(S): V

(Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S):

Parameter Symbol

Power on rise time t
Power off time t

* : V

CC must be kept lower than 0.2 V before power-on.

R VCC

OFF VCC 50  ms Due to repetitive operation

Pin

name

Condition

Note : • The above values are used for creating a power-on reset.

• Some registers in the device are initialized only upon a po wer-on reset. To initialize these register, turn on

the power supply using the above values.

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

V

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, T A = −40 °C to +105 °C)

Min Max

0.05 30 ms *



Value

Units Remarks

tR

VCC

Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to
raise the voltage smoothly to suppress fluctuations as shown below.
In this case, change the supply voltage with the PLL clock not used. If the voltage drop is
1 V or fewer per second, however, you can use the PLL clock.

VCC

3.0 V
VSS

2.7 V

RAM data being held

0.2 V 0.2 V0.2 V

tOFF

It is recommended to keep the
rising speed of the supply voltage
at 50 mV/ms or slower.

47

MB90540/540G/545/545G Series

(5) Bus Timing (Read)

(MB90F543/F549 : V

(MB90543G(S)/547G(S)/548G(S)/F548GL(S): V

(Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S):

Parameter Symbol Pin name Condition

ALE pulse width t

LHLL ALE

ALE,

Valid address→ALE↓time t

AVLL

A16 to A23,
AD00 to
AD15

CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

CC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

V

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, T A = −40 °C to +105 °C)

Value

Units Remarks

Min Max

tCP/2 − 20  ns

t

CP/2 − 20  ns

ALE↓→Address valid time t

LLAX

ALE, AD00
to AD15

tCP/2 − 15  ns

A16 toA23,

Valid address→RD

↓time tAVRL

AD00 to

tCP − 15  ns

AD15, RD

Valid address→Valid data
input

RD

pulse width tRLRH RD 3 tCP/2 − 20  ns

t

AVDV

RD↓→Valid data input tRLDV

RD

↑→Data hold time tRHDX

RD

↓→ALE↑time tRHLH RD, ALE tCP/2 − 15  ns

RD

↑→Address valid time tRHAX

A16 to A23,
AD00 to
AD15

RD, AD00 to
AD15

RD, AD00 to
AD15

RD, A16 to
A23



 5 t

CP/2 − 60 ns

 3 tCP/2 − 60 ns

0  ns

tCP/2 − 10  ns

A16 to A23,

Valid address→CLK↑time t

AVCH

AD00 to

t

CP/2 − 20  ns

AD15, CLK

RD

↓→CLK↑time tRLCH RD, CLK tCP/2 − 20  ns

ALE↓→RD

48

↓time tLLRL ALE, RD tCP/2 − 15  ns

• Bus Timing (Read)

MB90540/540G/545/545G Series

CLK

ALE

RD

A16 to A23

AD00 to AD15

2.4 V

0.8 V

2.4 V

tAVCH

2.4 V

2.4 V

tLHLL

tAVLL

2.4 V

0.8 V

0.8 V

tLLAX

tLLRL

tAVRL tRLDV

tAVDV

Address Read data

2.4 V

0.8 V

tRLCH

2.4 V

0.8 V

tRLRH

0.8 VCC

0.2 V

CC

tRHLH

2.4 V

2.4 V

tRHAX

2.4 V

0.8 V

tRHDX

0.8 VCC

0.2 VCC

49

MB90540/540G/545/545G Series

(6) Bus Timing (Write)

(MB90F543/F549 : V

(MB90543G(S)/547G(S)/548G(S)/F548GL(S): V

CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S):

Parameter Symbol Pin name Condition

A16 to A23

Valid address→WR

↓time tAVWL

AD00 to AD15,
WR

WR

pulse width tWLWH WR 3 tCP/2 − 20  ns

CC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

V

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, T A = −40 °C to +105 °C)

Value

Min Max

CP − 15  ns

t

Units Remarks

Valid data output→WR

↑time tDVWH

WR↑→Data hold time tWHDX

WR

↑→Address valid time tWHAX

WR

↑→ALE↑time tWHLH WR, ALE tCP/2 − 15  ns

AD00 to AD15,
WR

AD00 to AD15,
WR

A16 to A23,
WR

3 tCP/2 − 20  ns



20  ns

tCP/2 − 10  ns

WR↑→CLK↑time tWLCH WR, CLK tCP/2 − 20  ns

• Bus Timing (Write)

tWLCH

CLK

ALE

tAVWL

2.4 V

tWHLH

tWLWH

2.4 V

50

WR (WRL, WRH)

A16 to A23

AD00 to AD15

2.4 V

0.8 V

2.4 V

0.8 V

0.8 V

tDVWH

2.4 V

Address Write data

0.8 V

2.4 V

tWHAX

2.4 V

0.8 V

tWHDX

2.4 V

0.8 V

MB90540/540G/545/545G Series

(7) Ready Input Timing

(MB90F543/F549 : V

(MB90543G(S)/547G(S)/548G(S)/F548GL(S): V

CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S):

Parameter Symbol Pin name Condition

RDY setup time t
RDY hold time t

RYHS RDY
RYHH RDY 0  ns

Note : If the RDY setup time is insufficient, use the auto-ready function.

• Ready Input Timing

CC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

V

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, T A = −40 °C to +105 °C)



Value

Units Remarks

Min Max

45  ns

CLK

ALE

RD/WR

RDY
no WAIT is used.

RDY
When WAIT is used
(1 cycle).

2.4 V

tRYHS tRYHH

0.8 V

CC

0.2 VCC

0.8 VCC

51

MB90540/540G/545/545G Series

(8) Hold Timing

(MB90F543/F549 : V

(MB90543G(S)/547G(S)/548G(S)/F548GL(S): V

CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S):

Parameter Symbol Pin name Condition

Pin floating→HAK↓time tXHAL HAK
HAK

↑time→Pin valid time tHAHV HAK tCP 2 tCP ns

CC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

V

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, T A = −40 °C to +105 °C)

Value

Min Max

30 t



Units Remarks

CP ns

Note : There is more than 1 cycle from the time HRQ is read to the time the HAK

is changed.

• Hold Timing

HAK

Each pin

tXHAL

2.4 V

0.8 V

0.8 V

High impedance

2.4 V

tHAHV

2.4 V

0.8 V

(9) UART0/1, Serial I/O Timing

(MB90F543/F549 : V

CC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S):

V

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, T A = −40 °C to +105 °C)

Value

Parameter Symbol Pin name Condition

Units Remarks

Min Max

Serial clock cycle time t

SCYC SCK0 to SCK2

SCK↓→SOT delay time tSLOV

Valid SIN→SCK↑ t

IVSH

SCK0 to SCK2,
SOT0 to SOT2

SCK0 to SCK2,
SIN0 to SIN2

Internal clock opera­tion output pins are

L = 80 pF + 1 TTL.

C

8 t

CP  ns

−80 80 ns

100  ns

SCK↑→Valid SIN hold time t

SHIX

SCK0 to SCK2,

SIN0 to SIN2
Serial clock “H” pulse width tSHSL SCK0 to SCK2
Serial clock “L” pulse width t

SCK↓→SOT delay time t

Valid SIN→SCK↑ t

SCK↑→Valid SIN hold time t

SLSH SCK0 to SCK2 4 tCP  ns

SLOV

IVSH

SHIX

SCK0 to SCK2,

SOT0 to SOT2

SCK0 to SCK2,

SIN0 to SIN2

SCK0 to SCK2,

SIN0 to SIN2

Note : • AC characteristic in CLK synchronized mode.

• C

L is load capacity value of pins when testing.

• For t

CP (Machine clock cycle time) , refer to “ (1) Clock Timing”.

52

External clock oper­ation output pins are
C

L = 80 pF + 1 TTL.

60  ns

CP  ns

4 t

 150 ns

60  ns

60  ns

• Internal Shift Clock Mode

MB90540/540G/545/545G Series

SCK

SOT

SIN

• External Shift Clock Mode

SCK

SOT

tSCYC

2.4 V

0.8 V 0.8 V
tSLOV

2.4 V

0.8 V

tIVSH tSHIX

0.8 V

CC

0.2 VCC

tSLSH tSHSL

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC
tSLOV

2.4 V

0.8 V

0.8 VCC

0.2 VCC

SIN

tIVSH tSHIX

0.8 V

CC

0.2 VCC

0.8 VCC

0.2 VCC

53

MB90540/540G/545/545G Series

(10) Timer Input Timing

(MB90F543/F549 : V

(MB90543G(S)/547G(S)/548G(S)/F548GL(S): V

(Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S):

Parameter Symbol Pin name Condition

TIWH TIN0, TIN1

t

Input pulse width

t

TIWL IN0 to IN7

• Timer Input Timing

0.8 VCC 0.8 VCC

tTIWH tTIWL

CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

CC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

V

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, T A = −40 °C to +105 °C)

 4 t

0.2 VCC 0.2 VCC

Value

Units Remarks

Min Max

CP  ns

(11) Timer Output Timing

(MB90F543/F549 : V

CC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

(Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S):

V

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, T A = −40 °C to +105 °C)

Value

Parameter Symbol Pin name Condition

Units Remarks

Min Max

CLK↑→T

OUT change time tTO

TOT0 to TOT1,
PPG0 to PPG3

 30  ns

• Timer Output Timing

2.4 V

CLK

T

OUT

2.4 V

0.8 V

t

TO

54

MB90540/540G/545/545G Series

(12) Trigger Input Timing

(MB90F543/F549 : V

(MB90543G(S)/547G(S)/548G(S)/F548GL(S): V

(Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S):

Parameter Symbol Pin name Condition

Input pulse width

• Trigger Input Timing

TRGH

t

tTRGL

INT0 to INT7,
ADTG

0.8 VCC 0.8 VCC

tTRGH tTRGL

CC = 4.5 to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

V

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, T A = −40 °C to +105 °C)

Value

Units Remarks

Min Max

5 t

CP  ns Under nomal operation



1 µs In stop mode

0.2 VCC 0.2 VCC

55

MB90540/540G/545/545G Series

5. A/D Converter

• Electrical Characteristics

(MB90F543/F549 : VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, 3.0 V ≤ AVRH − AVRL, TA = −40 °C to +85 °C)

(Other than MB90F543/F549 : VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, 3.0 V ≤ AVRH − AVRL, TA = −40 °C to +105 °C)

Parameter Symbol Pin name

Min Typ Max

Resolution    10 bit
Conversion error   ±5.0 LSB
Nonlinearity error    ±2.5 LSB

Value

Units Remarks

Differential nonlinearity
error

Zero transition voltage V

Full scale transition voltage V

   ±1.9 LSB

OT AN0 to AN7

FST AN0 to AN7

AVRL − 3.5

LSB

AVRH − 6.5

LSB

Compare time 352 t

Sampling time 64 t

Analog port input current I
Analog input voltage range V

AIN AN0 to AN7 −1  1 µA

AIN AN0 to AN7 AVRL  AVRH V

 AVRH AVRL + 2.7  AV

Reference voltage range

 AVRL 0  AVRH − 2.7 V

A AVCC  5  mA

I

Power supply current

I

AH AVCC  5 µA*

 400 600 µA Flash device

I

Reference voltage supply
current

Offset between input
channels

R AVRH

 140 260 µA Mask ROM

RH AVRH  5 µA*

I
 AN0 to AN7  4LSB

AVRL + 0.5

LSB

AVRH − 1.5

LSB

CP ns

CP ns

AVRL + 4.5

LSB

AVRH + 1.5

LSB

CC V

mV

mV

Internal
frequency :
16 MHz

Internal
frequency :
16 MHz

VCC = AVCC =

5.0 V ± 1%

* : When not using an A/D converter, this is the current (V

CC = AVCC = AVRH = 5.0 V) when the CPU is stopped.

Note: The functionality of the A/D converter is only guaranteed for VCC = 5.0 V ± 10 % (also for MB90543G(S)/

547G (S) /548GL (S) /F548GL (S) ) .

56

MB90540/540G/545/545G Series

• A/D Converter Glossary

Resolution : Analog changes that are identifiable with the A/D converter
Linearity error : The deviation of the straight line connecting the zero transition point (“00 0000 0000” ←→ “00

0000 0001”) with the full-scale transition point (“11 1111 1110”
conversion characteristics

Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the

theoretical value

Total error : The total error is defined as a difference between the actual v alue and the theoretical value, which

includes zero-transition error/full-scale transition error and linearity error.

Total error

3FF

←→ “11 1111 1111”) from actual

Actual conversion
Value

0.5 LSB

1024

Analog input

[V]

Digital output

1 LSB = (Theoretical value)

3FE

3FD

004

003

002

001

AVRL AVRH

AVRH − AVRL

VOT (Theoretical value) = AVRL + 0.5 LSB [V]

VFST (Theoretical value) = AVRH − 1.5 LSB [V]

NT − {1 LSB × (N − 1) + 0.5 LSB}

Total error for digital output N =

V

(measured value)

Actual conversion
characteristics

Theoretical
characteristics

1 LSB

0.5 LSB

{1 LSB × (N − 1) + 0.5 LSB}

V

NT

[LSB]

NT : Voltage at a transition of digital output from (N − 1) to N

V

(Continued)

57

MB90540/540G/545/545G Series

(Continued)

Linearity error Differential linearity error

3FF

3FE

3FD

004

Digital output

003

002

001

Linearity error of
digital output N

Actual conversion
value

{1 LSB × (N − 1) + VOT }

(measured value)

VOT

AVRL AVRH AVRL AVRH

NT − {1 LSB × (N − 1) + VOT}

V

=

Differential linearity error
of digital N

V

FST − VOT

1 LSB

=

1022

[V]

Theorential characteristics

N + 1

Actual conversion value

VFST

(measured value)

N

V

NT

Actual conversion
characteristics

Theoretical
characteristics

Analog input Analog input

1 LSB

V (

N + 1) T − VNT

=

1 LSB

− 1 LSB [LSB]

N − 1

Digital output

N − 2

[LSB]

Acturel conversion
value

V (N + 1) T

(measured value)

(measured value)

VNT

V

OT : Voltage at transition of digital output from “000H” to “001H”

V

FST : Voltage at transition of digital output from “3FEH” to “3FFH”

• Notes on Using A/D Converter

Select the output impedance value for the e xternal circuit of analog input according to the following conditions, :

• Output impedance values of the external circuit of 15 kΩ or lower are recommended.

• When capacitors are connected to external pins, the capacitance of several thousand times the internal
capacitor value is recommended to minimized the eff ect of v oltage distribution between the e xternal capacitor
and internal capacitor.

Note : When the output impedance of the external circuit is too high, the sampling period for analog voltages ma y

not be sufficient (sampling period = 4.00 µs @machine clock of 16 MHz) .

• Equipment of analog input circuit model

Comparator

Analog input

3.2 kΩ Max
30 pF Max

•Error

The smaller the | AVRH − AVRL |, the greater the error would become relatively.

58

MB90540/540G/545/545G Series

6. Flash Memory Program/Erase Characteristics

Value

Parameter Condition

Min Typ Max

Units Remarks

Sector erase time

T

Chip erase time 

Word (16 bit width)
programming time

Erase/Program cycle  10,000 cycle

A = + 25 °C

V

CC = 5.0 V

 1 15 s Excludes 00H programming prior erasure

5  s

7  s

 16 3,600 µs Excludes system-level overhead

MB90F543/F543G (S) /
F548G (S) /F548GL (S)

MB90F549/F549G (S) /
F546G (S)

Excludes 00H
programming
prior erasure

59

MB90540/540G/545/545G Series

EXAMPLE CHARACTERISTICS

■■■■

• “H” level output voltage

• “L” level output voltage

VOH – IOH

5

4.5

4

3.5

3

2.5

VOH [V]

2

1.5

1

0.5

0

0 -10-8-6-4-2

(VCC = 4.5 V, Ta = +25˚C)

IOH [mA]

• “H” level input voltage/ “L” level input voltage
(Hysterisis inpiut)

0.9

0.8

0.7

0.6

0.5

VOL [V]

0.4

0.3

0.2

0.1

VOL – IOL

CC = 4.5 V,Ta = +25˚C)

(V

0

0

IOL [mA]

108642

60

5

4

3

Vin [V]

2

1

0

3 5.554.543.5

Vin – Vcc

(Ta = +25˚C)

VIH

VIL

6 6.5

Vcc [V]

• Power supply current (MB90549G)

MB90540/540G/545/545G Series

40

35

30

25

20

Icc [mA]

15

10

5

0

276543

Icc – Vcc

Vcc [V]

(Ta = +25˚C)

fcp = 16 MHz

fcp = 12 MHz

fcp = 10 MHz

fcp = 8 MHz

fcp = 4 MHz

fcp = 2 MHz

12

10

8

6

Icc [mA]

4

2

0

276543

Iccs – Vcc

(Ta = +25˚C)

fcp = 16 MHz

fcp = 12 MHz

fcp = 10 MHz

fcp = 8 MHz

fcp = 4 MHz

fcp = 2 MHz

Vcc [V]

600

500

400

300

ICTS [µA]

200

100

0

276543

ICTS – VCC

Vcc [V]

(Ta = +25˚C)

fcp = 2 MHz

100

90

80

70

60

50

ICCL [µA]

40

30

20

10

0

ICCL – VCC

(Ta = +25˚C)

fcp = 8 kHz

276543

Vcc [V]

61

MB90540/540G/545/545G Series

ICCLS [µA]

40

35

30

25

20

15

10

ICCLS – VCC

(Ta = +25˚C)

25

20

15

ICCT – VCC

(Ta = +25˚C)

ICCT [µA]

10

fcp = 8 kHz

5

5

0

2

6543

Vcc [V]

0

7

2

Vcc [V]

fcp = 8 kHz

6543

7

ICCH2 – VCC

100

90

85

70

60

50

ICCH2 [µA]

40

30

20

10

0

23456

(hardware standby, Ta = +25 ˚C)

VCC [V]

ICCH1 – VCC

20

18

16

14

12

10

ICCH1 [µA]

8

6

4

2

0

7

23456

(STOP, Ta = +25 ˚C)

7

VCC [V]

62

• Power supply current (MB90F549G)

MB90540/540G/545/545G Series

Icc – Vcc

45

40

35

30

25

20

ICC [mA]

15

10

5

0

23456

VCC [V]

fcp = 16 MHz

fcp = 12 MHz

(Ta = +25 ˚C)

fcp = 10 MHz

fcp = 8 MHz

fcp = 4 MHz

fcp = 2 MHz

Iccs – Vcc

14

12

10

8

6

ICC [mA]

4

2

0

7

23456

VCC [V]

(Ta = +25 ˚C)

fcp = 16 MHz

fcp = 12 MHz

fcp = 10 MHz

fcp = 8 MHz

fcp = 4 MHz

fcp = 2 MHz

7

ICTS – VCC

600

500

400

300

ICTS [µA]

200

100

0

23456

VCC [V]

(Ta = +25 ˚C)

fcp = 2 MHz

ICCL – VCC

300

250

200

150

ICCL [µA]

100

50

0

7

23456

VCC [V]

(Ta = +25 ˚C)

fcp = 8 kHz

7

63

MB90540/540G/545/545G Series

ICCLS – VCC

45

40

35

30

25

20

ICCLS [µA]

15

10

5

0

23456

VCC [V]

fcp = 8 MHz

(Ta = +25 ˚C)

ICCT – VCC

25

20

15

ICCT [µA]

10

5

0

7

23456

VCC [V]

(Ta = +25 ˚C)

fcp = 8 MHz

7

ICCH2 – VCC

100

90

85

70

60

50

ICCH2 [µA]

40

30

20

10

0

23456

(hardware standby, Ta = +25 ˚C)

VCC [V]

ICCH1 – VCC

20

18

16

14

12

10

ICCH1 [µA]

8

6

4

2

0

7

23456

(STOP, Ta = +25 ˚C)

7

VCC [V]

64

MB90540/540G/545/545G Series

ORDERING INFORMATION

■■■■

Part number Package Remarks

MB90F543PF
MB90F549PF
MB90F543GPF
MB90F543GSPF
MB90F546GPF
MB90F546GSPF
MB90F548GPF
MB90F548GSPF
MB90F548GLPF
MB90F548GLSPF
MB90F549GPF
MB90F549GSPF
MB90543GPF
MB90543GSPF
MB90547GPF
MB90547GSPF
MB90548GPF
MB90548GSPF
MB90549GPF
MB90549GSPF

MB90F543PFV
MB90F549PFV
MB90F543GPFV
MB90F543GSPFV
MB90F546GPFV
MB90F546GSPFV
MB90F548GPFV
MB90F548GSPFV
MB90F548GLSPFV
MB90F549GPFV
MB90F549GSPFV
MB90543GPFV
MB90543GSPFV
MB90547GSPFV
MB90547GSPFV
MB90548GPFV
MB90548GSPFV
MB90549GPFV
MB90549GSPFV

100-pin

100-pin

Plastic QFP

(FPT-100P-M06)

Plastic LQFP

(FPT-100P-M05)

65

MB90540/540G/545/545G Series

PACKAGE DIMENSIONS

■■■■

100-pin Plastic QFP

(FPT-100P-M06)

23.90±0.40(.941±.016)

20.00±0.20(.787±.008)

Note: Pins width and pins thickness include plating thickness.

5180

100-pin

Plastic LQFP

(FPT-100P-M05)

81

INDEX

100

1 30

0.65(.026)

"A"

C

2001 FUJITSU LIMITED F100008S-c-4-4

16.00±0.20(.630±.008)SQ

14.00±0.10(.551±.004)SQ

75

0.32±0.05

(.013±.002)

50

0.10(.004)

17.90±0.40
(.705±.016)

14.00±0.20
(.551±.008)

Details of "A" part

0.13(.005)

31

(Mounting height)

M

0.17±0.06

(.007±.002)

+0.35
–0.20

3.00

+.014
–.008

.118

0~8°

0.80±0.20

(.031±.008)

0.88±0.15

(.035±.006)

0.25(.010)

∗Pins width and pins thickness include plating thickness.

51

0.25±0.20

(.010±.008)

(Stand off)

Dimensions in mm (inches)

66

76 50

INDEX

100

125

0.50(.020)

C

2000 FUJITSU LIMITED F100007S-3c-5

0.20±0.05

(.008±.002)

0.08(.003)

0.08(.003)
Details of "A" part

+.008

+0.20

.059 –.004

–0.10

1.50
(Mounting height)

26

M

"A"

0.145±0.055

(.0057±.0022)

0°~8°

0.50±0.20

(.020±.008)

0.60±0.15

(.024±.006)

0.10±0.10

(.004±.004)

(Stand off)

0.25(.010)

Dimensions in mm (inches)

MB90540/540G/545/545G Series

FUJITSU LIMITED

All Rights Reserved.

The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.

The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.

The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.

F0207

FUJITSU LIMITED Printed in Japan

