FUJITSU MB90540, MB90545 DATA SHEET

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FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13703-1E

16-bit Proprietary Microcontroller

CMOS

F2MC-16LX MB90540/545 Series

MB90543/F543/549/F549/V540

DESCRIPTION

■

The MB90540/545 series with FULL-CAN and FLASH ROM is specially designed for automotive and industrial ap­plications. Its main features are two on board CAN Interfaces (one for MB90V545 series), which conform to V2.0
Part A and Part B, supporting very flexible message buffering. Thus, offering more functions than a normal full CAN
approach. In the new 0.5µm Technology Fujitsu now also offer FLASH-ROM. An internal voltage booster substitutes
the necessity of a second programming voltage.
An on board voltage regulator provides 3V to the internal MCU core. This constitutes a major advantage in terms of
EMI and power consumption.
The internal PLL clock frequency multiplier, provides an internal 62.5 nsec instruction cycle time with an external 4
MHz clock.
Further more it features 4 channels Output Capture Units and 8 channels Input Capture Units with a 16-bit free run­ning timer. Two UARTs constitute additional functionality for communication purposes.
The external bus interface allows full use to be made of the 16MByte address space.

FEATURES

■

• 16-bit core CPU : 4MHz external clock (16 MHz internal, 62.5 nsec instr. cycle time)

• 32 kHz Subsystem Clock

•New 0.5 µm CMOS Process Technology

• Internal voltage regulator supports 3V MCU core, offering low EMI and low power consumption figures

• FULL-CAN interfaces (MB90540 series : 2 interf., MB90545 series : 1 interf.); conform to Version 2.0 Par t A
and Part B, flexible message buffering (mailbox and FIFO buffering can be mixed)

(Continued)

PACKAGE

■

100-pin Plastic QFP 100-pin Plastic LQFP

(FPT-100P-M06) (FPT-100P-M05)

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MB90540/545 Series

(Continued)

• Powerful interrupt functions (8 progr. priority levels; 8 external interrupts)

2

•EI

OS - Automatic transfer function indep.of CPU

• 18-bit Time-base counter

• Watchdog Timer

• 2 full duplex UARTs; UAR T0 supports 10.4 KBaud (USA standard), UART 1 also for serial transfer with clock
(SCI) programmable

• Serial I/O: 1ch for synchronous data transfer

• A/D Converter: 8 ch. analog inputs (Resolution 10 bits or 8 bits)

• 16-bit reload timer * 2ch

• ICU (Input capture) 16bit * 8 ch

• OCU (Output capture) 16bit * 4ch

• 16-bit Programmable Pulse Generator 4ch

• External bus interface

• Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different
addressing modes; barrel shift; variety of pointers)

• 4-byte instruction execution queue

• signed multiply (16bit*16bit) and divide (32bit/16bit) instructions available

• Program Patch Function

• Fast Interrupt processing

• Low P ower Consumption - 10 different power saving modes: (Sleep, Stop, CPU intermittent mode, Hardware
standby,...)

• Package: 100-pin plastic QFP

Controller Area Network (CAN) - License of Robert Bosch GmbH

2

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MB90540/545 Series

PRODUCT LINEUP

■

The following table provides a quick outlook of the MB90540/545 Series

Features MB90V540 MB90F543/F549 MB90543/549

CPU F

2

MC-16LX CPU

System clock

ROM External
RAM 8 Kbytes 6 Kbytes 6 Kbytes

Technology

Operating
voltage range

Temperature
range

Package PGA-256 QFP100

UART0

UART1(SCI)

On-chip PLL clock multiplier ( × 1, × 2, × 3, × 4, 1/2 when PLL stop)
Minimum instruction execution time: 62.5 ns (4 MHz osc. PLL × 4)

Boot-block
Flash memory 128 K/256 Kbytes

0.5 µm CMOS with on-chip volt-

0.5 µm CMOS with on­chip voltage regulator
for internal power supply

Full duplex double buffer
Supports asynchronous/synchronous (with start/stop bit) transfer
Baud rate: 4808/5208/9615/10417/19230/38460/62500/500000 bps (asynchronous)
500K/1M/2Mbps (synchronous) at System clock = 16 MHz

Full duplex double buffer
Asynchronous (start-stop synchronized) and CLK-synchronous communication
Baud rate: 1202/2404/4808/9615/31250 bps (asynchronous)

62.5K/12K/250K/500K/1 Mbps (synchronous) at 6,8,10,12,16 MHz

age regulator for internal power
supply + Flash memory On-chip
charge pump for programming
voltage

5 V±10 %

− 40 to 85 °C

Mask ROM 128 K/256 Kbytes

0.5 µm CMOS with on-chip volt­age regulator for internal power
supply

Serial IO

A/D Converter

16-bit Reload
Timer
(2 channels)

16-bit IO Timer

16-bit
Output Compare
(4 channels)

Transfer can be started from MSB or LSB
Supports internal clock synchronized transfer and external clock synchronized transfer
Supports positive-edge and negative-edge clock synchronization
Baud rate : 31.25K/62.5K/125K/500K/1Mbps at System clock = 16MHz

10-bit or 8-bit resolution
8 input channels
Conversion time: 26.3 µs (per one channel)

Operation clock frequency: fsys/2
Supports External Event Count function

Signals an interrupt when overflow
Supports Timer Clear when a match with Output Compare(Channel 0)
Operation clock freq.: fsys/2

Signals an interrupt when a match with 16-bit IO Timer
Four 16-bit compare registers
A pair of compare registers can be used to generate an output signal

1

, fsys/23, fsys/25 (fsys = System clock frequency)

2

, fsys/24, fsys/26, fsys/28(fsys = System clock freq.)

(Continued)

3

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MB90540/545 Series

(Continued)

Features MB90V540 MB90F543/F549 MB90543/549

16-bit
Input Capture
(8 channels)

8/16-bit
Programmable
Pulse Generator
(4 channels)

Rising edge, falling edge or rising & falling edge sensitive
Four 16-bit Capture registers
Signals an interrupt upon external event

Supports 8-bit and 16-bit operation modes
Eight 8-bit reload counters
Eight 8-bit reload registers for L pulse width
Eight 8-bit reload registers for H pulse width
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler plus 8-bit reload counter
4 output pins
Operation clock freq.: fsys, fsys/2
(fsys = System clock frequency, fosc = Oscillation clock frequency)

1

, fsys/22, fsys/23, fsys/24 or 128µs@fosc=4MHz

CAN Interface
540 series:

2 channels
545 series:

1 channel
32 kHz Subclock Sub-clock for low power operation

External Interrupt
(8 channels)

IO Ports

Flash Memory 

Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering:
Full bit compare / Full bit mask / Two partial bit masks
Supports up to 1Mbps

Can be programmed edge sensitive or level sensitive
Virtually all external pins can be used as general purpose IO

All push-pull outputs and schmitt trigger inputs
Bit-wise programmable as input/output or peripheral signal

Supports automatic programming,
Embedded Algorithm

Write/Erase/Erase-Suspend/

Resume commands
A flag indicating completion of the
algorithm
Number of erase cycles: 10,000
times
Data retention time: 10 years
Flash Writer from Minato Electron­ics Inc.
Boot block configuration
Erase can be performed on each
block
Block protection with external pro­gramming voltage
Flash Security Feature:

protects the content of the

Flash memory

TM *1



*1:Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.

4

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MB90540/545 Series

PIN ASSIGNMENT

■

P20/A16
P21/A17
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23

P30/ALE

P32/WRL/WR

P33/WRH

P34/HRQ

P35/HAK

P36/RDY

P37/CLK
P40/SOT0
P41/SCK0

P42/SIN0
P43/SIN1

P44/SCK1

P45/SOT1
P46/SOT2
P47/SCK2

P50/SIN2
P51/INT4
P52/INT5

P31/RD

Vss

Vcc

(Top view)

P14/AD12

P13/AD11

P12/AD10

P11/AD09

P07/AD07

P06/AD06

P17/AD15

P16/AD14

P15/AD13

99989796959493929190898887868584838281

100

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

C

27
28
29
30

31323334353637383940414243444546474849

P10/AD08

P05/AD05

P04/AD04

P03/AD03

P02/AD02

P01/AD01

P00/AD00

VccX1X0

Vss

50

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

X0A
X1A
PA0
RST
P97/RX1
P96/TX1
P95/RX0
P94/TX0
P93/INT3
P92/INT2
P91/INT1
P90/INT0
P87/TOT1
P86/TIN1
P85/OUT1
P84/OUT0
P83/PPG3
P82/PPG2
P81/PPG1
P80/PPG0
P77/OUT3/IN7
P76/OUT2/IN6
P75/IN5
P74/IN4
P73/IN3
P72/IN2
P71/IN1
P70/IN0
HST
MD2

P54/INT7

P53/INT6

P55/ADTG

P63/AN3

P62/AN2

Vss

P65/AN5

P64/AN4

P67/AN7

P66/AN6

P56/TIN0

AVcc

AVss

AVR-

AVR+

P61/AN1

P60/AN0

P57/TOT0

MD0

MD1

(FPT-100P-M06)

5

MB90540/545 Series

PIN DESCRIPTION

■

No. Pin name Circuit type Function

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82
83

80
79

77 RST
52 HST C Hardware standby input

85 to 92

93 to 100

1 to 8

9

X0
X1

X0A
X1A

P00 to P07

AD00 to AD07

P10 to P17

AD08 to AD15

P20 to P27

A16 to A23

P30

ALE

A

(Oscillation)

A

(Oscillation)

B External reset request input

I

I

H

I

High speed oscillator input pins

Low speed oscillator input pins

General I/O port with programmable pullup. This function is enabled
in the single-chip mode.

I/O pins for 8 lower bits of the external address/data bus. This func­tion is enabled when the external bus is enabled.

General I/O port with programmable pullup. This function is enabled
in the single-chip mode.

I/O pins for 8 higher bits of the external address/data bus. This func­tion is enabled when the external bus is enabled.

General I/O port with programmable pullup. This function is enabled
in the single-chip mode.

Output pins for A16 to A23 ot the external address bus. This function
is enabled when the external bus is enabled.

General I/O port with programmable pullup. This function is enabled
in the single-chip mode.

Address latch enable output pin. This function is enabled when the
external bus is enabled.

10

12

13

P31

RD

P32

WRL

WR

P33

WRH

General I/O port with programmable pullup. This function is enabled

I

I

I

in the single-chip mode.
Read strobe output pin for the data bus. This function is enabled

when the external bus is enabled.
General I/O port with programmable pullup. This function is enabled

in the single-chip mode or when the WR
Write strobe output pin for the data bus. This function is enabled

when both the external bus and the WR
abled. WRL
16-bit access while WR is used to write-strobe 8 bits of the data bus
in 8-bit access.

General I/O port with programmable pullup. This function is enabled
in the single-chip mode or external bus 8-bit mode or when WRH
output is disabled.

Write strobe output pin for the 8 higher bits of the data bus. This
function is enabled when the external bus is enabled, when the ex­ternal bus 16-bit mode is selected, and when the WRH
enabled.

is used to write-strobe 8 lower bits of the data bus in

/WRL pin output is disabled.

/WRL pin output are en-

pin

output pin is

6

MB90540/545 Series

No. Pin name Circuit type Function

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14

15

16

17

18

P34

HRQ

P35

HAK

P36

RDY

P37

CLK

P40

SOT0

General I/O port with programmable pullup. This function is enabled

I

I

I

H

G

in the single-chip mode or when hold function is disabled.
Hold request input pin. This function is enabled when both the ex-

ternal bus and the hold function are enabled.
General I/O port with programmable pullup. This function is enabled

in the single-chip mode or when hold function is disabled.
Hold acknowledge output pin. This function is enabled when both

the external bus and the hold function are enabled.
General I/O port with programmable pullup. This function is enabled

in the single-chip mode or when the external ready function is dis­abled.

Ready input pin. This function is enabled when both the external
bus and the external ready function are enabled.

General I/O port with programmable pullup. This function is enabled
in the single-chip mode or when the clock output is disabled.

CLK output pin. This function is enabled when both the external bus
and CLK output are enabled.

General I/O port. This function is enabled when UART0 disables se­rial data output.

Serial data output pin for UART0. This function is enabled when
UART0 enables serial data output.

19

20

21

22

24

P41

SCK0

P42

SIN0

P43

SIN1

P44

SCK1

P45

SOT1

General I/O port. This function is enabled when UART0 disables

G

G

G

G

G

clock output.
Clock I/O pin for UART0. This function is enabled when UART0 en-

ables clock output.
General I/O port. This function is always enabled.
Serial data input pin for UART0. While UART0 is operating for input,

the input of the pin is used as required. Except when the function is
intentionally used, output from the other functions must be stopped.

General I/O port. This function is always enabled.
Serial data input pin for UART1. While UART1 is operating for input,

the input of the pin is used as required. Except when the function is
intentionally used, output from the other functions must be stopped.

General I/O port. This function is enabled when UART1 disables
clock output.

Clock pulse input/output pin for UART1. This function is enabled
when UART1 enables clock output.

General I/O port. This function is enabled when UART1 disables se­rial data output.

Serial data output pin for UART1. This function is enabled when
UART1 enables serial data output.

7

MB90540/545 Series

No. Pin name Circuit type Function

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25

26

28

29 to 32

33

38 to 41

P46

SOT2

P47

SCK2

P50

SIN2

P51 to P54

INT4 to INT7

P55

ADTG

P60 to P63

AN0 to AN3

General I/O port. This function is enabled when the Serial IO dis-

G

G

D

D

D

E

ables serial data output.
Serial data output pin for the Serial IO. This function is enabled

when the Serial IO enables serial data output.
General I/O port. This function is enabled when the Serial IO dis-

ables clock output.
Clock pulse input/output pin for the Serial IO. This function is en-

abled when the Serial IO enables clock output.
General I/O port. This function is always enabled.
Serial data input pin for the Serial IO. While the Serial IO is operat-

ing for input, the input of the pin is used as required. Except when
the function is intentionally used, output from the other functions
must be stopped.

General I/O port. This function is always enabled.
External interrupt request input pins for INT4 to INT7. While external

interrupt is allowed, the input of the pin is used as required. Except
when the function is intentionally used, output from the other func­tions must be stopped.

General I/O port. This function is always enabled.
Trigger input pin for the A/D converter. While the A/D converter is

operating for input, the input of the pin is used as required. Except
when the function is intentionally used, output from the other func­tions must be stopped.

General I/O port. The function is enabled when the analog input en­able register specifies port.

Analog input pins for the A/D converter. This function is enabled
when the analog input enable register specifies AD.

8

43 to 46

47

48

P64 to P67

AN4 to AN7

P56

TIN0

P57

TOT0

General I/O port. The function is enabled when the analog input en-

E

D

D

able register specifies port.
Analog input pins for the A/D converter. This function is enabled

when the analog input enable register specifies AD.
General I/O port. This function is always enabled.
Event input pin for the reload timers 0. While the reload timer is op-

erating for input, the input of the pin is used as required. Except
when the function is intentionally used, output from the other
functions must be stopped.

General I/O port. This function is enabled when the reload
timers 0 disables output.

Output pin for the reload timers 0. This function is enabled when the
reload timers 0 enables output.

MB90540/545 Series

No. Pin name Circuit type Function

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53 to 58

59 to 60

61 to 64

65 to 66

P70 to P75

IN0 to IN5

P76 to P77

OUT2 to OUT3

IN6 to IN7

P80 to P83

PPG0 to PPG3

P84 to P85

OUT0 to OUT1

General I/O ports. This function is always enabled.

D

D

D

D

Data sample input pins for input captures ICU0 to ICU5. While the
ICU is for input, the input of the pin is used as required. Except when
the function is intentionally used, output from the other functions
must be stopped.

General I/O ports. This function is enabled when the OCU disables
waveform output.

Waveform output pins for output compares OCU2 and OCU3. This
function is enabled when the OCU enables waveform output.

Data sample input pin for input captures ICU6 and ICU7. While the
ICU is for input, the input of the pin is used as required. Except when
the function is intentionally used, output from the other functions
must be stopped.

General I/O ports. This function is enabled when PPG disables
waveform output.

Output pins for PPGs. This function is enabled when PPG enables
waveform output.

General I/O ports. This function is enabled when the OCU disables
waveform output.

Waveform output pins for output compares OCU0 and OCU1. This
function is enabled when the OCU enables waveform output.

67

68

69 to 72

73

74

P86

TIN1

P87

TOT1

P90 to P93

INT0 to INT3

P94

TX0
P95

RX0

General I/O port. This function is always enabled.

D

D

D

D

D

Event input pin for the reload timers 1. While the reload timer is op­erating for input, the input of the pin is used as required. Except
when the function is intentionally used, output from the other
functions must be stopped.

General I/O port. This function is enabled when the reload
timers 0 disables output.

Output pin for the reload timers 1 This function is enabled when the
reload timers 1 enables output.

General I/O port. This function is always enabled.
External interrupt request input pins for INT0 to INT3. While external

interrupt is allowed, the input of the pin is used as required. Except
when the function is intentionally used, output from the other func­tions must be stopped.

General I/O port. This function is enabled when CAN0 disables out­put.

TX Output pin for CAN0. This function is enabled when CAN0 en­ables output.

General I/O port. This function is always enabled.
RX input pin for CAN0 Interface. When the CAN function is used,

output from the other functions must be stopped.

9

MB90540/545 Series

No. Pin name Circuit type Function

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P96

75

TX1
P97

76

78 PA0 D General I/O port. This function is always enabled.

34 AVCC Power supply

37 AVSS Power supply Dedicated ground pin for the A/D Converter

35 AVR+ Power supply

36 AVR- Power supply Lower reference voltage input for the A/D Converter
49

50
51 MD2 F

RX1

MD0
MD1

D

D

C

General I/O port. This function is enabled when CAN1 disables out­put.

TX Output pin for CAN1. This function is enabled when CAN1 en­ables output (only MB90540 series).

General I/O port. This function is always enabled.
RX input pin for CAN1 Interface. When the CAN function is used,

output from the other functions must be stopped (only MB90540 se­ries).

Power supply for the A/D Converter. This power supply must be
turned on or off while a voltage higher than or equal to AVcc is ap­plied to Vcc.

Reference voltage input for the A/D Converter. This power supply
must be turned on or off while a voltage higher than or equal to
AVR+ is applied to AVcc.

Input pins for specifying the operating mode. The pins must be di­rectly connected to Vcc or Vss.

Input pin for specifying the operating mode. The pin must be directly
connected to Vcc or Vss.

27 C

23; 84 V
11; 42

81

This is the power supply stabilization capacitor pin. It should be con­nected externally to an 0.1 µF ceramic capacitor.

CC

V

SS

Power supply Power supply for digital circuits
Power supply Ground for digital circuits

10

MB90540/545 Series

I/O CIRCUIT TYPE

■

Circuit type Diagram Remarks

X1

X0

A

Standby control signal

• Oscillation feedback resistor:
1 MΩ approx.

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• Hysteresis input with pull-up
Resistor: 50 kΩ approx.

B

C

D

R

R

R

V

R

CC

P-ch

N-ch

HYS

• Hysteresis input

HYS

•CMOS output

• Hysteresis input

HYS

11

MB90540/545 Series

Circuit type Diagram Remarks

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CC

V

P-ch

N-ch

•CMOS output

• Hysteresis input

• Analog input

E

Analog input

R

HYS

• Hysteresis input

R

F

R

HYS

• Pull-down Resistor: 50 kΩ approx.
(except FLASH devices)

•CMOS output

CC

V

• Hysteresis input

• TTL input (FLASH devices only)

P-ch

N-ch

G

R

R

HYS

TTL

T

12

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MB90540/545 Series

Circuit type Diagram Remarks

•CMOS output

CC

V

CC

V

CNTL

P-ch

• Hysteresis input

• Programmable pullup resistor:
50 kΩ approx.

H

R

N-ch

HYS

•CMOS output

CC

V

CC

V

CNTL

• Hysteresis input

• TTL input (FLASH devices only)

• Programmable pullup resistor:

P-ch

N-ch

50 kΩ approx.

I

R

R

HYS

TTL

T

13

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MB90540/545 Series

HANDLING DEVICES

■

(1) Preventing latch-up

CMOS IC chips may suffer latch-up under the following conditions:

• A voltage higher than Vcc or lower than Vss is applied to an input or output pin.

• A voltage higher than the rated voltage is applied between Vcc and Vss.

• The AVcc power supply is applied before the Vcc voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.

(2) Handling unused input pins

Do not leave unused input pins open, as doing so may cause misoperation of the device. Use a pull-up or pull­down resistor.

(3) Using external clock

To use external clock, drive the X0 and X1 pins in reverse phase.
Below is a diagram of how to use external clock.

MB90540/545 Series

X0

X1

Using external clock

(4) Power supply pins (Vcc/Vss)

Ensure that all Vcc-level power supply pins are at the same potential. In addition, ensure the same for all Vss­level power supply pins. (See the figure below.) If there are more than one Vcc or Vss system, the device may
operate incorrectly even within the guaranteed operating range.

Vcc
Vss

Vcc

Vss

MB90540/545

Vcc

Series

Vss

Vcc

Vss

Vss

(5) Pull-up/down resistors

The MB90540/545 Series does not support internal pull-up/down resistors(except P ort0 - Port3:pull-up resistors).
Use external components where needed.

14

Vcc

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MB90540/545 Series

(6) Crystal Oscillator Circuit

Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.

It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand
area for stabilizing the operation.

(7) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on the A/D converter power supply(AV
turning-on the digital power supply (V

CC

).

Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage not exceed AVR + or AV

(turning on/off the analog and digital power supplies simultaneously

CC

is acceptable).

(8) Connection of Unused Pins of A/D Converter

Connect unused pins of A/D converter to AV

= VCC, AVSS = AVR

CC

, A VR

CC

, A VR

+

+

) and analog inputs (AN0 to AN7) after

−

= VSS.

(9) N.C. Pin

The N.C. (internally connected) pin must be opened for use.

(10) Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
or more ms (0.2 V to 2.7 V).

(11) Initialization

In the device, there are internal registers which is initialized only by a po wer-on reset. To initialize these registers
turning on the power again.

(12) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions

In the Signed multiplication and division instructions (“DIV A, Ri” and “DIVW A, RWi”), the value of the corre­sponding bank register (DTB, ADB, USB, SSB) is set in “00h”.

If the values of the corresponding bank register (DTB,ADB ,USB,SSB) are setting other than “00h”, the remainder
by the execution result of the instruction is not stored in the register of the instruction operand.

15

MB90540/545 Series

BLOCK DIAGRAM

■

X0,X1
X0A,X1A

RSTX
HSTX

Clock

Controller

To Top / Lineup / Index

16LX

CPU

SOT0
SCK0
SIN0

SOT1
SCK1
SIN1

SCK2
SOT2
SIN2

AVCC
AVSS
AN[7:0]
AVR+
AVR­ADTG

RAM 6 KB

ROM 128 KB

/256 KB

Prescaler

UART0

Prescaler

UART1

(SCI)

Prescaler

Serial I/O

10-bit ADC

8 ch.

FMC-16 Bus

IO Timer

Input

Capture

8 ch.

Output

Compare

4 ch.

8/16-bit

PPG
4 ch.

CAN

Controller

16-bit Reload

Timer 2 ch.

External

Bus

Interface

IN[5:0]

IN[7:6]/OUT[3:2]

OUT[1:0]

PPG[3:0]

RX[1:0]*

TX[1:0]*

TIN[1:0]

TOT[1:0]

AD[15:00]

A[23:16]

ALE

RD

WRL

WRH

HRQ

HAK
RDY

CLK

16

External
Interrupt

INT[7:0]

MEMORY SPACE

■
The memory space of the MB90540/545 Series is shown below

MB90V540 MB90543/F543 MB90549/F549

To Top / Lineup / Index

MB90540/545 Series

FFFFFF

FF0000

FEFFFF

FE0000

FDFFFF

FD0000

FCFFFF

FC0000

00FFFF

004000
003FFF

003900

0020FF
001FF5

001FF0

H

H

H

H

H

(FF bank)

H

(FE bank)

H

(FD bank)

H

(FC bank)

External External

H

(Image of FF

H
H

Peripheral

H

External

H
H

ROM correction

H

ROM

ROM

ROM

ROM

ROM
bank)

FFFFFF

FF0000

FEFFFF

FE0000

00FFFF

004000
003FFF

003900

002000

0018FF

H

H

H

(FF bank)

H

(FE bank)

H

(Image of FF

H
H

Peripheral

H

H

H

ROM

ROM

External

ROM

bank)

External

FFFFFF

FF0000

FEFFFF

FE0000

FDFFFF
FD0000

FCFFFF
FC0000

00FFFF

004000

003FFF

003900

002000

0018FF

H

H

H

H

H

H

H

H

H

(Image of FF

H
H

H

H

H

ROM

(FF bank)

ROM

(FE bank)

ROM

(FD bank)

ROM

(FC bank)

ROM

bank)

Peripheral

External

RAM 6K

RAM 6K

RAM 8K

000100

H

000100

H

000100

H

External External External
0000BF
000000

H
H

Peripheral

0000BF
000000

H
H

Peripheral

0000BF

000000

H
H

Peripheral

Memory space map

The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler
effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without using the far spec­ification in the pointer declaration.
For example, an attempt to access 00C000

accesses the value at FFC000H in ROM.

H

The ROM area in bank FF exceeds 48 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF4000

and FFFFFFH is visible in bank 00, while the image between FF0000H and FF3FFFH

H

is visible only in bank FF.

17

To Top / Lineup / Index

MB90540/545 Series

I/O MAP

■

Address Register Abbreviation Access Pripheral Initial value

00

H

Port 0 data register PDR0 R/W Port 0 XXXXXXXX

B

01

H

02

H

03

H

04

H

05

H

06

H

07

H

08

H

09

H

0A

H

0BH to 0F

10

H

11

H

12

H

13

H

14

H

15

H

16

H

Port 1 data register PDR1 R/W Port 1 XXXXXXXX
Port 2 data register PDR2 R/W Port 2 XXXXXXXX
Port 3 data register PDR3 R/W Port 3 XXXXXXXX
Port 4 data register PDR4 R/W Port 4 XXXXXXXX
Port 5 data register PDR5 R/W Port 5 XXXXXXXX
Port 6 data register PDR6 R/W Port 6 XXXXXXXX
Port 7 data register PDR7 R/W Port 7 XXXXXXXX
Port 8 data register PDR8 R/W Port 8 XXXXXXXX
Port 9 data register PDR9 R/W Port 9 XXXXXXXX
Port A data register PDRA R/W Port A _ _ _ _ _ _ _X

H

Reserved
Port 0 direction register DDR0 R/W Port 0 0 0 0 0 0 0 0 0
Port 1 direction register DDR1 R/W Port 1 0 0 0 0 0 0 0 0
Port 2 direction register DDR2 R/W Port 2 0 0 0 0 0 0 0 0
Port 3 direction register DDR3 R/W Port 3 0 0 0 0 0 0 0 0
Port 4 direction register DDR4 R/W Port 4 0 0 0 0 0 0 0 0
Port 5 direction register DDR5 R/W Port 5 0 0 0 0 0 0 0 0
Port 6 direction register DDR6 R/W Port 6 0 0 0 0 0 0 0 0

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

17
18

19
1A
1B
1C
1D
1E
1F

20

21

22

23

H

H

H

H

H

H

H

H

H

H

H

H

H

Port 7 direction register DDR7 R/W Port 7 0 0 0 0 0 0 0 0
Port 8 direction register DDR8 R/W Port 8 0 0 0 0 0 0 0 0
Port 9 direction register DDR9 R/W Port 9 0 0 0 0 0 0 0 0
Port A direction register DDRA R/W Port A _ _ _ _ _ _ _0

Analog Input Enable ADER R/W Port 6, A/D 1 1 1 1 1 1 1 1
Port 0 Pullup control register PUCR0 R/W Port 0 0 0 0 0 0 0 0 0
Port 1 Pullup control register PUCR1 R/W Port 1 0 0 0 0 0 0 0 0
Port 2 Pullup control register PUCR2 R/W Port 2 0 0 0 0 0 0 0 0
Port 3 Pullup control register PUCR3 R/W Port 3 0 0 0 0 0 0 0 0

Serial Mode Control Register 0 UMC0 R/W

0 0 0 0 0 1 0 0

Status Register 0 USR0 R/W 0 0 0 1 0 0 0 0

Input/Output Data Register 0

UIDR0/

UODR0

R/W XXXXXXXX

UART0

Rate and Data Register 0 URD0 R/W 0 0 0 0 0 0 0X

B

B

B

B

B

B

B

B

B

B

B

B

B

(Continued)

18

To Top / Lineup / Index

MB90540/545 Series

Address Register Abbreviation Access Peripheral Initial value

24
25

26
27

28
29

2A

2B
2C
2D
2E
2F

30
31
32
33
34

H

H

H

H

H

H

H

H

H

H

H

H

H

H

Serial Mode Register 1 SMR1 R/W

Serial Control Register 1 SCR1 R/W 0 0 0 0 0 1 0 0

Input/Output Data Register 1

SIDR1/

SODR1

R/W XXXXXXXX

UART1

Serial Status Register 1 SSR1 R/W 0 0 0 0 1_0 0

UART1 Prescaler Control Register U1CDCR R/W 0_ _ _1 1 1 1

Edge Selector SES1 R/W _ _ _ _ _ _ _0

Reserved

Serial IO Prescaler SCDCR R/W
Serial Mode Control SMCS R/W _ _ _ _0 0 0 0
Serial Mode Control SMCS R/W 0 0 0 0 0 0 1 0

Serial IO

Serial Data SDR R/W XXXXXXXX

Edge Selector SES2 R/W _ _ _ _ _ _ _0

External Interrupt Enable ENIR R/W

External Interrupt Request EIRR R/W XXXXXXXX

0 0 0 0 0 0 0 0

0_ _ _1 1 1 1

0 0 0 0 0 0 0 0

B

B

B

B

B

B

B

B

B

B

B

B

B

External Interrupt

H

H

H

External Interrupt Level ELVR R/W 0 0 0 0 0 0 0 0
External Interrupt Level ELVR R/W 0 0 0 0 0 0 0 0

A/D Control Status 0 ADCS0 R/W

0 0 0 0 0 0 0 0

B

B

B

35
36
37
38

39
3A
3B
3C
3D
3E
3F

40

41

42

43

44

45

46

H

A/D Control Status 1 ADCS1 R/W 0 0 0 0 0 0 0 0

A/D Converter

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

PPG0 operation mode control register
PPG1 operation mode control register

PPG0 and PPG1 clock select register PPG01 R/W 0 0 0 0 0 0 _ _

PPG2 operation mode control register
PPG3 operation mode control register

PPG2 and PPG3 clock select register PPG23 R/W 0 0 0 0 0 0 _ _

PPG4 operation mode control register
PPG5 operation mode control register

PPG4 and PPG5 clock select register PPG45 R/W 0 0 0 0 0 0 _ _

PPG6 operation mode control register
PPG7 operation mode control register

PPG6 and PPG7 clock select register PPG67 R/W 0 0 0 0 0 0 _ _

A/D Data 0 ADCR0 R XXXXXXXX
A/D Data 1 ADCR1 R/W 0 0 0 0 1 _ XX

PPGC0 R/W
PPGC1 R/W 0 _ 0 0 0 0 0 1

16-bit Programable

Pulse

Generator 0/1

0 _ 0 0 0 _ _ 1

Reserved
PPGC2 R/W
PPGC3 R/W 0 _ 0 0 0 0 0 1

16-bit Programable

Pulse

Generator 2/3

Reserved
PPGC4 R/W
PPGC5 R/W 0 _ 0 0 0 0 0 1

16-bit Programable

Pulse

Generator 4/5

0 _ 0 0 0 _ _ 1

Reserved
PPGC6 R/W
PPGC7 R/W 0 _ 0 0 0 0 0 1

16-bit Programable

Pulse

Generator 6/7

0 _ 0 0 0 _ _ 1

0 _ 0 0 0 _ _1

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

(Continued)

19

To Top / Lineup / Index

MB90540/545 Series

Address Register Abbreviation Access Peripheral Initial value

47

to 4B

H

4C

H

H

Input Capture Control Status 0/1 ICS01 R/W Input Capture 0/1 0 0 0 0 0 0 0 0

Reserved

B

4D

4E
4F
50
51

52

53
54

55
56

57
58

59
5A
5B

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

Input Capture Control Status 2/3 ICS23 R/W Input Capture 2/3 0 0 0 0 0 0 0 0
Input Capture Control Status 4/5 ICS45 R/W Input Capture 4/5 0 0 0 0 0 0 0 0
Input Capture Control Status 6/7 ICS67 R/W Input Capture 6/7 0 0 0 0 0 0 0 0

Timer Control Status 0 TMCSR0 R/W

0 0 0 0 0 0 0 0

Timer Control Status 0 TMCSR0 R/W _ _ _ _ 0 0 0 0

Timer 0/Reload 0

Timer 0/Reload 0

TMR0/

TMRLR0

TMR0/

TMRLR0

R/W XXXXXXXX

R/W XXXXXXXX

Timer Control Status 1 TMCSR1 R/W

16-bit Reload

Timer 0

0 0 0 0 0 0 0 0

Timer Control Status 1 TMCSR1 R/W _ _ _ _ 0 0 0 0

Timer 1/Reload 1

Timer 1/Reload 1

TMR1/

TMRLR1

TMR1/

TMRLR1

R/W XXXXXXXX

R/W XXXXXXXX

Output Compare Control Status 0 OCS0 R/W
Output Compare Control Status 1 OCS1 R/W _ _ _0 0 0 0 0
Output Compare Control Status 2 OCS2 R/W
Output Compare Control Status 3 OCS3 R/W _ _ _ 0 0 0 0 0

16-bit Reload

Timer 1

Output Compare

0/1

Output Compare

2/3

0 0 0 0 _ _ 0 0

0 0 0 0 _ _ 0 0

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

5CH to 6B

6C

H

6D

H

6E

H

6F

H

70H to 7F

80

to 8F

H

to 9D

90

H

9E

H

9F

H

A0

H

A1

H

A2H to A4

H

Timer Data TCDT R/W
Timer Data TCDT R/W 0 0 0 0 0 0 0 0

Reserved

0 0 0 0 0 0 0 0

I/O Timer

Timer Control TCCS R/W 0 0 0 0 0 0 0 0

ROM Mirror ROMM R/W ROM Mirror _ _ _ _ _ _ _ 1

H

H

H

Reserved for CAN 0 Interface . Refer to “CAN Controller Hardware Manual”
Reserved for CAN 1 Interface . Refer to “CAN Controller Hardware Manual”

Reserved

ROM Correction Control Status PACSR R/W ROM Correction 0 0 0 0 0 0 0 0

Delayed Interrupt/release DIRR R/W Delayed Interrupt _ _ _ _ _ _ _ 0

Low-power Mode LPMCR R/W

Clock Selector CKSCR R/W

H

Reserved

Low Power

Controller

Low Power

Controller

0 0 0 1 1 0 0 0

1 1 1 1 1 1 0 0

B

B

B

B

B

B

B

B

(Continued)

20

To Top / Lineup / Index

MB90540/545 Series

(Continued)

Address Register Abbreviation Access Peripheral Initial value

A5
A6
A7

Automatic ready function select reg. ARSR W

H

H

H

External address output control reg. HACR W 0 0 0 0 0 0 0 0

Bus control signal select register ECSR W 0 0 0 0 0 0 0 _

External Memory

Access

0 0 1 1 _ _ 0 0

B

B

B

A8

H

A9

H

AA

H

ABH to AD

AE

H

AF

H

B0

H

B1

H

B2

H

B3

H

B4

H

B5

H

B6

H

B7

H

B8

H

B9

H

BA

H

BB

H

Watchdog Control WDTC R/W Watchdog Timer XXXXX 1 1 1

Time Base Timer Control TBTC R/W Time Base Timer 1 - - 0 0 1 0 0

Watch timer control register WTC R/W Watch Timer 1 X 0 0 0 0 0 0

H

Flash Control Status

(Flash only, otherwise reserved)

Interrupt control register 00 ICR00 R/W
Interrupt control register 01 ICR01 R/W 0 0 0 0 0 1 1 1
Interrupt control register 02 ICR02 R/W 0 0 0 0 0 1 1 1
Interrupt control register 03 ICR03 R/W 0 0 0 0 0 1 1 1
Interrupt control register 04 ICR04 R/W 0 0 0 0 0 1 1 1
Interrupt control register 05 ICR05 R/W 0 0 0 0 0 1 1 1
Interrupt control register 06 ICR06 R/W 0 0 0 0 0 1 1 1
Interrupt control register 07 ICR07 R/W 0 0 0 0 0 1 1 1
Interrupt control register 08 ICR08 R/W 0 0 0 0 0 1 1 1
Interrupt control register 09 ICR09 R/W 0 0 0 0 0 1 1 1
Interrupt control register 10 ICR10 R/W 0 0 0 0 0 1 1 1
Interrupt control register 11 ICR11 R/W 0 0 0 0 0 1 1 1

Reserved

FMCS R/W Flash Memory 0 0 0 X 0 _ _ 0

Reserved

0 0 0 0 0 1 1 1

Interrupt

controller

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

BC

H

BD

H

BE

H

BF

H

COH to FF

H

Interrupt control register 12 ICR12 R/W 0 0 0 0 0 1 1 1
Interrupt control register 13 ICR13 R/W 0 0 0 0 0 1 1 1
Interrupt control register 14 ICR14 R/W 0 0 0 0 0 1 1 1
Interrupt control register 15 ICR15 R/W 0 0 0 0 0 1 1 1

External

Address Register Abbreviation Access Peripheral Initial value

1FF0
1FF1
1FF2

H

H

H

ROM Correction Address 0 PADR0 R/W

XXXXXXXX
ROM Correction Address 1 PADR0 R/W XXXXXXXX
ROM Correction Address 2 PADR0 R/W XXXXXXXX

ROM Correction

1FF3
1FF4
1FF5

H

H

H

ROM Correction Address 3 PADR1 R/W XXXXXXXX
ROM Correction Address 4 PADR1 R/W XXXXXXXX
ROM Correction Address 5 PADR1 R/W XXXXXXXX

B

B

B

B

B

B

B

B

B

B

21

To Top / Lineup / Index

MB90540/545 Series

Address Register Abbreviation Access Peripheral Initial value

3900

H

3901

H

3902

H

3903

H

3904

H

3905

H

3906

H

3907

H

3908

H

3909

H

390A

H

390B

H

390C

H

390D

H

390E

H

390F

H

3910H to 3917

3918

H

3919

H

391A

H

Reload L PRLL0 R/W

Reload H PRLH0 R/W XXXXXXXX

16-bit Program-

XXXXXXXX

B

B

able Pulse

Reload L PRLL1 R/W XXXXXXXX

Generator 0/1

Reload H PRLH1 R/W XXXXXXXX

Reload L PRLL2 R/W

Reload H PRLH2 R/W XXXXXXXX

16-bit Program-

XXXXXXXX

B

B

B

B

able Pulse

Reload L PRLL3 R/W XXXXXXXX

Generator 2/3

Reload H PRLH3 R/W XXXXXXXX

Reload L PRLL4 R/W

Reload H PRLH4 R/W XXXXXXXX

16-bit Program-

XXXXXXXX

B

B

B

B

able Pulse

Reload L PRLL5 R/W XXXXXXXX

Generator 4/5

Reload H PRLH5 R/W XXXXXXXX

Reload L PRLL6 R/W

Reload H PRLH6 R/W XXXXXXXX

16-bit Program-

XXXXXXXX

B

B

B

B

able Pulse

Reload L PRLL7 R/W XXXXXXXX

Generator 6/7

Reload H PRLH7 R/W XXXXXXXX

H

Input Capture 0 IPCP0 R

Reserved

XXXXXXXX

Input Capture 0 IPCP0 R XXXXXXXX

B

B

B

B

Input Captue 0/1

Input Capture 1 IPCP1 R XXXXXXXX

B

22

391B
391C
391D
391E
391F

3920
3921
3922
3923
3924
3925
3926
3927

H

H

H

Input Capture 1 IPCP1 R XXXXXXXX
Input Capture 2 IPCP2 R

XXXXXXXX

Input Capture 2 IPCP2 R XXXXXXXX

B

B

B

Input Captue 2/3

H

H

H

H

Input Capture 3 IPCP3 R XXXXXXXX
Input Capture 3 IPCP3 R XXXXXXXX
Input Capture 4 IPCP4 R

XXXXXXXX

Input Capture 4 IPCP4 R XXXXXXXX

B

B

B

B

Input Captue 4/5

H

H

H

H

Input Capture 5 IPCP5 R XXXXXXXX
Input Capture 5 IPCP5 R XXXXXXXX
Input Capture 6 IPCP6 R

XXXXXXXX

Input Capture 6 IPCP6 R XXXXXXXX

B

B

B

B

Input Captue 6/7

H

H

Input Capture 7 IPCP7 R XXXXXXXX
Input Capture 7 IPCP7 R XXXXXXXX

B

B

(Continued)