The MB90520 series is a general-purpose 16-bit microcontroller developed and designed by Fujitsu for process
control applications in consumer products that require high-speed real-time processing.
The instruction set of the F
instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division
instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for
processing long word data.
The MB90520 series has peripheral resources of 8/10-bit A/D converter, 8-bit D/A converter, UART (SCI),
extended I/O serial interfaces 0 and 1, 8/16-bit up/down counter/timers 0 and 1, 8/16-bit PPG timers 0 and 1,
I/O timer (16-bit free-run timers 1 and 2, input captures 0 and 1 (ICU), output compares 0 and 1 (OCU)), and
an LCD controller/driver.
2
MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
*:F
2
MC-16LX CPU core inherits AT architecture of the F2MC* family with additional
FEATURES
■
•Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from divided-b y-2 of oscillation or one to four times the oscillation
(at oscillation of 4 MHz, 4 MHz to 16 MHz).
The system can be operated by a sub-clock (rated at 32.768 kHz).
Minimum instruction execution time: 62.5 ns (at oscillation of 4 MHz, four times the oscillation clock, operation
at V
CC of 5.0 V)
PACKAGES
■
120-pin Plastic LQFP
(FPT-120P-M05)
120-pin Plastic QFP
(FPT-120P-M13)
(Continued)
MB90520 Series
(Continued)
• Maximum memory space
16 Mbytes
• Instruction set optimized for controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
Enhanced signed multiplication/division instruction and RETI instruction functions
Enhanced precision calculation realized by 32-bit accumulator
• Instruction set designed for high level language (C) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
• Program patch function (for two address pointers)
• Low-power consumption (stand-by) mode
Sleep mode (mode in which CPU operating clock is stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Hardware stand-by mode
Clock mode (mode in which other than sub-clock and timebase timer are stopped)
•Process
CMOS technology
• I/O port
General-purpose I/O ports (CMOS): 53 ports
•UART (SCI)
With full-duplex double buffer
Clock asynchronized or clock synchronized transmission can be selectively used.
• DTP/external interrupt circuit (8 channels)
A module for starting extended intelligent I/O service (EI
by an external input.
• Wak e-up interrupt
Receives external interrupt requests and generates an interrupt request upon an “L” level input.
• Delayed interrupt generation module
Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels)
8/10-bit resolution can be selectively used.
Starting by an external trigger input.
Conversion time: minimum 15.0 µs (at machine clock frequency of 16 MHz, including sampling time)
• 8-bit D/A converter (based on the R-2R system)
8-bit resolution: 2 channels (independent)
Setup time: 12.5 µs
• Clock timer: 1 channel
• LCD controller/driver
A common driver and a segment driver that can directly drive the LCD (liquid crystal display) panel
• Clock output function
2
OS) and generating an external interrupt triggered
Note: Do not set external bus mode for the MB90520 series because it cannot be operated in this mode.
3
MB90520 Series
PRODUCT LINEUP
■
Part number
Item
ClassificationMask ROM productFlash ROM product Evaluation product
ROM size64 kbytes128 kbytesNone
RAM size4 kbytes6 kbytes
CPU functions
MB90522MB90523MB90F523MB90V520
Number of instructions: 351
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1 bit, 8 bits, 16 bits
Minimum execution time: 62.5 ns
(at machine clock frequency of 16 MHz)
Interrupt processing time: 1.5 µs
(at machine clock frequency of 16 MHz, minimum value)
Stop conversion mode (converts selected channel and stop operation repeatedly)
Number of channels: 1 (8-bit × 2 channels)
PPG operation of 8-bit or 16-bit
Pulse wave of given intervals and given duty ratios can be output.
Pulse interval: 62.5 ns to 1 µs (at machine clock frequency of 16 MHz)
Number of channels: 1 (8-bit × 2 channels)
Event input: 6 channels
8-bit up/down counter/timer used: 2 channels
8-bit re-load/compare function supported: 1 channel
16-bit
I/O timer
4
16-bit free-run
timers 1, 2
Number of channels: 2
Overflow interrupts
(Continued)
(Continued)
MB90520 Series
Part number
Item
Output
16-bit
I/O timer
DTP/external interrupt circuit
Wake-up intrrupt
Delayed interrupt generation
module
Extended I/O serial
interfaces 0, 1
Timebase timer
compares 0, 1
(OCU)
Input captures
0, 1 (ICU)
MB90523MB90523MB90F523MB90V520
Number of channels: 8
Pin input factor: Match signal of compare register
Number of channels: 2
Rewriting register value upon pin input (rising, falling, or both edges)
Number of inputs: 8
Started by rising edge, falling edge, “H” level input, or “L” level input.
External interrupt circuit or extended intelligent I/O service (EI
Number of inputs: 8
Started by “L” level input.
Interrupt generation module for switching tasks
Used in real-time operating systems.
Clock synchronized transmission (3125 bps to 1 Mbps)
LSB first/MSB first
18-bit counter
Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms
(at oscillation of 4 MHz)
2
OS) can be used.
8-bit resolution
8-bit D/A converter
LCD controller/driver
Watchdog timer
Low-power consumption
(stand-by) mode
ProcessCMOS
Power supply voltage for
operation*
* :Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)
Assurance for the MB90V520 is given only for operation with a tool at a power voltage of 3.0 V to 5.5 V, an
operating temperature of 0 to 55 degrees centigrade, and an operating frequency of 1 MHz to 16 MHz.
Note: For more information about each package, see section “■ Package Dimensions.”
DIFFERENCES AMONG PRODUCTS
■
Memory Size
In evaluation with an evaluation chip, note the difference between the evaluation chip and the chip actually used.
The following items must be taken into consideration.
• The MB90V520 does not have an internal ROM. How ev er , operations equivalent to those perf ormed by a chip
with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM
size by setting the development tool.
• In the MB90V520, images from FF4000
mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.)
• In the MB90522, images from FF4000
FF only.
• In the MB90523/F523, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH
to bank FE and bank FF.
H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH are
H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH to bank
89 to 87MD0 to MD2CThis is an input pin for selecting operation modes.
95 to 101P00 to P06DThis is a general-purpose I/O port.
102P07DThis is a general-purpose I/O port.
103 to 110P10 to 17DThis is a general-purpose I/O port.
111,
112,
113,
114
115P24EThis is a general-purpose I/O port.
116P25EThis is a general-purpose I/O port.
1
2
X0,
93
73
90RSTCThis is an external reset request signal input pin.
86HST
X1
X0A,
X1A
INT0 to INT6This is a request input pin of the DTP/external interrupt circuit ch.0
WI0 to WI7This is an I/O pin for wake-up interrupts.
P20,
P21,
P22,
P23
IC00,
IC01,
IC10,
IC11
AIN0This port can be used as count clock A input for 8/16-bit up/down
BIN0This port can be used as count clock B input for 8/16-bit up/down
Circuit
type
A This is a high-speed crystal oscillator pin.
BThis is a low-speed crystal oscillator pin.
Connect directly to V
CThis is a hardware stand-by input pin.
This function can be set by the port 0 input pull-up resistor setup
register (RDR0) for input. For output, however, this function is
invalid.
to ch.6.
This function can be set by the port 0 input pull-up resistor setup
register (RDR0) for input. For output, however, this function is
invalid.
This function can be set by the port 1 input pull-up resistor setup
register (RDR1) for input. For output, however, this function is
invalid.
EThis is a general-purpose I/O port.
This is a trigger input pin for input capture (ICU) 0 and 1.
Since this input is used as required for input capture 0 and 1 (ICU)
ch.0, ch.01, ch.10 and ch.11 input operation, output by other
functions must be suspended except for intentional operation.
counter/timer 0.
counter/timer 0.
CC or VSS.
Function
*1: FPT-120P-M05
*2: FPT-120P-M13
8
(Continued)
Pin no.
Pin name
LQFP-120*
QFP-120*
117P26EThis is a general-purpose I/O port.
118P27EThis is a general-purpose I/O port.
120P30EThis is a general-purpose I/O port.
1
2
ZIN0This port can be used as count clock Z input for 8/16-bit up/down
INT7This is a request input pin of the DTP/external interrupt circuit
ADTG
1P31EThis is a general-purpose I/O port.
CKOTThis is a clock monitor function output pin.
2P32EThis is a general-purpose I/O port.
OUT0This is an event output pin for output compare 0 (OCU) ch.0.
3P33EThis is a general-purpose I/O port.
OUT1This is an event output pin for output compare 0 (OCU) ch.1.
4P34EThis is a general-purpose I/O port.
OUT2This is an event output pin for output compare 0 (OCU) ch.2.
5P35EThis is a general-purpose I/O port.
OUT3This is an event output pin for output compare 0 (OCU) ch.3.
6P36EThis is a general-purpose I/O port.
PG00This is an output pin of 8/16-bit PPG timer 0.
Circuit
type
counter/timer 0.
ch.7.
This is an external trigger input pin of the 8/10-bit A/D converter.
Since this input is used as required for 8/10-bit A/D conv erter input
operation, output by other functions must be suspended e xcept f or
intentional operation.
This function is valid when clock monitor output is enabled.
This function becomes valid when waveform output from the
OUT0 is disabled.
This function is valid when output for each channel is enabled.
This function becomes valid when waveform output from the
OUT1 is disabled.
This function is valid when output for each channel is enabled.
This function becomes valid when waveform output from the
OUT2 is disabled.
This function is valid when output for each channel is enabled.
This function becomes valid when waveform output from the
OUT3 is disabled.
This function is valid when output for each channel is enabled.
This function becomes valid when wa vef orm output from the PG00
is disabled.
This function becomes valid when waveform output from PG00 is
enabled.
MB90520 Series
Function
*1: FPT-120P-M05
*2: FPT-120P-M13
(Continued)
9
MB90520 Series
Pin no.
Pin name
LQFP-120*
QFP-120*
1
2
7P37EThis is a general-purpose I/O port.
PG01This is an output pin of 8/16-bit PPG timer 0.
9,
10
11P42DThis is a general-purpose I/O port.
12P43DThis is a general-purpose I/O port.
13P44DThis is a general-purpose I/O port.
14P45DThis is a general-purpose I/O port.
P40,
P41
PG10,
PG11
SIN0This is a serial data input pin of UART (SCI).
SOT0This is a serial data output pin of UART (SCI).
SCK0This is a serial clock I/O pin of UART (SCI).
SIN1This is a data input pin for extended I/O serial interface 0.
Circuit
type
This function becomes valid when wa vef orm output from the PG01
is disabled.
This function becomes valid when waveform output from PG01 is
enabled.
DThis is a general-purpose I/O port.
This function becomes valid when wa vef orm output from the PG10
and PG11 are disabled.
This function can be set by the pull-up resistor setup register
(RDR4) for input. For output, however, this function is invalid.
This is an output pin of 8/16-bit PPG timer 1.
This function becomes valid when waveform outputs from PG10
and PG11 are enabled.
This function can be set by the pull-up resistor setup register
(RDR4) for input. For output, however, this function is invalid.
Because this input is used as required when UART (SCI) is
performing input operations, it is necessary to stop outputs by
other functions unless such outputs are made intentionally.
When using other output functions as well, disable output during
SIN operation.
This function can be set by the pull-up resistor setup register
(RDR4) for input. For output, however, this function is invalid.
This function becomes valid when serial data output from UART
(SCI) is enabled.
This function can be set by the pull-up resistor setup register
(RDR4) for input. For output, however, this function is invalid.
This function becomes valid when serial clock output from UART
(SCI) is enabled.
This function can be set by the port 4 input pull-up resistor setup
register (RDR4) for input. For output, however, this function is
invalid.
Since this input is used as required for serial data input operation,
output by other functions must be suspended e xcept for intentional
operation. When using other output functions as well, disable
output during SIN operation.
Function
*1: FPT-120P-M05
*2: FPT-120P-M13
10
(Continued)
Pin no.
Pin name
LQFP-120*
QFP-120*
40,
46 to 53P60 to P67KThis is a general-purpose I/O port.
1
2
15P46DThis is a general-purpose I/O port.
SOT1This is a data output pin for extended I/O serial interface 0.
16P47DThis is a general-purpose I/O port.
SCK1This is a serial clock I/O pin for extended I/O serial interface 0.
35P50DThis is a general-purpose I/O port.
SIN2This is a data input pin for extended I/O serial interface 1.
AIN1This port can be used as count clock A input for 8/16-bit up/down
36P51DThis is a general-purpose I/O port.
SOT2This is a data output pin for extended I/O serial interface 1.
BIN1This port can be used as count clock B input for 8/16-bit up/down
37P52DThis is a general-purpose I/O port.
SCK2This is a serial clock I/O pin for extended I/O serial interface 1.
ZIN1This port can be used as control clock Z input for 8/16-bit up/do wn
P53,
41
P54
DA0,
DA1
AN0 to AN7These are analog input pins of the 8/10-bit A/D converter.
Circuit
type
This function can be set by the port 4 input pull-up resistor setup
register (RDR4) for input. For output, however, this function is
invalid.
This function becomes valid when serial data output from SOT1 is
enabled.
This function can be set by the port 4 input pull-up resistor setup
register (RDR4) for input. For output, however, this function is
invalid.
This function becomes valid when serial clock output from SCK1 is
enabled.
Since this input is used as required for serial data input operation,
output by other functions must be suspended e xcept for intentional
operation.
counter/timer 1.
This function becomes valid when serial data output from SOT2 is
enabled.
counter/timer 1.
This function becomes valid when serial clock output from serial
SCK2 is enabled.
counter/timer 1.
IThis is a general-purpose I/O port.
These are analog signal output pins for 8-bit D/A converter ch.0
and ch.1.
The input function become valid when the analog input enable
register (ADER) is set to select a port.
This function is valid when the analog input enable register
(ADER) is enabled.
Function
MB90520 Series
*1: FPT-120P-M05
*2: FPT-120P-M13
(Continued)
11
MB90520 Series
Pin no.
Pin name
57
58
1
2
P70,
P72
TI0,
TI1
OUT4,
OUT6
P71,
P73
LQFP-120*
QFP-120*
55,
56,
Circuit
type
EThis is a general-purpose I/O port.
These are event input pins for 16-bit re-load timers 0 and 1.
Since this input is used as required for 16-bit re-load timers 0 and
1 operation, output by other functions must be suspended except
for intentional operation.
These are event output pins for output compare 1 (OCU) ch.4 and
ch.6.
This function is valid when output for each channel is enabled.
EThis is a general-purpose I/O port.
This function is valid when TO0 and TO1 output are disabled.
Function
TO0,
TO1
OUT5,
OUT7
These are output pins for 16-bit re-load timers 0 and 1.
This function is valid when TO0 and TO1 output are enabled.
These are event output pins for output compare 1 (OCU) ch.5 and
ch.7.
This function is valid when output for each channel is enabled.
59 to 62P74 to P77LThis is a general-purpose I/O port.
This function is valid with port output specified for the LCD
controller/driver control register.
COM0 to
COM3
These are common pins for the LCD controller/driver.
This function is valid with common output specified for the LCD
controller/driver control register.
64 to 71P80 to P87LThis is a general-purpose I/O port.
This function is valid with port output specified for the LCD
controller/driver control register.
SEG16 to
SEG23
These are segment outputs for the LCD controller/driver.
This function is valid with segment output specified for the LCD
controller/driver control register.
72,
75 to 81
P90,
P91 to P97
MThis is a general-purpose I/O port.
The maximum I
OL can be 10mA.
This function is valid with port output specified for the LCD
controller/driver control register.
SEG24,
SEG25 to
SEG31
17 to 24SEG00 to
SEG07
FThese are pins dedicated to LCD segments 00 to 07 for the LCD
These are segment outputs for the LCD controller/driver.
This function is valid with port output specified for the LCD
controller/driver control register.
controller/driver.
25 to 32PA0 to PA7LThis is a general-purpose I/O port.
This function is valid with port output specified for the LCD
controller/driver control register.
SEG08 to
SEG15
These are pins for LCD segments 08 to 15 for the LCD controller/
driver.
Units of four ports or segments can be selected by the internal
register in the LCD controller.
*1: FPT-120P-M05
*2: FPT-120P-M13
(Continued)
12
MB90520 Series
(Continued)
Pin no.
1
LQFP-120*
QFP-120*
Pin name
2
34CGThis is a capacitance pin for power supply stabilization.
82 to 85V0 to V3NThis is a pin for the reference power supply for the LCD controller/
8,
V
CCPower
54,
94
33,
V
SSPower
63,
91,
119
42AV
CCHThis is a power supply for the analog circuit.
43AVRHJThis is a reference v oltage input to the analog circuit.
44AVRLHThis is a reference voltage input to the analog circuit.
45AV
38DV
39DV
SSHThis is a GND level of the analog circuit.
CCHThis is the Vref input pin for the D/A converter.
SSHThis is the GND level pin for the D/A converter.
Circuit
type
supply
supply
Function
Connect an external ceramic capacitor rated at about 0.1 µF. This
capacitor is not, however, required for the M90F523 (flash
product).
driver.
This is a power supply (5.0 V) input pin to the digital circuit.
This provides the GND level (0.0 V) input pin for the digital circuit.
Make sure to turn on/turn off this power supply with a voltage
exceeding AV
CC applied to VCC.
Make sure to turn on/turn off this power supply with a voltage
exceeding AVRH applied to AV
The voltage to be applied must not exceed V
The potential must be the same as V
CC.
CC.
SS.
*1: FPT-120P-M05
*2: FPT-120P-M13
13
MB90520 Series
I/O CIRCUIT TYPE
■
TypeCircuitRemarks
A• High-speed oscillation feedback resistor
X1
approx. 1MΩ
X0
Nch
Pch
Pch
Nch
Standby control signal
B• Low-speed oscillation feedback resistor
X1A
X0A
Nch
Pch
Pch
Nch
Standby control signal
approx. 1MΩ
C• Hysteresis input
R
Hysteresis input
14
D• Hysteresis input (can be set with the input
Pch
Pch
Selecting signal
with or without a
input pull-up resistor
pull-up resistor)
CMOS level output
• Pull-up resistor approx. 50 kΩ
• Provided with a standby control function
I
OL= 4 mA
Nch
R
Hysteresis input
Standby control for
input interruption
for input interruption
(Continued)
MB90520 Series
TypeCircuitRemarks
E• CMOS hysteresis input/output
Pch
R
IOL= 4 mA
F• Pins dedicated to segment output
CC
V
Nch
Hysteresis input
Standby control for input interruption
• CMOS level output
• Provided with a standby control function
for input interruption
Pch
Nch
R
G• C pin output
(Pin for capacitor connection)
Pch
Nch
N.C. pin for the MB90F523
H• Analog power input protector
Pch
AVP
Nch
I• CMOS hysteresis input/output
• Pin for analog output/CMOS output
(During analog output, CMOS output is
not produced.)
Pch
CC
V
(Analog output has priority over CMOS
Nch
output: DAE = 1)
• Provided with a standby control function
I
OL= 4 mA
R
Hysteresis input
Standby control for input interruption
DAO
for input interruption
(Continued)
15
MB90520 Series
TypeCircuitRemarks
J• Input pin for ref+ power for the A/D
Pch
Nch
Pch
Nch
ANE
AVR
ANE
K• Hysteresis input/analog input
Pch
Nch
converter
Provided with power protection
• CMOS output
• Provided with a standby control for input
interruption
I
OL= 4 mA
R
Standby control for input interruption
Hysteresis input
Analog input
L• CMOS hysteresis input/output
Pch
• Segment input
• Standby control to cut off the input is
available in segment input operation
Nch
R
Standby control for input interruption
IOL= 4 mA
Hysteresis input
SEG
M• Hysteresis input
Nch
• Nch open-drain output
(High current for LCD drive)
• Standby control to cut off the input is
R
IOL= 10 mA
Nch
Hysteresis input
Standby control for input interruption
available in segment input operation
16
N• Reference power supply pin for the LCD
controller
IOL= 10 mA
Pch
Nch
R
MB90520 Series
HANDLING DEVICES
■
1. Ensuring that the Voltage does not exceed the Maximum Rating (to Avoid a Latch-up).
In CMOS ICs, a latch-up phenomenon is caused when a voltage exceeding VCC or below VSS is applied to
input or output pins or if a voltage exceeding the rating is applied across VCC and VSS.
When a latch-up is caused, the power supply current may be dramatically increased, resulting in thermal
breakdown of devices. To avoid the latch-up, make sure that the voltage does not exceed the maximum rating.
In turning on/turning off the analog power supply, make sure the analog power voltages (AVCC, AVRH, DVCC)
and analog input voltages do not exceed the digital voltage (V
And also make sure the voltages applied to the LCD power supply pins (V3 to V0) do not exceed the power
supply voltage (V
CC).
2. Handling Unused Pins
• Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. Unused
input pins should be pulled-up or pull-down through at least 2 kΩ resistance.
• Unused input/output pins may be left open in output state, but if such pins are in input state they should be
handled in the same way as input pins.
CC).
3. Notes on Using External Clock
In using the external clock, drive X0 pin only and leave X1 pin unconnected.
Using external cloc k
•
X0
Open
MB90520 series
X1
4. Unused Sub Clock Mode
If sub clock modes are not used, the oscillator should be connected to the X0A pin and X1A pin.
5. Power Supply Pins
In products with multiple Vcc or Vss pins, pins with the same potential are internally connected in the device to
avoid abnormal operations including latch-ups. However, the pins should be connected to external powers and
ground lines to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused
by the rise in the ground level, and to conform to the total current rating.
Make sure to connect V
It is recommended that a bypass capacitor of around 0.1 µF be placed between the V
device.
cc and Vss pins via lowest impedance to power lines.
cc and Vss pins near the
17
MB90520 Series
Using
•
power supply pins
V
CC
V
SS
V
CC
V
SS
V
SS
MB90520 series
V
CC
V
SS
V
CC
V
SS
V
CC
6. Crystal Oscillator Circuit
Noise around the X0 and X1 pins may cause abnormal operation in this device. In designing printed circuit
boards, the X0 and X1 pins and crystal oscillator (or ceramic oscillator), as well as the bypass capacitor to the
ground, should be placed as close as possible, and the related wiring should have as few crossings with other
wiring as possible.
Circuit board artwork in which the area of the X0 and X1 pins is surrounded by grounding is recommended for
stabilizing the operation.
7. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVRL, DVCC,
DVSS) and analog inputs (AN0 to AN7) after turning on the digital power supply (VCC).
Turn off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that AVRH and DV
acceptable).
CC do not exceed AVCC (turning on/off the analog and digital supplies simultaneously is
8. Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter and those of D/A converter to AVCC = DVCC = VCC, AVSS = AVRH = AVRL
= V
SS.
9. N.C. Pin
The N.C. (internally connected) pin must be opened for use.
10.Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 µs or more (0.2 V to 2.7 V).
11.Use of SEG/COM Pins for the LCD Controller/Driver as Ports
In MB90520 series, pins SEG08 to SEG31, and COM0 to COM3 can also be used as general-purpose ports.
The electrical standard is such that pins SEG08 to SEG23, and COM0 to COM3 have the same ratings as the
CMOS output port, while pins SEG24 to SEG31 have the same ratings as the open-drain type.
18
MB90520 Series
12.
Indeterminate outputs from ports 0 and 1
The outputs from ports 0 and 1 become indeterminate during oscillation setting time of step-down circuit (during
a power-on reset) after the power is turned on.
Pay attention to the port output timing shown as follow
Timming chart of indeterminate outputs from ports o and 1
•
Oscillation setting time
∗2
Step-down circuit
setting time
∗1
Vcc(power-supply pin)
PONR(power-on reset) signal
(external asynchronous reset) signal
RST
RST(internal reset) signal
Oscillation clock signal
KA(internal operation clock A) signal
KB(internal operation clock B) signal
PORT(port output)signal
indereterminate period
* : 1:Step-down circuit setting time : 217/oscillation clock frequency (oscillation clock frequency of 16 MHz: 8.19 ms)
* :2:Oscillation setting time: 2
18
/oscillation clock frequency (oscillation cllock frequency of 16 MHz: 16.38 ms)
13.Initialization
The device contains internal registers that can be initialized only by a power-on reset. To initialize the internal
registers, restart the power supply.
14. Interrupt Recovery from Standby
If an external interrupt is used for recovery from standby, use an “H” level input request. An “L” level request
causes abnormal operation.
15.Precautions for Use of “DIV A, Ri”, and “DIVW A, Ri” Instructions
The signed multiplication-division instructions “DIV A, Ri”, and “DIVW A, RWi” should be used when the
corresponding bank registers (DTB, ADB, USB, SSB) are set to value “00h”. If the corresponding bank registers
(DTB, ADB, USB, SSB) are set to a value other than “00h,” then the remainder obtained after the execution of
the instruction will not be placed in the instruction operand register.
Notes: Actually 16-bit free-run timer 1 is supported although two free-run timers are seemingly supported.
*1: The clock control circuit comprises a watchdog timer, a timebase timer, and a power consumption controller.
*2: A register for setting a pull-up resistor is supported.
*3: This is a high-current port for an LCD drive.
*4: A register for setting a pull-up resistor is supported. Signals in the CMOS level are input and output.
*5: Also used for LCD output. With this port used as is, Nch open-drain output develops . A register f or setting a pull-up resi stor
is supported.
20
CC
SS
MEMORY MAP
■
H
FFFFFF
Address #1
H
FE0000
H
010000
Address #2
H
004000
H
002000
Address #3
H
000100
H
0000C0
H
000000
Single chip mode
A mirroring function
is supported.
*: Addresses #1, #2 and #3 vary with product type.
Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C
compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 are assigned to the
same address, enabling reference of the table on the ROM without stating “far.”
For e xample, if an attempt has been made to access 00C000
H, the contents of the ROM at FFC000H are
actually accessed. Since the ROM area of the FF bank exceeds 48k bytes, the whole area cannot be
reflected in the image for the 00 bank. The ROM data at FF4000
were the image for 00400
the area of FF4000
H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in
H to FFFFFFH.
H to FFFFFFH looks, therefore, as if it
21
MB90520 Series
2
F
MC-16LX CPU PROGRAMMING MODEL
■
• Dedicated registers
AHAL
USP
SSP
PS
PC
DPR
PCB
DTB
USB
: Accumlator (A)
Dual 16-bit register used for storing results of calculation, etc. The two 16-bit
registers can be combined to be used as a 32-bit register.
: User stack pointer (USP)
16-bit pointer for containing a user stack address.
: System stack pointer (SSP)
16-bit pointer for displaying the status of the system stack address.
: Processor status (PS)
16-bit register for displaying the system status.
: Program counter (PC)
16-bit register for displaying the storing location of the current instruction code.
: Direct page register (DPR)
8-bit register for specifying bit 8 through 15 of the operand address in the short
direct addressing mode.
: Program bank register (PCB)
8-bit register for displaying the program space.
: Data bank register (DTB)
8-bit register for displaying the data space.
: User stack bank register (USB)
8-bit register for displaying the user stack space.
32-bit
16-bit
SSB
ADB
8-bit
: System stack bank register (SSB)
8-bit register for displaying the system stack space.
: Additional data bank register (ADB)
8-bit register for displaying the additional data space.
22
• General-purpose registers
MB90520 Series
Maximum of 32 banks
H
000180
+ (RP × 10H )
• Processor status (PS)
ILMRPCCR
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PS
ILM2B4ILM1 ILM0B3B2B1B0—ISTNZVC
R7
R5
R3
R1
RW3
RW2
RW1
RW0
16-bit
R6
R4
R2
R0
RW7
RL3
RW6
RW5
RL2
RW4
RL1
RL0
Initial value
— : Unused
X : Indeterminate
00 00000010XXXXX
—
23
MB90520 Series
I/O MAP
■
Address
000000
Abbreviated
register
Register name
name
HPDR0Port 0 data register R/WPort 0XX X XXXXX B
Read/
write
Resource nameInitial value
000001HPDR1Port 1 data register R/WPort 1XX X XXXXX B
000002HPDR2Port 2 data register R/WPort 2XX X XXXXX B
000003HPDR3Port 3 data register R/WPort 3XX X XXXXX B
000004HPDR4Port 4 data register R/WPort 4XX X XXXXX B
000005HPDR5Port 5 data register R/WPort 5XX X XXXXX B
000006HPDR6Port 6 data register R/WPort 6XX X XXXXX B
000007HPDR7Port 7 data register R/WPort 7XX X XXXXX B
000008HPDR8Port 8 data register R/WPort 8XX X XXXXX B
000009HPDR9Port 9 data register R/WPort 9XX X XXXXX B
00000AHPDRAPort A data register R/WPort AXXXXX X X X B
00000BHLCDCMRPort 7/COM pin selection registerR/W
00000CH
OCP4OCU compare register ch.4R/W
00000DHXXXXXXXXB
Port 7,
LCD controller/driver
16-bit I/O timer
(output compare 1
(OCU) section)
XXXX0 000B
XXXXXXXXB
00000EH(Disabled)
00000F
HEIFRWake-up interrupt flag registerR/W
Wake-up interrupt
XXXXXXX0 B
000010HDDR0Port 0 direction registerR/WPort 00 0 0 0 0 0 0 0 B
000011HDDR1Port 1 direction registerR/WPort 10 0 0 0 0 0 0 0 B
000012HDDR2Port 2 direction registerR/WPort 20 0 0 0 0 0 0 0 B
000013HDDR3Port 3 direction registerR/WPort 30 0 0 0 0 0 0 0 B
000014HDDR4Port 4 direction registerR/WPort 40 0 0 0 0 0 0 0 B
000015HDDR5Port 5 direction registerR/WPort 5XXX 0 0 0 0 0 B
000016HDDR6Port 6 direction registerR/WPort 60 0 0 0 0 0 0 0 B
000017HDDR7Port 7 direction registerR/WPort 70 0 0 0 0 0 0 0 B
000018HDDR8Port 8 direction registerR/WPort 80 0 0 0 0 0 0 0 B
000019HDDR9Port 9 direction registerR/WPort 90 0 0 0 0 0 0 0 B
00001AHDDRAPort A direction registerR/WPort A0 0 0 0 0 0 0 0 B
00001BHADERAnalog input enable registerR/W
00001CH
OCP5OCU compare register ch.5R/W
00001DHXXXXXXXXB
Port 6,
A/Dconverter
16-bit I/O timer
(output compare 1
(OCU) section)
11111111B
XXXXXXXXB
00001EH(Disabled)
00001F
HEICRWake-up interrupt enable registerW
Wake-up interrupt
00000000B
24
(Continued)
MB90520 Series
Address
register
Register name
name
Abbreviated
000020
HSMRSerial mode register R/W
000021HSCRSerial control register
Read/
write
R/W or
W
Resource
name
Initial value
00000000B
00000100B
UART
000022H
SIDR/
SODR
000023HSSRSerial status register
000024HSMCSL0Serial mode control lower status register 0R/W
000025HSMCSH0Serial mode control upper status register 0R/W0 0 0 0 0 0 1 0 B
000026HSDR0Serial data register 0R/WXXXXXXXXB
Serial input data register/
serial output data register
R
W
R/W or
R
(SCI)
Extended I/O
serial
interface 0
XXXXXXXX
00001X00B
XXXX0 000B
Communica-
000027HCDCRCommunications prescaler control registerR/W
tions prescaler
0XXX1111B
control register
000028HSMCSL1Serial mode control lower status register 1R/W
000029HSMCSH1Serial mode control upper status register 1R/W0 0 0 0 0 0 1 0 B
00002AHSDR1Serial data register 1R/WXXXXXXXXB
0000XX00
00002FHXXX0 00 00B
000030HENIRDTP/interrupt enable registerR/W
000031HEIRRDTP/interrupt factor registerR/WX X X X XXXX B
000032H
DTP/external
interrupt circuit
00000000B
00000000
ELVRRequest level setting registerR/W
000033H00000000B
000034H
OCP6OCU compare register ch.6R/W
000035HXXXXXXXXB
16-bit I/O timer
(output com-
pare 1 (OCU)
section)
000036HADCS1A/D control status register lower digitsR/W
000037HADCS2A/D control status register upper digitsR/W0 0 0 0 0 0 0 0 B
000038HADCR1A/D data register lower digitsRX X X X XXXX B
8/10-bit A/D
converter
XXXXXXXXB
00000000B
000039HADCR2A/D data register upper digitsR or W0 0 0 0 1 XX X B
00003AHDADR0D/A converter data register ch.0R/W
00003BHDADR1D/A converter data register ch.1R/WXXXXX X X X B
00003CHDACR0D/A control register 0R/WXXXXXXX0B
8-bit D/A
converter
XXXXXXXXB
00003DHDACR1D/A control register 1R/WXXXXXXX0B
00003EHCLKRClock output enable registerR/W
Clock monitor
function
XXXX0 000B
(Continued)
B
B
B
25
MB90520 Series
Address
register
Register name
name
Abbreviated
00003F
000040
H(Disabled)
HPRLL0PPG0 re-load register LR/W
000041HPRLH0PPG0 re-load register HR/WXXXX X X X X B
000042HPRLL1PPG1 re-load register LR/WXX X XXXXX B
000043HPRLH1PPG1 re-load register HR/WXXXX X X X X B
000044HPPGC0PPG0 operating mode control registerR/W0 X 0 0 0 X X 1 B
000045HPPGC1PPG1 operating mode control registerR/W0 X 0 0 0 0 0 1 B
000046H
PPGOE0/
PPGOE1
PPG0 and 1 output control registersR/W0 0 0 0 0 0 0 0
000047H(Disabled)
000048
H
Timer control status register lower ch.0
TMCSR0
000049HTimer control status register upper ch.0XXXX 0 0 0 0 B
00004AH
00004BHXXXXXXXXB
00004CH
control register
0000A1HCKSCRClock select register
0000A2H
to
(Disabled)
0000A7H
0000A8
HWDTCWatchdog timer control registerR or WWatchdog timerX X XXXXXX B
0000A9HTBTCTimebase timer control registerR/WTimebase timer1 XX 0 0 0 0 0 B
0000AAHWTCClock timer control register
0000ABH
to
0000AD
0000AE
H
HFMCSFlash control registerR/WFlash interface1 XX 0 0 1 0 0 B
(Disabled)
0000AFH(Disabled)
0000B0
HICR00Interrupt control register 00R/W
0000B1HICR01Interrupt control register 01R/W0 0 0 0 0 1 1 1 B
0000B2HICR02Interrupt control register 02R/W0 0 0 0 0 1 1 1 B
0000B3HICR03Interrupt control register 03R/W0 0 0 0 0 1 1 1 B
0000B4HICR04Interrupt control register 04R/W0 0 0 0 0 1 1 1 B
0000B5HICR05Interrupt control register 05R/W0 0 0 0 0 1 1 1 B
0000B6HICR06Interrupt control register 06R/W0 0 0 0 0 1 1 1 B
0000B7HICR07Interrupt control register 07R/W0 0 0 0 0 1 1 1 B
0000B8HICR08Interrupt control register 08R/W0 0 0 0 0 1 1 1 B
0000B9HICR09Interrupt control register 09R/W0 0 0 0 0 1 1 1 B
0000BAHICR10Interrupt control register 10R/W0 0 0 0 0 1 1 1 B
0000BBHICR11Interrupt control register 11R/W0 0 0 0 0 1 1 1 B
0000BCHICR12Interrupt control register 12R/W0 0 0 0 0 1 1 1 B
0000BDHICR13Interrupt control register 13R/W0 0 0 0 0 1 1 1 B
Read/
write
R/W
R/W
R/W or
W
R/W or
R
R/W or
R
Resource nameInitial value
3
Address match
detection
00000000B
function
Delayed inter-
rupt generation
XXXXXXX0 B
module
Low-power
00011000B
consumption
(stand-by) mode
11111100
Clock timer1X001000B
00000111B
Interrupt
controller
(Continued)
B
28
(Continued)
MB90520 Series
Address
register
Register name
name
Abbreviated
0000BE
HICR14Interrupt control register 14R/W
0000BFHICR15Interrupt control register 15R/W0 0 0 0 0 1 1 1 B
Read/
write
Resource nameInitial value
Interrupt
00000111B
controller
0000C0H
to
(External area)*
1
0000FFH
000100H
to
00####
(RAM area)*
H
2
00####H
to
001FEF
001FF0H
001FF1HProgram address detection register 1R/WXXXXXX X X B
H
Program address detection register 0R/W
PADR0
(Reserved area)*
3
XXXXXXXX
Address match
001FF2HProgram address detection register 2R/WXXXXXX X X B
001FF3H
001FF4HProgram address detection register 4R/WXXXXXX X X B
PADR1
Program address detection register 3R/WX X X X X X X X
detection
function
001FF5HProgram address detection register 5R/WXXXXXX X X B
001FF6H
to
001FFF
(Reserved area)*
H
3
B
B
Descriptions for read/write
R/W: Readable and writable
R: Read only
W: Write only
Descriptions for initial value
0 : The initial value is “0.”
1 : The initial value is “1.”
X : The initial value is indeterminate.
*1: This area is the only external access area having an address of 0000FF
H or lower . An access oper ation to this
area is handled as that to external I/O area.
*2: For details of the “RAM area”, see the memory map.
*3: The “reserved area” is basically disabled because it is used in the system.
*4: “Area used by the system” is the area set by the resistor for evaluating tool.
Notes: • F or bits initialized by reset operations , the initial value set by the reset oper ation is listed as an initial value.
Note that the values are different from reading results.
For LPMCR/CKSCR/WDTC, there are cases in which initialization is performed or not performed,
depending on the types of the reset. The value listed is the initial value in cases where initialization is per
formed.
• The addresses following 0000FF
H are reserved. No external bus access signal is generated.
• Boundary ####H between the “RAM area” and the“ reserved area” varies with the product models.
• Channels 0 to 3 of the OCU compare register use 16-bit free-run timer 2, while channels 4 to 7 of the OCU
compare register use 16-bit free-run timer 1. 16-bit free-run timer 1 is also used by input captures (ICU)
0 and 1.
29
MB90520 Series
INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTERS
Port 0 through A are general-purpose I/O ports having a combined function as a resource input. The I/O ports
can be used as general-purpose I/O ports only in the single-chip mode.
• Operation as output port
The pin is configured as an output port by setting the corresponding bit of the DDR register to “1”.
Writing data to PDR register when the port is configured as output, the data is retained in the output latch in
the PDR and directly output to the pin.
The value of the pin (the same value retained in the output latch of PDR) can be read out b y reading the PDR
register.
Note: When a read-modify-write type instruction (e.g. bit set instruction) is performed to the port data register,
the destination bit of the operation is set to the specified value, not affecting the bits configured by the
DDR register for output. However, values of bits configured as inputs by the DDR register are changed
because input values to the pins are written into the output latch. To avoid this situation, configure the
pins by the DDR register as output after writing output data to the PDR register when switching the bit
used as input to output.
• Operation as input port
The pin is configured as input by setting the corresponding bit of the DDR register to “0.”
When the pin is configured as an input, the output buffer is turned off and the pin is put into a high-impedance
status.
When data is written into the PDR register, the data is retained in the output latch of the PDR, b ut pin outputs
are unaffected.
Reading the PDR register reads out the pin level (“0” or “1”).
32
(2) Register Configuration
• Port 0 data register (PDR0)
Address
H
000000
• Port 1 data register (PDR1)
Address
H
000001
R/WR/WR/WR/WR/WR/WR/WR/W
• Port 2 data register (PDR2)
Address
H
000002
• Port 3 data register (PDR3)
Address
H
000003
• Port 4 data register (PDR4)
Address
H
000004
• Port 5 data register (PDR5)
Address
H
000005
• Port 6 data register (PDR6)
Address
H
000006
MB90520 Series
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
P07P06P05P04P03P02P01P00
R/WR/WR/WR/WR/WR/WR/WR/W
bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
P17P16P15P14P13P12P11P10
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
P27P26P25P24P23P22P21P20
R/WR/WR/WR/WR/WR/WR/WR/W
bit 15 bit 14 bit 13bit 12bit 11 bit 10bit 9bit 8
P37P36P35
R/WR/WR/WR/WR/WR/WR/WR/W
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
P47P46P45P44P43P42P41P40
R/WR/WR/WR/WR/WR/WR/WR/W
bit 15 bit 14 bit 13bit 12bit 11 bit 10bit 9bit 8
———P54P53P52P51P50
———
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
P67P66P65P64P63P62P61P60
R/WR/WR/WR/WR/WR/WR/WR/W
P34
P33P32P31P30
R/WR/WR/WR/WR/W
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
B
B
B
B
B
B
B
• Port 7 data register (PDR7)
Address
H
000007
• Port 8 data register (PDR8)
Address
H
000008
• Port 9 data register (PDR9)
Address
H
000009
bit 15 bit 14 bit 13bit 12bit 11 bit 10bit 9bit 8
P77P76P75P74P73P72P71P70
R/WR/WR/WR/WR/WR/WR/WR/W
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
P87P86P85P84P83P82P81P80
R/WR/WR/WR/WR/WR/WR/WR/W
bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
P97P96
P95
P94P93P92P91P90
R/WR/WR/WR/WR/WR/WR/WR/W
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
(Continued)
B
B
B
33
MB90520 Series
• Port A data register (PDRA)
Address
00000A
H
bit 7bit 6bit 5bit 4
PA7PA6PA5PA4PA3PA2PA1PA0
R/WR/WR/WR/WR/WR/WR/WR/W
• Port 0 direction register (DDR0)
Address
000010
H
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
D07D06D05D04D03D02D01D00
R/WR/WR/WR/WR/WR/WR/WR/W
• Port 1 direction register (DDR1)
Address
000011
H
bit 15 bit 14 bit 13bit 12bit 11 bit 10bit 9bit 8
D17D16D15D14D13D12D11D10
R/WR/WR/WR/WR/WR/WR/WR/W
• Port 2 direction register (DDR2)
Address
000012
H
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
D27D26D25D24D23D22D21D20
R/WR/WR/WR/WR/WR/WR/WR/W
• Port 3 direction register (DDR3)
Address
000013
bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
H
D37D36D35D34D33D32D31D30
• Port 4 direction register (DDR4)
Address
000014
H
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
D47D46D45D44D43D42D41D40
R/WR/WR/WR/WR/WR/WR/WR/W
• Port 5 direction register (DDR5)
Address
000015
H
bit 15 bit 14 bit 13bit 12bit 11 bit 10bit 9bit 8
———D54D53D52D51D50
R/WR/WR/WR/WR/WR/WR/WR/W
• Port 6 direction register (DDR6)
Address
000016
H
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
D67D66D65D64D63D62D61D60
R/WR/WR/WR/WR/WR/WR/WR/W
• Port 7 direction register (DDR7)
Address
000017
H
bit 15 bit 14 bit 13bit 12bit 11 bit 10bit 9bit 8
D77D76D75D74D73D72D71D70
R/WR/WR/WR/WR/WR/WR/WR/W
bit 2bit 1bit 0
bit 3
R/WR/WR/WR/WR/W
Initial value
XXXXXXXX
Initial value
00000000
Initial value
00000000
Initial value
00000000
Initial value
00000000
Initial value
00000000
Initial value
XXX00000
Initial value
00000000
Initial value
00000000
B
B
B
B
B
B
B
B
B
34
• Port 8 direction register (DDR8)
Address
000018
H
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
D87D86D85D84D83D82D81D80
R/WR/WR/WR/WR/WR/WR/WR/W
Initial value
00000000
B
(Continued)
(Continued)
• Port 9 direction register (DDR9)
Address
000019
H
bit 15 bit 14 bit 13bit 12bit 11 bit 10bit 9bit 8
D97D96D95D94D93D92D91D90
R/WR/WR/WR/WR/WR/WR/WR/W
• Port A direction register (DDRA)
Address
00001A
H
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
DA7DA6DA5DA4DA3DA2DA1DA0
R/WR/WR/WR/WR/WR/WR/WR/W
• Port 0 input pull-up resistor setup register (RDR0)
Address
00008C
H
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00
R/WR/WR/WR/WR/WR/WR/WR/W
• Port 1 input pull-up resistor setup register (RDR1)
Address
00008D
bit 15 bit 14 bit 13bit 12bit 11 bit 10bit 9bit 8
H
RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10
R/WR/WR/WR/WR/WR/WR/WR/W
• Port 4 input pull-up resistor setup register (RDR4)
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
• Input pull-up resistor setup register (RDR)
PDR (port data register)
PDR read
Output latch
PDR write
DDR (port direction register)
Pch
Pin
Nch
Standby control (SPL=1)
To resource input
Pull-up resistor
About 50 kΩ
(5.0 V)
Pch
Pch
Pin
36
Direction latch
DDR write
Internal data bus
Standby control: Stop, timebase timer mode and SPL=1
DDR read
RDR latch
RDR write
RDR read
RDR (input pull-up resistor setup register)
Nch
Standby control
(SPL=1)
• Analog input enable register (ADER)
ADER (analog input enable register)
ADER read
ADER latch
ADER write
PDR (port data register)
PDR read
MB90520 Series
To analog input
RMW
(read-modify-write
type instruction)
Internal data bus
Output latch
PDR write
DDR (port direction register)
Direction latch
DDR write
DDR read
Standby control: Stop, timebase timer mode and SPL=1
Pch
Pin
Nch
Standby control
(SPL=1)
37
MB90520 Series
2. Timebase Timer
The timebase timer is a 18-bit free-run counter (timebase counter) for counting up in synchronization to the
internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from
four types : 2
The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation
stabilization time or the watchdog timer, etc.
To oscillation stabilization
time selector of clock control block
B
18
38
Power-on reset
Start stop-mode
CKSCR : MCS = 1→0*
Timebase timer control register
(TBTC)
Switch machine clock from oscillation clock to PLL clock
*1:
Interrupt number
*2:
OF : Overflow
HCLK : Oscillation clock frequency
1
Timebase timer
interrupt signal
2
#12*
Counter
clear circuit
Reserved
timer selector
Clear TBOF
——
Interval
Set TBOF
TBIETBRTBOFTBC1 TBC0
MB90520 Series
3. Watchdog Timer
The watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the CPU when
the counter is not cleared for a preset period of time.
(1) Register Configuration
• Watchdog timer control register (WDTC)
Address
0000A8
R: Read only
W: Write only
X : Indeterminate
(2) Block Diagram
Watchdog timer
Start sleep-mode
Start hold status
Start stop-mode
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
H
Counter clear
control circuit
PONR STBR WRST ERST SRST WTEWT1WT0
RRRRRWWW
Watchdog timer control register (WDTC)
PONR STBR WRST ERST SRST WTE WT1 WT0
2
CLR and start
Count clock
selector
CLR
counter
2-bit
Overflow
CLR
Watchdog timer
reset generation
circuit
Initial value
XXXXXXXX
To internal reset
generation circuit
B
Clear
(Timebase timer counter)
Divided-by-2
of HCLK
HCLK : Oscillation clock frequency
× 2
1
2
...
× 2
4
8
× 29× 210× 211× 212× 213× 214× 215× 216× 217× 2
× 2
18
39
MB90520 Series
4. 8/16-bit PPG Timer 0, 1
The 8/16-bit PPG timer is a 2-CH re-load timer module for outputting pulse having giv en frequencies/duty ratios.
The two modules perform the following operation by combining functions.
• 8-bit PPG timer output 2-CH independent output mode
This is a mode for operating independent 2-CH 8-bit PPG timers, in which PG00 and PG10 pins correspond
to outputs from PPG0 and PPG1 respectively.
• 16-bit PPG timer output operation mode
In this mode, PPG0 and PPG1 are combined to be operated as a 1-CH 8/16-bit PPG timer 0 and 1 operating
as a 16-bit timer. Because outputs during 16-bit PPG timer output operation mode are re versed by an underflow
from PPG1, the same output pulses are output from PG10 and PG11 pins.
• 8 + 8-bit PPG timer output operation mode
In this mode, PPG0 is operated as an 8-bit prescaler register, in which an underflow output of PPG0 is used
as a clock source for PPG1.
A prescaler output of PPG0 is output from PG00 and PG01 pins. PPG output of PPG1 is output from PG10 and
PG11 pins.
• PPG output operation
A pulse wave with any period/duty ratio is output. The module can also be used as a D/A converter with an
external add-on circuit.
40
(1) Register Configuration
• PPG0 operating mode control register (PPGC0)
Address
000044
H
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
PEN0—PE00PIE0PUF0——
R/W—R/WR/WR/W———
• PPG1 operating mode control register (PPGC1)
Address
000045
H
bit 15 bit 14 bit 13bit 12bit 11 bit 10bit 9bit 8
PEN1—PE10PIE1PUF1 MD1MD0
R/W—R/WR/WR/WR/WR/WR/W
• PPG0 output control register (PPGOE0)
Address
000046
H
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11PE01
R/WR/WR/WR/WR/WR/WR/WR/W
• PPG1 output control register (PPGOE1)
Address
000046
H
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11PE01
R/WR/WR/WR/WR/WR/WR/WR/W
• PPG0 re-load register H (PRLH0)
Address
000041
H
bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
R/WR/WR/WR/WR/WR/WR/WR/W
MB90520 Series
Initial value
Reserved
Reserved
0X000XX1
Initial value
0X000001
Initial value
00000000
Initial value
00000000
Initial value
XXXXXXXX
B
B
B
B
B
• PPG1 re-load register H (PRLH1)
Address
000043
H
bit 15 bit 14 bit 13bit 12bit 11 bit 10bit 9bit 8
R/WR/WR/WR/WR/WR/WR/WR/W
• PPG0 re-load register L (PRLL0)
Address
000040
H
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
R/WR/WR/WR/WR/WR/WR/WR/W
• PPG1 re-load register L (PRLL1)
Address
H
000042
R/W:Readable and writable
X : Indeterminate
— : Undefined bits (read value undefined)
The 16-bit re-load timer has an internal clock mode for counting down in synchronization to three types of internal
clocks and an event count mode for counting down by detecting a given edge of the pulse input to the external
bus pin. Either of the two functions can be selectively used.
For this timer, an “underflow” is defined as the timing of transition from the counter value of “0000
H” to “FFFFH.”
According to this definition, an underflow occurs after a counter value of [re-load register setting value + 1] .
In operating the counter, the re-load mode for repeating counting operation after re-loading a counter value after
an underflow or the one-shot mode for stopping the counting operation after an underflow can be selectively used.
Because the timer can generate an interrupt upon an underflow, the timer conforms to the extended intelligent
2
I/O service (EI
OS).
The MB90520 series has 2 channels of 16-bit re-load timers.
(1) Register Configuration
• Timer control status register upper digits ch.0, ch.1 (TMCSR0, TMCSR1 : H)
TMCSR0 : 000049
Address
TMCSR1 : 00004D
bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
H
————CSL1CSL0 MOD2 MOD1
H
————R/WR/WR/WR/W
Initial value
XXXX0000
B
• Timer control status register lower digits ch.0, ch.1 (TMCSR0, TMCSR1 : L)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
H
H
H
WWWWWWWWWWWWWWWW
H
44
Initial value
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
B
B
B
B
(2) Block Diagram
MB90520 Series
Internal data bus
TMRLR0*
1
<TMRLR1>
1
TMR0*
<TMR1>
16-bit timer register (down counter) UF
Count clock generation circuit
3
Pin
φ
Prescaler
Input
control
circuit
External
clock
P70/TI0/OUT4*
<P72/TI1/OUT6>
1
32
Function select
16-bit re-load register
CLK
Gate input
Valid clock
decision
circuit
Internal
clock
Clock
selecter
Re-load signal
CLKClear
Select
signal
Wait signal
Output control circuit
Output signal
generation
circuit
Reverse
Re-load
control
circuit
EN
Operation
control
circuit
To UART *
<To 8/10-bit
1
A/D converter>
Pin
P71/TO0/OUT5*
<P73/TO1/OUT7>
1
————
Timer control status register (TMCSR0)*
CSL1 CSL0 MOD2MOD1MOD0OUTE OUTL RELD INTE UF CNTE TRG
1
<TMCSR1>
*1: The timer has ch.0 and ch.1, and figures bracketed by < > are for ch.1
*2: Interrupt number
φ: Machine clock frequency
Clear
2
CS
EI
Interrupt request signal
1, *2
#38*
<#40>
45
MB90520 Series
6. 16-bit I/O Timer
The 16-bit I/O timer module consists of two 16-bit free-run timers, two input capture circuits (ICU), and eight
output comparators (OCU). This module allows two independent waveforms to be output on the basis of the
16-bit free-run timer. Input pulse width and external clock periods can, therefore, be measured.
•Block diagram
Internal data bus
Input capture 0, 1
(ICU)
Dedicated
bus
16-bit
free-run timer 1, 2
Dedicated
bus
Output compare 0, 1
(OCU)
46
MB90520 Series
(1) 16-bit Free-run Timer 1, 2
The 16-bit free-run timer consists of a 16-bit up counter, a control register and a communications prescaler
register. The value output from the timer counter is used as basic time (base timer) for input capture (ICU) and
output compare (OCU).
• A counter operation clock can be selected from four internal clocks (φ/4, φ/16, φ/64 and φ/256).
• An interrupt can be generated by overflow of counter value or compare match with OCU compare register 0
and 4. (Compare match requires mode settings.)
• The counter value can be initialized to “0000
register 0 and 4.
• Register configuration
• Free-run timer data register 1, 2 (TCDT1, TCDT2)
H” by a reset, software clear or compare match with OCU compare
TCDT1 : 000057
Address
000056
TCDT2 : 000067
000066
bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
• Free-run timer control status register 1, 2 (TCCS1, TCCS2)
Address
TCCS1 : 000058
TCCS2 : 000068
R/W: Readable and writable
bit 7bit 6bit 5bit 4
H
Reserved
H
IVF
STOPIVFECLRMODECLK0CLK1
bit 3bit 2bit 1bit 0
R/WR/WR/WR/WR/WR/WR/WR/W
• Block diagram
Free-run timer data register (TCDT1)*1 <TCDT2>
Communications
φ
prescaler register
2
Free-run timer
control status register
(TCCS1) *
1
<TCCS2>
Reserved
OF
IVFIVFE STOP MODE CLR CLK1 CLK0
16-bit counter
STOPCLKCLR
Count value output
to ICO and OCU
OCU compare register 0
match signal
Initial value
00000000
00000000
00000000
00000000
Initial value
00000000
00000000
Internal data bus
B
B
B
B
B
B
*1: The timer has ch.1 and ch.2, and figures bracketed by < > are for ch.2.
*2: Interrupt number
φ:Machine clock frequency
OF: Overflow
16-bit free-run timer
interrupt request
1, *2
#14*
<#28>
47
MB90520 Series
(2) Input Capture 0, 1 (ICU)
The input capture (ICU) generates an interrupt request to the CPU while storing the current counter value of
the 16-bit free-run timer to the ICU data register (IPCP) upon input of a trigger edge from the external pin.
There are two sets (two channels) of input capture external pins and ICU data registers, enabling measurements
of a maximum of four events.
• The input capture has two sets of external input pins (IN0, IN1) and ICU registers (IPCP), enabling
measurements of a maximum of four events.
• Trigger edge direction can be selected from rising/falling/both edges.
• The input capture can be set to generate an interrupt request at the storage timing of the counter value of the
16-bit free-run timer to the ICU data register (IPCP).
• The input compare conforms to the extended intelligent I/O service (EI
• The input capture ( ICU) function is suited for measurements of intervals (frequencies) and pulse-widths.
• Register configuration
2
OS).
• ICU data register ch.0 ch.1 (IPCP0, IPCP1)
IPCP0(upper) : 000051
IPCP1(upper) : 000053
IPCP0(lower) : 000050
IPCP1(lower) : 000052
AddressInitial value
AddressInitial value
Note: This register holds a 16-bit free-run timer value when the valid edge of the corresponding external pin input waveform
is detected. (This register can be word-accessed, but not programmed.)
bit 15bit 14
H
CP15CP14
H
R
bit 7
H
CP07
H
R
R
bit 6
CP06
R
bit 13bit 12bit 11bit 10bit 9
CP13
R
bit 5
CP05
RR
CP12CP11
RR
bit 4bit 3
CP04CP03
R
CP10CP09
R
bit 2bit 1bit 0
CP02
R
R
CP01
RR
bit 8
CP08
R
CP00
• ICU control status register (ICS01)
Address
000054
R/W: Readable and writable
R : Read only
X :Indeterminate
bit 7
H
ICP1
R/W
bit 6 bit 5
ICP0
R/W
ICE1ICE0
R/W
bit 4
R/W
bit 3
EG11EG10EG01
R/WR/W
bit 2 bit 1
R/W
bit 0
EG00
R/W
XXXXXXXX
XXXXXXXX
Initial value
00000000
B
B
B
48
•Block diagram
P20/IC00
Pin
P21/IC01
Pin
P22/IC10
Pin
P23/IC11
Pin
ICU control status register (ICS01)
Edge detection circuit
Data latch signal
2
2
ICP1
ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
Internal data bus
Output latch
IPCP0(upper)
IPCP1(upper)
Latch
signal
MB90520 Series
ICU data register (IPCP)
IPCP0(lower)
IPCP1(lower)
16
16
16-bit free-run
timer 1, 2
* : Interrupt number
Interrupt request
#31*
Interrupt request
#32*
49
MB90520 Series
(3) Output Compare 0, 1 (OCU)
The output compare (OCU) is two sets of compare units each consisting of an eight-channel OCU compare
register, a comparator and a control register.
An interrupt request can be generated for each channel upon a match detection by performing time-division
comparison between the OCU compare data register setting value and the counter value of the 16-bit free-run
timer.
The OUT pin can be used as a waveform output pin for reversing output upon a match detection or a generalpurpose output port for directly outputting the setting value of the CMOD bit.
C
•Register
• OCU control status register ch.01, ch.23, ch.45, ch.67 (OCS01, OCS23, OCS45, OCS67)
The 8/16-bit up/down counter/timer consists of six event input pins, two 8-bit up/down counters, two 8-bit
re-load compare registers, and their controllers.
(1) Register Configuration
• Up/down count register 0 (UDCR0)
Address
000080
H
bit 7bit 6bit 5bit 4
D06D07
RRRRRRRR
• Up/down count register 1 (UDCR1)
Address
000081
bit 15bit 14bit 13 bit 12 bit 11bit 10bit 9bit 8
H
D17D16D15D14D13D12D11D10
RRRRRRRR
• Re-load compare register 0 (RCR0)
Address
H
000082
• Re-load compare register 1 (RCR1)
Address
H
000083
bit 7bit 6bit 5bit 4
D06D07
WWWWWWWW
bit 15bit 14bit 13 bit 12bit 11 bit 10bit 9bit 8
D17D16D15D14D13D12D11D10
WWWWWWWW
• Counter status register 0, 1 (CSR0, CSR1)
Address
CSR0 : 000084
CSR1 : 000088
H
H
bit 7bit 6bit 5bit 4
CITECSTR
R/WR/WR/WR/WR/WR/WRR
• Counter control register 0, 1 (CCRL0, CCRL1)
Address
CCRL0 : 000086
CCRL1 : 00008A
H
H
bit 7bit 6bit 5bit 4
CTUT
—
R/WR/WR/WR/WR/WR/WR/W
—
• Counter control register 0 (CCRH0)
Address
000087
H
bit 15bit 14bit 13 bit 12 bit 11bit 10bit 9bit 8Initial value
M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
R/WR/WR/WR/WR/WR/WR/WR/W
• Counter control register 1 (CCRH1)
Address
00008B
bit 15bit 14bit 13 bit 12 bit 11bit 10bit 9bit 8
H
CDCF CFIECLKS CMS1 CMS0 CES1 CES0
—
R/WR/WR/WR/WR/WR/WR/W
—
bit 3bit 2bit 1bit 0
D04D05D02D03D00D01
bit 3bit 2bit 1bit 0
D04D05D02D03D00D01
bit 3bit 2bit 1bit 0
CMPFUDIEUDFFOVFFUDF0UDF1
bit 3bit 2bit 1bit 0
RLDEUCRECGSCUDCCCGE0CGE1
Initial value
00000000
Initial value
00000000
Initial value
00000000
Initial value
00000000
Initial value
00000000
Initial value
X0000000
00000000
Initial value
X0000000
B
B
B
B
B
B
B
B
R/W: Readable and writable
R : Read only
W : Write only
— : Undefined bits (read value undefined)
53
MB90520 Series
(2) Block Diagram
• Block diagram of 8/16-bit up/down counter/timer 0
Internal data bus
RCR0
Re-load compare register 0
UDCR0
Up/down count register 0
Counter control
register 0 (CCRL0)
UDCC
—
CTUTCGE1 CGE0UCRE
RLDE
CGSC
Re-load
control
circuit
CARRY/
BORROW
(to channel 1)
P26/ZIN0/INT7
Pin
φ
P24/AIN0
Pin
Pin
P25/BIN0
CDCFCES1 CES0CFIECMS1CLKSCMS0
M16E
Counter control register 0 (CCRH0)
* : Interrupt number
φ: Machine clock frequency
Edge/level
detection
circuit
Prescaler
UP/down count
clock selector
Counter clear
circuit
Count clock
Counter status
register 0 (CSR0)
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
Overflow
Underflow
Compare
control circuit
Interrupt request
#21*
Interrupt request
#22*
M16E
(to channel 1)
54
MB90520 Series
• Block diagram of 8/16-bit up/down counter/timer 1
Internal data bus
RCR1
Re-load compare register 1
UDCR1
Up/down count register 1
Counter control
register 1 (CCRL1)
CGSC
Counter clear
UP/down count
clock selector
circuit
Count clock
Counter status
register 1
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
P52/SCK2/ZIN1
Pin
CARRY/BORRW
(from channel 0)
P50/SIN2/AIN1
Pin
CTUTCGE1 CGE0UCREUDCCRLDE
—
Edge/level
detection
circuit
φ
Prescaler
(CSR1)
Overflow
Underflow
Re-load
control
circuit
Compare
control circuit
Pin
P51/SOT2/BIN1
M16E
(from channel 1)
—
Counter control register 1 (CCRH1)
* : Interrupt number
φ: Machine clock frequency
Interrupt request
#29*
Interrupt request
#30*
CDCFCES1 CES0CFIECMS1CLKSCMS0
55
MB90520 Series
8. Extended I/O Serial Interface 0, 1
The extended I/O serial interface transfers data using a clock synchronization system having an 8-bit x 1 channel
configuration.
For data transfer, you can select LSB first/MSB first.
(1) Register Configuration
• Serial mode control upper status register 0, 1 (SMCSH0, SMCSH1)
SMCSH0 : 000025
SMCSH1 : 000029
Address
• Serial mode control lower status register 0, 1 (SMCSL0, SMCSL1)
Address
SMCSL0 : 000024
SMCSL1 : 000028
• Serial data register 0, 1 (SDR0, SDR1)
SDR0 : 000026
SDR1 : 00002A
H
H
Address
bit 15bit 14bit 13 bit 12bit 11 bit 10bit 9bit 8
H
SMD2 SMD1 SMD0SIESIRBUSY STOP STRT
H
R/WR/WR/WR/WR/WRR/WR/W
bit 7bit 6bit 5bit 4
——
————
H
H
bit 7bit 6bit 5bit 4
D6D7
R/WR/WR/WR/WR/WR/WR/WR/W
bit 3bit 2bit 1bit 0
——
R/WR/WR/WR/W
D4D5D2D3D0D1
BDSMODESCOESOE
bit 3bit 2bit 1bit 0
Initial value
00000010
Initial value
XXXX0000
Initial value
XXXXXXXX
B
B
B
R/W: Readable and writable
R : Read only
X :Indeterminate
— : Undefined bits (read value undefined)
56
(2) Block Diagram
(MSB first) D0 to D7D7 to D0 (LSB first)
MB90520 Series
Internal data bus
Pin
P45/SIN1
Pin
P50/SIN2/AIN1
Pin
P47/SCK1
Pin
P52/SCK2/ZIN1
Internal clock
210
SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT
Serial mode control
status register
(SMCSH
*: Interrupt number
,L)
Serial data register
(SDR)
Control circuit
3
Transfer direction selection
Read
Write
Shift clock counter
————
MODE
Pin
P46/SOT1
Pin
P51/SOT2/BIN1
BDS SOE
Interrupt request
#15 (SMCS0)*
#17 (SMCS1)*
SCOE
57
MB90520 Series
9. UART (SCI)
UART (SCI) is a general-purpose serial data communication interface for performing synchronous or
asynchronous communication (start-stop synchronization system).
• Data buffer: Full-duplex double buffer
• Transfer mode:Clock synchronized (with start and stop bit)
Clock asynchronized (start-stop synchronization system)
• Communications prescaler control register (CDCR)
Address
000027
H
bit 15 bit 14bit 13bit 12 bit 11bit 10bit 9bit 8
MD———DIV3DIV2DIV1DIV0
R/W———R/WR/WR/WR/W
Reserved
SCKE SOE
Initial value
00000100
Initial value
00000000
Initial value
00001X00
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
0XXX1111
B
B
B
B
B
B
R/W:Readable and writable
R : Read only
W:Write only
X : Indeterminate
— : Undefined bits (read value undefined)
59
MB90520 Series
(2) Block Diagram
Dedicated baud
rate generator
16-bit re-load timer 0
External clock
Pin
P42/SCK0
Clock
selector
Receive
clock
detection circuit
Receive
control circuit
Start bit
Control bus
Transmit
clock
Transmit
control circuit
Transmit start
circuit
Receive
interrupt signal
#37*
Transmit
interrupt signal
#39*
Pin
P42/SIN0
Receive condition
decision circuit
SMR
register
Receive bit
Receive parity
Shift register for
reception
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
counter
counter
SIDRSODR
Reception
complete
Internal data bus
SCR
register
Transmit bit
counter
Transmit parity
counter
Shift register for
transmission
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR
register
Pin
P43/SOT0
Start transmission
2
OS reception
To EI
error generation
signal (to CPU)
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
60
* : Interrupt number
MB90520 Series
10. DTP/External Interrupt Circuit
The DTP (Data Transfer Peripheral), which is located between the peripheral circuit outside the device and the
2
F
MC-16LX CPU, receives an interrupt request or DMA request generated by the external peripheral circuit*
for transmission to the F
As with request levels, two types of “H” and “L” can be selected for the intelligent I/O service. Rising and falling
edges as well as “H” and “L” can be selected for an external interrupt request.
* :The external peripheral circuit is connected outside the MB90520 series device.
(1) Register Configuration
• DTP/interrupt factor register (EIRR)
Address
000031
• DTP/interrupt enable register (ENIR)
Address
000030
• Request level setting register (ELVR)
Address
ELVR (lower) : 000032
2
MC-16LX CPU. It is used to activate the intelligent I/O service or interrupt processing.
bit 15 bit 14 bit 13bit 12bit 11 bit 10bit 9bit 8
ER7ER6ER5ER4ER3ER2ER1ER0
H
R/WR/WR/WR/WR/WR/WR/WR/W
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
H
EN7EN6EN5EN4EN3EN2EN1EN0
R/WR/WR/WR/WR/WR/WR/WR/W
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
H
LB3LA3LB2LA2LB1LA1LB0LA0
R/WR/WR/WR/WR/WR/WR/WR/W
Initial value
XXXXXXXX
Initial value
00000000
Initial value
00000000
B
B
B
Address
ELVR (upper) : 000033
R/W: Readable and writable
X : Indeterminate
bit 15 bit 14 bit 13bit 12bit 11 bit 10bit 9bit 8
LB7LA7LB6LA6LB5LA5LB4LA4
Wake-up interrupts transmit interrupt request (“L” level) generated by peripheral equipment located between
external peripheral devices and the F
The interrupt does not conform to the exterded intelligent I/O service (EI
(1) Register Configuration
• Wake-up interrupt flag register (EIFR)
2
MC-16LX CPU to the CPU and invoke interrupt processing.
2
OS).
Address
00000F
bit 15 bit 14 bit 13bit 12bit 11 bit 10bit 9bit 8
H
———————WIF
———————R/W
• Wake-up interrupt enable register (EICR)
Address
00001F
R/W: Readable and writable
W : Write only
— : Undefined bits (read value undefined)
bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
H
EN7EN6EN5EN4EN3EN2EN1EN0
WWWWWWWW
(2) Block Diagram
Wake-up interrupt
enable register (EICR)
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0———
P10/WI0 Pin
Internal data bus
XXXXXXX0
Wake-up interrupt flag
register (EIFR)
————WIF
Interrupt request detection circuit
Initial value
Initial value
00000000
B
B
P11/WI1
P12/WI2
P13/WI3
P14/WI4
P15/WI5
P16/WI6
P17/WI7
Pin
Pin
Pin
Pin
Pin
Pin
Pin
*: Interrupt number
Wake-up interrupt
request
#16*
63
MB90520 Series
12. Delayed Interrupt Generation Module
The delayed interrupt generation module generates interrupts for switching tasks. By using this module,
hardware interrupt requests to the CPU can be generated and cancelled using software.
2
This module does not conform to the extended intelligent I/O service (EI
bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
H
———————R0
———————R/W
The DIRR is the register used to control delay interrupt request generation/cancellation. Programming this
register with “1” generates a delay interrupt request. Programming this register with “0” cancels a delay interrupt
request. Upon a reset, an interrupt is canceled. The undefined bit area can be programmed with either “0” or
“1.” For future extension, however, it is recommended that bit set and clear instructions be used to access this
register.
The 8/10-bit A/D converter converts analog voltage input to the analog input pins (input voltage) to digital values
(A/D conversion) and has the following features:
• Minimum conversion time: minim um 15.0 µs (at machine clock frequency of 16 MHz, including sampling time)
• Minimum sampling period: 4 µs/8 µs (at machine clock frequency of 16 MHz)
• Compare time: 99/176 machine cycles per channel
(99 machine cycles are used for a machine clock frequency below 10 MHz.)
• Conversion method: RC successive approximation method with a sample and hold circuit
• 8/10-bit resolution
• Analog input pins: Selectable from eight channels by software
Single conversion mode: Selects and converts one channel.
Scan conversion mode: Conv erts two or more successiv e channels. Up to eight channels can be programmed.
Continuous conversion mode: Repeatedly converts specified channels.
Stop conversion mode: Stops conversion after completing a conversion for one channel and wait for the
next activation (conversion can be started synchronously).
• Interrupt requests can be generated and the extended intelligent I/O service (EI
end of A/D conversion. Furthermore, A/D conversion result data can be transferred to the memory, enabling
efficient continuous processing.
• When interrupts are enabled, there is no loss of data ev en in contin uous operations because the conversion
data protection function is in effect.
• Starting factors for conversion: Selectable from software activation, external trigger (falling edge) and timer
(rising edge).
2
OS) can be started after the
65
MB90520 Series
(1) Register Configuration
• A/D control status register upper digits (ADCS2)
Address
H
000037
• A/D control status register lower digits (ADCS1)
The 8-bit D/A converter, which is based on the R-2R system, supports 8-bit resolution mode. It contains two
channels, each of which can be controlled in terms of output by the D/A control register.
(1) Register Configuration
• D/A converter data register ch.0 (DADR0)
Address
H
00003A
• D/A converter data register ch.1 (DADR1)
Address
H
00003B
• D/A control register 0 (DACR0)
Address
H
00003C
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00
R/WR/WR/WR/WR/WR/WR/WR/W
bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10
R/WR/WR/WR/WR/WR/WR/WR/W
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
———————DAE0
———————R/W
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXX0
B
B
B
• D/A control register 1 (DACR1)
Address
H
00003D
R/W: Readable and writable
X : Indeterminate
— : Undefined bits (read value undefined)
bit 15 bit 14 bit 13bit 12bit 11 bit 10bit 9bit 8
———————DAE1
———————R/W
Initial value
XXXXXXX0
B
68
•Block Diagram
Internal data bus
D/A converter data register ch.1 (DADR1)D/A converter data register ch.0 (DADR0)
The LCD (liquid crystal display) controller/driver, which contains a 16-byte display data memory, controls LCD
indication using four common output pins and 32 segment output pins. It can select three types of duty output
and directly drive the LCD panel.
(1) Register Configuration
• LCDC control register 0 (LCR0)
Address
H
00006A
• LCDC control register 1 (LCR1)
Address
H
00006B
• Port 7/COM pin selection register (LCDCMR)
Address
H
00000B
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
CSSLCEN VSELBKMS1MS0FP1FP0
R/WR/WR/WR/WR/WR/WR/WR/W
bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
ReservedSEG5 SEG4
R/WR/WR/WR/WR/WR/WR/WR/W
bit 15 bit 14 bit 13bit 12bit 11 bit 10bit 9bit 8
————COM3 COM2 COM1 COM0
————R/WR/WR/WR/W
ReservedSEG3 SEG2 SEG1 SEG0
Initial value
00010000
Initial value
00000000
Initial value
XXXX0000
B
B
B
• RAM for LCD indication (VRAM)
Address
H
000070
to
H
00007F
R/W: Readable and writable
X : Indeterminate
— : Undefined bits (read value undefined)
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
b7b6b5b4b3b2b1b0
R/WR/WR/WR/WR/WR/WR/WR/W
Initial value
XXXXXXXX
B
71
MB90520 Series
(2) Block Diagram
PinV0
LCDC control
CSS
HCLK
LCLK
Internal data bus
Reserved
register 0
(LCR0)
LCEN VSEL
Prescaler
Indication RAM
SEG5 SEG4
LCDC control register 1
(LCR1)
BK MS1 MS0 FP1 FP0
Timing
controller
(16 bytes)
Reserved
Controller section
2
SEG3
SEG2
32
SEG1 SEG0
Split resistor
generatorAC
6
PinV1
PinV2
PinV3
PinP74/COM0
PinP76/COM2
Common driverSegment driver
PinP77/COM3
PinSEG00
PinSEG01
PinSEG02
PinP95/SEG29
PinP75/COM1
. . . . . . . . .
. . . . . . . . .
72
HCLK: Oscillation frequency
LCLK : Sub-clock frequency
PinP96/SEG30
PinP97/SEG31
MB90520 Series
17. Communications Prescaler Register
This register controls machine clock division.
Output from the communications prescaler register is used for UART (SCI) and extended I/O serial interface.
The communications prescaler register is so designed that a constant baud rate may be acquired for various
machine clocks.
(1) Register Configuration
• Communications prescaler control register (CDCR)
Address
000027
R/W: Readable and writable
— : Undefined bits (read value undefined)
bit 15 bit 14 bit 13bit 12bit 11 bit 10bit 9bit 8
H
MD———DIV3DIV2DIV1DIV0
R/W———R/WR/WR/WR/W
Initial value
0XXX1111
B
73
MB90520 Series
18. Address Match Detection Function
When the address is equal to a value set in the address detection register, the instruction code loaded into the
CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set
instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program
patching function to be implemented.
Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value
set in the address detection register matches an address and if the interrupt enable bit is set at “1,” the instruction
code loaded into the CPU is replaced forcibly with the INT9 instruction code.
(1) Register Configuration
• Program address detection register 0 to 2 (PADR0)
Address
PADR0 (High order address) : 001FF2
bit 23 bit 22bit 21bit 20 bit 19 bit 18 bit 17bit 16
H
R/WR/WR/WR/WR/WR/WR/WR/W
Address
PADR0 (Middle order address) : 001FF1
bit 15 bit 14bit 13bit 12 bit 11 bit 10bit 9bit 8
H
R/WR/WR/WR/WR/WR/WR/WR/W
Address
PADR0 (Low order address) : 001FF0
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
H
R/WR/WR/WR/WR/WR/WR/WR/W
• Program address detection register 3 to 5 (PADR1)
Address
PADR1 (High order address) : 001FF5
Address
PADR1 (Middle order address) : 001FF4
Address
PADR1 (Low order address) : 001FF3
bit 23 bit 22bit 21bit 20 bit 19 bit 18 bit 17bit 16
H
R/WR/WR/WR/WR/WR/WR/WR/W
bit 15 bit 14bit 13bit 12 bit 11 bit 10bit 9bit 8
H
R/WR/WR/WR/WR/WR/WR/WR/W
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
H
R/WR/WR/WR/WR/WR/WR/WR/W
• Program address detection control status register (PACSR)
Address
00009E
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
Reserved
H
Reserved
Reserved
Reserved
R/WR/WR/WR/WR/WR/WR/WR/W
AD1E
Reserved
AD0E
Reserved
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
00000000
B
B
B
B
B
B
B
74
R/W: Readable and writable
X : Indeterminate
— : Undefined bits (read value undefined)
(2) Block Diagram
MB90520 Series
Address latch
Address detection register
Enable bit
Internal data bus
Compare
INT9
instruction
2
F
MC-16LX
CPU core
75
MB90520 Series
19. ROM Mirroring Function Selection Module
The ROM mirror function select module enables the R OM data from the FF bank to be read also from the 00 bank.
(1) Register Configuration
• ROM mirroring function selection register (ROMM)
Address
00006F
W : Write only
— : Undefined bits (read value undefined)
bit 15 bit 14 bit 13 bit 12bit 11 bit 10bit 9bit 8
———————MI
H
———————W
Note: Do not access this register during operation at addresses 004000
(2) Block Diagram
ROM mirroring function selection
register (ROMM)
Address area
Address
Internal data bus
FF bank00 bank
H to 00FFFFH.
Initial value
XXXXXXX1
B
76
Data
ROM
MB90520 Series
20. Low-power Consumption (Stand-b y) Mode
The F2MC-16LX has the following CPU operating modes configured b y selection of an operating clock and cloc k
operation control.
•Clock mode
PLL clock mode: A mode in which the CPU and peripheral equipment are driven by PLL-multiplied oscillation
clock.
Main clock mode: A mode in which the CPU and peripheral equipment are driven by drivided-by-2 of the
oscillation clock. The PLL multiplication circuits stops in the main clock mode.
• Sub-clock mode
The sub-clock mode causes the CPU to operate only with the sub-clock. This mode uses the sub-clock
frequency divided by four as the operating clock frequency while stopping the main clock and PLL clock.
• CPU intermittent operation mode
The CPU intermittent operation mode is a mode for reducing power consumption by operating the CPU
intermittently while external bus and peripheral functions are operated at a high speed.
• Hardware stand-b y mode
The hardware standby mode is a mode f or reducing pow er consumption by stopping cloc k supply to the CPU
by the low-pow er consumption control circuit (sleep mode), stopping clock supplies to the CPU and peripheral
functions (timebase timer mode), and stopping oscillation clock (stop mode, hardware stand-by mode). Of
these modes, modes other than the PLL clock mode are low power consumption modes.
(1) Register Configuration
• Clock select register (CKSCR)
Address
0000A1
bit 15 bit 14 bit 13bit 12bit 11 bit 10bit 9bit 8
H
SCMMCMWS1WS0SCSMCSCS1CS0
RRR/WR/WR/WR/WR/WR/W
• Low-power consumption mode control register (LPMCR)
Address
0000A0
R/W: Readable and writable
R : Read only
W : Write only
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
H
STPSLPSPLRSTTMDCG1CG0SSR
WWR/WWWR/WR/WR/W
Initial value
11111100
Initial value
00011000
B
B
77
MB90520 Series
(2) Block Diagram
Standby control circuit
Low-power consumption mode control register (LPMCR)
STP
SLP SPL RST TMD CG1 CG0 SSR
CPU intermittent
operation cycle
selector
2
Clock mode
Sleep signal
Stop signal
CPU clock
control circuit
CPU operation
clock
Hardware
standby
Reset
Interrupt
PinX0
PinX1
Clock selector
Clock oscillator
SQ
R
SQ
R
PLL multiplication
circuit
Divided-
Oscillation
clock
by-2
Peripheral clock
SQ
R
control circuit
Machine clock
SQ
R
2
2
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock select register (CKSCR)
Main
clock
Dividedby-2048
Divided-
by-4
Divided-
by-4
Timebase timer
To watchdog timer
Peripheral function
operation clock
Oscillation
stabilization
time selector
Divided-
by-8
78
PinX0A
PinX1A
S : Set
R : Reset
Q : Output
Sub-clock oscillator
Sub-clock
Dividedby-1024
Clock timer
Divided-
by-8
Divided-
by-2
Divided-
by-2
MB90520 Series
21.Clock Monitor Function
The clock monitor function outputs the frequency-divided machine clock signal (for monitor ing purposes) from
the CKOT pin.
(1) Register configuration
• Clock output enable register
Address
H
00003E
R/W:Readable and writable
—:Undefined bits (read value undefined)
(2) Block Diagram
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
CKEN FRQ2 FRQ1 FRQ0
CKEN
FQR2
FQR1
FQR0
Internal data bus
Machine clock frequency
φ :
R/W
Divider
circuit
R/WR/WR/W
φ
P31/CKOT
Initial value
XXXXXXX1
B
79
MB90520 Series
ELECTRICAL CHARACTERISTICS
■
1. Absolute Maximum Ratings
Parameter
Power supply voltage
(AVSS = VSS = 0.0 V)
Rating
Symbol
UnitRemarks
Min.Max.
V
CCVSS – 0.3VSS + 6.0V
AV
CCVSS – 0.3VSS + 6.0V*1
AVRH,
AVRL
CCVSS – 0.3VSS + 6.0V*2
DV
SS – 0.3VSS + 6.0V*1
V
Input voltage V
IVSS – 0.3VCC + 6.0V*3
Output voltageVOVSS – 0.3VCC + 6.0V*3
“L” level maximum output current I
“L” level average output current I
OL15mA*4
OLAV4mA*5
“L” level total maximum output current ΣIOL100mA
“L” level total average output currentΣI
“H” level maximum output currentI
OLAV50mA*6
OH–15mA*4
“H” level average output currentIOHAV–4mA*5
“H” level total maximum output current ΣI
“H” level total average output currentΣI
Power consumptionP
CC, AVRH, AVRL, and DVCC shall never exceed VCC. AVRL shall never exceed AVRH.
CC ≥AVCC ≥DVCC ≥3.0V
I and VO shall never exceed VCC + 0.3 V.
*4: The maximum output current is a peak value for a corresponding pin.
*5: Average output current is an average current value observed for a 100 ms period for a corresponding pin.
*6: Total average current is an average current value observed for a 100 ms period for all corresponding pins.
Note: Average output current = operating current × operating efficiency
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
80
2. Recommended Operating Conditions
Parameter
Power supply voltage
Symbol
CC3.05.5VNormal operation (MB90522, MB90523)
V
V
CC4.05.5V
CC3.05.5V
V
Value
Min.Max.
MB90520 Series
(AVSS = VSS = 0.0 V)
UnitRemarks
Normal operation (MB90F523)
Guaranteed frequency = 10 MHz
at 4.0 V to 4.5V
Retains status at the time operation
stops
Smoothing capacitorC
S0.11.0µF*
Operating temperatureTA–40+85°C
* : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be
connected to the V
CC pin must have a capacitance value higher than CS.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
• C pin diagram
C
S
C
81
MB90520 Series
3. DC Characteristics
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter SymbolPin nameCondition
P20 to P27,
P30 to P37,
“H” level
input
voltage
“L” level
input
voltage
“H” level
output
voltage
“L” level
output
voltage
Open-drain
output
leakage
current
Input
leakage
current
Pull-up
resistance
Pull-down
resistance
V
IHS
IHMMD0 to MD2VCC – 0.3—VCC + 0.3V
V
ILS
V
ILMMD0 to MD2VSS – 0.3—VSS + 0.3V
V
V
OH
V
OLAll output pins
I
leak
IL
I
UP
R
R
DOWNMD2—1530100kΩ
P53, P54,
P70 to P77,
P80 to P87,
PA0 to PA7,
P20 to P27,
P30 to P37,
P53, P54,
P70 to P77,
P80 to P87,
PA0 to PA7,
Other than P90
to P97
Output pin
P90 to P97
Other than P90
to P97
P00 to P07, P10
to P17, P40 to
P47, RST
, MD0,
MD1
VCC = 3.0 V to 5.5 V
(
MB90523)
VCC = 4.0 V to 5.5 V
(
MB90F523)
VCC = 4.5 V,
I
OH = –2.0 mA
CC = 4.5 V,
V
I
OL = 2.0 mA
——0.15µA
VCC = 5.5 V,
V
SS < VI < VCC
—1530100kΩ
Value
Min.Typ.Max.
CC—VCC + 0.3V
0.8 V
SS – 0.3— 0.2 VCCV
V
CC – 0.5——V
V
UnitRemarks
——0.4V
–5—5µA
(Continued)
82
CC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
(AV
Parameter SymbolPin nameCondition
I
CCVCC
I
CCVCC—85130mA MB90F523
CCVCC
I
I
CCVCC—90 140mA MB90F523
Internal operation
at 16 MHz
V
CC at 5.0 V
Normal operation
Internal operation
at 16 MHz
V
CC at 5.0 V
A/D converter
operation
I
CCVCC
I
CCVCC—95145mA MB90F523
Internal operation
at 16 MHz
V
CC at 5.0 V
D/A converter
operation
When data is
CCVCC
I
written or erased
in flash mode
Internal operation
at 16 MHz
V
CC at 5.0 V
In sleep mode
Internal operation
at 8 kHz
V
CC at 5.0 V
T
A = +25°C
Subsystem
Power
supply
current*
CCSVCC
I
I
CCSVCC—2530mA MB90F523
CCLVCC
I
I
CCLVCC—47mA MB90F523
operation
CCLSVCC
I
I
CCLSVCC—0.11mA MB90F523
Internal operation
at 8 kHz
V
CC at 5.0 V
TA = +25°C
In subsleep mode
I
CCTVCC
I
CCTVCC—3050µAMB90F523
Internal operation
at 8 kHz
V
CC at 5.0 V
TA = +25°C
In clock mode
I
Input
capacitance
CCHVCC
I
CCHVCC—0.110µAMB90F523
C
IN
Other than AVCC,
AVSS, C, VCC, VSS
TA = +25°C
In stop mode
——1080pF
MB90520 Series
Value
Min.Typ.Max.
—3040mA
—3545mA
—4050mA
—95140mA MB90F523
—712mA
—0.11.0mA
—3050µA
—1530µA
—520µA
UnitRemarks
MB90522,
MB90523
MB90522,
MB90523
MB90522,
MB90523
MB90522,
MB90523
MB90522,
MB90523
MB90522,
MB90523
MB90522,
MB90523
MB90522,
MB90523
(Continued)
83
MB90520 Series
(Continued)
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter SymbolPin nameCondition
Min.Typ.Max.
LCD split
resistor
R
LCD
V0 to V1,
V1 to V2,
V2 to V3
—50100200kΩ
Output
impedance
for COM0
R
VCOMCOM0 to COM3
——2.5kΩ
to COM3
V1 to V3 = 5.0 V
Output
impedance
for SEG00
R
VSEG
SEG00 to SEG31
——15kΩ
to SEG31
LCDC leak
current
I
LCDC
V0 to V3,
COM1 to COM3,
SEG00 to SEG31
——— ±5µA
* :The current value is preliminary and may be subject to change for enhanced characteristics without previous
notice.The power supply current is measured with an external clock.
Value
UnitRemarks
84
4. AC Characteristics
(1) Reset, Hardware Standby Input Timing
Parameter
Reset input timet
Hardware standby input time t
SymbolPin name Condition
RSTLRST
HSTLHST4 tCP*—ns
MB90520 Series
(AV
CC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
CL is a load capacitance connected to a pin under test.
L
of 80 pF must be connected to address data bus (AD15 to AD00).
C
0.2 V
RSTL
HSTL
t
, t
CC
0.2 V
CC
85
MB90520 Series
(2) Specification for Power-on Reset
Parameter
Power supply rising timet
Power supply cut-off timet
* :V
CC must be kept lower than 0.2 V before power-on.
Notes: • The above ratings are values for causing a power-on reset.
• T here are internal registers which can be initialized only by a power-on reset.
Apply power according to this rating to ensure initialization of the registers.
SymbolPin name Condition
RVCC
OFFVCC4—ms
R
t
—
(AV
SS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Min.Max.
UnitRemarks
0.0530ms*
Due to repeated
operations
0.2 V
2.7 V
0.2 V0.2 V
OFF
t
It is recommended to keep the rising
speed of the supply voltage at 50 mV/ms
or slower.
CC
V
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to raise the voltage
smoothly to suppress fluctuations as shown below.
In this case, change the supply voltage when the PLL clock is not in use. If the voltage drops 1 V or less per
second, however, the PLL clock may be used.
CC
V
0.2 V
SS
V
86
(3) Clock Timings
Parameter
Clock frequency
Clock cycle time
Input clock pulse width
Input clock rising/falling time
Internal operating clock
frequency
Internal operating clock cycle
time
Frequency fluctuation rate
locked
MB90520 Series
(AV
CC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
SymbolPin name Condition
F
CX0, X1—3—16MHz
F
CX0, X1
FCLX0A, X1A
t
HCYLX0, X162.5—333ns
HCYLX0, X1
t
LCYLX0A, X1A——30.5—µs
t
WH,
P
P
WL
P
WLH,
PWLL
CR,
t
t
CF
CP——1.5—16MHz
f
f
CP—
LCP———8.192—kHz
f
CP——62.5—333ns
t
t
CP—
LCP———122.1—µs
t
X0—10——ns
X0A——15.2—µs
X0, X0A———5ns
4.0 V to
4.5 V
—
4.0 V to
4.5 V
4.0 V to
4.5 V
4.0 V to
4.5 V
Min.Typ.Max.
∆f————5%*
Value
UnitRemarks
3—10MHz MB90F523
—32.768—kHz
100—333nsMB90F523
Recommended
duty ratio of
30% to 70%
External clock
operation
When the main
clock is used
1.5—10MHz
When the main
clock is used
When the
subclock is
used
When the main
clock is used
100—333ns
When the main
clock is used
When the
subclock is
used
* : The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied
PLL signal is locked.
+
+ α
| α |
∆f = × 100 (%)
O
f
Center frequency
O
f
– α
–
The PLL frequency deviation changes periodically from the preset frequency “(about CLK × (1CYC to 50 CYC),”
thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with
long intervals).
87
MB90520 Series
• X0, X1 clock timing
HCYL
t
0.8 V
X0
• X0A, X1A clock timing
0.8 V
X0A
• PLL operation guarantee range
Relationship between internal operating clock
(V)
frequency and power supply voltage
CC
5.5
4.5
4.0
3.3
3.0
Power supply voltage V
18316(MHz)
CC
WH
P
CC
WLH
P
0.8 V
LCYL
t
0.8 V
CC
0.2 V
CC
0.2 V
CC
WL
P
CF
t
CC
WLL
P
tCFt
MB90F523 operation guarantee range
PLL operation
guarantee range
MB90522,MB90523 operation guarantee range
12
10
Internal clock f
CP
CC
0.8 V
CC
0.2 V
CR
t
CC
0.8 V
CC
0.2 V
CR
MB90V520 operation guarantee range
88
(MHz)
16
CP
12
8
Internal clock f
4
3
2
Relationship between oscillating frequency and internal
operating clock frequency
Multiplied
-by-4
Multiplied
-by-3
481216(MHz)
3216
Multiplied
-by-2
Oscillation clock F
Multiplied
-by-1
C
Not multiplied
MB90520 Series
The AC ratings are measured for the following measurement reference voltages.
Resolution: Analog changes that are identifiable with the A/D converter
Linearity error: The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000
0001”) with the full-scale transition point (“11 1111 1110” ↔
conversion characteristics
Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value
Total error: The total error is defined as a difference between the actual value and the theoretical value, which
includes zero-transition error, full-scale transition error and linearity error.
Total error
3FF
“11 1111 1111”) from actual
3FE
3FD
t
u
p
t
u
o
l
004
a
t
i
g
i
D
003
002
001
1 LSB = (Theoretical value)
VOT (Theoretical value) = AVRL + 0.5 LSB [V]
FST
V
(Theoretical value) = AVRH – 1.5 LSB [V]
AVRH – AVRL
Actual conversion
characteristics
1024
{1 LSB × (N – 1) + 0.5 LSB}
(measured value)
Actual conversion
characteristics
Theoretical
characteristics
0.5 LSB
Analog inputAVRLAVRH
[V]
Total error for digital output N
VNT: Voltage at a transition of digital output from (N – 1) to N
V
NT
0.5 LSB
=
NT
– {1 LSB × (N – 1) + 0.5 LSB}
V
1 LSB
[LSB]
96
(Continued)
(Continued)
MB90520 Series
Linearity error
3FF
Actual conversion
3FE
characteristics
{1 LSB × (N – 1)
OT
}
3FD
t
u
p
t
u
o
l
004
a
t
i
g
i
D
003
002
001
+ V
OT
V
Theoretical
characteristics
(mesured value)
FST
V
(measured value)
NT
V
(measured value)
Actual conversion
characteristics
Analog inputAVRLAVRHAnalog inputAVRLAVRH
NT
V
Linearity error of
digital output N
Differential linearity error
of digital N
FST
V
1 LSB
OT
: Voltage at transition of digital output from “000H” to “001H”
V
FST
: Voltage at transition of digital output from “3FEH” to “3FFH”
V
– V
=
1022
– {1 LSB × (N – 1) + VOT}
=
OT
[V]
1 LSB
(N + 1)T
V
=
1 LSB
– V
NT
– 1 LSB [LSB]
[LSB]
t
u
p
t
u
o
l
a
t
i
g
i
D
N + 1
N – 1
N – 2
Differential linearity error
Theoretical
characteristics
Actual conversion
characteristics
N
(N + 1)T
V
(measured value)
NT
V
(measured value)
Actual conversion
characteristics
7. Notes for A/D Conversion
Analog inputs should have external circuit impedance of approximately 5 kΩ or less.
External capacitance, if used, should be several thousand times the level of the chip’s internal capacitance in
consideration of the effects of partial potential between the external and internal capacitance.
If the impedance of the external circuit is too high, the analog voltage sampling interval may be insufficient (using
a sampling interval of 4.00 µs and a machine clock frequency of 16 MHz).
• Block diagram of analog input circuit model
ON
Analog input
R
MB90522, MB90523
ON
R
: Approx. 1.5 kΩ
C: Approx. 30 pF
MB90F523
ON
: Approx. 3.0 kΩ
R
C: Approx. 65 pF
Note: Listed values must be considered standards.
•Error
The smaller | AVRH – AVRL | is, the greater the error is.
C
Comparator
97
MB90520 Series
8. D/A Converter
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, TA = –40°C to +85°C)