FUJITSU MB90520 DATA SHEET

查询MB90522供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13702-4E

16-bit Proprietary Microcontroller

CMOS

F2MC-16LX MB90520 Series

MB90522/523/F523/V520

DESCRIPTION

■

The MB90520 series is a general-purpose 16-bit microcontroller developed and designed by Fujitsu for process control applications in consumer products that require high-speed real-time processing. The instruction set of the F instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data. The MB90520 series has peripheral resources of 8/10-bit A/D converter, 8-bit D/A converter, UART (SCI), extended I/O serial interfaces 0 and 1, 8/16-bit up/down counter/timers 0 and 1, 8/16-bit PPG timers 0 and 1, I/O timer (16-bit free-run timers 1 and 2, input captures 0 and 1 (ICU), output compares 0 and 1 (OCU)), and an LCD controller/driver.

MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.

*:F

MC-16LX CPU core inherits AT architecture of the F2MC* family with additional

FEATURES

■

•Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from divided-b y-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz). The system can be operated by a sub-clock (rated at 32.768 kHz). Minimum instruction execution time: 62.5 ns (at oscillation of 4 MHz, four times the oscillation clock, operation

at V

CC of 5.0 V)

PACKAGES

■

120-pin Plastic LQFP

(FPT-120P-M05)

120-pin Plastic QFP

(FPT-120P-M13)

(Continued)

MB90520 Series

(Continued)

• Maximum memory space 16 Mbytes

• Instruction set optimized for controller applications Rich data types (bit, byte, word, long word)

Rich addressing mode (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions Enhanced precision calculation realized by 32-bit accumulator

• Instruction set designed for high level language (C) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions

• Program patch function (for two address pointers)

• Enhanced execution speed 4-byte instruction queue

• Enhanced interrupt function 8 levels, 34 factors

• Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI

• Embedded ROM size and types Mask ROM: 64 kbytes/128 kbytes Flash ROM: 128 kbytes

• Embedded RAM size Mask ROM: 4 kbytes Flash ROM: 4 kbytes Evaluation product: 6 kbytes

• Low-power consumption (stand-by) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) CPU intermittent operation mode Hardware stand-by mode Clock mode (mode in which other than sub-clock and timebase timer are stopped)

•Process CMOS technology

• I/O port General-purpose I/O ports (CMOS): 53 ports

General-purpose I/O ports (via pull-up resistors): 24 ports General-purpose I/O ports (open-drain): 8 ports Total: 85 ports

•Timer Timebase timer/watchdog timer: 1 channel 8/16-bit PPG timers 0, 1: 8-bit × 2 channels or 16-bit × 1 channel

• 16-bit re-load timers 0, 1: 2 channels

OS): Up to 16 channels

(Continued)

MB90520 Series

(Continued)

• 16-bit I/O timer 16-bit free-run timers 1, 2: 2 channels Input captures 0, 1 (ICU): Generates an interrupt request by latching a 16-bit free-run timer counter value upon

detection of an edge input to the pin.

Output compares 0, 1 (OCU): Generates an interrupt request and reverses the output le vel upon detection of a

match between the 16-bit free-run timer counter value and the compare setting value.

8/16-bit up/down counter/timers 0, 1: 1 channel (8-bit × 2 channels)

• Extended I/O serial interfaces 0, 1: 1 channel

•UART (SCI) With full-duplex double buffer Clock asynchronized or clock synchronized transmission can be selectively used.

• DTP/external interrupt circuit (8 channels) A module for starting extended intelligent I/O service (EI

by an external input.

• Wak e-up interrupt Receives external interrupt requests and generates an interrupt request upon an “L” level input.

• Delayed interrupt generation module Generates an interrupt request for switching tasks.

• 8/10-bit A/D converter (8 channels) 8/10-bit resolution can be selectively used. Starting by an external trigger input. Conversion time: minimum 15.0 µs (at machine clock frequency of 16 MHz, including sampling time)

• 8-bit D/A converter (based on the R-2R system) 8-bit resolution: 2 channels (independent)

Setup time: 12.5 µs

• Clock timer: 1 channel

• LCD controller/driver A common driver and a segment driver that can directly drive the LCD (liquid crystal display) panel

• Clock output function

OS) and generating an external interrupt triggered

Note: Do not set external bus mode for the MB90520 series because it cannot be operated in this mode.

MB90520 Series

PRODUCT LINEUP

■

Part number

Item

Classification Mask ROM product Flash ROM product Evaluation product ROM size 64 kbytes 128 kbytes None RAM size 4 kbytes 6 kbytes

CPU functions

MB90522 MB90523 MB90F523 MB90V520

Number of instructions: 351 Instruction bit length: 8 bits, 16 bits Instruction length: 1 byte to 7 bytes Data bit length: 1 bit, 8 bits, 16 bits

Minimum execution time: 62.5 ns

(at machine clock frequency of 16 MHz)

Interrupt processing time: 1.5 µs

(at machine clock frequency of 16 MHz, minimum value)

Ports

UART (SCI)

8/10-bit A/D converter

8/16-bit PPG timers 0, 1

8/16-bit up/down counter/ timers 0, 1

General-purpose I/O ports (CMOS output): 53

General-purpose I/O ports (via pull-up resistor): 24

General-purpose I/O ports (N-ch open-drain output): 8

Total: 85

Clock synchronized transmission (62.5 kbps to 1 Mbps)

Clock asynchronized transmission (1202 bps to 9615 bps)

Transmission can be performed by bi-directional serial transmission or by

master/slave connection.

Conversion precision: 8/10-bit can be selectively used.

Number of inputs: 8

One-shot conversion mode (converts selected channel only once)

Scan conversion mode (converts two or more successive channels and can

program up to 8 channels.)

Continuous conversion mode (converts selected channel continuously)

Stop conversion mode (converts selected channel and stop operation repeatedly)

Number of channels: 1 (8-bit × 2 channels)

PPG operation of 8-bit or 16-bit

Pulse wave of given intervals and given duty ratios can be output.

Pulse interval: 62.5 ns to 1 µs (at machine clock frequency of 16 MHz)

Number of channels: 1 (8-bit × 2 channels)

Event input: 6 channels

8-bit up/down counter/timer used: 2 channels

8-bit re-load/compare function supported: 1 channel

16-bit I/O timer

16-bit free-run timers 1, 2

Number of channels: 2

Overflow interrupts

(Continued)

MB90520 Series

Part number

Item

Output

16-bit I/O timer

DTP/external interrupt circuit

Wake-up intrrupt

Delayed interrupt generation module

Extended I/O serial interfaces 0, 1

Timebase timer

compares 0, 1 (OCU)

Input captures 0, 1 (ICU)

MB90523 MB90523 MB90F523 MB90V520

Number of channels: 8

Pin input factor: Match signal of compare register

Number of channels: 2

Rewriting register value upon pin input (rising, falling, or both edges)

Number of inputs: 8

Started by rising edge, falling edge, “H” level input, or “L” level input.

External interrupt circuit or extended intelligent I/O service (EI

Number of inputs: 8

Started by “L” level input.

Interrupt generation module for switching tasks

Used in real-time operating systems.

Clock synchronized transmission (3125 bps to 1 Mbps)

LSB first/MSB first

18-bit counter

Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms

(at oscillation of 4 MHz)

OS) can be used.

8-bit resolution

8-bit D/A converter

LCD controller/driver

Watchdog timer

Low-power consumption (stand-by) mode

Process CMOS Power supply voltage for

operation*

* :Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)

Assurance for the MB90V520 is given only for operation with a tool at a power voltage of 3.0 V to 5.5 V, an operating temperature of 0 to 55 degrees centigrade, and an operating frequency of 1 MHz to 16 MHz.

Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms

Sleep/stop/CPU intermittent operation/clock timer/hardware stand-by

Number of power supply pins for LCD drive: 4

3.0 V to 5.5 V 4.0 V to 5.5 V 3.0 V to 5.5 V

Number of channels: 2 channels

Based on R-2R system

Number of common output pins: 4

Number of segment output pins: 32

RAM for LCD indication: 16 bytes

Booster for LCD drive: Internal

Split resistor for LCD drive: Internal

(at oscillation of 4 MHz, minimum value)

MB90520 Series

PACKAGE AND CORRESPONDING PRODUCTS

■

Package MB90522 MB90523 MB90F523

FPT-120P-M05 FPT-120P-M13

: Available × : Not available

Note: For more information about each package, see section “■ Package Dimensions.”

DIFFERENCES AMONG PRODUCTS

■

Memory Size

In evaluation with an evaluation chip, note the difference between the evaluation chip and the chip actually used. The following items must be taken into consideration.

• The MB90V520 does not have an internal ROM. How ev er , operations equivalent to those perf ormed by a chip with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by setting the development tool.

• In the MB90V520, images from FF4000 mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.)

• In the MB90522, images from FF4000 FF only.

• In the MB90523/F523, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to bank FE and bank FF.

H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH are

H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH to bank

PIN ASSIGNMENT

■

MB90520 Series

(Top view)

P31/CKOT P32/OUT0 P33/OUT1 P34/OUT2 P35/OUT3 P36/PG00 P37/PG01

V P40/PG10 P41/PG11 P42/SIN0 P43/SOT0 P44/SCK0 P45/SIN1 P46/SOT1 P47/SCK1 SEG00 SEG01 SEG02 SEG03 SEG04 SEG05 SEG06 SEG07 PA0/SEG08 PA1/SEG09 PA2/SEG10 PA3/SEG11 PA4/SEG12 PA5/SEG13

P30

VSSP27/ADTG

P26/ZIN0/INT7

P25/BIN0

P24/AIN0

P23/IC11

P22/IC10

P21/IC01

P20/IC00

P17/WI7

P16/WI6

P15/WI5

P14/WI4

P13/WI3

P12/WI2

P11/WI1

P10/WI0

P07

P06/INT6

P05/INT5

P04/INT4

P03/INT3

P02/INT2

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

3132333435363738394041424344454647484950515253545556575859

1009998979695949392

P01/INT1

P00/INT0

VCCX1X0V

90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

RST MD0 MD1 MD2 HST V3 V2 V1 V0 P97/SEG31 P96/SEG30 P95/SEG29 P94/SEG28 P93/SEG27 P92/SEG26 P91/SEG25 X0A X1A P90/SEG24 P87/SEG23 P86/SEG22 P85/SEG21 P84/SEG20 P83/SEG19 P82/SEG18 P81/SEG17 P80/SEG16

V P77/COM3 P76/COM2

PA6/SEG14

PA7/SEG15

VSSC

P50/SIN2/AIN1

P51/SOT2/BIN1

P52/SCK2/ZIN1

DVCCDVSSP53/DA0

P54/DA1

AVCCAVRH

AVRL

(FPT-120P-M05) (FPT-120P-M13)

AVSSP60/AN0

P61/AN1

P62/AN2

P63/AN3

P64/AN4

P65/AN5

P66/AN6

P67/AN7

VCCP70/TI0/OUT4

P71/TO0/OUT5

P72/TI1/OUT6

P73/TO1/OUT7

P74/COM0

P75/COM1

MB90520 Series

PIN DESCRIPTION

■

Pin no.

Pin name

LQFP-120*

QFP-120*

92,

74,

89 to 87 MD0 to MD2 C This is an input pin for selecting operation modes.

95 to 101 P00 to P06 D This is a general-purpose I/O port.

102 P07 D This is a general-purpose I/O port.

103 to 110 P10 to 17 D This is a general-purpose I/O port.

111, 112, 113,

114

115 P24 E This is a general-purpose I/O port.

116 P25 E This is a general-purpose I/O port.

X0,

90 RST C This is an external reset request signal input pin. 86 HST

X1 X0A,

X1A

INT0 to INT6 This is a request input pin of the DTP/external interrupt circuit ch.0

WI0 to WI7 This is an I/O pin for wake-up interrupts. P20,

P21, P22, P23

IC00, IC01, IC10, IC11

AIN0 This port can be used as count clock A input for 8/16-bit up/down

BIN0 This port can be used as count clock B input for 8/16-bit up/down

Circuit

type

A This is a high-speed crystal oscillator pin.

B This is a low-speed crystal oscillator pin.

Connect directly to V

C This is a hardware stand-by input pin.

This function can be set by the port 0 input pull-up resistor setup register (RDR0) for input. For output, however, this function is invalid.

to ch.6.

This function can be set by the port 0 input pull-up resistor setup register (RDR0) for input. For output, however, this function is invalid.

This function can be set by the port 1 input pull-up resistor setup register (RDR1) for input. For output, however, this function is invalid.

E This is a general-purpose I/O port.

This is a trigger input pin for input capture (ICU) 0 and 1. Since this input is used as required for input capture 0 and 1 (ICU) ch.0, ch.01, ch.10 and ch.11 input operation, output by other functions must be suspended except for intentional operation.

counter/timer 0.

CC or VSS.

Function

*1: FPT-120P-M05 *2: FPT-120P-M13

(Continued)

Pin no.

Pin name

LQFP-120*

QFP-120*

117 P26 E This is a general-purpose I/O port.

118 P27 E This is a general-purpose I/O port.

120 P30 E This is a general-purpose I/O port.

ZIN0 This port can be used as count clock Z input for 8/16-bit up/down

INT7 This is a request input pin of the DTP/external interrupt circuit

ADTG

1 P31 E This is a general-purpose I/O port.

CKOT This is a clock monitor function output pin.

2 P32 E This is a general-purpose I/O port.

OUT0 This is an event output pin for output compare 0 (OCU) ch.0.

3 P33 E This is a general-purpose I/O port.

OUT1 This is an event output pin for output compare 0 (OCU) ch.1.

4 P34 E This is a general-purpose I/O port.

OUT2 This is an event output pin for output compare 0 (OCU) ch.2.

5 P35 E This is a general-purpose I/O port.

OUT3 This is an event output pin for output compare 0 (OCU) ch.3.

6 P36 E This is a general-purpose I/O port.

PG00 This is an output pin of 8/16-bit PPG timer 0.

Circuit

type

counter/timer 0.

ch.7.

This is an external trigger input pin of the 8/10-bit A/D converter. Since this input is used as required for 8/10-bit A/D conv erter input operation, output by other functions must be suspended e xcept f or intentional operation.

This function is valid when clock monitor output is enabled.

This function becomes valid when waveform output from the OUT0 is disabled.

This function is valid when output for each channel is enabled.

This function becomes valid when waveform output from the OUT1 is disabled.

This function is valid when output for each channel is enabled.

This function becomes valid when waveform output from the OUT2 is disabled.

This function is valid when output for each channel is enabled.

This function becomes valid when waveform output from the OUT3 is disabled.

This function is valid when output for each channel is enabled.

This function becomes valid when wa vef orm output from the PG00 is disabled.

This function becomes valid when waveform output from PG00 is enabled.

MB90520 Series

Function

*1: FPT-120P-M05 *2: FPT-120P-M13

(Continued)

MB90520 Series

Pin no.

Pin name

LQFP-120*

QFP-120*

7 P37 E This is a general-purpose I/O port.

PG01 This is an output pin of 8/16-bit PPG timer 0.

11 P42 D This is a general-purpose I/O port.

12 P43 D This is a general-purpose I/O port.

13 P44 D This is a general-purpose I/O port.

14 P45 D This is a general-purpose I/O port.

P40, P41

PG10, PG11

SIN0 This is a serial data input pin of UART (SCI).

SOT0 This is a serial data output pin of UART (SCI).

SCK0 This is a serial clock I/O pin of UART (SCI).

SIN1 This is a data input pin for extended I/O serial interface 0.

Circuit

type

This function becomes valid when wa vef orm output from the PG01 is disabled.

This function becomes valid when waveform output from PG01 is enabled.

D This is a general-purpose I/O port.

This function becomes valid when wa vef orm output from the PG10 and PG11 are disabled. This function can be set by the pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid.

This is an output pin of 8/16-bit PPG timer 1. This function becomes valid when waveform outputs from PG10 and PG11 are enabled.

This function can be set by the pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid.

Because this input is used as required when UART (SCI) is performing input operations, it is necessary to stop outputs by other functions unless such outputs are made intentionally. When using other output functions as well, disable output during SIN operation.

This function can be set by the pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid.

This function becomes valid when serial data output from UART (SCI) is enabled.

This function can be set by the pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid.

This function becomes valid when serial clock output from UART (SCI) is enabled.

This function can be set by the port 4 input pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid.

Since this input is used as required for serial data input operation, output by other functions must be suspended e xcept for intentional operation. When using other output functions as well, disable output during SIN operation.

Function

*1: FPT-120P-M05 *2: FPT-120P-M13

(Continued)

Pin no.

Pin name

LQFP-120*

QFP-120*

40,

46 to 53 P60 to P67 K This is a general-purpose I/O port.

15 P46 D This is a general-purpose I/O port.

SOT1 This is a data output pin for extended I/O serial interface 0.

16 P47 D This is a general-purpose I/O port.

SCK1 This is a serial clock I/O pin for extended I/O serial interface 0.

35 P50 D This is a general-purpose I/O port.

SIN2 This is a data input pin for extended I/O serial interface 1.

AIN1 This port can be used as count clock A input for 8/16-bit up/down

36 P51 D This is a general-purpose I/O port.

SOT2 This is a data output pin for extended I/O serial interface 1.

BIN1 This port can be used as count clock B input for 8/16-bit up/down

37 P52 D This is a general-purpose I/O port.

SCK2 This is a serial clock I/O pin for extended I/O serial interface 1.

ZIN1 This port can be used as control clock Z input for 8/16-bit up/do wn

P53,

P54 DA0,

DA1

AN0 to AN7 These are analog input pins of the 8/10-bit A/D converter.

Circuit

type

This function can be set by the port 4 input pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid.

This function becomes valid when serial data output from SOT1 is enabled.

This function can be set by the port 4 input pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid.

This function becomes valid when serial clock output from SCK1 is enabled.

Since this input is used as required for serial data input operation, output by other functions must be suspended e xcept for intentional operation.

counter/timer 1.

This function becomes valid when serial data output from SOT2 is enabled.

counter/timer 1.

This function becomes valid when serial clock output from serial SCK2 is enabled.

counter/timer 1.

I This is a general-purpose I/O port.

These are analog signal output pins for 8-bit D/A converter ch.0 and ch.1.

The input function become valid when the analog input enable register (ADER) is set to select a port.

This function is valid when the analog input enable register (ADER) is enabled.

Function

MB90520 Series

*1: FPT-120P-M05 *2: FPT-120P-M13

(Continued)

MB90520 Series

Pin no.

Pin name

P70, P72

TI0, TI1

OUT4, OUT6

P71, P73

LQFP-120*

QFP-120*

55,

56,

Circuit

type

E This is a general-purpose I/O port.

These are event input pins for 16-bit re-load timers 0 and 1. Since this input is used as required for 16-bit re-load timers 0 and 1 operation, output by other functions must be suspended except for intentional operation.

These are event output pins for output compare 1 (OCU) ch.4 and ch.6. This function is valid when output for each channel is enabled.

E This is a general-purpose I/O port.

This function is valid when TO0 and TO1 output are disabled.

Function

TO0, TO1

OUT5, OUT7

These are output pins for 16-bit re-load timers 0 and 1. This function is valid when TO0 and TO1 output are enabled.

These are event output pins for output compare 1 (OCU) ch.5 and ch.7. This function is valid when output for each channel is enabled.

59 to 62 P74 to P77 L This is a general-purpose I/O port.

This function is valid with port output specified for the LCD controller/driver control register.

COM0 to COM3

These are common pins for the LCD controller/driver. This function is valid with common output specified for the LCD controller/driver control register.

64 to 71 P80 to P87 L This is a general-purpose I/O port.

This function is valid with port output specified for the LCD controller/driver control register.

SEG16 to SEG23

These are segment outputs for the LCD controller/driver. This function is valid with segment output specified for the LCD controller/driver control register.

72,

75 to 81

P90, P91 to P97

M This is a general-purpose I/O port.

The maximum I

OL can be 10mA.

This function is valid with port output specified for the LCD controller/driver control register.

SEG24, SEG25 to SEG31

17 to 24 SEG00 to

SEG07

F These are pins dedicated to LCD segments 00 to 07 for the LCD

These are segment outputs for the LCD controller/driver. This function is valid with port output specified for the LCD controller/driver control register.

controller/driver.

25 to 32 PA0 to PA7 L This is a general-purpose I/O port.

This function is valid with port output specified for the LCD controller/driver control register.

SEG08 to SEG15

These are pins for LCD segments 08 to 15 for the LCD controller/ driver. Units of four ports or segments can be selected by the internal register in the LCD controller.

*1: FPT-120P-M05 *2: FPT-120P-M13

(Continued)

MB90520 Series

(Continued)

Pin no.

LQFP-120*

QFP-120*

Pin name

34 C G This is a capacitance pin for power supply stabilization.

82 to 85 V0 to V3 N This is a pin for the reference power supply for the LCD controller/

CC Power

54,

33,

SS Power

63, 91,

119

42 AV

CC H This is a power supply for the analog circuit.

43 AVRH J This is a reference v oltage input to the analog circuit.

44 AVRL H This is a reference voltage input to the analog circuit. 45 AV 38 DV

39 DV

SS H This is a GND level of the analog circuit. CC H This is the Vref input pin for the D/A converter.

SS H This is the GND level pin for the D/A converter.

Circuit

type

supply

Function

Connect an external ceramic capacitor rated at about 0.1 µF. This capacitor is not, however, required for the M90F523 (flash product).

driver. This is a power supply (5.0 V) input pin to the digital circuit.

This provides the GND level (0.0 V) input pin for the digital circuit.

Make sure to turn on/turn off this power supply with a voltage exceeding AV

CC applied to VCC.

Make sure to turn on/turn off this power supply with a voltage exceeding AVRH applied to AV

The voltage to be applied must not exceed V

The potential must be the same as V

CC.

SS.

*1: FPT-120P-M05 *2: FPT-120P-M13

MB90520 Series

I/O CIRCUIT TYPE

■

Type Circuit Remarks

A • High-speed oscillation feedback resistor

approx. 1MΩ

Nch

Pch

Pch Nch

Standby control signal

B • Low-speed oscillation feedback resistor

X1A

X0A

Nch

Pch Pch

Nch

Standby control signal

approx. 1MΩ

C • Hysteresis input

Hysteresis input

D • Hysteresis input (can be set with the input

Pch

Selecting signal with or without a input pull-up resistor

pull-up resistor) CMOS level output

• Pull-up resistor approx. 50 kΩ

• Provided with a standby control function

OL = 4 mA

Nch

Hysteresis input

Standby control for input interruption

for input interruption

(Continued)

MB90520 Series

Type Circuit Remarks

E • CMOS hysteresis input/output

Pch

IOL = 4 mA

F • Pins dedicated to segment output

Nch

Hysteresis input

Standby control for input interruption

• CMOS level output

• Provided with a standby control function for input interruption

Pch

Nch

G • C pin output

(Pin for capacitor connection)

Pch

Nch

N.C. pin for the MB90F523

H • Analog power input protector

Pch

AVP

Nch

I • CMOS hysteresis input/output

• Pin for analog output/CMOS output (During analog output, CMOS output is not produced.)

Pch

(Analog output has priority over CMOS

Nch

output: DAE = 1)

• Provided with a standby control function

OL = 4 mA

Hysteresis input

Standby control for input interruption

DAO

for input interruption

(Continued)

MB90520 Series

Type Circuit Remarks

J • Input pin for ref+ power for the A/D

Pch

Nch

Pch Nch

ANE AVR ANE

K • Hysteresis input/analog input

Pch

Nch

converter Provided with power protection

• CMOS output

• Provided with a standby control for input interruption

OL = 4 mA

Standby control for input interruption

Hysteresis input

Analog input

L • CMOS hysteresis input/output

Pch

• Segment input

• Standby control to cut off the input is available in segment input operation

Nch

Standby control for input interruption

IOL = 4 mA

Hysteresis input

SEG

M • Hysteresis input

Nch

• Nch open-drain output (High current for LCD drive)

• Standby control to cut off the input is

IOL = 10 mA

Nch

Hysteresis input

Standby control for input interruption

available in segment input operation

N • Reference power supply pin for the LCD

controller

IOL = 10 mA

Pch

Nch

MB90520 Series

HANDLING DEVICES

■

1. Ensuring that the Voltage does not exceed the Maximum Rating (to Avoid a Latch-up).

In CMOS ICs, a latch-up phenomenon is caused when a voltage exceeding VCC or below VSS is applied to input or output pins or if a voltage exceeding the rating is applied across VCC and VSS. When a latch-up is caused, the power supply current may be dramatically increased, resulting in thermal breakdown of devices. To avoid the latch-up, make sure that the voltage does not exceed the maximum rating. In turning on/turning off the analog power supply, make sure the analog power voltages (AVCC, AVRH, DVCC) and analog input voltages do not exceed the digital voltage (V And also make sure the voltages applied to the LCD power supply pins (V3 to V0) do not exceed the power supply voltage (V

CC).

2. Handling Unused Pins

• Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. Unused input pins should be pulled-up or pull-down through at least 2 kΩ resistance.

• Unused input/output pins may be left open in output state, but if such pins are in input state they should be handled in the same way as input pins.

CC).

3. Notes on Using External Clock

In using the external clock, drive X0 pin only and leave X1 pin unconnected.

Using external cloc k

•

Open

MB90520 series

4. Unused Sub Clock Mode

If sub clock modes are not used, the oscillator should be connected to the X0A pin and X1A pin.

5. Power Supply Pins

In products with multiple Vcc or Vss pins, pins with the same potential are internally connected in the device to avoid abnormal operations including latch-ups. However, the pins should be connected to external powers and ground lines to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect V It is recommended that a bypass capacitor of around 0.1 µF be placed between the V device.

cc and Vss pins via lowest impedance to power lines.

cc and Vss pins near the

MB90520 Series

Using

•

power supply pins

MB90520 series

6. Crystal Oscillator Circuit

Noise around the X0 and X1 pins may cause abnormal operation in this device. In designing printed circuit boards, the X0 and X1 pins and crystal oscillator (or ceramic oscillator), as well as the bypass capacitor to the ground, should be placed as close as possible, and the related wiring should have as few crossings with other wiring as possible. Circuit board artwork in which the area of the X0 and X1 pins is surrounded by grounding is recommended for stabilizing the operation.

7. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVRL, DVCC, DVSS) and analog inputs (AN0 to AN7) after turning on the digital power supply (VCC). Turn off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that AVRH and DV acceptable).

CC do not exceed AVCC (turning on/off the analog and digital supplies simultaneously is

8. Connection of Unused Pins of A/D Converter

Connect unused pins of A/D converter and those of D/A converter to AVCC = DVCC = VCC, AVSS = AVRH = AVRL = V

SS.

9. N.C. Pin

The N.C. (internally connected) pin must be opened for use.

10.Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 µs or more (0.2 V to 2.7 V).

11.Use of SEG/COM Pins for the LCD Controller/Driver as Ports

In MB90520 series, pins SEG08 to SEG31, and COM0 to COM3 can also be used as general-purpose ports. The electrical standard is such that pins SEG08 to SEG23, and COM0 to COM3 have the same ratings as the CMOS output port, while pins SEG24 to SEG31 have the same ratings as the open-drain type.

MB90520 Series

12.

Indeterminate outputs from ports 0 and 1

The outputs from ports 0 and 1 become indeterminate during oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on. Pay attention to the port output timing shown as follow

Timming chart of indeterminate outputs from ports o and 1

•

Oscillation setting time

∗2

Step-down circuit

setting time

∗1

Vcc(power-supply pin)

PONR(power-on reset) signal

(external asynchronous reset) signal

RST

RST(internal reset) signal

Oscillation clock signal

KA(internal operation clock A) signal KB(internal operation clock B) signal

PORT(port output)signal

indereterminate period

* : 1:Step-down circuit setting time : 217/oscillation clock frequency (oscillation clock frequency of 16 MHz: 8.19 ms) * :2:Oscillation setting time: 2

/oscillation clock frequency (oscillation cllock frequency of 16 MHz: 16.38 ms)

13.Initialization

The device contains internal registers that can be initialized only by a power-on reset. To initialize the internal registers, restart the power supply.

14. Interrupt Recovery from Standby

If an external interrupt is used for recovery from standby, use an “H” level input request. An “L” level request causes abnormal operation.

15.Precautions for Use of “DIV A, Ri”, and “DIVW A, Ri” Instructions

The signed multiplication-division instructions “DIV A, Ri”, and “DIVW A, RWi” should be used when the corresponding bank registers (DTB, ADB, USB, SSB) are set to value “00h”. If the corresponding bank registers (DTB, ADB, USB, SSB) are set to a value other than “00h,” then the remainder obtained after the execution of the instruction will not be placed in the instruction operand register.

16.

Precautions for Use of REALOS

Extended intelligent I/O service(EI

OS) cannot be used, when REALOS is used.

MB90520 Series

BLOCK DIAGRAM

■

X0, X1 X0A, X1A RST HST

P07 P00/INT0 to P06/INT6

P24/AIN0 P25/BIN0 P26/ZIN0/INT7

P20/IC00 P21/IC01

P32/OUT0 P33/OUT1 P34/OUT2 P35/OUT3

P31/CKOT P30

P36/PG00 P37/PG01

P40/PG10 P41/PG11

P42/SIN0 P43/SOT0 P44/SCK0

P45/SIN1 P46/SOT1 P47/SCK1

Oscillation clock

Sub clock

F2MC-16LX

CPU

Clock control

block*

(including

timebase timer)

Port 0*

DTP/ external interrupt

circuit

Port 2*

8/16-bit

up/down

counter/timer

0, 1

16-bit

I/O timer 1

Input

capture 0

(ICU)

16-bit

free-run

timer 1 Output

compare 0

(OCU)

Clock output

Port 3*

8/16-bit

PPG

timer 0, 1

UART

(SCI)

SIO ch.0

Port 4*

Port 8*

LCD

controller/

driver

Port 7*

, 9*5, A*

P80/SEG16 to P87/SEG23

P90/SEG24 to P97/SEG31

PA0/SEG08 to PA7/SEG15

SEG00 to SEG07

V0 to V3

P74/COM0 to P77/COM3

16-bit re-load timer 0

16-bit re-load timer 1

16-bit

I/O timer 2

Output

compare

(OCU)

16-bit free-run

timer 2

capture 1

Input (ICU)

Port 2*

Port 6*

Intrnal data bus

8/10-bit

A/D

converter

P70/TI0/OUT4 P71/TO0/OUT5 P72/TI1/OUT6 P73/TO1/OUT7

P22/IC10 P23/IC11

P60/AN0 to P67/AN7

AV AVRH AVRL P27/ADTG

Port 2*

Interrupt controller

Port 5*

P50/SIN2/AIN1

SIO ch.1

P51/SOT2/BIN1 P52/SCK2/ZIN1

P10/WI0 to P17/WI7

Port 1*

Wake-up

interrupt

8-bit D/A

converter

× 2 ch.

P53/DA0 P54/DA1

DV DV

Other pins

MD0 to MD2,

, V

C, V

RAM ROM

Notes: Actually 16-bit free-run timer 1 is supported although two free-run timers are seemingly supported. *1: The clock control circuit comprises a watchdog timer, a timebase timer, and a power consumption controller. *2: A register for setting a pull-up resistor is supported. *3: This is a high-current port for an LCD drive. *4: A register for setting a pull-up resistor is supported. Signals in the CMOS level are input and output. *5: Also used for LCD output. With this port used as is, Nch open-drain output develops . A register f or setting a pull-up resi stor

is supported.

CC SS

MEMORY MAP

■

FFFFFF

Address #1

FE0000

010000

Address #2

004000

002000 Address #3

000100

0000C0

000000

Single chip mode A mirroring function is supported.

ROM area

(image of

bank FF)

RAM

Peripheral

MB90520 Series

Part number Address #1* Address #2 * Address #3 *

MB90522 FF0000

H 004000H 001100H

MB90523 FE0000H 004000H 001100H MB90F523 FE0000H 004000H 001100H

: Internal access memory : Access prohibited

*: Addresses #1, #2 and #3 vary with product type.

Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C

compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 are assigned to the same address, enabling reference of the table on the ROM without stating “far.”

For e xample, if an attempt has been made to access 00C000

H, the contents of the ROM at FFC000H are

actually accessed. Since the ROM area of the FF bank exceeds 48k bytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000 were the image for 00400 the area of FF4000

H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in

H to FFFFFFH.

H to FFFFFFH looks, therefore, as if it

MB90520 Series

MC-16LX CPU PROGRAMMING MODEL

■

• Dedicated registers

AH AL

USP

SSP

DPR

PCB

DTB

USB

: Accumlator (A)

Dual 16-bit register used for storing results of calculation, etc. The two 16-bit registers can be combined to be used as a 32-bit register.

: User stack pointer (USP)

16-bit pointer for containing a user stack address.

: System stack pointer (SSP)

16-bit pointer for displaying the status of the system stack address.

: Processor status (PS)

16-bit register for displaying the system status.

: Program counter (PC)

16-bit register for displaying the storing location of the current instruction code.

: Direct page register (DPR)

8-bit register for specifying bit 8 through 15 of the operand address in the short direct addressing mode.

: Program bank register (PCB)

8-bit register for displaying the program space.

: Data bank register (DTB)

8-bit register for displaying the data space.

: User stack bank register (USB)

8-bit register for displaying the user stack space.

32-bit

16-bit

SSB

ADB

8-bit

: System stack bank register (SSB)

8-bit register for displaying the system stack space.

: Additional data bank register (ADB)

8-bit register for displaying the additional data space.

• General-purpose registers

MB90520 Series

Maximum of 32 banks

000180

+ (RP × 10H )

• Processor status (PS)

ILM RP CCR

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

ILM2 B4ILM1 ILM0 B3 B2 B1 B0 — I S T N Z V C

R7 R5

R3 R1

RW3 RW2 RW1 RW0

16-bit

R6 R4

R2 R0

RW7

RL3

RW6 RW5

RL2

RW4

RL1

RL0

Initial value

— : Unused

X : Indeterminate

00 000000 10XXXXX

—

MB90520 Series

I/O MAP

■

Address

000000

Abbreviated

name

H PDR0 Port 0 data register R/W Port 0 XX X XXXXX B

Read/

write

Resource name Initial value

000001H PDR1 Port 1 data register R/W Port 1 XX X XXXXX B 000002H PDR2 Port 2 data register R/W Port 2 XX X XXXXX B 000003H PDR3 Port 3 data register R/W Port 3 XX X XXXXX B 000004H PDR4 Port 4 data register R/W Port 4 XX X XXXXX B 000005H PDR5 Port 5 data register R/W Port 5 XX X XXXXX B 000006H PDR6 Port 6 data register R/W Port 6 XX X XXXXX B 000007H PDR7 Port 7 data register R/W Port 7 XX X XXXXX B 000008H PDR8 Port 8 data register R/W Port 8 XX X XXXXX B 000009H PDR9 Port 9 data register R/W Port 9 XX X XXXXX B

00000AH PDRA Port A data register R/W Port A XXXXX X X X B 00000BH LCDCMR Port 7/COM pin selection register R/W 00000CH

OCP4 OCU compare register ch.4 R/W

00000DH XXXXXXXXB

Port 7,

LCD controller/driver

16-bit I/O timer

(output compare 1

(OCU) section)

XXXX0 000B XXXXXXXXB

00000EH (Disabled) 00000F

H EIFR Wake-up interrupt flag register R/W

Wake-up interrupt

XXXXXXX0 B 000010H DDR0 Port 0 direction register R/W Port 0 0 0 0 0 0 0 0 0 B 000011H DDR1 Port 1 direction register R/W Port 1 0 0 0 0 0 0 0 0 B 000012H DDR2 Port 2 direction register R/W Port 2 0 0 0 0 0 0 0 0 B 000013H DDR3 Port 3 direction register R/W Port 3 0 0 0 0 0 0 0 0 B 000014H DDR4 Port 4 direction register R/W Port 4 0 0 0 0 0 0 0 0 B 000015H DDR5 Port 5 direction register R/W Port 5 XXX 0 0 0 0 0 B 000016H DDR6 Port 6 direction register R/W Port 6 0 0 0 0 0 0 0 0 B 000017H DDR7 Port 7 direction register R/W Port 7 0 0 0 0 0 0 0 0 B 000018H DDR8 Port 8 direction register R/W Port 8 0 0 0 0 0 0 0 0 B 000019H DDR9 Port 9 direction register R/W Port 9 0 0 0 0 0 0 0 0 B

00001AH DDRA Port A direction register R/W Port A 0 0 0 0 0 0 0 0 B 00001BH ADER Analog input enable register R/W 00001CH

OCP5 OCU compare register ch.5 R/W

00001DH XXXXXXXXB

Port 6,

A/Dconverter

16-bit I/O timer

(output compare 1

(OCU) section)

11111111B

XXXXXXXXB

00001EH (Disabled) 00001F

H EICR Wake-up interrupt enable register W

Wake-up interrupt

00000000B

(Continued)

MB90520 Series

Address

name

Abbreviated

000020

H SMR Serial mode register R/W

000021H SCR Serial control register

Read/

write

R/W or

Resource

name

Initial value

00000000B 00000100B

UART

000022H

SIDR/

SODR 000023H SSR Serial status register 000024H SMCSL0 Serial mode control lower status register 0 R/W

000025H SMCSH0 Serial mode control upper status register 0 R/W 0 0 0 0 0 0 1 0 B 000026H SDR0 Serial data register 0 R/W XXXXXXXXB

Serial input data register/ serial output data register

R/W or

(SCI)

Extended I/O

serial

interface 0

XXXXXXXX

00001X00B XXXX0 000B

Communica-

000027H CDCR Communications prescaler control register R/W

tions prescaler

0XXX1111B

control register 000028H SMCSL1 Serial mode control lower status register 1 R/W 000029H SMCSH1 Serial mode control upper status register 1 R/W 0 0 0 0 0 0 1 0 B 00002AH SDR1 Serial data register 1 R/W XXXXXXXXB

Extended I/O

serial

interface 1

XXXX0 000B

00002BH (Disabled) 00002C 00002DH XXX0 0000B 00002EH

OCS45 OCU control status register ch.45 R/W

OCS67 OCU control status register ch.67 R/W

16-bit I/O timer

(output com-

pare 1 (OCU)

section)

0000XX00B

0000XX00 00002FH XXX0 00 00B 000030H ENIR DTP/interrupt enable register R/W 000031H EIRR DTP/interrupt factor register R/W X X X X XXXX B 000032H

DTP/external

interrupt circuit

00000000B

00000000

ELVR Request level setting register R/W

000033H 00000000B 000034H

OCP6 OCU compare register ch.6 R/W

000035H XXXXXXXXB

16-bit I/O timer

(output com-

pare 1 (OCU)

section)

000036H ADCS1 A/D control status register lower digits R/W 000037H ADCS2 A/D control status register upper digits R/W 0 0 0 0 0 0 0 0 B 000038H ADCR1 A/D data register lower digits R X X X X XXXX B

8/10-bit A/D

converter

XXXXXXXXB

00000000B

000039H ADCR2 A/D data register upper digits R or W 0 0 0 0 1 XX X B 00003AH DADR0 D/A converter data register ch.0 R/W 00003BH DADR1 D/A converter data register ch.1 R/W XXXXX X X X B 00003CH DACR0 D/A control register 0 R/W XXXXXXX0B

8-bit D/A

converter

XXXXXXXXB

00003DH DACR1 D/A control register 1 R/W XXXXXXX0B 00003EH CLKR Clock output enable register R/W

Clock monitor

function

XXXX0 000B

(Continued)

MB90520 Series

Address

name

Abbreviated

00003F

000040

H (Disabled) H PRLL0 PPG0 re-load register L R/W

000041H PRLH0 PPG0 re-load register H R/W XXXX X X X X B 000042H PRLL1 PPG1 re-load register L R/W XX X XXXXX B 000043H PRLH1 PPG1 re-load register H R/W XXXX X X X X B 000044H PPGC0 PPG0 operating mode control register R/W 0 X 0 0 0 X X 1 B 000045H PPGC1 PPG1 operating mode control register R/W 0 X 0 0 0 0 0 1 B

000046H

PPGOE0/

PPGOE1

PPG0 and 1 output control registers R/W 0 0 0 0 0 0 0 0

000047H (Disabled) 000048

Timer control status register lower ch.0

TMCSR0

000049H Timer control status register upper ch.0 XXXX 0 0 0 0 B 00004AH 00004BH XXXXXXXXB 00004CH

TMR0/

TMRLR0

16-bit timer register upper, lower ch.0/ 16-bit re-load register upper, lower ch.0

Timer control status register lower ch.1

TMCSR1

00004DH Timer control status register upper ch.1 XXXX 0 0 0 0 B 00004EH 00004FH XXXXXXXXB

TMR1/

TMRLR1

16-bit timer register upper, lower ch.1/ 16-bit re-load register upper, lower ch.1

000050H

IPCP0 ICU data register ch.0 R

000051H XXXXXXXXB

000052H

IPCP1 ICU data register ch.1 R

000053H XXXXXXXXB

000054H ICS01 ICU control status register R/W 0 0 0 0 0 0 0 0 B

000055H (Disabled)

000056

TCDT1 Free-run timer data register 1 R/W

000057H 00000000B

000058H TCCS1

Free-run timer control status register 1

000059H (Disabled) 00005A

OCP0 OCU compare register ch.0 R/W

00005BH XXXXXXXXB 00005CH

OCP1 OCU compare register ch.1 R/W

00005DH XXXXXXXXB 00005EH

OCP2 OCU compare register ch.2 R/W

00005FH XXXXXXXXB

000060H

OCP3 OCU compare register ch.3 R/W

000061H XXXXXXXXB

Read/

write

Resource name Initial value

XXXXXXXXB

8/16-bit PPG

timer 0, 1

00000000

R/W

16-bit re-load

timer 0

XXXXXXXX

R/W

00000000

R/W

16-bit re-load

timer 1

XXXXXXXX

R/W

XXXXXXXXB

16-bit I/O timer

(input compare 0,

1 (ICU) section)

16-bit I/O timer

XXXXXXXX

00000000

(16-bit free-run

R/W 00000000B

timer 1 section)

XXXXXXXXB

XXXXXXXX

16-bit I/O timer

(output compare 0

(OCU) section)

XXXXXXXX

(Continued)

MB90520 Series

Address

name

Abbreviated

000062

OCS01 OCU control status register ch.01 R/W

000063H XXX00000B 000064H

OCS23 OCU control status register ch.23 R/W

000065H XXX00000B 000066H

TCDT2 Free-run timer data register 2 R/W

000067H 00000000B 000068H TCCS2

Free-run timer control status register 2

000069H (Disabled) 00006A

H LCR0

LCDC control registers 0 and 1

00006BH LCR1 R/W 00000000B

00006CH

OCP7 OCU compare register ch.7 R/W

00006DH XXXXXXXXB 00006EH (Disabled)

00006F

H ROMM

ROM mirroring function selection register

000070H

VRAM RAM for LCD indication R/W

00007FH

000080H UDCR0 Up/down count register 0 R 000081H UDCR1 Up/down count register 1 R 0 0 0 0 0 0 0 0 B 000082H RCR0 Re-load compare register 0 W 0 0 0 0 0 0 0 0 B 000083H RCR1 Re-load compare register 1 W 0 0 0 0 0 0 0 0 B 000084H CSR0 Counter status register 0 R/W 00000000B 000085H

(Reserved area)*

000086H CCRL0

Counter control register 0 R/W

000087H CCRH0 00000000B 000088H CSR1 Counter status register 1 R/W 00000000B 000089H

(Reserved area)*

00008AH CCRL1

Counter control register 1 R/W

00008BH CCRH1 X0000000B

00008CH RDR0

00008DH RDR1

00008EH RDR4

Port 0 input pull-up resistor setup register

Port 1 input pull-up resistor setup register

Port 4 input pull-up resistor setup register

Read/

write

Resource name Initial value

0000XX00B

16-bit I/O timer

(output compare 0

(OCU) section)

16-bit I/O timer

(16-bit free-run

R/W 00000000B

R/W

timer 2 section)

LCD controller/

0000XX00

00000000B

00010000B

driver

16-bit I/O timer

(output compare 1 (OCU) section)

XXXXXXXXB

ROM mirroring

function

XXXXXXX1 B

selection module

LCD controller/

driver

XXXXXXXXB

00000000B

8/16-bit up/down

counter/timer

0, 1

8/16-bit up/down

X0000000

counter/timer

0, 1

8/16-bit up/down

X0000000B

counter/timer

0, 1

R/W Port 0 00000000

R/W Port 1 00000000B

R/W Port 4 00000000B

(Continued)

MB90520 Series

Address

name

Abbreviated

00008F 00009D

00009EH PACSR

00009FH DIRR

0000A0H LPMCR

(Area used by the system)*

Program address detection control status register

Delayed interrupt factor generation/ cancellation register

Low-power consumption mode

control register 0000A1H CKSCR Clock select register 0000A2H

(Disabled)

0000A7H 0000A8

H WDTC Watchdog timer control register R or W Watchdog timer X X XXXXXX B

0000A9H TBTC Timebase timer control register R/W Timebase timer 1 XX 0 0 0 0 0 B

0000AAH WTC Clock timer control register 0000ABH

0000AD 0000AE

H FMCS Flash control register R/W Flash interface 1 XX 0 0 1 0 0 B

(Disabled)

0000AFH (Disabled)

0000B0

H ICR00 Interrupt control register 00 R/W

0000B1H ICR01 Interrupt control register 01 R/W 0 0 0 0 0 1 1 1 B 0000B2H ICR02 Interrupt control register 02 R/W 0 0 0 0 0 1 1 1 B 0000B3H ICR03 Interrupt control register 03 R/W 0 0 0 0 0 1 1 1 B 0000B4H ICR04 Interrupt control register 04 R/W 0 0 0 0 0 1 1 1 B 0000B5H ICR05 Interrupt control register 05 R/W 0 0 0 0 0 1 1 1 B 0000B6H ICR06 Interrupt control register 06 R/W 0 0 0 0 0 1 1 1 B 0000B7H ICR07 Interrupt control register 07 R/W 0 0 0 0 0 1 1 1 B 0000B8H ICR08 Interrupt control register 08 R/W 0 0 0 0 0 1 1 1 B 0000B9H ICR09 Interrupt control register 09 R/W 0 0 0 0 0 1 1 1 B

0000BAH ICR10 Interrupt control register 10 R/W 0 0 0 0 0 1 1 1 B 0000BBH ICR11 Interrupt control register 11 R/W 0 0 0 0 0 1 1 1 B 0000BCH ICR12 Interrupt control register 12 R/W 0 0 0 0 0 1 1 1 B 0000BDH ICR13 Interrupt control register 13 R/W 0 0 0 0 0 1 1 1 B

Read/

write

R/W

R/W or

Resource name Initial value

Address match

detection

00000000B

function

Delayed inter-

rupt generation

XXXXXXX0 B

module

Low-power

00011000B

consumption

(stand-by) mode

11111100

Clock timer 1X001000B

00000111B

Interrupt

controller

(Continued)

MB90520 Series

Address

name

Abbreviated

0000BE

H ICR14 Interrupt control register 14 R/W

0000BFH ICR15 Interrupt control register 15 R/W 0 0 0 0 0 1 1 1 B

Read/

write

Resource name Initial value

Interrupt

00000111B

controller

0000C0H

(External area)*

0000FFH 000100H

00####

(RAM area)*

00####H

001FEF

001FF0H 001FF1H Program address detection register 1 R/W XXXXXX X X B

Program address detection register 0 R/W

PADR0

(Reserved area)*

XXXXXXXX

Address match

001FF2H Program address detection register 2 R/W XXXXXX X X B 001FF3H 001FF4H Program address detection register 4 R/W XXXXXX X X B

PADR1

Program address detection register 3 R/W X X X X X X X X

detection

function

001FF5H Program address detection register 5 R/W XXXXXX X X B 001FF6H

001FFF

(Reserved area)*

Descriptions for read/write

R/W: Readable and writable R: Read only W: Write only

Descriptions for initial value

0 : The initial value is “0.” 1 : The initial value is “1.” X : The initial value is indeterminate.

*1: This area is the only external access area having an address of 0000FF

H or lower . An access oper ation to this

area is handled as that to external I/O area. *2: For details of the “RAM area”, see the memory map. *3: The “reserved area” is basically disabled because it is used in the system. *4: “Area used by the system” is the area set by the resistor for evaluating tool.

Notes: • F or bits initialized by reset operations , the initial value set by the reset oper ation is listed as an initial value.

Note that the values are different from reading results. For LPMCR/CKSCR/WDTC, there are cases in which initialization is performed or not performed, depending on the types of the reset. The value listed is the initial value in cases where initialization is per formed.

• The addresses following 0000FF

H are reserved. No external bus access signal is generated.

• Boundary ####H between the “RAM area” and the“ reserved area” varies with the product models.

• Channels 0 to 3 of the OCU compare register use 16-bit free-run timer 2, while channels 4 to 7 of the OCU compare register use 16-bit free-run timer 1. 16-bit free-run timer 1 is also used by input captures (ICU) 0 and 1.

MB90520 Series

INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTERS

■

Interrupt source

support

Interrupt vector Interrupt control register

Number Address ICR Address

Reset × # 08 FFFFDC INT9 instruction × # 09 FFFFD8 Exception × # 10 FFFFD4 8/10-bit A/D converter # 11 FFFFD0 Timebase timer × # 12 FFFFCCH DTP0/DTP1 (external interrupt 0/

external interrupt 1)

# 13 FFFFC8

16-bit free-run timer 1 overflow × # 14 FFFFC4H Extended I/O serial interface 0 # 15 FFFFC0H Wake-up interrupt × # 16 FFFFBCH Extended I/O serial interface 1 # 17 FFFFB8H DTP2/DTP3 (external interrupt 2/

external interrupt 3) 8/16-bit PPG timer 0 counter

borrow DTP4/DTP5 (external interrupt 4/

external interrupt 5) 8/16-bit up/down counter/timer 0

compare match 8/16-bit up/down counter/timer 0

overflow up/down inversion

× # 19 FFFFB0

# 18 FFFFB4

# 20 FFFFAC

# 21 FFFFA0

# 22 FFFFA4

Priority

H ——High H —— H ——

ICR00 0000B0H

ICR01 0000B1H

ICR02 0000B2H

ICR03 0000B3H

ICR04 0000B4H

ICR05 0000B5H

8/16-bit PPG timer 1 counter borrow

× # 23 FFFFA0

ICR06 0000B6H

DTP6/DTP7 (external interrupt 6/ external interrupt 7)

Output compare 1 (OCU) ch.4/ch.5 match

# 24 FFFF9C

# 25 FFFF98

ICR07 0000B7H

Clock prescaler × # 26 FFFF94H Output compare 1 (OCU) ch.6/ch.7

match

# 27 FFFF90

ICR08 0000B8H

16-bit free-run timer 2 overflow × # 28 FFFF8CH 8/16-bit up/down counter/timer 1

compare match

# 29 FFFF88

ICR09 0000B9H

8/16-bit up/down counter/timer 1 overflow, up/down inversion

# 30 FFFF84

Input capture 0 (ICU) include # 31 FFFF80H

ICR10 0000BAH

Input capture 1 (ICU) include # 32 FFFF7CH Low

(Continued)

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