FUJITSU MB90480, MB90485 DATA SHEET

查询MB90487BPF供应商
FUJITSU SEMICONDUCTOR
DATA SHEET
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90480/485 Series
MB90F481/F482/487B/488B/483C MB90F488B/F489B/V480/V485B
DESCRIPTION
The MB90480/485 series is a 16-bit general-purpose FUJITSU microcontroller designed for process control in consumer devices and other applications requiring high-speed real-time processing.
2
The F
MC-16LX CPU core instruction set retains the AT architecture of the F2MC*1 family, with additional instruc­tions for high-level languages, expanded addressing mode, enhanced multiply-drive instructions, and complete bit processing. In addition, a 32-bit accumulator is provided to enable long-word processing.
DS07-13722-8E
The MB90480/485 series features embedded peripheral resources including 8/16-bit PPG, expanded I/O serial interface, UART, 10-bit A/D converter, 16-bit I/O timer, 8/16-bit up/down-counter, PWC timer, I external interrupt, chip select, and 16-bit reload timer.
2
*1 : F
MC is the abbreviation for FUJITSU Flexible Microcontroller.
*2 : Purchase of Fujitsu I
components in an I by Philips.
2
C components conveys a license under the Philips I2C Patent Rights to use, these
2
C system provided that the system conforms to the I2C standard a Specification as defined
2C*2
interface, DTP/
FEATURES
•Clock
Minimum instruction execution time: 40.0 ns/6.25 MHz base frequency multiplied × 4 (25 MHz internal operating
• Maximum memory space: 16 Mbytes
frequency/3.3 V ± 0.3 V)
62.5 ns/4 MHz base frequency multiplied × 4 (16 MHz internal operating frequency/3.0 V ± 0.3 V) PLL clock multiplier
(Continued)
“Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Copyright©2002-2006 FUJITSU LIMITED All rights reserved
MB90480/485 Series
(Continued)
• Instruction set optimized for controller applications Supported data types (bit, byte, word, or long word)
Typical addressing modes (23 types) 32-bit accumulator for enhanced high-precision calculation Enhanced signed multiplication/division instruction and RETI instruction functions
• Instruction set designed for high-level programming language (C) and multi-task operations System stack pointer adopted Instruction set symmetry and barrel shift instructions
• Non-multiplex bus/multiplex bus compatible
• Enhanced execution speed 4-byte instruction queue
• Enhanced interrupt functions 8 levels setting with programmable priority, 8 external interrupts
• Data transfer function (µDMAC) Up to 16 channels
• Embedded ROM Flash versions : 192 Kbytes, 256 Kbytes, 384 Kbytes, MASK versions : 192 Kbytes, 256 Kbytes
• Embedded RAM Flash versions : 4 Kbytes, 6 Kbytes, 10 Kbytes, 24 Kbytes, MASK versions : 10 Kbytes, 16 Kbytes
• General purpose ports Up to 84 ports (Includes 16 ports with input pull-up resistance settings, 16 ports with output open-drain settings)
• A/D converter 8-channel RC sequential comparison type (10-bit resolution, 3.68 µs conversion time (at 25 MHz) )
2
•I
C interface (MB90485 series only) : 1channel, P76/P77 N-ch open drain pin (without P-ch)
Do not apply high voltage in excess of recommended operating ranges to the N-ch open drain pin (with P-ch) in MB90V485B.
µPG (MB90485 series only) : 1 channel
• UART : 1 channel
• Extended I/O serial interface (SIO) : 2 channels
• 8/16-bit PPG : 3 channels (with 8-bit × 6 channel/16-bit × 3 channel mode switching function)
• 8/16-bit up/down counter/timer: 1 channel (with 8-bit × 2 channels/16-bit × 1-channel mode switching function)
• PWC (MB90485 series only) : 3 channels (Capable of compare the inputs to two of the three)
• 3 V/5 V I/F pin (MB90485 series only) P20 to P27, P30 to P37, P40 to P47, P70 to P77
• 16-bit reload timer : 1 channel
• 16-bit I/O timer : 2 channels input capture, 6 channels output compare, 1 channel free run timer
• On chip dual clock generator system
• Low-power consumption mode With stop mode, sleep mode, CPU intermittent operation mode, watch mode, timebase timer mode
• Packages : QFP 100/LQFP 100
• Process : CMOS technology
• Power supply voltage : 3 V, single power supply (some ports can be operated by 5 V power supply at MB90485 series)
2
MB90480/485 Series
PRODUCT LINEUP
MB90480 series
Part number
Item
Classification Flash memory product Evaluation product ROM size 192 Kbytes 256 Kbytes RAM size 4 Kbytes 6 Kbytes 16 Kbytes
CPU function
Ports
UART 1 channel, start-stop synchronized 8/16-bit PPG 8-bit × 6 channels/16-bit × 3 channels 8/16-bit up/down
counter/timer
16-bit free run timer
16-bit I/O timers
DTP/external interrupt circuit Number of external interrupt pin channels : 8 (edge or level detection) Extended I/O serial interface Embedded 2 channels
Timebase timer
A/D converter
Watchdog timer
Low-power consumption (standby) modes
Process CMOS
Type Not included security function
Emulator power supply*
Output compare (OCU)
Input capture (ICU)
2
MB90F481 MB90F482 MB90V480
Number of instructions : 351 Instruction bit length : 8-bit, 16-bit Instruction length : 1 byte to 7 bytes Data bit length : 1-bit, 8-bit, 16-bit Minimum instruction execution time : 40 ns (25 MHz machine clock)
General-purpose I/O ports: up to 84 General-purpose I/O ports (CMOS output) General-purpose I/O ports (with pull-up resistance) General-purpose I/O ports (N-ch open drain output)
Event input pins : 6, 8-bit up/down counters : 2 8-bit reload/compare registers : 2
Number of channels : 1 Overflow interrupt
Number of channels : 6 Pin input factor : A match signal of compare register
Number of channels : 2 Rewriting a register value upon a pin input (rising, falling, or both edges)
18-bit counter Interrupt cycles: 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator)
Conversion resolution : 8/10-bit, switchable One-shot conversion mode (converts selected channel 1 time only) Scan conversion mode (conversion of multiple consecutive channels,
programmable up to 8 channels) Continuous conversion mode (repeated conversion of selected channels) Stop conversion mode (conversion of selected channels with repeated pause)
Reset generation interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(minimum value, at 4 MHz base oscillator)
Stop mode, sleep mode, CPU intermittent operation mode, watch timer mode, timebase timer mode
1
User pin* 3 V/5 V versions
Included
,
*1 : User pin : P20 to P27, P30 to P37, P40 to P47, P70 to P77
*2 : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used.
Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply switching) about details.
Note : Ensure that you must write to Flash at V
CC = 3.13 V to 3.60 V (3.3 V + 10%, 5%) .
3
MB90480/485 Series
MB90485 series
Part number
Item
MB90487B MB90488B MB90F488B MB90V485B MB90F489B MB90483C
Flash
Classification MASK ROM product
ROM size 192 Kbytes 256 Kbytes 256 Kbytes 384 Kbytes 256 Kbytes
RAM size 10 Kbytes 10 Kbytes 10 Kbytes 16 Kbytes 24 Kbytes 16 Kbytes
Number of instructions : 351 Instruction bit length : 8-bit, 16-bit
CPU function
General-purpose I/O ports : up to 84
Ports
UART 1 channel, start-stop synchronized 8/16-bit PPG 8-bit × 6 channels/16-bit × 3 channels
8/16-bit up/down counter/timer
16-bit free run timer
16-bit I/O timers
Output compare (OCU)
General-purpose I/O ports (CMOS output) General-purpose I/O ports (with pull-up resistance) General-purpose I/O ports (N-ch open drain output)
Event input pins : 6, 8-bit up/down counters : 2 8-bit reload/compare registers : 2
Number of channels : 1 Overflow interrupt
Number of channels : 6 Pin input factor: A match signal of compare register
Instruction length : 1 byte to 7 bytes Data bit length : 1-bit, 8-bit, 16-bit Minimum instruction execution time : 40 ns (25 MHz machine clock)
memory
product
Evaluation
product
Flash
memory
product
MASK ROM
product
Input capture (ICU)
DTP/external interrupt circuit
Extended I/O serial interface
2
C interface*
I µPG 1 channel
PWC 3 channels
Timebase timer
A/D converter
4
2
Number of channels : 2 Rewriting a register value upon a pin input (rising, falling, or both edges)
Number of external interrupt pin channels: 8 (edge or level detection)
Embedded 2 channels
1 channel
18-bit counter Interrupt cycles : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator)
Conversion resolution : 8/10-bit, switchable One-shot conversion mode (converts selected channel 1 time only) Scan conversion mode (conversion of multiple consecutive channels,
Continuous conversion mode (repeated conversion of selected channels) Stop conversion mode (conversion of selected channels with repeated pause)
programmable up to 8 channels)
(Continued)
(Continued)
Item
Part number
MB90480/485 Series
MB90487B MB90488B MB90F488B MB90V485B MB90F489B MB90483C
Watchdog timer
Low-power consumption (standby) modes
Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(minimum value, at 4 MHz base oscillator)
Stop mode, sleep mode, CPU intermittent operation mode, watch timer mode, timebase timer mode
Process CMOS
Type
Emulator power supply*
3
3 V/5 V power
3 V/5 V
power
supply*
3 V/5 V
power
1
supply*
1
supply*
Included
security
1
3 V/5 V
power
supply*
function
⎯⎯ ⎯Included ⎯⎯
3 V/5 V power
Included
1
supply*
security
function
1
3 V/5 V
power
supply*
*1 : 3 V/5 V I/F pin : All pins should be for 3 V power supply without P20 to P27, P30 to P37, P40 to P47, and
P70 to P77.
*2 : P76/P77 pins are N-ch open drain pins (without P-ch) at built-in I
2
C. However, MB90V485B uses the N-ch open
drain pin (with P-ch) .
*3 : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used.
Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details.
Notes : As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/µPG/I
2
C
become CMOS input.
Ensure that you must write to Flash at V
CC = 3.13 V to 3.60 V (3.3 V + 10%, 5%) .
1
5
MB90480/485 Series
PIN ASSIGNMENT
P17/AD15/D15
P16/AD14/D14
P15/AD13/D13
P14/AD12/D12
P13/AD11/D11
99989796959493929190898887868584838281
100
1P20/A16 P21/A17 P22/A18 P23/A19
P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3
P30/A00/AIN0 P31/A01/BIN0
P32/A02/ZIN0 P33/A03/AIN1 P34/A04/BIN1
P35/A05/ZIN1 P36/A06/PWC0* P37/A07/PWC1*
P40/A08/SIN2
P41/A09/SOT2
P42/A10/SCK2 P43/A11/MT00* P44/A12/MT01*
P45/A13/EXTC*
P46/A14/OUT4
P47/A15/OUT5
SS
V
V
CC
P70/SIN0 P71/SOT0 P72/SCK0
P73/TIN0
5
2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31P74/TOT0
32333435363738394041424344454647484950
(TOP VIEW)
P12/AD10/D10
P11/AD09/D09
P10/AD08/D08
P07/AD07/D07
P06/AD06/D06
P05/AD05/D05
P04/AD04/D04
P03/AD03/D03
P02/AD02/D02
P01/AD01/D01
CC3
SS
X1X0V
P00/AD00/D00
V
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
X0A X1A P57/CLK RST P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE PA3/OUT3 PA2/OUT2 PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/PPG5 P94/PPG4 P93/FRCK/ADTG/CS3 P92/SCK1/CS2 P91/SOT1/CS1 P90/SIN1/CS0 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2 MD2
SS
CC
AV
P76/SCL*
P77/SDA*
P75/PWC2*
AV
AVRH
P60/AN0
P61/AN1
P62/AN2
P63/AN3
Vss
P64/AN4
P65/AN5
P66/AN6
P67/AN7
MD0
P80/IRQ0
P81/IRQ1
MD1
(FPT-100P-M06)
* : These are the pins for MB90485 series. The pins for MB90480 series are P36/A06, P37/A07,
P43/A11, P44/A12, P45/A13, P75 to P77.
Note : MB90485 series only
2
I
C pin P77 and P76 are N-ch open drain pin (without P-ch) . However, MB90V485B uses
the N-ch open drain pin (with P-ch) .
P20 to P27, P30 to P37, P40 to P47 and P70 to P77 are also used as 3 V/5 V I/F pin.
As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for
PWC/µPG/I
2
C become CMOS input.
6
(TOP VIEW)
MB90480/485 Series
P22/A18
P23/A19 P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3
P30/A00/AIN0
1/A01/BIN0
P3
V
SS
P32/A02/ZIN0 P33/A03/AIN1 P34/A04/BIN1
P35/A05/ZIN1 P36/A06/PWC0* P37/A07/PWC1*
P40/A08/SIN2
P41/A09/SOT2
P42/A10/SCK2 P43/A11/MT00* P44/A12/MT01*
V
CC5
P45/A13/EXTC*
P46/A14/OUT4
P47/A15/OUT5
P70/SIN0
P02/AD02/D02
P01/AD01/D01
P07/AD07/D07
P06/AD06/D06
P05/AD05/D05
P04/AD04/D04
P12/AD10/D10
P11/AD09/D09
P21/A17
P20/A16
P17/AD15/D15
9998979695949392919089888786858483828180797877
100
1 2
3
4 5 6 7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
26272
P14/AD12/D12
P16/AD14/D14
P15/AD13/D13
8
293031323334353637383940414243444546474849
P10/AD08/D08
P13/AD11/D11
P03/AD03/D03
P00/AD00/D00
CC3
V
X1X0V
SS
X0A
X1A
P57/CLK
76
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
ST
R P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE PA 3/OUT3 PA2/OUT2 PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/PPG5 P94/PPG4 P93/FRCK/ADTG/CS3 P92/SCK1/CS2 P91/SOT1/CS1 P90/SIN1/CS0 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3
SS
CC
AV
AV
AVRH
P60/AN0
P73/TIN0
P76/SCL*
P72/SCK0
P74/TOT0
P71/SOT0
P77/SDA*
P75/PWC2*
P61/AN1
SS
V
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
P80/IRQ0
P81/IRQ1
MD0
MD1
MD2
P82/IRQ2
(FPT-100P-M05)
* : These are the pins for MB90485 series. The pins for MB90480 series are P36/A06, P37/A07, P43/
A11, P44/A12, P45/A13, P75 to P77.
Note : MB90485 series only
2
I
C pin P77 and P76 are N-ch open drain pin (without P-ch) . However, MB90V485B uses
the N-ch open drain pin (with P-ch) .
P20 to P27, P30 to P37, P40 to P47 and P70 to P77 are also used as 3 V/5 V I/F pin.
As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/
2
µPG/I
C become CMOS input.
7
MB90480/485 Series
PIN DESCRIPTIONS
QFP*
Pin No.
1
LQFP*
Pin name
2
I/O
circuit
3
type*
82 80 X0 A Clock (oscillator) input pin
83 81 X1 A Clock (oscillator) output pin
80 78 X0A A Clock (32 kHz oscillator) input pin
79 77 X1A A Clock (32 kHz oscillator) output pin
77 75 RST
B Reset input pin
This is a general purpose I/O port. A setting in the port 0 input
P00 to P07
resistance register (RDR0) can be used to apply pull-up resistance (RD00-RD07 = “1”) . (Disabled when pin is set for output.)
85 to 92 83 to 90
AD00 to
AD07
D00 to D07
C
(CMOS)
In multiplex mode, these pins function as the external address/data bus low I/O pins.
In non-multiplex mode, these pins function as the external data bus low output pins.
This is a general purpose I/O port. A setting in the port 1 input
P10 to P17
resistance register (RDR1) can be used to apply pull-up resistance (RD10-RD17 = “1”) . (Disabled when pin is set for output.)
93 to
100
91 to 98
AD08 to
AD15
D08 to D15
C
(CMOS)
In multiplex mode, these pins function as the external address/data bus high I/O pins.
In non-multiplex mode, these pins function as the external data bus high output pins.
Function
1 to 4
99, 100,
1, 2
5 to 8 3 to 6
97
This is a general purpose I/O port. When the bits of external address
P20 to P23
output control register (HACR) are set to "1" in external bus mode, these pins function as general purpose I/O ports.
When the bits of external address output control register (HACR) are set to "0" in multiplex mode, these pins function as address high output pins (A16-A19). When the bits of external address output control register (HACR) are
A16 to A19
E
CMOS/H)
(
set to "0" in non-multiplex mode, these pins function as address high output pins (A16-A19).
This is a general purpose I/O port. When the bits of external address
P24 to P27
output control register (HACR) are set to "1" in external bus mode, these pins function as general purpose I/O ports.
When the bits of external address output control register (HACR) are set to "0" in multiplex mode, these pins function as address high output pins (A20-A23). When the bits of external address output control register (HACR) are
A20 to A23
E
CMOS/H)
(
set to "0" in non-multiplex mode, these pins function as address high output pins (A20-A23).
PPG0 to
PPG3
P30
A00
E
CMOS/H)
(
Output pins for PPG.
This is a general purpose I/O port.
In non-multiplex mode, this pin functions as an external address pin.
AIN0 8/16-bit up/down timer input pin (ch.0) .
(Continued)
8
MB90480/485 Series
Pin No.
1
QFP*
LQFP*
10 8
12 10
13 11
14 12
15 13
16, 17 14, 15
Pin
name
2
P31
A01 In non-multiplex mode, this pin functions as an external address pin.
I/O
circuit
3
type*
E
( CMOS/H)
Function
This is a general purpose I/O port.
BIN0 8/16-bit up/down timer input pin (ch.0) .
P32
A02 In non-multiplex mode, this pin functions as an external address pin.
E
(
CMOS/H)
This is a general purpose I/O port.
ZIN0 8/16-bit up/down timer input pin (ch.0)
P33
A03 In non-multiplex mode, this pin functions as an external address pin.
E
(
CMOS/H)
This is a general purpose I/O port.
AIN1 8/16-bit up/down timer input pin (ch.1) .
P34
A04 In non-multiplex mode, this pin functions as an external address pin.
E
(
CMOS/H)
This is a general purpose I/O port.
BIN1 8/16-bit up/down timer input pin (ch.1) .
P35
A05 In non-multiplex mode, this pin functions as an external address pin.
E
(
CMOS/H)
This is a general purpose I/O port.
ZIN1 8/16-bit up/down timer input pin (ch.1)
P36, P37
A06, A07
P36, P37
A06, A07
PWC0,
PWC1*
(
4
D
(CMOS)
E
CMOS/H)
MB90480
series
MB90485
series
This is a general purpose I/O port.
In non-multiplex mode, this pin functions as an external address pin.
This is a general purpose I/O port.
In non-multiplex mode, this pin functions as an external address pin.
This is a PWC input pin.
18 16
19 17
20 18
P40
A08 In non-multiplex mode, this pin functions as an external address pin.
G
CMOS/H)
(
This is a general purpose I/O port.
SIN2 Extended I/O serial interface input pin.
P41
A09 In non-multiplex mode, this pin functions as an external address pin.
F (CMOS)
This is a general purpose I/O port.
SOT2 Extended I/O serial interface output pin.
P42
A10 In non-multiplex mode, this pin functions as an external address pin.
G
(
CMOS/H)
This is a general purpose I/O port.
SCK2 Extended I/O serial interface clock input/output pin.
(Continued)
9
MB90480/485 Series
Pin No.
1
QFP*
LQFP*
21, 22 19, 20
24 22
25, 26 23, 24
I/O
Pin name
2
P43, P44
A11, A12
P43, P44
A11, A12
MT00,
MT01
P45
A13
P45
A13
EXTC*
P46, P47
A14, A15 In non-multiplex mode, this pin functions as an external address pin.
OUT4/
OUT5
circuit
F (CMOS)
F (CMOS)
(CMOS)
CMOS/H)
(
4
(CMOS)
type*
F
G
F
3
This is a general purpose I/O port.
MB90480
series
In non-multiplex mode, this pin functions as an external address pin.
This is a general purpose I/O port.
MB90485
series
In non-multiplex mode, this pin functions as an external address pin.
µPG output pin.
This is a general purpose I/O port.
MB90480
series
In non-multiplex mode, this pin functions as an external address pin.
This is a general purpose I/O port.
MB90485
series
In non-multiplex mode, this pin functions as an external address pin.
µPG input pin.
This is a general purpose I/O port.
Output compare event output pins.
Function
70 68
71 69
72 70
73 71
P50
ALE
P51
RD
P52
WRL
P53
WRH
D
(CMOS)
D
(CMOS)
D
(CMOS)
D
(CMOS)
This is a general purpose I/O port. In external bus mode, this pin functions as the ALE pin.
In external bus mode, this pin functions as the address load enable (ALE) signal pin.
This is a general purpose I/O port. In external bus mode, this pin functions as the RD
pin.
In external bus mode, this pin functions as the read strobe output (RD) signal pin.
This is a general purpose I/O port. In external bus mode, when the WRE bit in the EPCR register is set to “1”, this pin functions as the WRL
pin.
In external bus mode, this pin functions as the lower data write strobe output (WRL
) pin. When the WRE bit in the EPCR register is set to “0”,
this pin functions as a general purpose I/O port.
This is a general purpose I/O port. In external bus mode with 16-bit bus width, when the WRE bit in the EPCR register is set to “1”, this pin functions as the WRH
pin.
In external bus mode with 16-bit bus width, this pin functions as the upper data write strobe output (WRH
) pin. When the WRE bit in the EPCR register is set to “0”, this pin functions as a general purpose I/O port.
(Continued)
10
MB90480/485 Series
Pin No.
1
QFP*
74 72
75 73
76 74
78 76
38 to
41
LQFP*
36 to 39
I/O
Pin name
2
circuit
3
type*
Function
This is a general purpose I/O port. In external bus mode, when the
P54
D
(CMOS)
HRQ
HDE bit in the EPCR register is set to “1”, this pin functions as the HRQ pin.
In external bus mode, this pin functions as the hold request input (HRQ) pin. When the HDE bit in the EPCR register is set to “0”, this pin functions as a general purpose I/O port.
This is a general purpose I/O port. In external bus mode, when the
P55
D
(CMOS)
HAK
HDE bit in the EPCR register is set to “1”, this pin functions as the HAK pin.
In external bus mode, this pin functions as the hold acknowledge out­put (HAK
) pin. When the HDE bit in the EPCR register is set to “0”, this
pin functions as a general purpose I/O port.
This is a general purpose I/O port. In external bus mode, when the
P56
D
(CMOS)
RDY
RYE bit in the EPCR register is set to “1”, this pin functions as the RDY pin.
In external bus mode, this pin functions as the external ready (RDY) input pin. When the RYE bit in the EPCR register is set to “0”, this pin functions as a general purpose I/O port.
This is a general purpose I/O port. In external bus mode, when the
P57
D
(CMOS)
CLK
CKE bit in the EPCR register is set to “1”, this pin functions as the CLK pin.
In external bus mode, this pin functions as the machine cycle clock (CLK) output pin. When the CKE bit in the EPCR register is set to “0”, this pin functions as a general purpose I/O port.
P60 to P63
AN0 to AN3 These are the analog input pins for A/D converter.
H
(CMOS)
These are general purpose I/O ports.
43 to
46
41 to 44
27 25
28 26
29 27
30 28
31 29
P64 to P67
AN4 to AN7 These are the analog input pins for A/D converter.
P70
SIN0 This is the UART serial data input pin.
P71
SOT0 This is the UART serial data output pin.
P72
SCK0 This is the UART serial communication clock I/O pin.
P73
TIN0 This is the 16-bit reload timer event input pin.
P74
TOT0 This is the 16-bit reload timer output pin.
H
(CMOS)
G
(
CMOS/H)
F
(CMOS)
G
CMOS/H)
(
G
(
CMOS/H)
F
(CMOS)
These are general purpose I/O ports.
This is a general purpose I/O port.
This is a general purpose I/O port.
This is a general purpose I/O port.
This is a general purpose I/O port.
This is a general purpose I/O port.
(Continued)
11
MB90480/485 Series
Pin No.
1
QFP*
LQFP*
32 30
33 31
34 32
47, 48 45, 46
I/O
2
Pin name
P75
P75
PWC2*
P76
P76
4
SCL*
4
circuit
3
type*
F
(CMOS)
G
CMOS/H)
(
F
(CMOS)
I
(NMOS/H)
MB90480
series
MB90485
series
MB90480
series
MB90485
series
This is a general purpose I/O port.
This is a general purpose I/O port.
This is a PWC input pin.
This is a general purpose I/O port.
This is a general purpose I/O port.
Serves as the I2C interface data I/O pin. During opera­tion of the I impedance state.
P77
P77
SDA*
4
F
(CMOS)
I
(NMOS/H)
MB90480
series
MB90485
series
This is a general purpose I/O port.
This is a general purpose I/O port.
Serves as the I2C interface data I/O pin. During opera­tion of the I impedance state.
P80, P81
IRQ0, IRQ1 External interrupt input pins.
E
(
CMOS/H)
These are general purpose I/O ports.
Function
2
C interface, leave the port output in a high
2
C interface, leave the port output in a high
52 to 57 50 to 55
58 56
59 57
60 58
61 59
62 60
P82 to P87
IRQ2 to IRQ7 External interrupt input pins.
E
CMOS/H)
(
P90
SIN1 Extended I/O serial interface data input pin.
E
CMOS/H)
(
These are general purpose I/O ports.
This is a general purpose I/O port.
CS0 Chip select 0.
P91
SOT1 Extended I/O serial interface data output pin.
D
(CMOS)
This is a general purpose I/O port.
CS1 Chip select 1.
P92
SCK1 Extended I/O serial interface clock input/output pin.
E
(
CMOS/H)
This is a general purpose I/O port.
CS2 Chip select 2.
P93
FRCK
ADTG
E
(
CMOS/H)
This is a general purpose I/O port.
When the free run timer is in use, this pin functions as the external clock input pin.
When the A/D converter is in use, this pin functions as the external trigger input pin.
CS3 Chip select 3.
P94
PPG4 PPG timer output pin.
D
(CMOS)
This is a general purpose I/O port.
(Continued)
12
(Continued)
Pin No.
1
QFP*
LQFP*
2
Pin name
I/O
circuit
type*
MB90480/485 Series
Function
3
63 61
64 62
65 63
66 to 69 64 to 67
OUT0 to OUT3
35 33 AV
P95
PPG5 PPG timer output pin.
P96
IN0 Input capture ch.0 trigger input pin.
P97
IN1 Input capture ch.1 trigger input pin.
PA0 to PA3
D
(CMOS)
E
(
CMOS/H)
E
(
CMOS/H)
D
(CMOS)
CC A/D converter analog power supply input pin.
This is a general purpose I/O port.
This is a general purpose I/O port.
This is a general purpose I/O port.
These are general purpose I/O ports.
Output compare event output pins.
36 34 AVRH A/D converter reference voltage input pin.
37 35 AV
49 to 51 47 to 49 MD0 to MD2
84 82 V
SS A/D converter GND pin.
J
CMOS/H)
(
CC3 3.3 V ± 0.3 V power supply pins (VCC3) .
Operating mode selection input pins.
MB90480
series
3.3 V ± 0.3 V power supply pin. Usually, use VCC = VCC3 = VCC5 as a 3 V power supply.
3 V/5 V power supply pin.
23 21 V
CC5
MB90485
series
5 V power supply pin when P20 to P27, P30 to P37, P40 to P47, P70 to P77 are used as 5 V I/F pins. Usually, use V
CC = VCC3 = VCC5 as a 3 V power supply
(when the 3 V power supply is used alone) .
11, 42, 819, 40,
79
SS GND pins.
V
*1 : QFP : FPT-100P-M06
*2 : LQFP : FPT-100P-M05
*3 : For the I/O circuit type, refer to “ I/O CIRCUIT TYPES”.
*4 : As for MB90V485B, input pins become CMOS input.
13
MB90480/485 Series
I/O CIRCUIT TYPES
Type Circuit Remarks
• Feedback resistance
X1, X1A
X0, X0A
• With standby control
A
Standby control signal
Hysteresis input with pull-up resistance
X1, X0 : approx. 1 M X1A, X0A : approx. 10 M
B
Hysteresis input
• With input pull-up resistance
CTL
P-ch P-ch
C
N-ch
CMOS
control
• CMOS level input/output
CMOS level input/output
P-ch
N-ch
D
CMOS
14
• Hysteresis input
P-ch
N-ch
• CMOS level output
E
CMOS
(Continued)
MB90480/485 Series
(Continued)
Type Circuit Remarks
• CMOS level input/output
P-ch
Open drain control signal
F
N-ch
P-ch
CMOS
Open drain control signal
G
N-ch
Hysteresis input
• With open drain control
• CMOS level output
• Hysteresis input
• With open drain control
• CMOS level input/output
P-ch
N-ch
• Analog input
H
CMOS
Analog input
• Hysteresis input
N-ch
Digital output
• N-ch open drain output
I
(Flash memory product)
(Flash memory product)
• CMOS level input
• With high voltage control for flash testing
Control signal
J
Mode input
Diffusion resistance
(MASK ROM product)
(MASK ROM product) Hysteresis input
Hysteresis input
15
MB90480/485 Series
HANDLING DEVICES
1. Be careful never to exceed maximum rated voltages (preventing latch-up)
In CMOS IC devices, a condition known as latch-up may occur if voltages higher than VCC or lower than VSS are applied to input or output pins other than medium-or high-voltage pins, or if the voltage applied between V V
SS pins exceeds the rated voltage level.
When latch-up occurs, the power supply current increases rapidly causing the possibility of thermal damage to circuit elements. Therefore it is necessary to ensure that maximum ratings are not exceeded in circuit operation. Similarly, when turning the analog power supply on or off, it is necessary to ensure that the analog power supply voltages (AV
2. Treatment of unused pins
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 k. Any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins.
3. Treatment of Power Supply Pins (VCC/VSS)
When multiple VCC/VSS pins are present, device design considerations for prevention of latch-up and unwanted electromagnetic interference, abnormal strobe signal operation due to ground level rise, and conformity with total output current ratings require that all power supply pins must be externally connected to power supply or ground. Consideration should be given to connecting power supply sources to the V impedance as possible. It is also recommended that a bypass capacitor of approximately 0.1 µF be placed between the V
CC and AVRH) and analog input voltages do not exceed the digital power supply (VCC) .
CC/VSS pins of this device with as low
CC and VSS lines as close to this device as possible.
CC and
4. Crystal Oscillator Circuits
Noise around the X0/X1, or X0A/X1A pins may cause this device to operate abnormally. In the interest of stable operation it is strongly recommended that printed circuit board artwork places ground bypass capacitors as close as possible to the X0/X1, X0A/X1A and crystal oscillator (or ceramic oscillator) and that oscillator lines do not cross the lines of other circuits.
5. Precautions when turning the power supply on
In order to prevent abnormal operation in the chip’s internal step-down circuits, a voltage rise time during power­on of 50 µs (0.2 V to 2.7 V) or greater should be assured.
6. Supply Voltage Stabilization
Even within the operating range of VCC supply voltage, rapid voltage fluctuations may cause abnormal operation. As a standard for power supply voltage stability, it is recommended that the peak-to-peak V commercial supply frequency (50 MHz to 60 MHz) be 10 % or l es s o f V
CC, and that the transient voltage fluctuation
CC ripple voltage at
be no more than 0.1 V/ms or less when the power supply is turned on or off.
7. Proper power-on/off sequence
The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be turned on after the digital power supply (V off before the digital power supply (V when pins used as analog input pins are doubled as input ports, be sure that the input voltage does not exceed AV
CC) is turned on. The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be shut
CC) is shut off. Care should be taken that AVRH does not exceed AVCC. Even
CC.
16
MB90480/485 Series
8. Treatment of power supply pins on models with A/D converters
Even when the A/D converters are not in use, be sure to make the necessary connections AVCC = AVRH = VCC, and AV
9. Notes on Using Power Supply
Only the MB90485 series usually uses a 3 V power supply. By setting VCC3 = 3 V power supply and VCC5 = 5 V power supply, P20 to P27, P30 to P37, P40 to P47 and P70 to P77 can be interfaced as 5 V power supplies separately from the main 3 V power supply. Note that the analog power supplies (such as AV the A/D converter can be used only as 3 V power supplies.
10. Notes on Using External Clock
Even when using an external clock signal, an oscillation stabilization delay is applied after a power-on reset or when recovering from sub-clock or stop mode. When using an external clock, 25 MHz should be the upper frequency limit. The following figure shows a sample use of external clock signals.
SS = VSS.
CC and AVSS) for
X0
OPEN
X1
11. Treatment of NC pins
NC (internally connected) pins should always be left open.
12. Notes on during operation of PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operation if such failure occurs.
13. When the MB90480/485 series microcontroller is used as a single system
When the MB90480/485 series microcontroller is used as a single system, use connections so the X0A = VSS, and X1A = Open.
14. Writing to Flash memory
For writing to Flash memory, always ensure that the operating voltage VCC is between 3.0 V and 3.6 V.
17
MB90480/485 Series
BLOCK DIAGRAM
X0, X1, RST X0A, X1A MD2, MD1, MD0
SIN0 SOT0 SCK0
SIN1, SIN2 SOT1, SOT 2 SCK1, SCK2
AV
CC
AVR H AV
SS
ADTG AN0
to
AN7
PWC0
PWC1
PWC2
Clock control
8
Circuit
RAM
ROM
µDMAC
Communication
prescaler
UART
Extended I/O serial
interface × 2 channels
A/D converter
( 10-bit )
PWC × 3 channels
F2MC16LX series core
2
CPU
Interrupt controller
8/16-bit PPG
8/16-bit
up/down
counter/timer
µPG
MC-16LX Bus
2
F
Chip select
PPG0, PPG1 PPG2, PPG3 PPG4, PPG5
AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1
EXTC MT00 MT01
CS0, CS1, CS2, CS3
Input/output timer
16-bit input capture ×
2 channels
16-bit output compare ×
6 channels
16-bit free-run timer
16-bit reload timer
2
I
C interface
External interrupt
IN0, IN1
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5
TIN0 TOT0
SCL SDA
8
IRQ0
to
IRQ7
18
I/O port
888888888
P00
P10
P20
P30
P40
P50
P60
to to to to to to to to to to to
P07
P17
P27
P37
P47
P57
P67
P70
P77
P80
P87
8
P90
P97
4
PA 0
PA 3
: Only MB90485 series
P00 to P07 (8 pins) : with an input pull-up resistance setting register. P10 to P17 (8 pins) : with an input pull-up resistance setting register. P40 to P47 (8 pins) : with an open drain setting register. P70 to P77 (8 pins) : with an open drain setting register.
MB90485 series only
2
I
C pin P77 and P76 are N-ch open drain pin (without P-ch) . However, MB90V485B uses
the N-ch open drain pin (with P-ch) .
P20 to P27, P30 to P37, P40 to P47 and P70 to P77 are also used as 3 V/5 V I/F pin.
As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/
2
µPG/I
C become CMOS input.
Note : In the above diagram, I/O ports share internal function blocks and pins. However, when a
set of pins is used with an internal module, it cannot also be used as an I/O port.
MEMORY MAP
• MB90F481/F482/487B/488B/483C/F488B/V480/V485B/F489B
Internal ROM
FFFFFF
Address #1
010000
Address #2
Address #3
H
Single chip
ROM area ROM area
H
ROM area
FF bank image
external bus
ROM area
FF bank image
MB90480/485 Series
External ROM
external bus
000100
0000D0
000000
RAM RAM
H
H
H
Register
Peripheral Peripheral Peripheral
RAM
: Internal
Register
: External : Access inhibited
Register
* : In models where address #3 overlaps with address #2, this external area does not exist.
Model Address #1 Address #2 Address #3
MB90F481 FC0000
H *
1
001100
H
MB90F482 FC0000H 001900H MB90487B FD0000H 002900H MB90488B FC0000H 002900H
MB90F488B FC0000H 002900H
004000H or 008000H, selected by the MS bit in the ROMM register
MB90V480 (FC0000H) 004000H
MB90V485B (FC0000H) 004000H
MB90483C FB0000H*
MB90F489B F90000H *
*1 : No memory cells from FC0000
4
2
H to FC7FFFH and FE0000H to FE7FFFH.
0080000H fixed 006100H*
004000H
3
The upper part of the 00 bank is set up to mirror the image of FF bank ROM, to enable efficient use of small model C compilers. Because the lower 16-bit address of the FF bank and the lower 16-bit address of the 00 bank are the same, enabling reference to tables in ROM without using the for specification in the pointer declaration. For example, in accessing address 00C000
H it is actually the contents of ROM at FFC000H that are accessed.
If the MS bit in the ROMM register is set to “0”, the ROM area in the FF bank will exceed 48 Kbytes and it is not possible to reflect the entire area in the image in the 00 bank. Therefore the image from FF4000H to FFFFFFH is reflected in the 00 bank and the area from FF0000
H to FF3FFFH can be seen in the FF bank only.
(Continued)
19
MB90480/485 Series
(Continued)
*2 : In MB90F489B, there is no access to F8 bank and FC bank on the single-chip mode or the internal-ROM
external-bus mode.
*3 : Because installed-RAM area is larger than MB90V485B, MB90F489B should execute emulation in an area
that is larger than 004000
*4 : In MB90483C, there is no access to F8 bank to FA bank and FC bank on the single-chip mode or the internal-
ROM external-bus mode.
H by the emulation memory area setting on the tool side.
20
• MB90F489B
MB90480/485 Series
FFFFFF
FF0000 FEFFFF
FE0000 FDFFFF
FD0000 FCFFFF
FC0000 FBFFFF
FB0000 FAFFFF
FA0000 F9FFFF
F90000 F8FFFF
F80000 F7FFFF
Single chip
H
ROM (FF bank)
H
H
ROM (FE bank)
H
H
ROM (FD bank)
H
H
H
H
ROM (FB bank)
H
H
ROM (FA bank)
H
H
ROM (F9 bank)
H
H
H
H
Internal ROM
external bus
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
External ROM
external bus
010000 00FFFF
008000 007FFF
006100 0060FF
000100 0000FF
0000D0 0000CF
000000
H
H
ROM area
FF bank image
H
H
H
H
H
H
H
H
Peripheral Peripheral Peripheral
H
: Internal : External : Access inhibited
Register
ROM area
FF bank image
RAMRAM
Register
RAM
Register
21
MB90480/485 Series
• MB90483C
FFFFFF
FF0000 FEFFFF
FE0000 FDFFFF
FD0000 FCFFFF
FC0000 FBFFFF
FB0000 FAFFFF
FA0000 F9FFFF
F90000 F8FFFF
F80000 F7FFFF
Single chip
H
ROM (FF bank)
H
H
ROM (FE bank)
H
H
ROM (FD bank)
H
H
H
H
ROM (FB bank)
H
H
H
H
H
H
H
H
Internal ROM
external bus
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FB bank)
External ROM
external bus
010000 00FFFF
004000
or
008000 004000 003FFF
000100 0000FF
0000D0 0000CF
000000
H
H
H
H
H
H
H
H
H
H
H
ROM area
FF bank image
Peripheral
ROM area
FF bank image
RAMRAM
RegisterRegister
Peripheral
RAM
Peripheral
Register
: Internal : External : Access inhibited
22
F2MC-16L CPU PROGRAMMING MODEL
•Dedicated registers
MB90480/485 Series
AH AL
•General purpose registers
32-bit
USP
SSP
PS
PC
16-bit
DPR
PCB
DTB
USB
SSB
ADB
8-bit
Accumulator
User stack pointer
System stack pointer
Processor status
Program counter
Direct page register
Program bank register
Data bank register
User stack bank register
System stack bank register
Additional data bank register
•Processor status
PS RP CCR
000180
H + RP × 10H
15 13
ILM
MSB LSB
12 8 70
16-bit
RW0
RW1
RW2
RW3
R1 R0
R3 R2
R5
R7 R6
R4
RL0
RL1
RW4
RL2
RW5
RW6
RL3
RW7
23
MB90480/485 Series
I/O MAP
Address Register name
00
H Port 0 data register PDR0 R/W Port 0 XXXXXXXXB
Abbreviated
register name
Read/
Write
Resource name Initial value
01H Port 1 data register PDR1 R/W Port 1 XXXXXXXXB 02H Port 2 data register PDR2 R/W Port 2 XXXXXXXXB 03H Port 3 data register PDR3 R/W Port 3 XXXXXXXXB 04H Port 4 data register PDR4 R/W Port 4 XXXXXXXXB 05H Port 5 data register PDR5 R/W Port 5 XXXXXXXXB 06H Port 6 data register PDR6 R/W Port 6 XXXXXXXXB
XXXXXXXX
07H Port 7 data register PDR7 R/W Port 7
(MB90480 series)
11XXXXXX
(MB90485 series)
H Port 8 data register PDR8 R/W Port 8 XXXXXXXXB
08 09H Port 9 data register PDR9 R/W Port 9 XXXXXXXXB 0AH Port A data register PDRA R/W Port A ----XXXXB
0BH Up/down timer input enable register UDRE R/W
0CH Interrupt/DTP enable register ENIR R/W 0DH Interrupt/DTP source register EIRR R/W XXXXXXXXB 0EH Request level setting register 0FH Request level setting register R/W 00000000B
ELVR
R/W 00000000B
Up/down timer
input control
DTP/external interrupts
XX000000B
00000000B
10H Port 0 direction register DDR0 R/W Port 0 00000000B 11H Port 1 direction register DDR1 R/W Port 1 00000000B 12H Port 2 direction register DDR2 R/W Port 2 00000000B 13H Port 3 direction register DDR3 R/W Port 3 00000000B 14H Port 4 direction register DDR4 R/W Port 4 00000000B 15H Port 5 direction register DDR5 R/W Port 5 00000000B 16H Port 6 direction register DDR6 R/W Port 6 00000000B
00000000
17H Port 7 direction register DDR7 R/W Port 7
(MB90480 series)
XX000000
(MB90485 series)
H Port 8 direction register DDR8 R/W Port 8 00000000B
18 19H Port 9 direction register DDR9 R/W Port 9 00000000B 1AH Port A direction register DDRA R/W Port A ----0000B
1BH Port 4 output pin register ODR4 R/W
1CH Port 0 input resistance register RDR0 R/W
1DH Port 1 input resistance register RDR1 R/W
(Open-drain control)
(resistance control)
(resistance control)
Port 4
Port 0
Port 1
00000000B
00000000B
00000000B
00000000
1EH Port 7 output pin register ODR7 R/W
(Open-drain control)
Port 7
(MB90480 series)
XX000000
(MB90485 series)
H Analog input enable register ADER R/W Port 6, A/D 11111111B
1F
B
B
B
B
B
B
24
(Continued)
MB90480/485 Series
Address Register name
20
H Serial mode register SMR R/W
Abbreviated
register name
21H Serial control register SCR W, R/W 00000100B 22H Serial input/output register SIDR/SODR R/W XXXXXXXXB
Read/
Write
Resource name Initial value
00000X00B
UART
23H Serial status register SSR R, R/W 00001000B 24H (Reserved area)
25
26H 27H 00000010B
register
Serial mode control status register 0 SMCS0 R/W
Communication prescaler control
H
CDCR R/W
Communication
prescaler (UART)
SIO1 (ch.0)
00--0000B
----0000
28H Serial data register 0 SDR0 R/W XXXXXXXXB
29H
2AH 2BH 00000010B
Communication prescaler control register 0
Serial mode control status register 1 SMCS1 R/W
SDCR0 R/W
Communication
prescaler
SIO1 (ch.0)
SIO2 (ch.1)
0---0000B
----0000
2CH Serial data register 1 SDR1 R/W XXXXXXXXB
Communication
prescaler
SIO2 (ch.1)
0---0000B
XXXXXXXXB
2DH
Communication prescaler control register 1
SDCR1 R/W
2EH Reload register L (ch.0) PPLL0 R/W 2FH Reload register H (ch.0) PPLH0 R/W XXXXXXXXB 30H Reload register L (ch.1) PPLL1 R/W XXXXXXXXB 31H Reload resister H (ch.1) PPLH1 R/W XXXXXXXXB 32H Reload register L (ch.2) PPLL2 R/W XXXXXXXXB 33H Reload register H (ch.2) PPLH2 R/W XXXXXXXXB 34H Reload register L (ch.3) PPLL3 R/W XXXXXXXXB 35H Reload register H (ch.3) PPLH3 R/W XXXXXXXXB 36H Reload register L (ch.4) PPLL4 R/W XXXXXXXXB 37H Reload register H (ch.4) PPLH4 R/W XXXXXXXXB
8/16-bit PPG
(ch.0 to ch.5)
38H Reload register L (ch.5) PPLL5 R/W XXXXXXXXB 39H Reload register H (ch.5) PPLH5 R/W XXXXXXXXB 3AH PPG0 operating mode control register PPGC0 R/W 0X000XX1B
3BH PPG1 operating mode control register PPGC1 R/W 0X000001B 3CH PPG2 operating mode control register PPGC2 R/W 0X000XX1B 3DH PPG3 operating mode control register PPGC3 R/W 0X000001B
3EH PPG4 operating mode control register PPGC4 R/W 0X000XX1B
3FH PPG5 operating mode control register PPGC5 R/W 0X000001B
40H PPG0, PPG1 output control register PPG01 R/W 8/16-bit PPG 00000000B
41H (Reserved area)
H PPG2, PPG3 output control register PPG23 R/W 8/16-bit PPG 00000000B
42
43H (Reserved area)
B
B
(Continued)
25
MB90480/485 Series
Address Register name
44
H
PPG4, PPG5 output control register PPG45 R/W 8/16-bit PPG 00000000B
Abbre-
viated
register
name
Read/
Write
Resource name Initial value
45H (Reserved area) 46
H
47H ADCS2 W, R/W 00000000B 48H 49H ADCR2 W, R 00000XXXB
Control status register
Data register
4AH Output compare register (ch.0) lower digits 4BH Output compare register (ch.0) upper digits 00000000B 4CH Output compare register (ch.1) lower digits 4DH Output compare register (ch.1) upper digits 00000000B 4EH Output compare register (ch.2) lower digits
4FH Output compare register (ch.2) upper digits 00000000B 50H Output compare register (ch.3) lower digits 51H Output compare register (ch.3) upper digits 00000000B 52H Output compare register (ch.4) lower digits 53H Output compare register (ch.4) upper digits 00000000B 54H Output compare register (ch.5) lower digits 55H Output compare register (ch.5) upper digits 00000000B
ADCS1 R/W
ADCR1 R XXXXXXXX
A/D converter
OCCP0 R/W
OCCP1 R/W
OCCP2 R/W
OCCP3 R/W
16-bit
input/output
OCCP4 R/W
timer output
compare
OCCP5 R/W
(ch.0 to ch.5)
00000000
00000000
00000000B
00000000B
00000000B
00000000B
00000000B
56H Output control register (ch.0) OCS0 R/W 0000--00B 57H Output control register (ch.1) OCS1 R/W ---00000B 58H Output control register (ch.2) OCS2 R/W 0000--00B
59H Output control register (ch.3) OCS3 R/W ---00000B 5AH Output control register (ch.4) OCS4 R/W 0000--00B 5BH Output control register (ch.5) OCS5 R/W ---00000B
5CH
5DH
5EH
5FH
Input capture data register (ch.0) lower digits
Input capture data register (ch.0) upper digits
Input capture data register (ch.1) lower digits
Input capture data register (ch.1) upper digits
IPCP0
IPCP1
R
R XXXXXXXXB
16-bit
XXXXXXXX
input/output
R XXXXXXXX
timer input
capture
(ch.0, ch.1)
R XXXXXXXXB
60H Input capture control status register ICS01 R/W 00000000B
61H (Reserved area)
B
B
B
B
B
26
(Continued)
MB90480/485 Series
Abbreviated
Address Register name
H Timer counter data register lower digits TCDT R/W
62
register
name
Read/
Write
Resource name Initial value
00000000B 63H Timer counter data register upper digits TCDT R/W 00000000B 64H Timer control status register TCCS R/W 00000000B 65H Timer control status register TCCS R/W 0--00000B 66H Compare clear register lower digits 67H Compare clear register upper digits XXXXXXXXB
CPCLR R/W
68H Up/down count register (ch.0) UDCR0 R
16-bit input/output
timer free run timer
XXXXXXXXB
00000000B 69H Up/down count register (ch.1) UDCR1 R 00000000B 6AH Reload/compare register (ch.0) RCR0 W 00000000B 6BH Reload/compare register (ch.1) RCR1 W 00000000B
6CH
6DH
Counter control register (ch.0) lower digits
Counter control register (ch.0) upper digits
CCRL0 W, R/W 0X00X000B
CCRH0 R/W 00000000B
8/16-bit up/down
6EH (Reserved area)
6F
H ROM mirror function select register ROMM R/W
70H
71H
Counter control register (ch.1) lower digits
Counter control register (ch.1) upper digits
CCRL1 W, R/W
CCRH1 R/W -0000000
ROM mirroring
function
8/16-bit up/down
------+1B
0X00X000
72H Counter status register (ch.0) CSR0 R, R/W 00000000B 73H (Reserved area) 74
H Counter status register (ch.1) CSR1 R, R/W 8/16-bit UDC 00000000B
75H (Reserved area)
76
H*
77H* 0000000XB 78H*
79H* 00000000B 7AH* 7BH* 0000000XB 7CH* 7DH* 00000000B 7EH* 7FH* 0000000XB
80H*
81H* 00000000B
PWC control/status register PWCSR0 R, R/W
PWC (ch.0)
PWC data buffer register PWCR0 R/W
PWC control/status register PWCSR1 R, R/W
PWC (ch.1)
PWC data buffer register PWCR1 R/W
PWC control/status register PWCSR2 R, R/W
PWC (ch.2)
PWC data buffer register PWCR2 R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
82H* Dividing ratio control register DIVR0 R/W PWC (ch.0) ------00B
83H (Reserved area)
84H* Dividing ratio control register DIVR1 R/W PWC (ch.1) ------00B
85H (Reserved area)
86
H* Dividing ratio control register DIVR2 R/W PWC (ch.2) ------00B
87H (Reserved area)
B
B
(Continued)
27
MB90480/485 Series
Abbreviated
Address Register name
88
H* Bus status register IBSR R
register
name
Read/
Write
Resource name Initial value
00000000
89H* Bus control register IBCR R/W 00000000B
2
I
8AH* Clock control register ICCR R/W --0XXXXXB
C
8BH* Address register IADR R/W -XXXXXXXB 8CH* Data register IDAR R/W XXXXXXXXB
8DH (Reserved area)
8E
H* µPG control status register PGCSR R/W µPG 00000---B
8FH to 9BH (Disabled)
9C
H µDMAC status register lower digits DSRL R/W µDMAC 00000000B
9DH µDMAC status register upper digits DSRH R/W µDMAC 00000000B
9EH
9FH
A0H
Program address detection control status resister
Delayed interrupt source general/ cancel register
Low-power consumption mode control register
PACSR R/W
DIRR R/W
LPMCR W, R/W
A1H Clock select register CKSCR R, R/W
Address match
detection function
Delayed interrupt
generator module
Low-power
consumption
Low-power
consumption
00000000B
-------0
00011000
11111100B
A2H, A3H (Reserved area)
A4
H µDMAC stop status register DSSR R/W µDMAC 00000000B
A5H Automatic ready function select register ARSR W External pins 0011 - -00B A6H External address output control register HACR W External pins ********B A7H Bus control signal select register EPCR W External pins 1000*10 -B A8H Watchdog timer control register WDTC R, W Watchdog timer XXXXX111B
A9H Timebase timer control register TBTC W, R/W Timebase timer 1XX00100B AAH Watch timer control register WTC R, R/W Watch timer 10001000B ABH (Reserved area) AC
H µDMAC enable register lower digits DERL R/W µDMAC 00000000B
ADH µDMAC enable register upper digits DERH R/W µDMAC 00000000B
AEH Flash memory control status register FMCS W, R/W
Flash memory
interface
000X0000B
AFH (Disabled)
B0
H Interrupt control register 00 ICR00 W, R/W
XXXX0111B B1H Interrupt control register 01 ICR01 W, R/W XXXX0111B B2H Interrupt control register 02 ICR02 W, R/W XXXX0111B B3H Interrupt control register 03 ICR03 W, R/W XXXX0111B B4H Interrupt control register 04 ICR04 W, R/W XXXX0111B
Interrupt controller B5H Interrupt control register 05 ICR05 W, R/W XXXX0111B B6H Interrupt control register 06 ICR06 W, R/W XXXX0111B B7H Interrupt control register 07 ICR07 W, R/W XXXX0111B B8H Interrupt control register 08 ICR08 W, R/W XXXX0111B
B
B
B
28
(Continued)
MB90480/485 Series
(Continued)
Abbreviated
Address Register name
B9
H Interrupt control register 09 ICR09 W, R/W
register
name
BAH Interrupt control register 10 ICR10 W, R/W XXXX0111B BBH Interrupt control register 11 ICR11 W, R/W XXXX0111B BCH Interrupt control register 12 ICR12 W, R/W XXXX0111B BDH Interrupt control register 13 ICR13 W, R/W XXXX0111B BEH Interrupt control register 14 ICR14 W, R/W XXXX0111B
BFH Interrupt control register 15 ICR15 W, R/W XXXX0111B C0H Chip select area mask register 0 CMR0 R/W C1H Chip select area register 0 CAR0 R/W 11111111B C2H Chip select area mask register 1 CMR1 R/W 00001111B C3H Chip select area register 1 CAR1 R/W 11111111B C4H Chip select area mask register 2 CMR2 R/W 00001111B C5H Chip select area register 2 CAR2 R/W 11111111B C6H Chip select area mask register 3 CMR3 R/W 00001111B C7H Chip select area register 3 CAR3 R/W 11111111B C8H Chip select control register CSCR R/W ----000*B
C9H Chip select active level register CALR R/W ----0000B CAH CBH ----0000B CCH CDH
Timer control status register TMCSR R/W
16-bit timer register/ 16-bit reload register
TMR/TMRLR
CEH (Reserved area)
CF
H PLL output control register PLLOS W
D0H to FFH (External area)
100
H to #H (RAM area)
1FF0
1FF2
1FF3
1FF5
Program address detection register 0
H
(Low order address) Program address detection register 0
(Middle order address) Program address detection register 0
H
(High order address) Program address detection register 1
H
(Low order address) Program address detection register 1
(Middle order address) Program address detection register 1
H
(High order address)
PADR0 R/W
PADR1 R/W
Read/
Write
Resource name Initial value
XXXX0111B
Interrupt controller
00001111B
Chip select
function
00000000
16-bit reload timer
R/W XXXXXXXXB
Low-power
consumption
Address match
detection function
Address match
detection function
------X0B
XXXXXXXX
XXXXXXXX
B
B1FF1H
B1FF4H
* : These registers are only for MB90485 series.
They are used as the reserved area on MB90480 series.
(Continued)
29
MB90480/485 Series
(Continued)
Descriptions for read/write
R/W : Readable and writable R : Read only W : Write only
Descriptions for initial value
0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined.
- : This bit is not used. * : The initial value of this bit is “1” or “0”.
The value depends on the mode pin (MD2, MD1 and MD0) .
+ : The initial value of this bit is “1” or “0”.
The value depends on the RAM area of device.
30
MB90480/485 Series
INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
Interrupt source
Clear of
2
EI
OS
µDMAC
channel number
Interrupt vector Interrupt control register
Number Address Number Address
Reset × #08 FFFFDC INT9 instruction × #09 FFFFD8 Exception × #10 FFFFD4
INT0 (IRQ0) 0 #11 FFFFD0 INT1 (IRQ1) × #12 FFFFCCH INT2 (IRQ2) × #13 FFFFC8H INT3 (IRQ3) × #14 FFFFC4H INT4 (IRQ4) × #15 FFFFC0H INT5 (IRQ5) × #16 FFFFBCH INT6 (IRQ6) × #17 FFFFB8H INT7 (IRQ7) × #18 FFFFB4H PWC1 (MB90485 series only) × #19 FFFFB0H PWC2 (MB90485 series only) × #20 FFFFACH
PWC0 (MB90485 series only) 1 #21 FFFFA8H PPG0/PPG1 counter borrow × × #22 FFFFA4H PPG2/PPG3 counter borrow × × #23 FFFFA0H PPG4/PPG5 counter borrow × × #24 FFFF9CH
8/16-bit up/down counter/ timer (ch.0, ch.1) compare/ underflow/overflow/up/down
× #25 FFFF98
inversion
Input capture (ch.0) load 5 #26 FFFF94H
Input capture (ch.1) load 6 #27 FFFF90H
Output compare (ch.0) match 8 #28 FFFF8CH
Output compare (ch.1) match 9 #29 FFFF88H
Output compare (ch.2) match 10 #30 FFFF84H Output compare (ch.3) match × #31 FFFF80H Output compare (ch.4) match × #32 FFFF7CH Output compare (ch.5) match × #33 FFFF78H
UART sending completed 11 #34 FFFF74H
16-bit free run timer overflow, 16-bit reload timer underflow*
2
12 #35 FFFF70H
UART receiving completed 7 #36 FFFF6CH
SIO1 (ch.0) 13 #37 FFFF68H
SIO2 (ch.1) 14 #38 FFFF64H
H ⎯⎯ H ⎯⎯ H ⎯⎯
H
ICR00 0000B0H
ICR01 0000B1H
ICR02 0000B2H
ICR03 0000B3H
ICR04 0000B4H
ICR05 0000B5H
ICR06 0000B6H
H
ICR07 0000B7H
ICR08 0000B8H
ICR09 0000B9H
ICR10 0000BAH
ICR11 0000BBH
ICR12 0000BCH
ICR13 0000BDH
(Continued)
31
MB90480/485 Series
(Continued)
µDMAC
channel number
Interrupt source
2
I
C interface
(MB90485 series only)
Clear of
2
EI
OS
× × #39 FFFF60H
A/D conversion 15 #40 FFFF5CH
Flash write/erase, timebase timer, watch timer *
Delay interrupt generator module
1
× × #41 FFFF58H
× × #42 FFFF54H
× : Interrupt request flag is not cleared by the interrupt clear signal.
: Interrupt request flag is cleared by the interrupt clear signal. : Interrupt request flag is cleared by the interrupt clear signal (stop request present) .
*1 : The Flash write/erase, timebase timer, and watch timer cannot be used at the same time. *2 : When the 16-bit reload timer underflow interrupt is changed from enable (TMCSR : INTE = 1) to disable
(TMCSR : INTE = 0) , disable the interrupt in the interrupt control register (ICR12 : IL2 to 0 : 111 the INTE bit to 0.
Interrupt vector Interrupt control register
Number Address Number Address
ICR14 0000BEH
ICR15 0000BFH
B) , then set
Note : If there are two interrupt sources for the same interrupt number, the resource will clear both interrupt request
flags at the EI
2
OS/µDMAC interrupt clear signal. Therefore if either of the two sources uses the EI2OS/
µDMAC function, the other interrupt function cannot be used. The interrupt request enable bit for the corre­sponding resource should be set to “0” and interrupt requests from that resource should be handled by software polling.
32
MB90480/485 Series
PERIPHERAL RESOURCES
1. I/O Ports
The I/O ports perform the functions of either sending data from the CPU to the I/O pins, or loading information from the I/O into the CPU, according to the setting of the corresponding port data register (PDR) . The input/ output direction of each I/O pin can be set in individual bit units by the port direction register (DDR) for each I/ O port. The MB90480/485 series has 84 input/output pins. The I/O ports are port 0 through port A.
(1) Port Data Registers
PDR0 Initial value Access
Address : 000000
H Undefined R/W*
7654 321 0
P06P07 P05 P04 P03 P02 P01 P00
1
PDR1
Address : 000001
PDR2
Address : 000002
PDR3
Address : 000003
PDR4
Address : 000004
PDR5
Address : 000005
PDR6
Address : 000006
PDR7
Address : 000007
PDR8
Address : 000008
7654 321 0
H Undefined R/W*
H Undefined R/W*
H Undefined R/W*
H Undefined R/W*
H Undefined R/W*
H Undefined R/W*
H Undefined*
H Undefined R/W*
P16P17 P15 P14 P13 P12 P11 P10
7654 321 0
P26P27 P25 P24 P23 P22 P21 P20
7654 321 0
P36P37 P35 P34 P33 P32 P31 P30
7654 321 0
P46P47 P45 P44 P43 P42 P41 P40
7654 321 0
P56P57 P55 P54 P53 P52 P51 P50
7654 321 0
P66P67 P65 P64 P63 P62 P61 P60
7654 321 0
P76P77 P75 P74 P73 P72 P71 P70
7654 321 0
P86P87 P85 P84 P83 P82 P81 P80
2
R/W*
1
1
1
1
1
1
1
1
PDR9
Address : 000009
PDRA
Address : 00000A
H Undefined R/W*
H Undefined R/W*
7654 321 0
P96P97 P95 P94 P93 P92 P91 P90
7654 321 0
⎯⎯PA3 PA2 PA1 PA0
1
1
*1 : The R/W indication for I/O ports is somewhat different than R/W access to memory, and involves the following
operations.
Input mode
Read : Reads the corresponding signal pin level. Write : Writes to the output latch.
Output mode
Read : Reads the value from the data register latch. Write : Outputs the value to the corresponding signal pin.
*2 : The initial value of this bit is “11XXXXXX
B” on MB90485 series.
33
MB90480/485 Series
(2) Port Direction Registers
DDR0 Initial value Access
Address : 000010
76543 21 0
H 00000000B R/W
D06D07 D05 D04 D03 D02 D01 D00
DDR1
Address : 000011
DDR2
Address : 000012
DDR3
Address : 000013
DDR4
Address : 000014
DDR5
Address : 000015
DDR6
Address : 000016
DDR7
Address : 000017
DDR8
Address : 000018
76543210
H 00000000B R/W
H 00000000B R/W
H 00000000B R/W
H 00000000B R/W
H 00000000B R/W
H 00000000B R/W
H 00000000B*
D77*
H 00000000B R/W
D16D17 D15 D14 D13 D12 D11 D10
76543210
D26D27 D25 D24 D23 D22 D21 D20
76543210
D36D37 D35 D34 D33 D32 D31 D30
76543210
D46D47 D45 D44 D43 D42 D41 D40
76543210
D56D57 D55 D54 D53 D52 D51 D50
76543210
D66D67 D65 D64 D63 D62 D61 D60
76543210
1
76543210
1
D76*
D86D87 D85 D84 D83 D82 D81 D80
D75 D74 D73 D72 D71 D70
2
R/W
DDR9
Address : 000019
DDRA
Address : 00001A
76543210
H 00000000B R/W
H ----0000B R/W
D96D97 D95 D94 D93 D92 D91 D90
76543210
⎯⎯DA3 DA2 DA1 DA0
*1 : The value is set to “” on MB90485 series only. *2 : The initial value of this bit is “XX000000
B” on MB90485 series only.
When a set of pins is functioning as a port, the corresponding signal pins are controlled as follows.
0 : Input mode. 1 : Output mode. Reset to “0”.
Notes : When any of these registers are accessed using a read-modify-write type instruction (such as a bit set
instruction) , the bit specified in the instruction will be set to the indicated value. However, the contents of output registers corresponding to any other bits having input settings will be rewritten to the input values of those pins at that time. For this reason, when changing any pin that has been used for input to output, first write the desired value to the PDR register before setting the DDR register for output.
P76, P77 (MB90485 series only)
This port has no DDR. To use P77 and P76 as I enabled (to use P77 and P76 for general purposes, disable I
2
C pins, set the PDR value to “1” so that port data remains
2
C) . The port is an open drain output (with no P-ch) . To use it as an input port, therefore, set the PDR to “1” to turn off the output transistor and add a pull-up resistor to the external output.
34
MB90480/485 Series
(3) Port Input Resistance Registers
RDR0 Initial value Access
Address : 00001C
76543210
H 00000000B R/W
RD06RD07 RD05 RD04 RD03 RD02 RD01 RD00
RDR1
Address : 00001D
76543210
H 00000000B R/W
RD16RD17 RD15 RD14 RD13 RD12 RD11 RD10
These registers control the use of pull-up resistance in input mode.
0 : No pull-up resistance in input mode. 1 : With pull-up resistance in input mode.
In output mode, these registers have no function (no pull-up resistance) . Input/output mode settings are controlled by the setting of port direction (DDR) registers. In case of a stop (SPL = 1) , no pull-up resistance is applied (high impedance) . Using of this function is prohibited when an external bus is used. Do not write to these registers.
(4) Port Output Pin Registers
ODR7 Initial value Access
Address : 00001E
ODR4
Address : 00001B
76543210
H 00000000B*
H 00000000B R/W
1
OD77*
76543210
1
OD76*
OD46OD47 OD45 OD44 OD43 OD42 OD41 OD40
OD75 OD74 OD73 OD72 OD71 OD70
2
R/W
*1 : The value is set to “” on MB90485 series only.
*2 : The initial value of this bit is “XX000000
B” on MB90485 series only.
These registers control open drain settings in output mode.
0 : Standard output port functions in output mode. 1 : Open drain output port in output mode.
In input mode, these registers have no function (Hi-Z output) . Input/output mode settings are controlled by the setting of port direction (DDR) registers. Using of this function is prohibited when an external bus is used. Do not write to these registers.
(5) Analog Input Enable Register
ADER Initial value Access
Address : 00001F
76543210
H 11111111B R/W
ADE6ADE7 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
This register controls the port 6 pins as follows.
0 : Port input/output mode. 1 : Analog input mode. The default value at reset is all “1”.
(6) Up/down Timer Input Enable Register
UDER Initial value Access
Address : 00000B
76543210
H XX000000B R/W
UDE5 UDE4 UDE3 UDE2 UDE1 UDE0
This register controls the port 3 pins as follows.
0 : Port input mode. 1 : Up/down timer input mode.The default value at reset is “0”.
35
MB90480/485 Series
2. UART
The UART is a serial I/O port for asynchronous (start-stop synchronized) communication as well as CLK synchronized communication.
• Full duplex double buffer
• Transfer modes : asynchronous (start-stop synchronized) , or CLK synchronized (no start bit or stop bit) .
• Multi-processor mode supported.
• Embedded proprietary baud rate generator Asynchronous : 76923/38461/19230/9615/500 k/250 kbps CLK synchronized : 16 M/8 M/4 M/2 M/1 M/500 kbps
• External clock setting available, allows use of any desired baud rate.
• Can use internal clock feed from PPG1.
• Data length : 7-bit (asynchronous normal mode only) or 8-bit.
• Master/slave type communication functions (in multi-processor mode) .
• Error detection functions (parity, framing, overrun)
• Transfer signals are NRZ encoded.
µDMAC supported (for receiving/sending)
36
(1) Register List
MB90480/485 Series
15 0
SCR
8 bits 8 bits
Serial mode register (SMR)
76543210
000020
H
MD1 CS2 CS1 CS0 SCKE SOE
R/W
MD0
R/W0R/W0R/W0R/W0R/WXR/W0R/W
0
Serial control register (SCR)
15 14 13 12 11 10 9 8
000021
H
PEN SBL CL A/D REC RXE TXE
R/W
0
P
R/W0R/W0R/W0R/W
Serial I/O register (SIDR/SODR)
76543210
000022
H
D7 D5 D4 D3 D2 D1 D0
R/W
X
D6
R/WXR/WXR/WXR/WXR/WXR/WXR/W
Serial status register (SSR)
15 14 13 12 11 10 9 8
000023
H
PE FRE RDRF TDRE BDS RIE TIE
ORE
R 0
R 0
R 0
Communication prescaler control register (CDCR)
15 14 13 12 11 10 9 8
000025
H
R/W
SRST
MD ⎯⎯DIV3 DIV2 DIV1 DIV0
R/W
0
0
⎯ ⎯
87
⎯ ⎯
CDCR
SMR
SIDR (R)/SODR (W)SSR
Reserved
0
R 0
R 1
R/W0R/W0R/W0R/W
W
1
R/W0R/W0R/W
0
R/W0R/W
0
X
0
0
Initial value
Initial value
Initial value
Initial value
Initial value
37
MB90480/485 Series
(2) Block Diagram
Control
signal
Proprietary baud rate generator
PPG1 (internal connection)
External clock
SIN0
Clock select
circuit
Receiving clock
Receiving control
circuit
Start bit detect
circuit
Sending clock
Receiving interrupt
(to CPU)
SCK0
Sending interrupt
(to CPU)
Sending control
circuit
Send start
circuit
Receiving status
decision circuit
µDMAC receiving error generation circuit (to CPU)
MD1 MD0 CS2
SMR
CS1 CS0
SCKE SOE
Receive bit
counter
Receiving parity
counter
Receiving shifter
Receiving
control
circuit
SIDR SODR
F2MC-16LX BUS
PEN P SBL
SCR SSR
CL A/D REC RXE TXE
Send bit
counter
Send parity
counter
SOT0
Sending shifter
Sending
start
PE ORE FRE RDRF TDRE BDS RIE TIE
38
Control signal
MB90480/485 Series
3. Expanded I/O Serial Interface
The expanded I/O serial interface is an 8-bit × 1-channel serial I/O interface for clock synchronized data transfer. A selection of LSB-first or MSB-first data transfer is provided.
There are two serial I/O operation modes.
• Internal shift clock mode : Data transfer is synchronized with the internal clock signal.
• External shift clock mode : Data transfer is synchronized with a clock signal input from the external clock signal pin (SCK) . In this mode the general-purpose port that shares the external clock signal pin (SCK) can be used for transfer according to CPU instructions.
(1) Register List
Serial mode control status register 0/1 (SMCS0, SMCS1)
Initial value
00000010B
Address : 000027
00002BH
H
15 14 13 12 11 10 9 8
SMD1SMD2 SMD0 SIE SIR BUSY STOP STRT
R/WR/W R/W R/W R/W R R/W R/W
Address : 000026H
00002AH
7654
⎯⎯MODE BDSSOE SCOE
⎯⎯
3 21 0
R/W R/W R/W R/W
Serial data register 0/1 (SDR0, SDR1)
Address : 000028H
00002CH
76543210
D6D7 D5 D4 D3 D2 D1 D0
R/WR/W R/W R/W R/W R/W R/W R/W
Communication prescaler control register 0/1 (SDCR0, SDCR1)
Address : 000029H
00002DH
15 14 13 12 11 10 9 8
MD ⎯⎯DIV3 DIV2 DIV1 DIV0
R/W
⎯⎯⎯R/W R/W R/W R/W
----0000B
XXXXXXXXB
0---0000B
39
MB90480/485 Series
(2) Block Diagram
Internal data bus
(MSB first) D0 to D7 D7 to D0 (LSB first)
Transfer direction selection
SIN1, SIN2
SDR (Serial Data Register)
SOT1, SOT2
SCK1, SCK2
Control circuit
Internal clock
21 0
SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT MODE BDS
Interrupt request
Internal data bus
Initial value
Read
Write
Shift clock
counter
SOE SCOE
40
MB90480/485 Series
4. 8/10-bit A/D Converter
The A/D converter converts analog input voltage to digital values, and provides the following features.
• Conversion time : minimum 3.68 µs per channel
(92 machine cycles at 25 MHz machine clock, including sampling time)
• Sampling time : minimum 1.92 µs per channel
(48 machine cycles at 25 MHz machine clock)
• RC sequential comparison conversion method, with sample & hold circuit.
• 8-bit or 10-bit resolution
• Analog input selection of 8 channels Single conversion mode : Conversion from one selected channel. Scan conversion mode : Conversion from multiple consecutive channels, programmable selection of up to 8 channels. Continuous conversion mode : Repeated conversion of specified channels. Stop conversion mode : Conversion from one channel followed by a pause until the next activation allows to synchronize with conversion start.
• At the end of A/D conversion, an A/D conversion completed interrupt request can be generated to the CPU. The interrupt can be used activate the µDMAC in order to transfer the results of A/D conversion to memory for efficient continuous processing.
• The starting factor conversion may be selected from software, external trigger (falling edge) , or timer (rising edge) .
(1) Register List
ADCS2, ADCS1 (Control status register)
ADCS1
Address : 000046
ADCS2
Address : 000047
76543210
H
MD1 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
0
R/W
15 14 13 12 11 10 9 8
H
BUSY INTE PAUS STS1 STS0 STRT
0
R/W
ADCR2, ADCR1 (Data register)
ADCR1
Address : 000048
ADCR2
Address : 000049
76543210
H
D7 D5 D4 D3 D2 D1 D0
X
R
15 14 13 12 11 10 9 8
H
S10 ST0 CT1 CT0 D9 D8
0
W
MD0
0
R/W0R/W0R/W0R/W0R/W0R/W0R/W
W
0
X R
X
R
Reserved
0
R/W
X R
X R
INT
0
R/W0R/W0R/W0R/W0R/W
D6
X
R
ST1
0
W
X
R
0
W
X R
0
W
X R
0
W
X R
X R
Initial value Bit attributes
Initial value Bit attributes
Initial value Bit attributes
Initial value Bit attributes
41
MB90480/485 Series
(2) Block Diagram
MP
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Input
circuit
Sample & hold
circuit
Comparator
AV
CC
AVRH
AVSS
D/A converter
Sequential
comparison register
Data bus
ADTG
Trigger activation
Timer
(PPG1 output)
Timer activation
φ
Data registers
ADCR1, ADCR2
Decoder
A/D control register 1
A/D control register 2
ADCS1, ADCS2
Operation clock
Prescaler
42
MB90480/485 Series
5. 8/16-bit PPG
The 8/16-bit PPG is an 8-bit reload timer module that produces a PPG output using a pulse from the timer operation. Hardware resources include 6 × 8-bit down counters, 12 × 8-bit reload timers, 3 × 16-bit control registers, 6 × external pulse output pins, and 6 × interrupt outputs. Note that MB90480/485 series has six channels for 8-bit PPG use, which can also be combined as PPG0 + PPG1, PPG2 + PPG3, and PPG4 + PPG5 to operate as a three-channel 16-bit PPG. The following is a summary of functions.
• 8-bit PPG output 6-channel independent mode : Provides PPG output operation on six independent channels.
• 16-bit PPG output operation mode : Provides 16-bit PPG output on three channels. The six original channels are used in combination as PPG0 + PPG1, PPG2 + PPG3, and PPG4 + PPG5.
•8 + 8-bit PPG output operation mode : Output from PPG0 (PPG2/PPG4) is used as clock input to PPG1 (PPG3/ PPG5) to provide to 8-bit PPG output at any desired period length.
• PPG output operation : Produces pulse waves at any desired period and duty ratio. The PPG module can also be used with external circuits as a D/A converter.
(1) Register List
PPGC0/PPGC2/PPGC4 (PPG0/PPG2/PPG4 operation mode control register)
00003A 00003CH 00003EH
H
76543210
X
Reserved
1
PEN0 PE00 PIE0 PUF0 ⎯⎯
R/W
0
⎯ ⎯
R/W0R/W0R/W
X
0
X
Read/write Initial value
PPGC1/PPGC3/PPGC5 (PPG1/PPG3/PPG5 operation mode control register)
00003B 00003DH 00003FH
H
15 14 13 12 11 10 9 8
PEN1 PE10 PIE1 PUF1 MD1 MD0
R/W
0
⎯ ⎯
R/W0R/W0R/W0R/W0R/W
X
0
Reserved
1
PPG01/PPG23/PPG45 (PPG0 to PPG5 output control register)
000040 000042H 000044H
H
76543210
PCS2 PCS0 PCM2 PCM1 PCM0
R/W
PCS1
R/W0R/W0R/W0R/W0R/W0R/W0R/W
0
ReservedReserved
0
PPLL0 to PPLL5 (Reload register L)
00002E 000030H 000032H 000034H 000036H
H
76543210
D07 D05 D04 D03 D02 D01 D00
R/W
D06
R/WXR/WXR/WXR/WXR/WXR/WXR/W
X
X
000038H
PPLH0 to PPLH5 (Reload register H)
00002F 000031H 000033H 000035H 000037H
H
15 14 13 12 11 10 9 8
D15 D13 D12 D11 D10 D09 D08
R/W
D14
R/WXR/WXR/WXR/WXR/WXR/WXR/W
X
X
000039H
Read/write Initial value
Read/write Initial value
Read/write Initial value
Read/write Initial value
43
MB90480/485 Series
(2) Block Diagram
• 8-bit PPG ch.0/2/4 block Diagram
Count clock select
Timebase counter output main clock × 512
“L”/“H” select
Peripheral clock × 16 Peripheral clock × 8 Peripheral clock × 4 Peripheral clock × 2 Peripheral clock
PCNT
(down counter)
“L”/“H” selector
PRLBHPRLL
PPG0/2/4
output enable
PPG0/2/4
output latch
PPGC0 (operation mode control)
PEN0
PUF0
PPG0/2/4
A/D converter
S
Q
R
PIE0
IRQ
ch.1/3/5 borrow
44
PRLL
“L” data bus
“H” data bus
• 8-bit PPG ch.1/3/5 Block Diagram
MB90480/485 Series
Count clock select
Timebase counter output main clock × 512
“L”/“H” select
Peripheral clock × 16 Peripheral clock × 8 Peripheral clock × 4 Peripheral clock × 2 Peripheral clock
PCNT
(down counter)
“L”/“H” selector
PPG1/3/5 output
UART0
S R
PPG1/3/5
Q
PIE1
IRQ
enable
PPG1/3/5
output latch
PEN1
PUF1
PRLBHPRLL
PPGC1 (operation mode control)
PRLL
“L” data bus
“H” data bus
45
MB90480/485 Series
6. 8/16-bit up/down Counter/Timer
8/16-bit up/down counter/timer consists of up/down counter/timer circuits including six event input pins, two 8-bit up/down counters, two 8-bit reload/compare registers, as well as the related control circuits.
(1) Principal Functions
• 8-bit count register enables counting in the range 0 to 256. (In 16-bit × 1 mode, counting is enabled in the range 0 to 65535)
• Count clock selection provides four count modes.
Count modes Timer mode
Up/down count mode Phase differential down count mode ( × 2) Phase differential down count mode ( × 8)
• In timer mode, there is a choice of two internal count clock signals.
Count clock 125 ns (8 MHz : × 2) (at 16 MHz operation) 0.5 µs (2 MHz : × 8)
• In up/down count mode, there is a choice of trigger edge detection for the input signal from external pins.
Edge detection Falling edge detection
Rising edge detection
Both rising/falling edge detection
Edge detection disabled
• In phase differential count mode, to handle encoder counting for motors, the encoder A-phase, B-phase, and Z-phase are each input, enabling easy and highly accurate counting of angle of rotation, speed of rotation, etc.
• The ZIN pin provides a selection of two functions.
ZIN pin Counter clear function
Gate functions
• A compare function and reload function are provided, each for use separately or in combination. Both functions can be activated together for up/down counting in any desired bandwidth.
Compare/reload function Compare function (output interrupt at compare events)
Compare function (output interrupt and clear counter at compare events)
Reload function (output interrupt and reload at underflow events)
Compare/reload function (output interrupt and clear counter at compare events, output interrupt
and reload at underflow events)
Compare/reload disabled
• Individual control over interrupts at compare, reload (underflow) and overflow events.
• Count direction flag enables identification of the last previous count direction.
• Interrupt generated when count direction changes.
46
(2) Register List
MB90480/485 Series
15 0
RCR1
Reserved area
CCRH0
Reserved area
CCRH1
8-bit
87
UDCR0UDCR1
RCR0
CSR0
CCRL0
CSR1
CCRL1
8-bit
CCRH0 (Counter Control Register High ch.0)
15 14 13 12 11 10 9 8
Address : 00006D
H 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
CDCFM16E CFIE CLKS CMS1 CMS0 CES1 CES0
CCRH1 (Counter Control Register High ch.1)
15 14 13 12 11 10 9 8
Address : 000071H -0000000B
CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
R/W R/W R/W R/W R/W R/W R/W
CCRL0/1 (Counter Control Register Low ch.0/ch.1)
Address Address
: 00006CH : 000070H
76543210
CTUTUDMS UCRE RLDE UDCC CGSC CGE1 CGE0
R/W W R/W R/W W R/W R/W R/W
CSR0/1 (Counter Status Register ch.0/ch.1)
Address Address
: 000072H : 000074H
76543210
CITECSTR UDIE CMPF OVFF UDFF UDF1 UDF0
R/W R/W R/W R/W R/W R/W R R
UDCR0/1 (Up Down Count Register ch.0/ch.1)
15 14 13 12 11 10 9 8
Address : 000069
H 00000000B
D16D17 D15 D14 D13 D12 D11 D10
RRRRRRRR
Initial value
Initial value
Initial value 0X00X000
Initial value
00000000
Initial value
B
B
76543210
Address : 000068
H 00000000B
D06D07 D05 D04 D03 D02 D01 D00
RRRRRRRR
RCR0/1 (Reload/Compare Register ch.0/ch.1)
15 14 13 12 11 10 9 8
Address : 00006BH 00000000B
WWWWWWWW
Address : 00006AH 00000000B
WWWWWWWW
D16D17 D15 D14 D13 D12 D11 D10
76543210
D06D07 D05 D04 D03 D02 D01 D00
Initial value
Initial value
Initial value
47
MB90480/485 Series
(3) Block Diagram
CGE1 CGE0 CGSC
Data bus
8-bit
RCR0 (Reload/ compare register 0)
ZIN0
AIN0
BIN0
Edge/level detection
UDCC
CES1CES0
CMS1CMS0
UDMS
Up/down
count
clock selection
Prescaler
CLKS
CTUT
UCRE
Reload control
RLDE
Counter clear
8-bit
UDCR0 (Up/down count register 0)
Count clock
UDF1 UDF0 CDCF CFIE
Interrupt
CSTR
output
UDFF OVFF
CITE UDIE
Carry
CMPF
48
MB90480/485 Series
7. DTP/External Interrupt
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16LX CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the requests to the F
(1) Detailed Register Descriptions
Interrupt/DTP Enable Register (ENIR : Enable Interrupt Request Register)
ENIR Initial value
Address : 00000C
Interrupt/DTP Source Register (EIRR : External Interrupt Request Register)
EIRR Initial value
Address : 00000D
Interrupt Level Setting Register (ELVR : External Level Register)
Address : 00000E
2
MC-16LX CPU to activate the extended intelligent µDMAC or interrupt processing.
76543210
H 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
15 14 13 12 11 10 9 8
H XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
H 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
EN6EN7 EN5 EN4 EN3 EN2 EN1 EN0
ER6ER7 ER5 ER4 ER3 ER2 ER1 ER0
76543210
LA3LB3 LB2 LA2 LB1 LA1 LB0 LA0
Initial value
Address : 00000F
(2) Block Diagram
F2MC-16 bus
15 14 13 12 11 10 9 8
H 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
4
4
4
8
Interrupt/DTP enable register
Gate
Interrupt/DTP source register
Interrupt level setting register
LA7LB7 LB6 LA6 LB5 LA5 LB4 LA4
Source F/F
Edge detection
circuit
4
Initial value
Request input
49
MB90480/485 Series
8. 16-bit Input/Output Timer
The 16-bit input/output timer module is composed of one 16-bit free run timer, six output compare and two input capture modules. These functions can be used to output six independent waveforms based on the 16-bit free run timer, enabling input pulse width measurement and external clock frequency measurement.
• Register List
• 16-bit free run timer
15 0
000066/67H
CPCLR
Compare-clear register
000062/63H
000064/65H
• 16-bit output compare
00004A, 4C, 4E, 50, 52, 54H
00004B, 4D, 4F, 51, 53, 55H
000056, 58, 5AH 000057, 59, 5BH
• 16-bit input capture
00005C, 5EH
00005D, 5FH
000060H
TCDT
TCCS
15 0
OCCP0 to OCCP5
OCS0/2/4OCS1/3/5
15 0
IPCP0, IPCP1
ICS01
Timer counter data register
Control status register
Output compare register
Output compare control registers
Input capture data register
Input capture control status register
50
•Block Diagram
MB90480/485 Series
Control logic
16-bit free run timer
Output compare 0
Output
Bus
compare 1
Output compare 2
Output compare 3
Output compare 4
Output compare 5
Interrupt
16-bit timer
Compare register 0
Compare register 1
Compare register 2
Compare register 3
Compare register 4
Compare register 5
Clear
To
each
block
TQ
TQ
TQ
TQ
TQ
TQ
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
Input capture 0
Input capture 1
Capture data register 0
Capture data register 1
Edge
selection
Edge
selection
IN0
IN1
51
MB90480/485 Series
(1) 16-bit Free Run Timer
The 16-bit free run timer is composed of a 16-bit up-down counter and control status register. The counter value of this timer is used as the base timer for the input capture and output compare.
• The counter operation provides a choice of eight clock types.
• A counter overflow interrupt can be produced.
• A mode setting is available to initialize the counter value whenever the output compare value matches the value in the compare clear register.
• Register List
Compare clear register (CPCLR)
Initial value
000067
15 14 13 12 11 10 9 8
H XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
CL14CL15 CL13 CL12 CL11 CL10 CL09 CL08
76543210
000066H XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
CL06CL07 CL05 CL04 CL03 CL02 CL01 CL00
Timer counter data register (TCDT)
15 14 13 12 11 10 9 8
000063H 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
000062
H 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
T14T15 T13 T12 T11 T10 T09 T08
76543210
Timer control status register (TCCS)
15 14 13 12 11 10 9 8
000065
000064
H 0--00000B
R/W R/W R/W R/W R/W R/W R/W R/W
76543210
H 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
Initial value
Initial value
T06T07 T05 T04 T03 T02 T01 T00
Initial value
ECKE MSI2 MSI1 MSI0 ICLR ICRE
Initial value
IVFEIVF STOP MODE SCLR CLK2 CLK1 CLK0
52
•Block Diagram
MB90480/485 Series
Bus
Interrupt request
IVF IVFE STOP MODE SCLR CLK1 CLK0
CLK2
16-bit free run timer
Count value output T15 to T00
16-bit compare clear register
Compare circuit
MSI2 to MSI0
ICLR
ICRE
φ
Prescaler
Clock
Interrupt request
A/D activation
53
MB90480/485 Series
(2) Output Compare
The output compare module is composed of a 16-bit compare register, compare output pin unit, and control register. When the value in the compare register in this module matches the 16-bit free run timer, the pin output levels can be inverted and an interrupt generated.
• There are six compare registers in all, each operating independently. A setting is available to allow two compare registers to be used to control output.
• Interrupts can be set in terms of compare match events.
• Register List
Output compare registers (OCCP0 to OCCP5)
Initial value
00000000B
00004B 00004DH 00004FH 000051H 000053H 000055H
15 14 13 12 11 10 9 8
H
R/W R/W R/W R/W R/W R/W R/W R/W
C14C15 C13 C12 C11 C10 C09 C08
7654321
00004A 00004CH 00004EH
H
R/W R/W R/W R/W R/W R/W R/W R/W
C06C07 C05 C04 C03 C02 C01 C00
000050H 000052H 000054H
Output control registers (OCS1/OCS3/OCS5)
15 14 13 12 11 10 9 8
000057H 000059H 00005BH
⎯⎯⎯R/W R/W R/W R/W R/W
⎯⎯CMOD OTE1 OTE0 OTD1 OTD0
Output control registers (OCS0/OCS2/OCS4)
76543210
000056 000058H 00005AH
H
R/W R/W R/W R/W ⎯⎯R/W R/W
ICP0ICPIC ICE1 ICE0 ⎯⎯CST1 CST0
0
Initial value
00000000B
Initial value
---00000B
Initial values
0000--00B
54
•Block Diagram
16-bit timer counter value (T15 to T00)
MB90480/485 Series
Compare control
Compare register 0 (2, 4)
16-bit timer counter value (T15 to T00)
Bus
Compare control
Compare register 1 (3, 5)
ICP1 ICP0 ICE0 ICE0
Control unit
Individual
control blocks
TQ
CMOD
TQ
OTE0
OTE1
OUT0 (2) (4)
OUT1 (3) (5)
Compare 1 (3) (5) interrupt
Compare 0 (2) (4) interrupt
55
MB90480/485 Series
(3) Input Capture
The input capture module performs the functions of detecting the rising edge, falling edge, or both edges of signal input from external circuits, and saving the 16-bit free run timer value at that moment to a register. An interrupt can also be generated at the instant of edge detection.
The input capture module consists of input capture registers and a control register. Each input capture module has its own external input pin.
• Selection of three types of valid edge for external input signals. Rising edge, falling edge, both edges.
• An interrupt can be generated when a valid edge is detected in the external input signal.
• Register List
Input capture data register (IPCP0, IPCP1)
Initial value
XXXXXXXXB
00005D 00005FH
15 14 13 12 11 10 9 8
H
CP14CP15 CP13 CP12 CP11 CP10 CP09 CP08
RRRRRRRR
76543210
00005C 00005EH
H
CP06CP07 CP05 CP04 CP03 CP02 CP01 CP00
RRRRRRRR
Input capture control status register (ICS01)
76543210
000060
H 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
ICP0ICP1 ICE1 ICE0 EG11 EG10 EG01 EG00
•Block Diagram
Capture data register 0
Bus
16-bit timer counter value (T15 to T00)
Edge detection
EG11 EG10 EG01 EG00
Initial value
XXXXXXXXB
Initial value
IN0
56
Capture data register 1
ICP1 ICP0 ICE1 ICE0
Edge detection
IN1
Interrupt
Interrupt
MB90480/485 Series
9. I2C Interface (MB90485 series only)
The I2C interface is a serial I/O port supporting the Inter IC BUS. Serves as a master/slave device on the I2C bus.
2
The I
C interface has the following functions.
Master/slave transmit/receive
Arbitration function
Clock synchronization
Slave address/general call address detection function
Forwarding direction detection function
Start condition repeated generation and detection
Bus error detection function
(1) Register List
Bus Status Register (IBSR)
Initial value
Initial value
000088
H 00000000B
Bus control register (IBCR)
000089
H 00000000B
BER BEIE SCC MSS ACK GCAA INTE INT
R/W R/W R/W R/W R/W R/W R/W R/W
765 43210
BB RSC AL LRB TRX AAS GCA FBT
RRR RRRRR
15 14 13 12 11 10 9 8
Clock control register (ICCR)
00008A
H --0XXXXXB
Address register (IADR)
00008B
H -XXXXXXXB
15 14 13 12 11 10 9 8
Data register (IDAR)
00008C
H XXXXXXXXB
765 43210
EN CS4 CS3 CS2 CS1 CS0
R/W R/W R/W R/W R/W R/W
A6 A5 A4 A3 A2 A1 A0
R/W R/W R/W R/W R/W R/W R/W
765 43210
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
Initial value
Initial value
57
MB90480/485 Series
(2) Block Diagram
ICCR
2
C enable
EN
ICCR
I
Clock dividing 1
56 78
Peripheral clock
CS4
CS3
MC-16LX Bus
2
F
CS2
CS1
CS0
IBSR
BB
RSC
LRB
TRX
FBT
AL
IBCR
BER
BEIE
INTE
Bus busy
Repeat start
Last Bit
Clock selection 1
Clock dividing 2
248 16 3264128 256
Clock selection 2
Start/stop condition detection
Tr ansmission/
Reception
First Byte
Arbitration lost detection
Interrupt request
Sync
Change timing
of shift clock edge
Error
IRQ
Shift clock generation
SCL
SDA
58
INT
IBCR
SCC
MSS
ACK
GCAA
IBSR
AAS
GCA
Start
Master
ACK enable
GC-ACK enable
Slave
Global call
End
Start/stop condition
detection
IDAR
Slave address
comparison
IADR
MB90480/485 Series
10. 16-bit Reload Timer
The 16-bit reload timer provides a choice of functions, including internal clock signals that count down in synchronization with three types of internal clock, as well as an event count mode that counts down at specified edge detection events in pulse signals input from external pins. This timer defines an underflow as a change in count value from 0000 setting value + 1”. The choice of counting operations includes reload mode, in which the count setting values is reloaded and counting continues following an underflow event, and one-shot mode, in which an underflow event causes counting to stop. An interrupt can be generated at counter underflow, and the timer is DTC compatible.
(1) Register List
• TMCSR (Timer control status register)
Timer control status register (high) (TMCSR)
0000CB
Timer control status register (low) (TMCSR)
0000CA
H to FFFFH. Thus an underflow will occur when counting from the value “reload register
15 14 13 12 11 10 9 8
H
⎯⎯CSL1 CSL0 MOD2 MOD1
76543210
H
MOD0 OUTL RELD INTE UF CNTE TRG
R/W
0
⎯ ⎯
OUTE
R/W0R/W0R/W0R/W0R/W0R/W0R/W
⎯ ⎯
⎯ ⎯
R/W0R/W0R/W0R/W
0
0
Read/Write Initial value
Read/Write Initial value
• 16-bit timer register/16-bit reload register
TMR/TMRLR (high)
15 14 13 12 11 10 9 8
0000CD
H
D15 D13 D12 D11 D10 D09 D08
R/W
D14
R/WXR/WXR/WXR/WXR/WXR/WXR/W
X
TMR/TMRLR (low)
76543210
0000CC
H
D07 D05 D04 D03 D02 D01 D00
R/W
D06
R/WXR/WXR/WXR/WXR/WXR/WXR/W
X
Read/Write
X
Initial value
Read/Write
X
Initial value
59
MB90480/485 Series
(2) Block Diagram
Internal data bus
TMRLR
16-bit reload register
TMR
16-bit timer register
(down counter)
CLK
Count clock generator circuit
Machine clock φ
Pin
(TIN0)
Prescaler
Input control
circuit
3
Clear
External clock
UF
Gate input
detection circuit
Reload signal
Valid clock
CLK
Clock
selector
Wait signal
Output signal
generation circuit
Inverted
Output signal
generation circuit
Reload
control
circuit
To A/D converter
Pin
(TOT0)
EN
Function selection
3
Select signal
2
Timer control status register (TMCSR)
RELDOUTL
Operation
control circuit
OUTE
60
11. µPG Timer (MB90485 series only)
The µPG timer performs pulse output in response to the external input.
(1) Register List
µPG control status register (PGCSR)
00008E
(2) Block Diagram
H 00000---B
76543210
PEN0 PE1 PE0 PMT1 PMT0
R/W R/W R/W R/W R/W
MB90480/485 Series
Initial value
MT00
MT00
Output latch
Control circuit
MT01
Output latch
MT01
Output enable
EXTC
61
MB90480/485 Series
12. PWC Timer (MB90485 series only)
The PWC timer is a 16-bit multifunction up-count timer capable of measuring the pulse width of the input signal. A total of three channels are provided, each consisting of a 16-bit up-count timer, an input pulse divider & divide ratio control register, a measurement input pin, and a 16-bit control register. These components provide the following functions.
Timer function : • Capable of generating an interrupt request at fixed intervals specified.
The internal clock used as the reference clock can be selected from
among three types.
Pulse width measurement function : Measures the time between arbitrary events based on external pulse
inputs.
The internal clock used as the reference clock can be selected from
among three types.
Measurement modes
- “H” pulse width ( to ) /“L” pulse width ( to ↓)
- Rising cycle ( to ) /Falling cycle ( to )
- Measurement between edges ( or to or )
The 8-bit input divider can be used for division measurement by dividing the input pulse by 22 × n (n = 1, 2, 3, 4) .
An interrupt can be generated upon completion of measurement.
One-time measurement or fast measurement can be selected.
62
(1) Register list
PWC control/status register (PWCSR0 to PWCSR2)
000077 00007BH 00007FH
H
15 14 13 12 11 10 9 8
STRT STOP EDIR EDIE OVIR OVIE ERR
R/W R/W R R/W R/W R/W R
PWC control/status register (PWCSR0 to PWCSR2)
000076H 00007AH 00007EH
76543210
CKS1 CKS0 PIS1 PIS0 S/C MOD2 MOD1 MOD0
R/W R/W R/W R/W R/W R/W R/W R/W
PWC data buffer register (PWCR0 to PWCR2)
000079H
00007DH
000081H
15 14 13 12 11 10 9 8
D15 D14 D13 D12 D11 D10 D9 D8
R/W R/W R/W R/W R/W R/W R/W R/W
MB90480/485 Series
Initial value
Reserved
0000000X
Initial value
00000000
Initial value
00000000
B
B
B
PWC data buffer register (PWCR0 to PWCR2)
000078H 00007CH
000080H
76543210
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
Dividing ratio control register (DIVR0 to DIVR2)
000082H
76543210
000084H 000086H
DIV1 DIV0
R/WR/W
Initial value
00000000B
Initial value
------00B
63
MB90480/485 Series
(2) Block Diagram
PWCR read
Error detection
ERR
MC-16 Bus
2
F
Flag set etc.
Reload
Data transfer
Overflow
16-bit up count timer
Control circuit
Start edge selection
Start of measurement edge
Completion of measurement edge
Control bit output
Completion of measurement interrupt request
Overflow interrupt request
Completion edge selection
Edge detection
PWCR
16
PIS0/PIS1
ERR
16
Dividing ON/OFF
CKS0/ CKS1
Clock
Timer clear
CKS1/CKS0
Count enable
8-bit divider
Internal clock (machine clock/4)
2
2
Clock divider
3
2
Divider clear
Input
waveform
comparator
PWC0
PWC1
64
15
PWCSR
2
Dividing ratio selection
DIVR
MB90480/485 Series
13. Watch Timer
The watch timer is a 15-bit timer using the sub clock. This circuit can generate interrupts at predetermined intervals. Also a setting is available to enable it to be used as the clock source for the watchdog timer.
(1) Register List
Watch timer control register (WTC)
76543210
0000AA
(2) Block Diagram
Watch timer control register (WTC)
H
WDCS WTIE WTOF WTR WTC2 WTC1 WTC0
R/W
SCE
R
R/W0R/W0R/W
1
0
R/W0R/W0R/W
1
0
Read/write Initial value
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
Clear
8
2
9
Sub clock
Watch counter
2102132142
2
10
2
11
2
12
2
13
2
14
15
2
Interval
selector
Interrupt
generator
circuit
Watch timer
interrupt
To watchdog timer
65
MB90480/485 Series
14. Watchdog timer
The watchdog timer is a 2-bit counter that uses the output from the timebase timer or watch timer as a count clock signal, and will reset the CPU if not cleared within a predetermined time interval after it is activated.
(1) Register List
Watchdog timer control register (WDTC)
76543210
0000A8
(2) Block Diagram
H
PONR WRST ERST SRST WTE WT1 WT0
R X
Reserved
X
R X
R X
R X
W
1
W
1
W
1
Read/write Initial value
Watch mode start Timebase timer mode start Sleep mode start Hold status start
Stop mode
start
HCLK × 2
SCLK
Watchdog timer control register (WDTC)
PONR WRST ERST SRST WTE WT1 WT0
Re-
served
Watchdog timer
Counter
clear
control
circuit
Clear
Time-base counter
1
× 2
× 2
2
× 2
1
2
× 2
× 2 2 210× 211× 212× 213× 214× 215× 216× 217× 2
× 2 2 210× 211× 212× 213× 214× 215× 216× 217× 2
2
Count
clock
selector
4
CLR
CLR and start
2-bit
counter
Watch timer control register (WTO) WDCS bit
Clock select register (CKSCR) SCM bit
CLR
Watchdog
reset
generator
circuit
4
18
18
Internal reset generator circuit
66
HCLK : Oscillator clock SCLK : Sub clock
MB90480/485 Series
15. Timebase Timer
The timebase timer is an 18-bit free run counter (timebase counter) that counts up in synchronization with the internal count clock signal (base oscillator × 2) , and functions as an interval timer with a choice of four types of time intervals. Other functions provided by this module include timer output for the oscillator stabilization wait period, and operating clock signal feed for other timer circuits such as the watchdog timer.
(1) Register List
Timebase timer control register (TBTC)
0000A9
(2) Block Diagram
HCLK × 2
Power-on reset
Stop mode start
Hold status start
CKSCR : MCS = 1→0*
CKSCR : SCS = 0→1*
H
15 14 13 12 11 10 9 8
RESV TBIE TBOF TBR TBC1 TBC0
R/W
1
⎯ ⎯
X
X
R/W0R/W
0
W
1
To PPG timer Timebase timer counter
× 2 2
2
× 2 2 210× 211× 212× 213× 214× 215× 216× 217× 2
OF
OF
Counter
clear
control
1
2
circuit
Interval timer
selector
TBOF clear
R/W0R/W
0
To watchdog timer
OF
TBOF set
Read/write Initial value
18
OF
To clock control module oscillator stabilization wait time selector
Timebase timer control register (TBTC)
RESV TBIE TBOF TBR TBC1 TBC0
⎯⎯
Timebase timer interrupt signal
OF : Overflow HCLK : Oscillator clock *1 : Switch machine clock from main clock or sub clock to PLL clock. *2 : Switch machine clock from sub clock to main clock.
67
MB90480/485 Series
16. Clock
The clock generator module controls the operation of the internal clock circuits that serve as the operating clock for the CPU and peripheral devices. This internal clock is referred to as the machine clock, and one cycle is referred to as a machine cycle. Also, the clock signals from the base oscillator are called the oscillator clock, and those from the PLL oscillator are called the PLL clock.
(1) Register List
Clock select register (CKSCR)
15 14 13 12 11 10 9 8
0000A1
PLL output select register (PLLOS)
0000CF
H
SCM WS1 WS0 SCS MCS CS1 CS0
H
MCM
R
R
1
15 14 13 12 11 10 9 8
⎯⎯ ⎯⎯PLL2
⎯ ⎯
R/W1R/W1R/W1R/W1R/W0R/W
1
⎯ ⎯
⎯ ⎯
⎯ ⎯
⎯ ⎯
Read/write Initial value
0
W
X
W
0
Read/write Initial value
68
(2) Block Diagram
Low-power consumption mode control register (LPMCR)
pin
RST
Standby control circuit
STP SLP SPL RST TMD CG1 CG0
Re-
served
MB90480/485 Series
Pin high-impedance
control circuit
Internal reset
generator circuit
Pin high-impedance control
Internal reset
Interrupt release
Clock generator module
SCLK
× 4
Sub clock
generator
circuit
pin
X0A
pin
X1A
pin
X0
pin
X1
CPU intermittent
operation selec
Standby control
circuit
Machine clock
Clock
selector
PLL multiplier
circuit
SCM
Clock select register (CKSCR)
System
clock
generator
circuit
HCLK
× 2
MCLK
Timebase timer
HCLK : Oscillator clock MCLK : Main clock SCLK : Sub clock
tor
CPU clock
control circuit
Peripheral
clock control
circuit
Oscillator stabilization wait release
PLL output select register (PLLOS)
⎯⎯⎯⎯⎯⎯⎯PLL2
2
2
MCM WS1WS0 SCS MCS CS1CS0
×
1024
× 2 × 4 × 4 × 4 × 2
To watchdog timer
Intermittent cycle selection
CPU clock
Stop, sleep signals
Stop signal
Peripheral clock
Oscillator
stabilization
wait period
selector
69
MB90480/485 Series
(3) Clock Feed Map
Clock generator module
X0A
pin
X1A
pin
X0
pin
X1
pin
Sub clock generator
circuit
System clock
generator
circuit
HCLK
PLL multiplier
× 4
× 2
MCLK
Watch timer
Timebase
timer
123 4
circuit
SCLK
PCLK
Clock
selector
CPU, µDMAC
Peripheral functions
4
Watchdog timer
4
8/16-bit PPG
timer 0
8/16-bit PPG
timer 1
8/16-bit PPG
timer 2
16-bit reload
φ
timer 0
PPG0, PPG1
pins
PPG2, PPG3
pins
PPG4, PPG5
pins
TIN0
pin
TOT0
pin
SCK0, SIN0
pins
UART0
SOT0
pin
SCK1, SCK2 SIN1, SIN2
Extended I/O
serial interface,
2 channels
8/16-bit
up/down counter
pins
SOT1, SOT2
pins
AIN0, AIN1 BIN0, BIN1
ZIN0, ZIN1
pins
70
HCLK : Oscillator clock MCLK : Main clock SCLK : Sub clock PCLK : PLL clock φ : Machine clock
Chip select
16-bit output
compare
16-bit free run
timer
16-bit input
capture
10-bit A/D
converter
External interrupt
Oscillator
3
stabilization
wait control
CS0, CS1, CS2, CS3
pins
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5
pins
FRCK
pin
IN0, IN1
pins
AN0 to AN7, ADTG
pins
IRQ0 to IRQ7
pin
MB90480/485 Series
17. Low-power Consumption Mode
The MB90480/485 series uses operating clock selection and clock operation controls to provide the following CPU operating modes :
• Clock modes (PLL clock mode, main clock mode, sub clock mode)
• CPU intermittent operating modes (PLL clock intermittent mode, main clock intermittent mode, sub clock intermittent mode)
• Standby modes (Sleep mode, timebase timer mode, stop mode, watch mode)
(1) Register List
Low-power consumption mode control register (LPMCR)
76543210
0000A0
H
STP SPL RST TMD CG1 CG0
W
SLP
0
W
R/W
0
0
W
R/W
1
1
Reserved
R/W0R/W0R/W
0
Read/write Initial value
71
MB90480/485 Series
(2) Block Diagram
Standby control circuit
Low-power consumption mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0
RST
pin
CPU intermittent
operating selector
Standby control
Interrupt release
Machine clock
Clock generator module
circuit
Re-
served
high-impedance
control circuit
Internal reset
generator circuit
CPU clock
control cir
Peripheral
clock control
Oscillator stabilization wait release
Pin
Pin high-impedance control
Internal reset
Intermittent cycle selection
cuit
CPU clock
Stop, sleep signals
Stop signal
Peripheral clock
circuit
Sub clock generator
circuit
pin
X0A
pin
X1A
HCLK : Oscillator clock MCLK : Main clock SCLK : Sub clock
× 4
X0
X1
pin
pin
SCLK
PLL multiplier
circuit
System
clock
generator
circuit
HCLK
Clock
selector
× 2
PLL output select register (PLLOS)
⎯⎯⎯⎯⎯⎯⎯PLL2
2
SCM
MCM WS1WS0 SCS MCS CS1CS0
Clock select register (CKSCR)
×
1024
MCLK
× 2 × 4 × 4 × 4 × 2
Timebase timer
2
To watchdog timer
Oscillator stabiliza-
tion
wait period
selector
72
(3) Status Transition Chart
External reset, watchdog timer reset, software reset
Power-on
Power-on reset
Oscillator stabilization wait ends
SLP = 1 SLP = 1 SLP = 1
TMD = 0 TMD = 0 TMD = 0
Main clock
mode
Interrupt
Main sleep
mode
Interrupt
MCS = 0
MCS = 1
Reset
SCS = 1
PLL clock
mode
PLL sleep
mode
MB90480/485 Series
SCS = 0
SCS = 0
SCS = 1
Interrupt
Interrupt
Sub clock
mode
Interrupt
Sub sleep
mode
Interrupt
Main timebase
timer mode
STP = 1 STP = 1 STP = 1
Main stop
mode
Oscillator
Interrupt
Main clock oscillator
stabilization wait
stabilization wait ends
PLL timebase
timer mode
PLL stop
mode
Interrupt
Main clock oscillator
stabilization wait
Oscillator stabilization wait ends
Interrupt
Sub clock oscillator
Watch mode
Sub stop
mode
Oscillator stabilization wait ends
stabilization wait
73
MB90480/485 Series
18. External Bus Pin Control Circuit
The external bus pin control circuit controls the external bus pins used to expand the CPU address/data bus connections to external circuits.
(1) Register List
• Auto ready function select register (ARSR)
Address : 0000A5H 0011--00B
15 14 13 12 11 10 9 8
IOR1 HMR1 HMR0 ⎯⎯LMR1 LMR0
IOR0
W
WWW ⎯⎯WW
• External address output control register (HACR)
Address : 0000A6
H ********B
76543210
E23 E21 E20 E19 E18 E17 E16
W
E22
WW W W WWW
• Bus control signal select register (EPCR)
Address : 0000A7
15 14 13 12 11 10 9 8
H 1000*10-B
CKE HDE IOBS HMBS WRE LMBS
RYE
W
WWW W WW
Initial value
Initial value
Initial value
W
*
(2) Block Diagram
: Write only : Not used : May be either “1” or “0”
P0 data
P0 direction
RB
Data control
Address control
P0
P1
P2
P3
P5
P4
P5
P0
74
Access control
Access control
MB90480/485 Series
19. Chip Select Function Description
The chip select module generates a chip select signals, which are used to facilitate connections to external memory devices. The MB90480/485 series has four chip select output pins, each having a chip select area register setting that specifies the corresponding hardware area and select signal that is output when access to the corresponding external address is detected.
• Chip select function features
The chip select function uses two 8-bit registers for each output pin. One of these registers (CARx) is able to detect memory areas in 64 Kbytes units by specifying the upper 8-bit of the address for match detection. The other register (CMRx) can be used to expand the detection area beyond 64 Kbytes by masking bits for match detection. Note that during external bus holds, the CS output is set to high impedance.
(1) Register List
15 0
CAR1
CAR3
Chip select area mask register (CMRx)
0000C0 0000C2H 0000C4H 0000C6H
H
76543210
M7 M5 M4 M3 M2 M1 M0
R/W
M6
R/W0R/W0R/W0R/W1R/W1R/W1R/W
0
Chip select area register (CARx)
0000C1 0000C3H 0000C5H 0000C7H
H
15 14 13 12 11 10 9 8
A7 A5 A4 A3 A2 A1 A0
R/W
1
A6
R/W1R/W1R/W1R/W1R/W1R/W1R/W
Chip select control register (CSCR)
76543210
0000C8
H
⎯⎯OPL3 OPL2 OPL1 OPL0
⎯ ⎯
⎯ ⎯
⎯ ⎯
8 7
CMR0CAR0
CMR1
CMR2CAR2
CMR3
CSCR R/WCALR
R/W0R/W0R/W0R/W
1
1
*
R/W
R/W
R/W
R/W
Read/write Initial value
Read/write Initial value
Read/write Initial value
Chip select active level register (CALR)
15 14 13 12 11 10 9 8
0000C9
H
⎯⎯ACTL3 ACTL2 ACTL1 ACTL0
⎯ ⎯
⎯ ⎯
⎯ ⎯
R/W0R/W0R/W0R/W
* : The initial value of this bit is “1” or “0”.
The value depends on the mode pin (MD2, MD1 and MD0) .
0
Read/write Initial value
75
MB90480/485 Series
(2) Block Diagram
CMRx
MC-16LX Bus
2
F
CARx
A23 to A16
Chip select output pins
76
MB90480/485 Series
20. ROM Mirror Function Select Module
The ROM mirror function selection module sets the data in ROM assigned to FF bank so that the data is read by access to 00 bank.
(1) Register List
ROM mirror function select register (ROMM)
Initial value
( + ) : MB90F489B : Read only, fixed at “1”
Other : Selectable, Initial value 0
Address : 00006F
- : Not used
(2) Block Diagram
15 14 13 12 11 10 9 8
H ------+1B
F
⎯⎯MS MI
2
MC-16LX bus
R/W R/W
(+)
ROM mirror function select
Address area
FF bank
00 bank
ROM
Note : Do not access ROM mirror function selection register (ROMM) on using the area of address 004000
00FFFF
H (008000H to 00FFFFH) .
H to
77
MB90480/485 Series
21. Interrupt Controller
The interrupt control register is built in interrupt controller, and is supported for all I/O of interrupt function. This register sets corresponding peripheral interrupt level.
(1) Register List
Interrupt control registers
Address : ICR01
ICR03 ICR05 ICR07 ICR09 ICR11 ICR13 ICR15
0000B1
H
0000B3H 0000B5H 0000B7H 0000B9H
0000BBH
0000BDH
0000BFH
Read/write
Initial value
15 14 13 12 11 10 9 8
⎯⎯
W
X
W
Reserved IL2 IL1 IL0
X
W
X
W
R/W
X
R/W1R/W1R/W
0
1
ICR01, 03, 05, 07, 09, 11, 13, 15
Interrupt control registers
Address : ICR00
ICR02 ICR04 ICR06 ICR08 ICR10 ICR12 ICR14
0000B0
H
0000B2H 0000B4H 0000B6H
0000B8H 0000BAH 0000BCH 0000BEH
Read/write
Initial value
76543210
⎯⎯
W
X
W
Reserved IL2 IL1 IL0
X
W
X
W
X
R/W0R/W1R/W1R/W
1
ICR00, 02, 04, 06, 08, 10, 12, 14
Note : The use of access involving read-modify-write instructions may lead to abnormal operation, and should be
avoided.
78
(2) Block Diagram
MC-16LX Bus
2
F
IL2
IL1
IL0
MB90480/485 Series
Interrupt priority setting
Interrupt requests
3233
(Peripheral resources)
3
(CPU)
Interrupt level
79
MB90480/485 Series
22. µDMAC
The µDMAC is a simplified DMA module with functions equivalent to EI2OS. The µDMAC has 16 DMA data transfer channels, and provides the following functions.
• Automatic data transfer between peripheral resources (I/O) and memory.
• CPU program execution stops during DMA operation.
• Incremental addressing for transfer source and destination can be turned on/off.
• DMA transfer control from the µDMAC enable register, µDMAC stop status register, µDMAC status register,
and descriptor.
• Stop requests from resources can stop DMA transfer.
• When DMA transfer is completed, the µDMAC status register sets a flag in the bit for the corresponding channel
on which transfer was completed, and outputs a completion interrupt to the interrupt controller.
(1) Register List
µDMAC enable register
Initial value
DERH : 0000AD
15 14 13 12 11 10 9 8
H 00000000B
EN14EN15 EN13 EN12 EN11 EN10 EN9 EN8
R/W
R/W R/W
R/W
R/WR/W
R/W R/W
µDMAC enable register
DERL : 0000AC
µDMAC stop status register
DSSR : 0000A4
µDMAC status register
DSRH : 00009D
µDMAC status register
DSRL : 00009C
76543210
H 00000000B
H 00000000B
15 14 13 12 11 10 9 8
H 00000000B
H 00000000B
EN6EN7 EN5 EN4 EN3 EN2 EN1 EN0
R/W
76543210
STP6STP7 STP5 STP4 STP3 STP2 STP1 STP0
R/W
DE14DE15 DE13 DE12 DE11 DE10 DE9 DE8
R/W
76543210
DE6DE7 DE5 DE4 DE3 DE2 DE1 DE0
R/W
R/W R/W
R/W R/W
R/W R/W
R/W R/W
R/W
R/W
R/W
R/W
R/WR/W
R/WR/W
R/WR/W
R/WR/W
R/W R/W
R/W R/W
R/W R/W
R/W R/W
Initial value
Initial value
Initial value
Initial value
80
(2) Block Diagram
MB90480/485 Series
IOA
I/O register
If transfer not ended
Memory space
µDMAC
Read by DER
descriptor
BAP
BufferTransfer
DCT
IOA : I/O address pointer BAP : Buffer address pointer DER : µDMAC enable register (ENx selection) DCT : Data counter
I/O register
µDMA controller
CPU
Peripheral function
(I/O)
DMA transfer request
If transfer is ended
Interrupt
controller
2
MC-16LX Bus F
81
MB90480/485 Series
23. Address Match Detection Function
When the address is equal to a value set in the address detection register, the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code (01 the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program patching function to be implemented.
Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value set in the address detection register matches an address and if the interrupt enable bit is set at “1”, the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code.
(1) Register List
• Program address detection register 0 (PADR0)
H). As a result, when the CPU executes a set instruction,
Address
PADR0 (Low order address) : 001FF0
Address
PADR0 (Middle order address) : 001FF1
Address
PADR0 (High order address) : 001FF2H
76543210
H
R/W R/W R/W R/W R/W R/W R/W R/W
76543210
H
R/W R/W R/W R/W R/W R/W R/W R/W
76543210
R/W R/W R/W R/W R/W R/W R/W R/W
• Program address detection register 1 (PADR1)
Address
PADR1 (Low order address) : 001FF3H
Address
PADR1 (Middle order address) : 001FF4H
Address
PADR1 (High order address) : 001FF5H
76543210
R/W R/W R/W R/W R/W R/W R/W R/W
76543210
R/W R/W R/W R/W R/W R/W R/W R/W
76543210
R/W R/W R/W R/W R/W R/W R/W R/W
• Program address detection control status register (PACSR)
Address
00009EH
76543210
RESV RESV RESV RESV AD1E RESV AD0E RESV
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
00000000
B
B
B
B
B
B
B
82
R/W : Readable and writable
X : Undefined
RESV : Reserved bit
(2) Block Diagram
MB90480/485 Series
Address latch
Address detection
register
Enable bit
Internal data bus
Compare
INT9 instruction
2
F
MC-16LX
CPU core
83
MB90480/485 Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol
VCC3VSS 0.3 VSS + 4.0 V
CC5VSS 0.3 VSS + 7.0 V
Power supply voltage*
1
V
AV
Rating
Unit Remarks
Min Max
CC VSS 0.3 VSS + 4.0 V *2
AVRH V
Input voltage*
Output voltage*
Maximum clamp current I
1
1
CLAMP −2.0 +2.0 mA *7
Total maximum clamp current Σ⏐I
“L” level maximum output current I
“L” level average output current I
OLAV 3mA*5
“L” level maximum total output current ΣI “L” level total average output current ΣI
“H” level maximum output current I
“H” level average output current I
OHAV ⎯−3mA*5
“H” level maximum total output current ΣI “H” level total average output current ΣI
Power consumption P
Operating temperature T
VI
VO
CLAMP⏐⎯ 20 mA *7
OL 10 mA *4
OL 60 mA
OLAV 30 mA *6
OH ⎯−10 mA *4
OH ⎯−60 mA
OHAV ⎯−30 mA *6
D 320 mW A −40 +85 °C
SS 0.3 VSS + 4.0 V *2
VSS 0.3 VSS + 4.0 V *3
SS 0.3 VSS + 7.0 V *3, *8, *9
V VSS 0.3 VSS + 4.0 V *3
SS 0.3 VSS + 7.0 V *3, *8, *9
V
Storage temperature Tstg −55 +150 °C
*1 : This parameter is based on VSS = AVSS = 0.0 V.
*2 : AV
*3 : V
CC and AVRH must not exceed VCC. Also, AVRH must not exceed AVCC.
I and V0 must not exceed VCC + 0.3 V. However, if the maximum current to/from and input is limited by some
means with external components, the I
CLAMP rating supersedes the VI rating.
*4 : Maximum output current is defined as the peak value for one of the corresponding pins.
*5 : Average output current is defined as the average current flow in a 100 ms interval at one of the corresponding
pins.
*6 : Average total output current is defined as the average current flow in a 100 ms interval at all corresponding pins. *7 : Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P90 to P97, PA0 to PA3
Use within recommended operating conditions.
Use at DC voltage (current) .
The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
(Continued)
84
MB90480/485 Series
(Continued)
Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the V other devices.
Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
Care must be taken not to leave the +B input pin open.
Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input.
Sample recommended circuits:
• Input/Output Equivalent circuits
Protective diode
Limiting
resistance
+B input (0 V to 16 V)
CC pin, and this may affect
V
CC
P-ch
N-ch
R
*8 : MB90485 series only
P20 to P27, P30 to P37, P40 to P47, P70 to P77 pins can be used as 5 V I/F pin on applied 5 V to V
CC5 pin.
P76 and P77 is N-ch open drain pin.
*9 : As for P76 and P77 (N-ch open drain pin) , even if using at 3 V simplicity (VCC3 = VCC5) , the ratings are applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
85
MB90480/485 Series
2. Recommended Operating Conditions
Parameter Symbol
Min Max
(VSS = AVSS = 0.0 V)
Value
Unit Remarks
CC3
V
1.8 3.6 V To maintain RAM state in stop mode
Power supply voltage
2.7 5.5 V During normal operation*
2.7 3.6 V During normal operation
V
CC5
1.8 5.5 V To maintain RAM state in stop mode*
All pins other than VIH2, VIHS, VIHM and V
IHX
MB90485 series only P76, P77 pins (N-ch open drain pins)
“H” level input voltage
IH 0.7 VCC VCC + 0.3 V
V
VIH2 0.7 VCC VSS + 5.8 V
VIHS 0.8 VCC VCC + 0.3 V Hysteresis input pins
V
IHM VCC 0.3 VCC + 0.3 V MD pin input
V
IHX 0.8 VCC VCC + 0.3 V X0A pin, X1A pin
VIL VSS 0.3 0.3 VCC V All pins other than VILS, VILM and VILX
VILS VSS 0.3 0.2 VCC V Hysteresis input pins
“L” level input voltage
V
ILM VSS 0.3 VSS + 0.3 V MD pin input
VILX VSS 0.3 0.1 V X0A pin, X1A pin
Operating temperature T
A −40 +85 °C
* : MB90485 series only
P20 to P27, P30 to P37, P40 to P47, P70 to P77 pins can be used as 5 V I/F pin on applied 5 V to V
CC5 pin.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
86
3. DC Characteristics
Parameter Symbol Pin name Condition
V
CC = 2.7 V,
I
“H” level output voltage
“L” level output voltage
Input leakage current
Pull-up resistance
Open drain output current
V
R
I
All output
OH
pins
All output
V
OL
pins
All input
IL
I
pins
PULL
P40 to P47,
leak
I
P70 to P77
CC
I
CCS
Power supply current
CCL
I
I
CCT
ICCH
Input capacitance
IN
C
Other than AV VCC, VSS
Notes :MB90485 series only
P40 to P47 and P70 to P77 are N-ch open drain pins with control, which are usually used as CMOS.
P76 and P77 are open drain pins without P-ch.
For use as a single 3 V power supply products, set V
When the device is used with dual power supplies, P20 to P27, P30 to P37, P40 to P47 and
P70 to P77 serve as 5 V pins while the other pins serve as 3 V I/O pins.
CC, AVSS,
OH = 1.6 mA
VCC = 4.5 V, I
OH = 4.0 mA
V
CC = 2.7 V,
I
OL = 2.0 mA
CC = 4.5 V,
V I
OH = 4.0 mA
VCC = 3.3 V, V
SS < VI < VCC
V
CC = 3.0 V,
at T
A = +25 °C
CC = 3.3 V,
At V internal 25 MHz operation, normal operation
CC = 3.3 V,
At V internal 25 MHz operation, Flash programming
CC = 3.3 V,
At V internal 25 MHz operation, sleep mode
CC = 3.3 V,
At V external 32 kHz, internal 8 kHz operation, sub clock operation (T
A = +25 °C)
At V
CC = 3.3 V,
external 32 kHz, internal 8 kHz operation, watch mode (T
T
A = +25 °C, stop mode,
At V
CC = 3.3 V
MB90480/485 Series
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 40 °C to +85 °C)
Val ue
Min Typ Max
CC3 0.3 ⎯⎯V
V
CC5 0.5 ⎯⎯V
V
⎯⎯0.4 V
⎯⎯0.4 V
10 ⎯+10 µA
20 53 200 k
⎯⎯0.1 10 µA
45 60 mA
55 70 mA
17 35 mA
15 140 µA
1.8 40 µA
A = +25 °C)
0.8 40 µA
⎯⎯515pF
CC = VCC3 = VCC5.
Unit
At using 5 V power supply
At using 5 V power supply
Remarks
87
MB90480/485 Series
4. AC Characteristics
(1) Clock Timing
Parameter
Sym-
bol
Pin name
Condi-
tion
(V
Val ue
Min Typ Max
SS = 0.0 V, TA = 40 °C to +85 °C)
Unit Remarks
Clock frequency
Clock cycle time
Input clock pulse width
Input clock rise, fall time
Internal operating clock frequency
3 25
3 50 External clock input 4 25 1 multiplied PLL
F
CH X0, X1
3 12.5 2 multiplied PLL
MHz
3 6.66 3 multiplied PLL 3 6.25 4 multiplied PLL 3 4.16 6 multiplied PLL 3 3.12 8 multiplied PLL
F
CL X0A, X1A ⎯⎯32.768 kHz C X0, X1 20 333 ns *1
t
t
CL X0A, X1A ⎯⎯30.5 ⎯µs
PWH
PWL
P
WLH
PWLL
t
cr
tcf
CP ⎯⎯1.5 25 MHz *1
f
X0 5 ⎯⎯ns
X0A ⎯⎯15.2 ⎯µs*2
X0 ⎯⎯⎯5 ns With external clock
fCPL ⎯⎯⎯8.192 kHz
External crystal oscillator
t
Internal operating clock cycle time
CP ⎯⎯40.0 666 ns *1
t
CPL ⎯⎯⎯122.1 ⎯µs
*1 : Be careful of the operating voltage. *2 : Duty ratio should be 50 % ± 3 %.
88
• X0, X1 clock timing
X0
• X0A, X1A clock timing
MB90480/485 Series
t
C
0.8 V
CC
0.2 V
CC
P
WH
t
cf
tCL
P
WL
t
cr
X0A
0.8 VCC
0.2 VCC
PWLH PWLL
tcf tcr
89
MB90480/485 Series
• Range of warranted PLL operation Internal operating clock frequency vs. Power supply voltage
3.6
3.0
2.7
CC (V)
V
Range of warranted PLL operation
Normal operating range
Power supply voltage
41.5
16
25
Internal clock fCP (MHz)
Notes: For A/D operating frequency, refer to “5. A/D Converter Electrical Characteristics”
Only at 1 multiplied PLL, use with more than f
CP = 4 MHz.
Base oscillator frequency vs. Internal operating clock frequency
3
8 × *
25
24
20
18
16
12
Internal clock fCP (MHz)
1.5
3
6 × *
4 ×
1,*2
*
9
8 6 4
34 8
5 6 10 40
1
3 × *
2
2 × *1,*
12.5 16 2520 32 50
1 × *
1
Base oscillator clock F
No multiplied
CH (MHz)
*1 : In setting as 1, 2, 3 and 4 multiplied PLL, when the internal clock is used at 20 MHz < fCP 25 MHz, set
the PLLOS register to “DIV2 bit = 1” and “PLL2 bit = 1”. [Example] When using the base oscillator frequency of 24 MHz at 1 multiplied PLL :
CKSCR register : CS1 bit = “0”, CS0 bit = “0” PLLOS register : PLL2 bit = “1”
[Example] When using the base oscillator frequency of 6 MHz at 3 multiplied PLL :
CKSCR register : CS1 bit = “1”, CS0 bit = “0” PLLOS register : PLL2 bit = “1”
*2 : In setting as 2 and 4 multiplied PLL, when the internal clock is used at 20 MHz < f
CP 25 MHz, the following
setting is also enabled. 2 multiplied PLL : CKSCR register : CS1 bit = “0”, CS0 bit = “0”
PLLOS register : PLL2 bit = “1”
4 multiplied PLL : CKSCR register : CS1 bit = “0”, CS0 bit = “1”
PLLOS register : PLL2 bit = “1”
*3 : When using in setting as 6 and 8 multiplied PLL, set the PLLOS register to “DIV2 bit = 0” and “PLL2 bit = 1”.
[Example] When using the base oscillator frequency of 4 MHz at 6 multiplied PLL :
CKSCR register : CS1 bit = “1”, CS0 bit = “0” PLLOS register : PLL2 bit = “1”
[Example] When using the base oscillator frequency of 3 MHz at 8 multiplied PLL :
CKSCR register : CS1 bit = “1”, CS0 bit = “1” PLLOS register : PLL2 bit = “1”
90
AC standards are set at the following measurement voltage values.
MB90480/485 Series
• Input signal waveform
Hysteresis input pins
0.8 VCC
0.2 VCC
• Pins other than hysteresis input/MD input
0.7 VCC
0.3 VCC
• Output signal waveform
Output pins
2.4 V
0.8 V
91
MB90480/485 Series
(2) Clock Output Timing
Parameter Symbol Pin name Conditions
SS = 0.0 V, TA = 40 °C to +85 °C)
(V
Val ue
Min Max
Unit Remarks
Cycle time t
CYC CLK tCP* ns
VCC = 3.0 V to 3.6 V tCP* / 2 15 tCP* / 2 + 15 ns at fCP = 25 MHz
CLK↑→CLK↓ t
* : t
CP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
CHCL CLK
2.4 V 2.4 V
CLK
VCC = 2.7 V to 3.3 V tCP* / 2 20 tCP* / 2 + 20 ns at fCP = 16 MHz
V
CC = 2.7 V to 3.3 V tCP* / 2 64 tCP* / 2 + 64 ns at fCP = 5 MHz
t
CYC
t
CHCL
0.8 V
92
MB90480/485 Series
(3) Reset Input Standards
CC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 40 °C to +85 °C)
(V
Parameter Symbol
Reset input time t
*1 : t
CP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
RSTL RST
Pin
name
Condi-
tions
Oscillator oscillation time*
*2 : Oscillator oscillation time is the time to 90 % of amplitude. For a crystal oscillator this is on the order of several
milliseconds to tens of milliseconds. For a ceramic oscillator, this is several hundred microseconds to several milliseconds. For an external clock signal the value is 0 ms.
• In stop mode
t
RSTL
RST
0.2 Vcc
Val ue
Min Max
1
16 t
CP*
2
+ 4 tCP*
1
0.2 Vcc
Unit Remarks
ns Normal operation
ms Stop mode
90 % of
X0
amplitude
Internal operating clock
Oscillator oscillation time
Internal reset
• Condition for measurement of AC standards
C
Pin
CLK, ALE : C AD15 to AD00 (address data bus) , RD A23 to A00/D15 to D00 : C
CL
4 t
CP
Oscillator stabilization wait time
Instruction execution
L : Load capacitance applied to pins during testing
L = 30 pF
, WR,
L = 30 pF
93
MB90480/485 Series
(4) Power-on Reset Standards
Parameter Symbol Pin name Conditions
CC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 40 °C to +85 °C)
(V
Val ue
Unit Remarks
Min Max
Power rise time t
R VCC
0.05 30 ms *
Power down time t
* : Power rise time requires V
OFF VCC 1 ms In repeated operation
CC < 0.2 V.
Notes: The above standards are for the application of a power-on reset.
Within the device, the power-on reset should be applied by switching the power supply off and on again.
t
R
V
CC
2.7 V
0.2 V 0.2 V0.2 V
t
OFF
Note : Rapid fluctuations in power supply voltage may trigger a power-on reset in some cases. As shown below,
when changing supply voltage during operation, it is recommended that voltage changes be suppressed and a smooth restart be applied.
Main power supply voltage
Sub power supply voltage
94
V
CC
RAM data maintenance
V
SS
The slope of voltage increase should be kept within 50 mV/ms.
(5) Bus Read Timing
Parameter Symbol Pin name Conditions
ALE pulse width t
Valid address ALEtime
LHLL ALE
tAVLL
Address,
ALE
MB90480/485 Series
CC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C)
(V
Value
Min Max
CP* / 2 15 ns
t
tCP* / 2 20 ns
tCP* / 2 35 ns
CP* / 2 17 ns
t tCP* / 2 40 ns
Unit Remarks
16 MHz < fCP 25 MHz
8 MHz < fCP 16 MHz
fCP 8 MHz
fCP 8 MHz
ALE↓→ address valid time
Valid address RD
time
Valid address valid data input
tLLAX
tAVRL
AVDV
t
ALE,
Address
RD,
address
Address,
Data
tCP* / 2 15 ns
tCP* 25 ns
5 tCP* / 2 55
3 tCP* / 2 − 25
5 tCP* / 2 − 80
ns
RD pulse width tRLRH RD
3 tCP* / 2 − 20
RD↓→ valid data input
tRLDV
RD↑→data hold time tRHDX
RD
↑→ALEtime tRHLH RD, ALE tCP* / 2 15 ns
RD
↑→
address valid time Valid address
CLKtime
RD
↓→CLKtime tRLCH RD, CLK tCP* / 2 17 ns
tRHAX
tAVCH
RD,
Data
RD,
Data
Address,
RD
Address,
CLK
0 ns
tCP* / 2 10 ns
tCP* / 2 17 ns
⎯ ⎯
ns
3 tCP* / 2 − 55 3 tCP* / 2 − 80
ns
fCP 8 MHz
ns
16 MHz < fCP 25 MHz
8 MHz < fCP 16 MHz
ns
fCP 8 MHz
ns
ALE↓→RD
CP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
* : t
time tLLRL RD, ALE tCP* / 2 15 ns
95
MB90480/485 Series
CLK
ALE
RD
In multiplexed mode
A23 to A16
AD15 to AD00
In non-multiplexed mode
A23 to A00
D15 to D00
2.4 V
0.8 V
2.4 V
tAVCH
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
2.4 V
tLHLL
tAVLL
0.8 V
tLLAX
tLLRL
tAVRL tRLDV
0.8 V
tAVDV
2.4 V
Address
0.8 V
tAVDV
tRLCH
2.4 V
tRLDV
tRLRH
0.7 VCC
0.3 V
0.7 VCC
CC
0.3 V
CC
2.4 V
tRHDX
Read data
tRHDX
Read data
tRHLH
2.4 V
tRHAX
2.4 V
0.8 V
0.7 VCC
0.3 VCC
tRHAX
2.4 V
0.8 V
0.7 VCC
0.3 VCC
96
MB90480/485 Series
(6) Bus Write Timing
CC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C)
(V
Parameter
Valid address→WR
WR
pulse width tWLWH WRL, WRH
time tAVWL Address, WR tCP* 15 ns
Sym-
bol
Pin name
Valid data output →WR↑time tDVWH Data, WR
Condi-
tion
3 tCP* / 2 25
3 tCP* / 2 20
3 tCP* / 2 15
10 ns
WR
↑→data hold time tWHDX
WR,
Data
20 ns
30 ns
WR↑→address valid time tWHAX WR, Address tCP* / 2 10 ns WR↑→ALEtime tWHLH WR, ALE tCP* / 2 15 ns
WR
↓→CLKtime tWLCH WR, CLK tCP* / 2 17 ns
Val ue
Min Max
ns
ns
ns
Unit Remarks
16 MHz < fCP 25 MHz
8 MHz < fCP 16 MHz
16 MHz < fCP 25 MHz
8 MHz < fCP 16 MHz
fCP 8 MHz
CP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
* : t
97
MB90480/485 Series
CLK
ALE
WR (WRL, WRH)
tWLCH
2.4 V
tWHLH
2.4 V
tWLWH
2.4 V
0.8 V
In multiplexed mode
A23 to A16
AD15 to AD00
In non-multiplexed mode
A23 to A00
D15 to D00
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
tAVWL
Address
2.4 V
0.8 V
2.4 V
0.8 V
tDVWH
Write data
tDVWH
Write data
tWHAX
2.4 V
0.8 V
tWHDX
2.4 V
0.8 V
tWHAX
2.4 V
0.8 V
tWHDX
2.4 V
0.8 V
98
(7) Ready Input Timing
Parameter Symbol Pin name Conditions
MB90480/485 Series
CC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C)
(V
Value
Min Max
Unit Remarks
RDY setup time t
RYHS
RDY
70 ns at fCP = 8 MHz
RDY hold time tRYHH 0 ns
35 ns
CLK
ALE
RD/WR
RDY wait not
2.4 V 2.4 V
tRYHS
tRYHH
0.8 VCC 0.8 VCC
inserted
RDY wait inserted (1 cycle)
0.2 V
CC0.2 VCC
tRYHS
99
MB90480/485 Series
(8) Hold Timing
Parameter Symbol Pin name Conditions
CC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 40 °C to +85 °C)
(V
Value
Unit Remarks
Min Max
Pin floatingHAK
time tXHAL HAK
30 t
CP*ns
HAK
↓→pin valid time tHAHV HAK tCP*2 tCP*ns
* : t
CP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
Note : One or more cycles are required from the time the HRQ pin is read until the HAK
HAK
Pins
0.8 V
tXHAL
2.4 V
0.8 V
2.4 V
tHAHV
High-Z
signal changes.
2.4 V
0.8 V
(9) UART Timing
CC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 40 °C to +85 °C)
(V
Parameter Symbol
Serial clock cycle time t
Pin
name
SCYC
Conditions
Value
Min Max
2
8 t
CP*
ns
80 +80 ns
SCK↓→SOT delay time t
SLOV
Internal shift clock
120 +120 ns f
mode output pins :
Valid SIN→SCK↑ t
IVSH
1
L*
= 80 pF + 1 TTL
C
100 ns 200 ns f
4 t
CP*
2
2
2
ns ns ns
SCK↑→valid SIN hold time t
SHIX tCP*
Serial clock “H” pulse width tSHSL
Serial clock “L” pulse width t
SLSH 4 tCP*
Unit Remarks
CP = 8 MHz
CP = 8 MHz
SCK↓→SOT delay time t
Valid SIN→SCK↑ t
SCK↑→valid SIN hold time t
*1 : C
L is the load capacitance applied to pins for testing.
*2 : t
CP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
SLOV
IVSH
SHIX
Note : The above rating is in CLK synchronous mode.
100
External shift clock
mode output pins :
1
L*
= 80 pF + 1 TTL
C
150 ns 200 ns f
60 ns
120 ns f
60 ns
120 ns f
CP = 8 MHz
CP = 8 MHz
CP = 8 MHz
Loading...