FUJITSU MB90480, MB90485 DATA SHEET

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FUJITSU SEMICONDUCTOR

DATA SHEET

16-bit Proprietary Microcontroller

CMOS

F2MC-16LX MB90480/485 Series

MB90F481/F482/487B/488B/483C MB90F488B/F489B/V480/V485B

■ DESCRIPTION

The MB90480/485 series is a 16-bit general-purpose FUJITSU microcontroller designed for process control in consumer devices and other applications requiring high-speed real-time processing.

The F

MC-16LX CPU core instruction set retains the AT architecture of the F2MC*1 family, with additional instructions for high-level languages, expanded addressing mode, enhanced multiply-drive instructions, and complete bit processing. In addition, a 32-bit accumulator is provided to enable long-word processing.

DS07-13722-8E

The MB90480/485 series features embedded peripheral resources including 8/16-bit PPG, expanded I/O serial interface, UART, 10-bit A/D converter, 16-bit I/O timer, 8/16-bit up/down-counter, PWC timer, I external interrupt, chip select, and 16-bit reload timer.

*1 : F

MC is the abbreviation for FUJITSU Flexible Microcontroller.

*2 : Purchase of Fujitsu I

components in an I by Philips.

C components conveys a license under the Philips I2C Patent Rights to use, these

C system provided that the system conforms to the I2C standard a Specification as defined

2C*2

interface, DTP/

■ FEATURES

•Clock

Minimum instruction execution time: 40.0 ns/6.25 MHz base frequency multiplied × 4 (25 MHz internal operating

• Maximum memory space: 16 Mbytes

frequency/3.3 V ± 0.3 V)

62.5 ns/4 MHz base frequency multiplied × 4 (16 MHz internal operating frequency/3.0 V ± 0.3 V) PLL clock multiplier

(Continued)

Be sure to refer to the “Check Sheet” for the latest cautions on development.

“Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.

MB90480/485 Series

(Continued)

• Instruction set optimized for controller applications Supported data types (bit, byte, word, or long word)

Typical addressing modes (23 types) 32-bit accumulator for enhanced high-precision calculation Enhanced signed multiplication/division instruction and RETI instruction functions

• Instruction set designed for high-level programming language (C) and multi-task operations System stack pointer adopted Instruction set symmetry and barrel shift instructions

• Non-multiplex bus/multiplex bus compatible

• Enhanced execution speed 4-byte instruction queue

• Enhanced interrupt functions 8 levels setting with programmable priority, 8 external interrupts

• Data transfer function (µDMAC) Up to 16 channels

• Embedded ROM Flash versions : 192 Kbytes, 256 Kbytes, 384 Kbytes, MASK versions : 192 Kbytes, 256 Kbytes

• Embedded RAM Flash versions : 4 Kbytes, 6 Kbytes, 10 Kbytes, 24 Kbytes, MASK versions : 10 Kbytes, 16 Kbytes

• General purpose ports Up to 84 ports (Includes 16 ports with input pull-up resistance settings, 16 ports with output open-drain settings)

• A/D converter 8-channel RC sequential comparison type (10-bit resolution, 3.68 µs conversion time (at 25 MHz) )

•I

C interface (MB90485 series only) : 1channel, P76/P77 N-ch open drain pin (without P-ch)

Do not apply high voltage in excess of recommended operating ranges to the N-ch open drain pin (with P-ch) in MB90V485B.

• µPG (MB90485 series only) : 1 channel

• UART : 1 channel

• Extended I/O serial interface (SIO) : 2 channels

• 8/16-bit PPG : 3 channels (with 8-bit × 6 channel/16-bit × 3 channel mode switching function)

• 8/16-bit up/down counter/timer: 1 channel (with 8-bit × 2 channels/16-bit × 1-channel mode switching function)

• PWC (MB90485 series only) : 3 channels (Capable of compare the inputs to two of the three)

• 3 V/5 V I/F pin (MB90485 series only) P20 to P27, P30 to P37, P40 to P47, P70 to P77

• 16-bit reload timer : 1 channel

• 16-bit I/O timer : 2 channels input capture, 6 channels output compare, 1 channel free run timer

• On chip dual clock generator system

• Low-power consumption mode With stop mode, sleep mode, CPU intermittent operation mode, watch mode, timebase timer mode

• Packages : QFP 100/LQFP 100

• Process : CMOS technology

• Power supply voltage : 3 V, single power supply (some ports can be operated by 5 V power supply at MB90485 series)

MB90480/485 Series

■ PRODUCT LINEUP

• MB90480 series

Part number

Item

Classification Flash memory product Evaluation product ROM size 192 Kbytes 256 Kbytes ⎯ RAM size 4 Kbytes 6 Kbytes 16 Kbytes

CPU function

Ports

UART 1 channel, start-stop synchronized 8/16-bit PPG 8-bit × 6 channels/16-bit × 3 channels 8/16-bit up/down

counter/timer

16-bit free run timer

16-bit I/O timers

DTP/external interrupt circuit Number of external interrupt pin channels : 8 (edge or level detection) Extended I/O serial interface Embedded 2 channels

Timebase timer

A/D converter

Watchdog timer

Low-power consumption (standby) modes

Process CMOS

Type Not included security function

Emulator power supply*

Output compare (OCU)

Input capture (ICU)

MB90F481 MB90F482 MB90V480

Number of instructions : 351 Instruction bit length : 8-bit, 16-bit Instruction length : 1 byte to 7 bytes Data bit length : 1-bit, 8-bit, 16-bit Minimum instruction execution time : 40 ns (25 MHz machine clock)

General-purpose I/O ports: up to 84 General-purpose I/O ports (CMOS output) General-purpose I/O ports (with pull-up resistance) General-purpose I/O ports (N-ch open drain output)

Event input pins : 6, 8-bit up/down counters : 2 8-bit reload/compare registers : 2

Number of channels : 1 Overflow interrupt

Number of channels : 6 Pin input factor : A match signal of compare register

Number of channels : 2 Rewriting a register value upon a pin input (rising, falling, or both edges)

18-bit counter Interrupt cycles: 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator)

Conversion resolution : 8/10-bit, switchable One-shot conversion mode (converts selected channel 1 time only) Scan conversion mode (conversion of multiple consecutive channels,

programmable up to 8 channels) Continuous conversion mode (repeated conversion of selected channels) Stop conversion mode (conversion of selected channels with repeated pause)

Reset generation interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms

(minimum value, at 4 MHz base oscillator)

Stop mode, sleep mode, CPU intermittent operation mode, watch timer mode, timebase timer mode

User pin* 3 V/5 V versions

⎯ Included

*1 : User pin : P20 to P27, P30 to P37, P40 to P47, P70 to P77

*2 : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used.

Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply switching) about details.

Note : Ensure that you must write to Flash at V

CC = 3.13 V to 3.60 V (3.3 V + 10%, −5%) .

MB90480/485 Series

• MB90485 series

Part number

Item

MB90487B MB90488B MB90F488B MB90V485B MB90F489B MB90483C

Flash

Classification MASK ROM product

ROM size 192 Kbytes 256 Kbytes 256 Kbytes ⎯ 384 Kbytes 256 Kbytes

RAM size 10 Kbytes 10 Kbytes 10 Kbytes 16 Kbytes 24 Kbytes 16 Kbytes

Number of instructions : 351 Instruction bit length : 8-bit, 16-bit

CPU function

General-purpose I/O ports : up to 84

Ports

UART 1 channel, start-stop synchronized 8/16-bit PPG 8-bit × 6 channels/16-bit × 3 channels

8/16-bit up/down counter/timer

16-bit free run timer

16-bit I/O timers

Output compare (OCU)

General-purpose I/O ports (CMOS output) General-purpose I/O ports (with pull-up resistance) General-purpose I/O ports (N-ch open drain output)

Event input pins : 6, 8-bit up/down counters : 2 8-bit reload/compare registers : 2

Number of channels : 1 Overflow interrupt

Number of channels : 6 Pin input factor: A match signal of compare register

Instruction length : 1 byte to 7 bytes Data bit length : 1-bit, 8-bit, 16-bit Minimum instruction execution time : 40 ns (25 MHz machine clock)

memory

product

Evaluation

product

Flash

memory

product

MASK ROM

product

Input capture (ICU)

DTP/external interrupt circuit

Extended I/O serial interface

C interface*

I µPG 1 channel

PWC 3 channels

Timebase timer

A/D converter

Number of channels : 2 Rewriting a register value upon a pin input (rising, falling, or both edges)

Number of external interrupt pin channels: 8 (edge or level detection)

Embedded 2 channels

1 channel

18-bit counter Interrupt cycles : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator)

Conversion resolution : 8/10-bit, switchable One-shot conversion mode (converts selected channel 1 time only) Scan conversion mode (conversion of multiple consecutive channels,

Continuous conversion mode (repeated conversion of selected channels) Stop conversion mode (conversion of selected channels with repeated pause)

programmable up to 8 channels)

(Continued)

Item

Part number

MB90480/485 Series

MB90487B MB90488B MB90F488B MB90V485B MB90F489B MB90483C

Watchdog timer

Low-power consumption (standby) modes

Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms

(minimum value, at 4 MHz base oscillator)

Stop mode, sleep mode, CPU intermittent operation mode, watch timer mode, timebase timer mode

Process CMOS

Type

Emulator power supply*

3 V/5 V power

3 V/5 V

power

supply*

3 V/5 V

power

supply*

Included

security

3 V/5 V

power

supply*

function

⎯⎯ ⎯Included ⎯⎯

3 V/5 V power

Included

supply*

security

function

3 V/5 V

power

supply*

*1 : 3 V/5 V I/F pin : All pins should be for 3 V power supply without P20 to P27, P30 to P37, P40 to P47, and

P70 to P77.

*2 : P76/P77 pins are N-ch open drain pins (without P-ch) at built-in I

C. However, MB90V485B uses the N-ch open

drain pin (with P-ch) .

*3 : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used.

Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details.

Notes : • As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/µPG/I

become CMOS input.

• Ensure that you must write to Flash at V

CC = 3.13 V to 3.60 V (3.3 V + 10%, − 5%) .

MB90480/485 Series

■ PIN ASSIGNMENT

P17/AD15/D15

P16/AD14/D14

P15/AD13/D13

P14/AD12/D12

P13/AD11/D11

99989796959493929190898887868584838281

100

1P20/A16 P21/A17 P22/A18 P23/A19

P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3

P30/A00/AIN0 P31/A01/BIN0

P32/A02/ZIN0 P33/A03/AIN1 P34/A04/BIN1

P35/A05/ZIN1 P36/A06/PWC0* P37/A07/PWC1*

P40/A08/SIN2

P41/A09/SOT2

P42/A10/SCK2 P43/A11/MT00* P44/A12/MT01*

P45/A13/EXTC*

P46/A14/OUT4

P47/A15/OUT5

P70/SIN0 P71/SOT0 P72/SCK0

P73/TIN0

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

31P74/TOT0

32333435363738394041424344454647484950

(TOP VIEW)

P12/AD10/D10

P11/AD09/D09

P10/AD08/D08

P07/AD07/D07

P06/AD06/D06

P05/AD05/D05

P04/AD04/D04

P03/AD03/D03

P02/AD02/D02

P01/AD01/D01

CC3

X1X0V

P00/AD00/D00

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

X0A X1A P57/CLK RST P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE PA3/OUT3 PA2/OUT2 PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/PPG5 P94/PPG4 P93/FRCK/ADTG/CS3 P92/SCK1/CS2 P91/SOT1/CS1 P90/SIN1/CS0 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2 MD2

P76/SCL*

P77/SDA*

P75/PWC2*

AVRH

P60/AN0

P61/AN1

P62/AN2

P63/AN3

Vss

P64/AN4

P65/AN5

P66/AN6

P67/AN7

MD0

P80/IRQ0

P81/IRQ1

MD1

(FPT-100P-M06)

* : These are the pins for MB90485 series. The pins for MB90480 series are P36/A06, P37/A07,

P43/A11, P44/A12, P45/A13, P75 to P77.

Note : MB90485 series only

• I

C pin P77 and P76 are N-ch open drain pin (without P-ch) . However, MB90V485B uses

the N-ch open drain pin (with P-ch) .

• P20 to P27, P30 to P37, P40 to P47 and P70 to P77 are also used as 3 V/5 V I/F pin.

• As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for

PWC/µPG/I

C become CMOS input.

(TOP VIEW)

MB90480/485 Series

P22/A18

P23/A19 P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3

P30/A00/AIN0

1/A01/BIN0

P32/A02/ZIN0 P33/A03/AIN1 P34/A04/BIN1

P35/A05/ZIN1 P36/A06/PWC0* P37/A07/PWC1*

P40/A08/SIN2

P41/A09/SOT2

P42/A10/SCK2 P43/A11/MT00* P44/A12/MT01*

CC5

P45/A13/EXTC*

P46/A14/OUT4

P47/A15/OUT5

P70/SIN0

P02/AD02/D02

P01/AD01/D01

P07/AD07/D07

P06/AD06/D06

P05/AD05/D05

P04/AD04/D04

P12/AD10/D10

P11/AD09/D09

P21/A17

P20/A16

P17/AD15/D15

9998979695949392919089888786858483828180797877

100

1 2

4 5 6 7

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

26272

P14/AD12/D12

P16/AD14/D14

P15/AD13/D13

293031323334353637383940414243444546474849

P10/AD08/D08

P13/AD11/D11

P03/AD03/D03

P00/AD00/D00

CC3

X1X0V

X0A

X1A

P57/CLK

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

R P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE PA 3/OUT3 PA2/OUT2 PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/PPG5 P94/PPG4 P93/FRCK/ADTG/CS3 P92/SCK1/CS2 P91/SOT1/CS1 P90/SIN1/CS0 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3

AVRH

P60/AN0

P73/TIN0

P76/SCL*

P72/SCK0

P74/TOT0

P71/SOT0

P77/SDA*

P75/PWC2*

P61/AN1

P62/AN2

P63/AN3

P64/AN4

P65/AN5

P66/AN6

P67/AN7

P80/IRQ0

P81/IRQ1

MD0

MD1

MD2

P82/IRQ2

(FPT-100P-M05)

* : These are the pins for MB90485 series. The pins for MB90480 series are P36/A06, P37/A07, P43/

A11, P44/A12, P45/A13, P75 to P77.

Note : MB90485 series only

• I

C pin P77 and P76 are N-ch open drain pin (without P-ch) . However, MB90V485B uses

the N-ch open drain pin (with P-ch) .

• P20 to P27, P30 to P37, P40 to P47 and P70 to P77 are also used as 3 V/5 V I/F pin.

• As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/

µPG/I

C become CMOS input.

MB90480/485 Series

■ PIN DESCRIPTIONS

QFP*

Pin No.

LQFP*

Pin name

I/O

circuit

type*

82 80 X0 A Clock (oscillator) input pin

83 81 X1 A Clock (oscillator) output pin

80 78 X0A A Clock (32 kHz oscillator) input pin

79 77 X1A A Clock (32 kHz oscillator) output pin

77 75 RST

B Reset input pin

This is a general purpose I/O port. A setting in the port 0 input

P00 to P07

resistance register (RDR0) can be used to apply pull-up resistance (RD00-RD07 = “1”) . (Disabled when pin is set for output.)

85 to 92 83 to 90

AD00 to

AD07

D00 to D07

(CMOS)

In multiplex mode, these pins function as the external address/data bus low I/O pins.

In non-multiplex mode, these pins function as the external data bus low output pins.

This is a general purpose I/O port. A setting in the port 1 input

P10 to P17

resistance register (RDR1) can be used to apply pull-up resistance (RD10-RD17 = “1”) . (Disabled when pin is set for output.)

93 to

100

91 to 98

AD08 to

AD15

D08 to D15

(CMOS)

In multiplex mode, these pins function as the external address/data bus high I/O pins.

In non-multiplex mode, these pins function as the external data bus high output pins.

Function

1 to 4

99, 100,

1, 2

5 to 8 3 to 6

This is a general purpose I/O port. When the bits of external address

P20 to P23

output control register (HACR) are set to "1" in external bus mode, these pins function as general purpose I/O ports.

When the bits of external address output control register (HACR) are set to "0" in multiplex mode, these pins function as address high output pins (A16-A19). When the bits of external address output control register (HACR) are

A16 to A19

CMOS/H)

(

set to "0" in non-multiplex mode, these pins function as address high output pins (A16-A19).

This is a general purpose I/O port. When the bits of external address

P24 to P27

output control register (HACR) are set to "1" in external bus mode, these pins function as general purpose I/O ports.

When the bits of external address output control register (HACR) are set to "0" in multiplex mode, these pins function as address high output pins (A20-A23). When the bits of external address output control register (HACR) are

A20 to A23

CMOS/H)

(

set to "0" in non-multiplex mode, these pins function as address high output pins (A20-A23).

PPG0 to

PPG3

P30

A00

CMOS/H)

(

Output pins for PPG.

This is a general purpose I/O port.

In non-multiplex mode, this pin functions as an external address pin.

AIN0 8/16-bit up/down timer input pin (ch.0) .

(Continued)

MB90480/485 Series

Pin No.

QFP*

LQFP*

10 8

12 10

13 11

14 12

15 13

16, 17 14, 15

name

P31

A01 In non-multiplex mode, this pin functions as an external address pin.

I/O

circuit

type*

( CMOS/H)

Function

This is a general purpose I/O port.

BIN0 8/16-bit up/down timer input pin (ch.0) .

P32

A02 In non-multiplex mode, this pin functions as an external address pin.

(

CMOS/H)

This is a general purpose I/O port.

ZIN0 8/16-bit up/down timer input pin (ch.0)

P33

A03 In non-multiplex mode, this pin functions as an external address pin.

(

CMOS/H)

This is a general purpose I/O port.

AIN1 8/16-bit up/down timer input pin (ch.1) .

P34

A04 In non-multiplex mode, this pin functions as an external address pin.

(

CMOS/H)

This is a general purpose I/O port.

BIN1 8/16-bit up/down timer input pin (ch.1) .

P35

A05 In non-multiplex mode, this pin functions as an external address pin.

(

CMOS/H)

This is a general purpose I/O port.

ZIN1 8/16-bit up/down timer input pin (ch.1)

P36, P37

A06, A07

P36, P37

A06, A07

PWC0,

PWC1*

(

(CMOS)

CMOS/H)

MB90480

series

MB90485

series

This is a general purpose I/O port.

In non-multiplex mode, this pin functions as an external address pin.

This is a general purpose I/O port.

In non-multiplex mode, this pin functions as an external address pin.

This is a PWC input pin.

18 16

19 17

20 18

P40

A08 In non-multiplex mode, this pin functions as an external address pin.

CMOS/H)

(

This is a general purpose I/O port.

SIN2 Extended I/O serial interface input pin.

P41

A09 In non-multiplex mode, this pin functions as an external address pin.

F (CMOS)

This is a general purpose I/O port.

SOT2 Extended I/O serial interface output pin.

P42

A10 In non-multiplex mode, this pin functions as an external address pin.

(

CMOS/H)

This is a general purpose I/O port.

SCK2 Extended I/O serial interface clock input/output pin.

(Continued)

MB90480/485 Series

Pin No.

QFP*

LQFP*

21, 22 19, 20

24 22

25, 26 23, 24

I/O

Pin name

P43, P44

A11, A12

P43, P44

A11, A12

MT00,

MT01

P45

A13

P45

A13

EXTC*

P46, P47

A14, A15 In non-multiplex mode, this pin functions as an external address pin.

OUT4/

OUT5

circuit

F (CMOS)

(CMOS)

CMOS/H)

(

(CMOS)

type*

This is a general purpose I/O port.

MB90480

series

In non-multiplex mode, this pin functions as an external address pin.

This is a general purpose I/O port.

MB90485

series

In non-multiplex mode, this pin functions as an external address pin.

µPG output pin.

This is a general purpose I/O port.

MB90480

series

In non-multiplex mode, this pin functions as an external address pin.

This is a general purpose I/O port.

MB90485

series

In non-multiplex mode, this pin functions as an external address pin.

µPG input pin.

This is a general purpose I/O port.

Output compare event output pins.

Function

70 68

71 69

72 70

73 71

P50

ALE

P51

P52

WRL

P53

WRH

(CMOS)

This is a general purpose I/O port. In external bus mode, this pin functions as the ALE pin.

In external bus mode, this pin functions as the address load enable (ALE) signal pin.

This is a general purpose I/O port. In external bus mode, this pin functions as the RD

pin.

In external bus mode, this pin functions as the read strobe output (RD) signal pin.

This is a general purpose I/O port. In external bus mode, when the WRE bit in the EPCR register is set to “1”, this pin functions as the WRL

pin.

In external bus mode, this pin functions as the lower data write strobe output (WRL

) pin. When the WRE bit in the EPCR register is set to “0”,

this pin functions as a general purpose I/O port.

This is a general purpose I/O port. In external bus mode with 16-bit bus width, when the WRE bit in the EPCR register is set to “1”, this pin functions as the WRH

pin.

In external bus mode with 16-bit bus width, this pin functions as the upper data write strobe output (WRH

) pin. When the WRE bit in the EPCR register is set to “0”, this pin functions as a general purpose I/O port.

(Continued)

MB90480/485 Series

Pin No.

QFP*

74 72

75 73

76 74

78 76

38 to

LQFP*

36 to 39

I/O

Pin name

circuit

type*

Function

This is a general purpose I/O port. In external bus mode, when the

P54

(CMOS)

HRQ

HDE bit in the EPCR register is set to “1”, this pin functions as the HRQ pin.

In external bus mode, this pin functions as the hold request input (HRQ) pin. When the HDE bit in the EPCR register is set to “0”, this pin functions as a general purpose I/O port.

This is a general purpose I/O port. In external bus mode, when the

P55

(CMOS)

HAK

HDE bit in the EPCR register is set to “1”, this pin functions as the HAK pin.

In external bus mode, this pin functions as the hold acknowledge output (HAK

) pin. When the HDE bit in the EPCR register is set to “0”, this

pin functions as a general purpose I/O port.

This is a general purpose I/O port. In external bus mode, when the

P56

(CMOS)

RDY

RYE bit in the EPCR register is set to “1”, this pin functions as the RDY pin.

In external bus mode, this pin functions as the external ready (RDY) input pin. When the RYE bit in the EPCR register is set to “0”, this pin functions as a general purpose I/O port.

This is a general purpose I/O port. In external bus mode, when the

P57

(CMOS)

CLK

CKE bit in the EPCR register is set to “1”, this pin functions as the CLK pin.

In external bus mode, this pin functions as the machine cycle clock (CLK) output pin. When the CKE bit in the EPCR register is set to “0”, this pin functions as a general purpose I/O port.

P60 to P63

AN0 to AN3 These are the analog input pins for A/D converter.

(CMOS)

These are general purpose I/O ports.

43 to

41 to 44

27 25

28 26

29 27

30 28

31 29

P64 to P67

AN4 to AN7 These are the analog input pins for A/D converter.

P70

SIN0 This is the UART serial data input pin.

P71

SOT0 This is the UART serial data output pin.

P72

SCK0 This is the UART serial communication clock I/O pin.

P73

TIN0 This is the 16-bit reload timer event input pin.

P74

TOT0 This is the 16-bit reload timer output pin.

(CMOS)

(

CMOS/H)

(CMOS)

CMOS/H)

(

CMOS/H)

(CMOS)

These are general purpose I/O ports.

This is a general purpose I/O port.

(Continued)

MB90480/485 Series

Pin No.

QFP*

LQFP*

32 30

33 31

34 32

47, 48 45, 46

I/O

Pin name

P75

PWC2*

P76

SCL*

circuit

type*

(CMOS)

CMOS/H)

(

(CMOS)

(NMOS/H)

MB90480

series

MB90485

series

MB90480

series

MB90485

series

This is a general purpose I/O port.

This is a PWC input pin.

This is a general purpose I/O port.

Serves as the I2C interface data I/O pin. During operation of the I impedance state.

P77

SDA*

(CMOS)

(NMOS/H)

MB90480

series

MB90485

series

This is a general purpose I/O port.

Serves as the I2C interface data I/O pin. During operation of the I impedance state.

P80, P81

IRQ0, IRQ1 External interrupt input pins.

(

CMOS/H)

These are general purpose I/O ports.

Function

C interface, leave the port output in a high

52 to 57 50 to 55

58 56

59 57

60 58

61 59

62 60

P82 to P87

IRQ2 to IRQ7 External interrupt input pins.

CMOS/H)

(

P90

SIN1 Extended I/O serial interface data input pin.

CMOS/H)

(

These are general purpose I/O ports.

This is a general purpose I/O port.

CS0 Chip select 0.

P91

SOT1 Extended I/O serial interface data output pin.

(CMOS)

This is a general purpose I/O port.

CS1 Chip select 1.

P92

SCK1 Extended I/O serial interface clock input/output pin.

(

CMOS/H)

This is a general purpose I/O port.

CS2 Chip select 2.

P93

FRCK

ADTG

(

CMOS/H)

This is a general purpose I/O port.

When the free run timer is in use, this pin functions as the external clock input pin.

When the A/D converter is in use, this pin functions as the external trigger input pin.

CS3 Chip select 3.

P94

PPG4 PPG timer output pin.

(CMOS)

This is a general purpose I/O port.

(Continued)

Pin No.

QFP*

LQFP*

Pin name

I/O

circuit

type*

MB90480/485 Series

Function

63 61

64 62

65 63

66 to 69 64 to 67

OUT0 to OUT3

35 33 AV

P95

PPG5 PPG timer output pin.

P96

IN0 Input capture ch.0 trigger input pin.

P97

IN1 Input capture ch.1 trigger input pin.

PA0 to PA3

(CMOS)

(

CMOS/H)

(

CMOS/H)

(CMOS)

CC ⎯ A/D converter analog power supply input pin.

This is a general purpose I/O port.

These are general purpose I/O ports.

Output compare event output pins.

36 34 AVRH ⎯ A/D converter reference voltage input pin.

37 35 AV

49 to 51 47 to 49 MD0 to MD2

84 82 V

SS ⎯ A/D converter GND pin.

CMOS/H)

(

CC3 ⎯ 3.3 V ± 0.3 V power supply pins (VCC3) .

Operating mode selection input pins.

MB90480

series

3.3 V ± 0.3 V power supply pin. Usually, use VCC = VCC3 = VCC5 as a 3 V power supply.

3 V/5 V power supply pin.

23 21 V

CC5 ⎯

MB90485

series

5 V power supply pin when P20 to P27, P30 to P37, P40 to P47, P70 to P77 are used as 5 V I/F pins. Usually, use V

CC = VCC3 = VCC5 as a 3 V power supply

(when the 3 V power supply is used alone) .

11, 42, 819, 40,

SS ⎯ GND pins.

*1 : QFP : FPT-100P-M06

*2 : LQFP : FPT-100P-M05

*3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPES”.

*4 : As for MB90V485B, input pins become CMOS input.

MB90480/485 Series

■ I/O CIRCUIT TYPES

Type Circuit Remarks

• Feedback resistance

X1, X1A

X0, X0A

• With standby control

Standby control signal

Hysteresis input with pull-up resistance

X1, X0 : approx. 1 MΩ X1A, X0A : approx. 10 MΩ

Hysteresis input

• With input pull-up resistance

CTL

P-ch P-ch

N-ch

CMOS

control

• CMOS level input/output

CMOS level input/output

P-ch

N-ch

CMOS

• Hysteresis input

P-ch

N-ch

• CMOS level output

CMOS

(Continued)

MB90480/485 Series

(Continued)

Type Circuit Remarks

• CMOS level input/output

P-ch

Open drain control signal

N-ch

P-ch

CMOS

Open drain control signal

N-ch

Hysteresis input

• With open drain control

• CMOS level output

• Hysteresis input

• With open drain control

• CMOS level input/output

P-ch

N-ch

• Analog input

CMOS

Analog input

• Hysteresis input

N-ch

Digital output

• N-ch open drain output

(Flash memory product)

• CMOS level input

• With high voltage control for flash testing

Control signal

Mode input

Diffusion resistance

(MASK ROM product)

(MASK ROM product) Hysteresis input

Hysteresis input

MB90480/485 Series

■ HANDLING DEVICES

1. Be careful never to exceed maximum rated voltages (preventing latch-up)

In CMOS IC devices, a condition known as latch-up may occur if voltages higher than VCC or lower than VSS are applied to input or output pins other than medium-or high-voltage pins, or if the voltage applied between V V

SS pins exceeds the rated voltage level.

When latch-up occurs, the power supply current increases rapidly causing the possibility of thermal damage to circuit elements. Therefore it is necessary to ensure that maximum ratings are not exceeded in circuit operation. Similarly, when turning the analog power supply on or off, it is necessary to ensure that the analog power supply voltages (AV

2. Treatment of unused pins

Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins.

3. Treatment of Power Supply Pins (VCC/VSS)

When multiple VCC/VSS pins are present, device design considerations for prevention of latch-up and unwanted electromagnetic interference, abnormal strobe signal operation due to ground level rise, and conformity with total output current ratings require that all power supply pins must be externally connected to power supply or ground. Consideration should be given to connecting power supply sources to the V impedance as possible. It is also recommended that a bypass capacitor of approximately 0.1 µF be placed between the V

CC and AVRH) and analog input voltages do not exceed the digital power supply (VCC) .

CC/VSS pins of this device with as low

CC and VSS lines as close to this device as possible.

CC and

4. Crystal Oscillator Circuits

Noise around the X0/X1, or X0A/X1A pins may cause this device to operate abnormally. In the interest of stable operation it is strongly recommended that printed circuit board artwork places ground bypass capacitors as close as possible to the X0/X1, X0A/X1A and crystal oscillator (or ceramic oscillator) and that oscillator lines do not cross the lines of other circuits.

5. Precautions when turning the power supply on

In order to prevent abnormal operation in the chip’s internal step-down circuits, a voltage rise time during poweron of 50 µs (0.2 V to 2.7 V) or greater should be assured.

6. Supply Voltage Stabilization

Even within the operating range of VCC supply voltage, rapid voltage fluctuations may cause abnormal operation. As a standard for power supply voltage stability, it is recommended that the peak-to-peak V commercial supply frequency (50 MHz to 60 MHz) be 10 % or l es s o f V

CC, and that the transient voltage fluctuation

CC ripple voltage at

be no more than 0.1 V/ms or less when the power supply is turned on or off.

7. Proper power-on/off sequence

The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be turned on after the digital power supply (V off before the digital power supply (V when pins used as analog input pins are doubled as input ports, be sure that the input voltage does not exceed AV

CC) is turned on. The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be shut

CC) is shut off. Care should be taken that AVRH does not exceed AVCC. Even

CC.

MB90480/485 Series

8. Treatment of power supply pins on models with A/D converters

Even when the A/D converters are not in use, be sure to make the necessary connections AVCC = AVRH = VCC, and AV

9. Notes on Using Power Supply

Only the MB90485 series usually uses a 3 V power supply. By setting VCC3 = 3 V power supply and VCC5 = 5 V power supply, P20 to P27, P30 to P37, P40 to P47 and P70 to P77 can be interfaced as 5 V power supplies separately from the main 3 V power supply. Note that the analog power supplies (such as AV the A/D converter can be used only as 3 V power supplies.

10. Notes on Using External Clock

Even when using an external clock signal, an oscillation stabilization delay is applied after a power-on reset or when recovering from sub-clock or stop mode. When using an external clock, 25 MHz should be the upper frequency limit. The following figure shows a sample use of external clock signals.

SS = VSS.

CC and AVSS) for

OPEN

11. Treatment of NC pins

NC (internally connected) pins should always be left open.

12. Notes on during operation of PLL clock mode

On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operation if such failure occurs.

13. When the MB90480/485 series microcontroller is used as a single system

When the MB90480/485 series microcontroller is used as a single system, use connections so the X0A = VSS, and X1A = Open.

14. Writing to Flash memory

For writing to Flash memory, always ensure that the operating voltage VCC is between 3.0 V and 3.6 V.

MB90480/485 Series

■ BLOCK DIAGRAM

X0, X1, RST X0A, X1A MD2, MD1, MD0

SIN0 SOT0 SCK0

SIN1, SIN2 SOT1, SOT 2 SCK1, SCK2

AVR H AV

ADTG AN0

AN7

PWC0

PWC1

PWC2

Clock control

Circuit

RAM

ROM

µDMAC

Communication

prescaler

UART

Extended I/O serial

interface × 2 channels

A/D converter

( 10-bit )

PWC × 3 channels

F2MC16LX series core

CPU

Interrupt controller

8/16-bit PPG

8/16-bit

up/down

counter/timer

µPG

MC-16LX Bus

Chip select

PPG0, PPG1 PPG2, PPG3 PPG4, PPG5

AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1

EXTC MT00 MT01

CS0, CS1, CS2, CS3

Input/output timer

16-bit input capture ×

2 channels

16-bit output compare ×

6 channels

16-bit free-run timer

16-bit reload timer

C interface

External interrupt

IN0, IN1

OUT0, OUT1, OUT2, OUT3, OUT4, OUT5

TIN0 TOT0

SCL SDA

IRQ0

IRQ7

I/O port

888888888

P00

P10

P20

P30

P40

P50

P60

to to to to to to to to to to to

P07

P17

P27

P37

P47

P57

P67

P70

P77

P80

P87

P90

P97

PA 0

PA 3

: Only MB90485 series

P00 to P07 (8 pins) : with an input pull-up resistance setting register. P10 to P17 (8 pins) : with an input pull-up resistance setting register. P40 to P47 (8 pins) : with an open drain setting register. P70 to P77 (8 pins) : with an open drain setting register.

MB90485 series only

• I

C pin P77 and P76 are N-ch open drain pin (without P-ch) . However, MB90V485B uses

the N-ch open drain pin (with P-ch) .

• P20 to P27, P30 to P37, P40 to P47 and P70 to P77 are also used as 3 V/5 V I/F pin.

• As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/

µPG/I

C become CMOS input.

Note : In the above diagram, I/O ports share internal function blocks and pins. However, when a

set of pins is used with an internal module, it cannot also be used as an I/O port.

■ MEMORY MAP

• MB90F481/F482/487B/488B/483C/F488B/V480/V485B/F489B

Internal ROM

FFFFFF

Address #1

010000

Address #2

Address #3

Single chip

ROM area ROM area

ROM area

FF bank image

external bus

ROM area

FF bank image

✽

MB90480/485 Series

External ROM

external bus

000100

0000D0

000000

RAM RAM

Peripheral Peripheral Peripheral

RAM

: Internal

: External : Access inhibited

* : In models where address #3 overlaps with address #2, this external area does not exist.

Model Address #1 Address #2 Address #3

MB90F481 FC0000

H *

001100

MB90F482 FC0000H 001900H MB90487B FD0000H 002900H MB90488B FC0000H 002900H

MB90F488B FC0000H 002900H

004000H or 008000H, selected by the MS bit in the ROMM register

MB90V480 (FC0000H) 004000H

MB90V485B (FC0000H) 004000H

MB90483C FB0000H*

MB90F489B F90000H *

*1 : No memory cells from FC0000

H to FC7FFFH and FE0000H to FE7FFFH.

0080000H fixed 006100H*

004000H

The upper part of the 00 bank is set up to mirror the image of FF bank ROM, to enable efficient use of small model C compilers. Because the lower 16-bit address of the FF bank and the lower 16-bit address of the 00 bank are the same, enabling reference to tables in ROM without using the for specification in the pointer declaration. For example, in accessing address 00C000

H it is actually the contents of ROM at FFC000H that are accessed.

If the MS bit in the ROMM register is set to “0”, the ROM area in the FF bank will exceed 48 Kbytes and it is not possible to reflect the entire area in the image in the 00 bank. Therefore the image from FF4000H to FFFFFFH is reflected in the 00 bank and the area from FF0000

H to FF3FFFH can be seen in the FF bank only.

(Continued)

MB90480/485 Series

(Continued)

*2 : In MB90F489B, there is no access to F8 bank and FC bank on the single-chip mode or the internal-ROM

external-bus mode.

*3 : Because installed-RAM area is larger than MB90V485B, MB90F489B should execute emulation in an area

that is larger than 004000

*4 : In MB90483C, there is no access to F8 bank to FA bank and FC bank on the single-chip mode or the internal-

ROM external-bus mode.

H by the emulation memory area setting on the tool side.

• MB90F489B

MB90480/485 Series

FFFFFF

FF0000 FEFFFF

FE0000 FDFFFF

FD0000 FCFFFF

FC0000 FBFFFF

FB0000 FAFFFF

FA0000 F9FFFF

F90000 F8FFFF

F80000 F7FFFF

Single chip

ROM (FF bank)

ROM (FE bank)

ROM (FD bank)

ROM (FB bank)

ROM (FA bank)

ROM (F9 bank)

Internal ROM

external bus

ROM (FF bank)

ROM (FE bank)

ROM (FD bank)

ROM (FB bank)

ROM (FA bank)

ROM (F9 bank)

External ROM

external bus

010000 00FFFF

008000 007FFF

006100 0060FF

000100 0000FF

0000D0 0000CF

000000

ROM area

FF bank image

Peripheral Peripheral Peripheral

: Internal : External : Access inhibited

ROM area

FF bank image

RAMRAM

RAM

MB90480/485 Series

• MB90483C

FFFFFF

FF0000 FEFFFF

FE0000 FDFFFF

FD0000 FCFFFF

FC0000 FBFFFF

FB0000 FAFFFF

FA0000 F9FFFF

F90000 F8FFFF

F80000 F7FFFF

Single chip

ROM (FF bank)

ROM (FE bank)

ROM (FD bank)

ROM (FB bank)

Internal ROM

external bus

ROM (FF bank)

ROM (FE bank)

ROM (FD bank)

ROM (FB bank)

External ROM

external bus

010000 00FFFF

004000

008000 004000 003FFF

000100 0000FF

0000D0 0000CF

000000

ROM area

FF bank image

Peripheral

ROM area

FF bank image

RAMRAM

RegisterRegister

Peripheral

RAM

Peripheral

: Internal : External : Access inhibited

■ F2MC-16L CPU PROGRAMMING MODEL

•Dedicated registers

MB90480/485 Series

AH AL

•General purpose registers

32-bit

USP

SSP

16-bit

DPR

PCB

DTB

USB

SSB

ADB

8-bit

Accumulator

User stack pointer

System stack pointer

Processor status

Program counter

Direct page register

Program bank register

Data bank register

User stack bank register

System stack bank register

Additional data bank register

•Processor status

PS RP CCR

000180

H + RP × 10H

15 13

ILM

MSB LSB

12 8 70

16-bit

RW0

RW1

RW2

RW3

R1 R0

R3 R2

R7 R6

RL0

RL1

RW4

RL2

RW5

RW6

RL3

RW7

MB90480/485 Series

■ I/O MAP

Address Register name

H Port 0 data register PDR0 R/W Port 0 XXXXXXXXB

Abbreviated

Read/

Write

Resource name Initial value

01H Port 1 data register PDR1 R/W Port 1 XXXXXXXXB 02H Port 2 data register PDR2 R/W Port 2 XXXXXXXXB 03H Port 3 data register PDR3 R/W Port 3 XXXXXXXXB 04H Port 4 data register PDR4 R/W Port 4 XXXXXXXXB 05H Port 5 data register PDR5 R/W Port 5 XXXXXXXXB 06H Port 6 data register PDR6 R/W Port 6 XXXXXXXXB

XXXXXXXX

07H Port 7 data register PDR7 R/W Port 7

(MB90480 series)

11XXXXXX

(MB90485 series)

H Port 8 data register PDR8 R/W Port 8 XXXXXXXXB

08 09H Port 9 data register PDR9 R/W Port 9 XXXXXXXXB 0AH Port A data register PDRA R/W Port A ----XXXXB

0BH Up/down timer input enable register UDRE R/W

0CH Interrupt/DTP enable register ENIR R/W 0DH Interrupt/DTP source register EIRR R/W XXXXXXXXB 0EH Request level setting register 0FH Request level setting register R/W 00000000B

ELVR

R/W 00000000B

Up/down timer

input control

DTP/external interrupts

XX000000B

00000000B

10H Port 0 direction register DDR0 R/W Port 0 00000000B 11H Port 1 direction register DDR1 R/W Port 1 00000000B 12H Port 2 direction register DDR2 R/W Port 2 00000000B 13H Port 3 direction register DDR3 R/W Port 3 00000000B 14H Port 4 direction register DDR4 R/W Port 4 00000000B 15H Port 5 direction register DDR5 R/W Port 5 00000000B 16H Port 6 direction register DDR6 R/W Port 6 00000000B

00000000

17H Port 7 direction register DDR7 R/W Port 7

(MB90480 series)

XX000000

(MB90485 series)

H Port 8 direction register DDR8 R/W Port 8 00000000B

18 19H Port 9 direction register DDR9 R/W Port 9 00000000B 1AH Port A direction register DDRA R/W Port A ----0000B

1BH Port 4 output pin register ODR4 R/W

1CH Port 0 input resistance register RDR0 R/W

1DH Port 1 input resistance register RDR1 R/W

(Open-drain control)

(resistance control)

Port 4

Port 0

Port 1

00000000B

00000000

1EH Port 7 output pin register ODR7 R/W

(Open-drain control)

Port 7

(MB90480 series)

XX000000

(MB90485 series)

H Analog input enable register ADER R/W Port 6, A/D 11111111B

(Continued)

MB90480/485 Series

Address Register name

H Serial mode register SMR R/W

Abbreviated

21H Serial control register SCR W, R/W 00000100B 22H Serial input/output register SIDR/SODR R/W XXXXXXXXB

Read/

Write

Resource name Initial value

00000X00B

UART

23H Serial status register SSR R, R/W 00001000B 24H (Reserved area)

26H 27H 00000010B

Serial mode control status register 0 SMCS0 R/W

Communication prescaler control

CDCR R/W

Communication

prescaler (UART)

SIO1 (ch.0)

00--0000B

----0000

28H Serial data register 0 SDR0 R/W XXXXXXXXB

29H

2AH 2BH 00000010B

Communication prescaler control register 0

Serial mode control status register 1 SMCS1 R/W

SDCR0 R/W

Communication

prescaler

SIO1 (ch.0)

SIO2 (ch.1)

0---0000B

----0000

2CH Serial data register 1 SDR1 R/W XXXXXXXXB

Communication

prescaler

SIO2 (ch.1)

0---0000B

XXXXXXXXB

2DH

Communication prescaler control register 1

SDCR1 R/W

2EH Reload register L (ch.0) PPLL0 R/W 2FH Reload register H (ch.0) PPLH0 R/W XXXXXXXXB 30H Reload register L (ch.1) PPLL1 R/W XXXXXXXXB 31H Reload resister H (ch.1) PPLH1 R/W XXXXXXXXB 32H Reload register L (ch.2) PPLL2 R/W XXXXXXXXB 33H Reload register H (ch.2) PPLH2 R/W XXXXXXXXB 34H Reload register L (ch.3) PPLL3 R/W XXXXXXXXB 35H Reload register H (ch.3) PPLH3 R/W XXXXXXXXB 36H Reload register L (ch.4) PPLL4 R/W XXXXXXXXB 37H Reload register H (ch.4) PPLH4 R/W XXXXXXXXB

8/16-bit PPG

(ch.0 to ch.5)

38H Reload register L (ch.5) PPLL5 R/W XXXXXXXXB 39H Reload register H (ch.5) PPLH5 R/W XXXXXXXXB 3AH PPG0 operating mode control register PPGC0 R/W 0X000XX1B

3BH PPG1 operating mode control register PPGC1 R/W 0X000001B 3CH PPG2 operating mode control register PPGC2 R/W 0X000XX1B 3DH PPG3 operating mode control register PPGC3 R/W 0X000001B

3EH PPG4 operating mode control register PPGC4 R/W 0X000XX1B

3FH PPG5 operating mode control register PPGC5 R/W 0X000001B

40H PPG0, PPG1 output control register PPG01 R/W 8/16-bit PPG 00000000B

41H (Reserved area)

H PPG2, PPG3 output control register PPG23 R/W 8/16-bit PPG 00000000B

43H (Reserved area)

(Continued)

MB90480/485 Series

Address Register name

PPG4, PPG5 output control register PPG45 R/W 8/16-bit PPG 00000000B

Abbre-

viated

name

Read/

Write

Resource name Initial value

45H (Reserved area) 46

47H ADCS2 W, R/W 00000000B 48H 49H ADCR2 W, R 00000XXXB

Control status register

Data register

4AH Output compare register (ch.0) lower digits 4BH Output compare register (ch.0) upper digits 00000000B 4CH Output compare register (ch.1) lower digits 4DH Output compare register (ch.1) upper digits 00000000B 4EH Output compare register (ch.2) lower digits

4FH Output compare register (ch.2) upper digits 00000000B 50H Output compare register (ch.3) lower digits 51H Output compare register (ch.3) upper digits 00000000B 52H Output compare register (ch.4) lower digits 53H Output compare register (ch.4) upper digits 00000000B 54H Output compare register (ch.5) lower digits 55H Output compare register (ch.5) upper digits 00000000B

ADCS1 R/W

ADCR1 R XXXXXXXX

A/D converter

OCCP0 R/W

OCCP1 R/W

OCCP2 R/W

OCCP3 R/W

16-bit

input/output

OCCP4 R/W

timer output

compare

OCCP5 R/W

(ch.0 to ch.5)

00000000

00000000B

56H Output control register (ch.0) OCS0 R/W 0000--00B 57H Output control register (ch.1) OCS1 R/W ---00000B 58H Output control register (ch.2) OCS2 R/W 0000--00B

59H Output control register (ch.3) OCS3 R/W ---00000B 5AH Output control register (ch.4) OCS4 R/W 0000--00B 5BH Output control register (ch.5) OCS5 R/W ---00000B

5CH

5DH

5EH

5FH

Input capture data register (ch.0) lower digits

Input capture data register (ch.0) upper digits

Input capture data register (ch.1) lower digits

Input capture data register (ch.1) upper digits

IPCP0

IPCP1

R XXXXXXXXB

16-bit

XXXXXXXX

input/output

R XXXXXXXX

timer input

capture

(ch.0, ch.1)

R XXXXXXXXB

60H Input capture control status register ICS01 R/W 00000000B

61H (Reserved area)

(Continued)

MB90480/485 Series

Abbreviated

Address Register name

H Timer counter data register lower digits TCDT R/W

name

Read/

Write

Resource name Initial value

00000000B 63H Timer counter data register upper digits TCDT R/W 00000000B 64H Timer control status register TCCS R/W 00000000B 65H Timer control status register TCCS R/W 0--00000B 66H Compare clear register lower digits 67H Compare clear register upper digits XXXXXXXXB

CPCLR R/W

68H Up/down count register (ch.0) UDCR0 R

16-bit input/output

timer free run timer

XXXXXXXXB

00000000B 69H Up/down count register (ch.1) UDCR1 R 00000000B 6AH Reload/compare register (ch.0) RCR0 W 00000000B 6BH Reload/compare register (ch.1) RCR1 W 00000000B

6CH

6DH

Counter control register (ch.0) lower digits

Counter control register (ch.0) upper digits

CCRL0 W, R/W 0X00X000B

CCRH0 R/W 00000000B

8/16-bit up/down

6EH (Reserved area)

H ROM mirror function select register ROMM R/W

70H

71H

Counter control register (ch.1) lower digits

Counter control register (ch.1) upper digits

CCRL1 W, R/W

CCRH1 R/W -0000000

ROM mirroring

function

8/16-bit up/down

------+1B

0X00X000

72H Counter status register (ch.0) CSR0 R, R/W 00000000B 73H (Reserved area) 74

H Counter status register (ch.1) CSR1 R, R/W 8/16-bit UDC 00000000B

75H (Reserved area)

77H* 0000000XB 78H*

79H* 00000000B 7AH* 7BH* 0000000XB 7CH* 7DH* 00000000B 7EH* 7FH* 0000000XB

80H*

81H* 00000000B

PWC control/status register PWCSR0 R, R/W

PWC (ch.0)

PWC data buffer register PWCR0 R/W

PWC control/status register PWCSR1 R, R/W

PWC (ch.1)

PWC data buffer register PWCR1 R/W

PWC control/status register PWCSR2 R, R/W

PWC (ch.2)

PWC data buffer register PWCR2 R/W

00000000B

82H* Dividing ratio control register DIVR0 R/W PWC (ch.0) ------00B

83H (Reserved area)

84H* Dividing ratio control register DIVR1 R/W PWC (ch.1) ------00B

85H (Reserved area)

H* Dividing ratio control register DIVR2 R/W PWC (ch.2) ------00B

87H (Reserved area)

(Continued)

MB90480/485 Series

Abbreviated

Address Register name

H* Bus status register IBSR R

name

Read/

Write

Resource name Initial value

00000000

89H* Bus control register IBCR R/W 00000000B

8AH* Clock control register ICCR R/W --0XXXXXB

8BH* Address register IADR R/W -XXXXXXXB 8CH* Data register IDAR R/W XXXXXXXXB

8DH (Reserved area)

H* µPG control status register PGCSR R/W µPG 00000---B

8FH to 9BH (Disabled)

H µDMAC status register lower digits DSRL R/W µDMAC 00000000B

9DH µDMAC status register upper digits DSRH R/W µDMAC 00000000B

9EH

9FH

A0H

Program address detection control status resister

Delayed interrupt source general/ cancel register

Low-power consumption mode control register

PACSR R/W

DIRR R/W

LPMCR W, R/W

A1H Clock select register CKSCR R, R/W

Address match

detection function

Delayed interrupt

generator module

Low-power

consumption

Low-power

consumption

00000000B

-------0

00011000

11111100B

A2H, A3H (Reserved area)

H µDMAC stop status register DSSR R/W µDMAC 00000000B

A5H Automatic ready function select register ARSR W External pins 0011 - -00B A6H External address output control register HACR W External pins ********B A7H Bus control signal select register EPCR W External pins 1000*10 -B A8H Watchdog timer control register WDTC R, W Watchdog timer XXXXX111B

A9H Timebase timer control register TBTC W, R/W Timebase timer 1XX00100B AAH Watch timer control register WTC R, R/W Watch timer 10001000B ABH (Reserved area) AC

H µDMAC enable register lower digits DERL R/W µDMAC 00000000B

ADH µDMAC enable register upper digits DERH R/W µDMAC 00000000B

AEH Flash memory control status register FMCS W, R/W

Flash memory

interface

000X0000B

AFH (Disabled)

H Interrupt control register 00 ICR00 W, R/W

XXXX0111B B1H Interrupt control register 01 ICR01 W, R/W XXXX0111B B2H Interrupt control register 02 ICR02 W, R/W XXXX0111B B3H Interrupt control register 03 ICR03 W, R/W XXXX0111B B4H Interrupt control register 04 ICR04 W, R/W XXXX0111B

Interrupt controller B5H Interrupt control register 05 ICR05 W, R/W XXXX0111B B6H Interrupt control register 06 ICR06 W, R/W XXXX0111B B7H Interrupt control register 07 ICR07 W, R/W XXXX0111B B8H Interrupt control register 08 ICR08 W, R/W XXXX0111B

(Continued)

MB90480/485 Series

(Continued)

Abbreviated

Address Register name

H Interrupt control register 09 ICR09 W, R/W

name

BAH Interrupt control register 10 ICR10 W, R/W XXXX0111B BBH Interrupt control register 11 ICR11 W, R/W XXXX0111B BCH Interrupt control register 12 ICR12 W, R/W XXXX0111B BDH Interrupt control register 13 ICR13 W, R/W XXXX0111B BEH Interrupt control register 14 ICR14 W, R/W XXXX0111B

BFH Interrupt control register 15 ICR15 W, R/W XXXX0111B C0H Chip select area mask register 0 CMR0 R/W C1H Chip select area register 0 CAR0 R/W 11111111B C2H Chip select area mask register 1 CMR1 R/W 00001111B C3H Chip select area register 1 CAR1 R/W 11111111B C4H Chip select area mask register 2 CMR2 R/W 00001111B C5H Chip select area register 2 CAR2 R/W 11111111B C6H Chip select area mask register 3 CMR3 R/W 00001111B C7H Chip select area register 3 CAR3 R/W 11111111B C8H Chip select control register CSCR R/W ----000*B

C9H Chip select active level register CALR R/W ----0000B CAH CBH ----0000B CCH CDH

Timer control status register TMCSR R/W

16-bit timer register/ 16-bit reload register

TMR/TMRLR

CEH (Reserved area)

H PLL output control register PLLOS W

D0H to FFH (External area)

100

H to #H (RAM area)

1FF0

1FF2

1FF3

1FF5

Program address detection register 0

(Low order address) Program address detection register 0

(Middle order address) Program address detection register 0

(High order address) Program address detection register 1

(Low order address) Program address detection register 1

(Middle order address) Program address detection register 1

(High order address)

PADR0 R/W

PADR1 R/W

Read/

Write

Resource name Initial value

XXXX0111B

Interrupt controller

00001111B

Chip select

function

00000000

16-bit reload timer

R/W XXXXXXXXB

Low-power

consumption

Address match

detection function

Address match

detection function

------X0B

XXXXXXXX

B1FF1H

B1FF4H

* : These registers are only for MB90485 series.

They are used as the reserved area on MB90480 series.

(Continued)

MB90480/485 Series

(Continued)

Descriptions for read/write

R/W : Readable and writable R : Read only W : Write only

Descriptions for initial value

0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined.

- : This bit is not used. * : The initial value of this bit is “1” or “0”.

The value depends on the mode pin (MD2, MD1 and MD0) .

+ : The initial value of this bit is “1” or “0”.

The value depends on the RAM area of device.

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