The MB90480/485 series is a 16-bit general-purpose FUJITSU microcontroller designed for process control in
consumer devices and other applications requiring high-speed real-time processing.
2
The F
MC-16LX CPU core instruction set retains the AT architecture of the F2MC*1 family, with additional instructions for high-level languages, expanded addressing mode, enhanced multiply-drive instructions, and complete
bit processing. In addition, a 32-bit accumulator is provided to enable long-word processing.
DS07-13722-8E
The MB90480/485 series features embedded peripheral resources including 8/16-bit PPG, expanded I/O serial
interface, UART, 10-bit A/D converter, 16-bit I/O timer, 8/16-bit up/down-counter, PWC timer, I
external interrupt, chip select, and 16-bit reload timer.
2
*1 : F
MC is the abbreviation for FUJITSU Flexible Microcontroller.
*2 : Purchase of Fujitsu I
components in an I
by Philips.
2
C components conveys a license under the Philips I2C Patent Rights to use, these
2
C system provided that the system conforms to the I2C standard a Specification as defined
2C*2
interface, DTP/
■ FEATURES
•Clock
Minimum instruction execution time: 40.0 ns/6.25 MHz base frequency multiplied × 4 (25 MHz internal operating
• Maximum memory space: 16 Mbytes
frequency/3.3 V ± 0.3 V)
62.5 ns/4 MHz base frequency multiplied × 4 (16 MHz internal operating
frequency/3.0 V ± 0.3 V) PLL clock multiplier
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
• Instruction set optimized for controller applications
Supported data types (bit, byte, word, or long word)
Typical addressing modes (23 types)
32-bit accumulator for enhanced high-precision calculation
Enhanced signed multiplication/division instruction and RETI instruction functions
• Instruction set designed for high-level programming language (C) and multi-task operations
System stack pointer adopted
Instruction set symmetry and barrel shift instructions
programmable up to 8 channels)
Continuous conversion mode (repeated conversion of selected channels)
Stop conversion mode (conversion of selected channels with repeated pause)
* : These are the pins for MB90485 series. The pins for MB90480 series are P36/A06, P37/A07, P43/
A11, P44/A12, P45/A13, P75 to P77.
Note : MB90485 series only
2
• I
C pin P77 and P76 are N-ch open drain pin (without P-ch) . However, MB90V485B uses
the N-ch open drain pin (with P-ch) .
• P20 to P27, P30 to P37, P40 to P47 and P70 to P77 are also used as 3 V/5 V I/F pin.
• As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/
2
µPG/I
C become CMOS input.
7
MB90480/485 Series
■ PIN DESCRIPTIONS
QFP*
Pin No.
1
LQFP*
Pin name
2
I/O
circuit
3
type*
8280X0AClock (oscillator) input pin
8381X1AClock (oscillator) output pin
8078X0AAClock (32 kHz oscillator) input pin
7977X1AAClock (32 kHz oscillator) output pin
7775RST
BReset input pin
This is a general purpose I/O port. A setting in the port 0 input
P00 to P07
resistance register (RDR0) can be used to apply pull-up resistance
(RD00-RD07 = “1”) . (Disabled when pin is set for output.)
85 to 92 83 to 90
AD00 to
AD07
D00 to D07
C
(CMOS)
In multiplex mode, these pins function as the external address/data
bus low I/O pins.
In non-multiplex mode, these pins function as the external data bus
low output pins.
This is a general purpose I/O port. A setting in the port 1 input
P10 to P17
resistance register (RDR1) can be used to apply pull-up resistance
(RD10-RD17 = “1”) . (Disabled when pin is set for output.)
93 to
100
91 to 98
AD08 to
AD15
D08 to D15
C
(CMOS)
In multiplex mode, these pins function as the external address/data
bus high I/O pins.
In non-multiplex mode, these pins function as the external data bus
high output pins.
Function
1 to 4
99, 100,
1, 2
5 to 83 to 6
97
This is a general purpose I/O port. When the bits of external address
P20 to P23
output control register (HACR) are set to "1" in external bus mode,
these pins function as general purpose I/O ports.
When the bits of external address output control register (HACR) are
set to "0" in multiplex mode, these pins function as address high
output pins (A16-A19).
When the bits of external address output control register (HACR) are
A16 to A19
E
CMOS/H)
(
set to "0" in non-multiplex mode, these pins function as address high
output pins (A16-A19).
This is a general purpose I/O port. When the bits of external address
P24 to P27
output control register (HACR) are set to "1" in external bus mode,
these pins function as general purpose I/O ports.
When the bits of external address output control register (HACR) are
set to "0" in multiplex mode, these pins function as address high
output pins (A20-A23).
When the bits of external address output control register (HACR) are
A20 to A23
E
CMOS/H)
(
set to "0" in non-multiplex mode, these pins function as address high
output pins (A20-A23).
PPG0 to
PPG3
P30
A00
E
CMOS/H)
(
Output pins for PPG.
This is a general purpose I/O port.
In non-multiplex mode, this pin functions as an external address pin.
AIN08/16-bit up/down timer input pin (ch.0) .
(Continued)
8
MB90480/485 Series
Pin No.
1
QFP*
LQFP*
108
1210
1311
1412
1513
16, 1714, 15
Pin
name
2
P31
A01In non-multiplex mode, this pin functions as an external address pin.
I/O
circuit
3
type*
E
( CMOS/H)
Function
This is a general purpose I/O port.
BIN08/16-bit up/down timer input pin (ch.0) .
P32
A02In non-multiplex mode, this pin functions as an external address pin.
E
(
CMOS/H)
This is a general purpose I/O port.
ZIN08/16-bit up/down timer input pin (ch.0)
P33
A03In non-multiplex mode, this pin functions as an external address pin.
E
(
CMOS/H)
This is a general purpose I/O port.
AIN18/16-bit up/down timer input pin (ch.1) .
P34
A04In non-multiplex mode, this pin functions as an external address pin.
E
(
CMOS/H)
This is a general purpose I/O port.
BIN18/16-bit up/down timer input pin (ch.1) .
P35
A05In non-multiplex mode, this pin functions as an external address pin.
E
(
CMOS/H)
This is a general purpose I/O port.
ZIN18/16-bit up/down timer input pin (ch.1)
P36, P37
A06, A07
P36, P37
A06, A07
PWC0,
PWC1*
(
4
D
(CMOS)
E
CMOS/H)
MB90480
series
MB90485
series
This is a general purpose I/O port.
In non-multiplex mode, this pin functions as an external
address pin.
This is a general purpose I/O port.
In non-multiplex mode, this pin functions as an external
address pin.
This is a PWC input pin.
1816
1917
2018
P40
A08In non-multiplex mode, this pin functions as an external address pin.
G
CMOS/H)
(
This is a general purpose I/O port.
SIN2Extended I/O serial interface input pin.
P41
A09In non-multiplex mode, this pin functions as an external address pin.
F (CMOS)
This is a general purpose I/O port.
SOT2Extended I/O serial interface output pin.
P42
A10In non-multiplex mode, this pin functions as an external address pin.
G
(
CMOS/H)
This is a general purpose I/O port.
SCK2Extended I/O serial interface clock input/output pin.
(Continued)
9
MB90480/485 Series
Pin No.
1
QFP*
LQFP*
21, 22 19, 20
2422
25, 26 23, 24
I/O
Pin name
2
P43, P44
A11, A12
P43, P44
A11, A12
MT00,
MT01
P45
A13
P45
A13
EXTC*
P46, P47
A14, A15In non-multiplex mode, this pin functions as an external address pin.
OUT4/
OUT5
circuit
F (CMOS)
F (CMOS)
(CMOS)
CMOS/H)
(
4
(CMOS)
type*
F
G
F
3
This is a general purpose I/O port.
MB90480
series
In non-multiplex mode, this pin functions as an external
address pin.
This is a general purpose I/O port.
MB90485
series
In non-multiplex mode, this pin functions as an external
address pin.
µPG output pin.
This is a general purpose I/O port.
MB90480
series
In non-multiplex mode, this pin functions as an external
address pin.
This is a general purpose I/O port.
MB90485
series
In non-multiplex mode, this pin functions as an external
address pin.
µPG input pin.
This is a general purpose I/O port.
Output compare event output pins.
Function
7068
7169
7270
7371
P50
ALE
P51
RD
P52
WRL
P53
WRH
D
(CMOS)
D
(CMOS)
D
(CMOS)
D
(CMOS)
This is a general purpose I/O port. In external bus mode, this pin
functions as the ALE pin.
In external bus mode, this pin functions as the address load enable
(ALE) signal pin.
This is a general purpose I/O port. In external bus mode, this pin
functions as the RD
pin.
In external bus mode, this pin functions as the read strobe output (RD)
signal pin.
This is a general purpose I/O port. In external bus mode, when the WRE
bit in the EPCR register is set to “1”, this pin functions as the WRL
pin.
In external bus mode, this pin functions as the lower data write strobe
output (WRL
) pin. When the WRE bit in the EPCR register is set to “0”,
this pin functions as a general purpose I/O port.
This is a general purpose I/O port. In external bus mode with 16-bit bus
width, when the WRE bit in the EPCR register is set to “1”, this pin
functions as the WRH
pin.
In external bus mode with 16-bit bus width, this pin functions as the
upper data write strobe output (WRH
) pin. When the WRE bit in the
EPCR register is set to “0”, this pin functions as a general purpose I/O
port.
(Continued)
10
MB90480/485 Series
Pin No.
1
QFP*
7472
7573
7674
7876
38 to
41
LQFP*
36 to 39
I/O
Pin name
2
circuit
3
type*
Function
This is a general purpose I/O port. In external bus mode, when the
P54
D
(CMOS)
HRQ
HDE bit in the EPCR register is set to “1”, this pin functions as the
HRQ pin.
In external bus mode, this pin functions as the hold request input
(HRQ) pin. When the HDE bit in the EPCR register is set to “0”, this
pin functions as a general purpose I/O port.
This is a general purpose I/O port. In external bus mode, when the
P55
D
(CMOS)
HAK
HDE bit in the EPCR register is set to “1”, this pin functions as the HAK
pin.
In external bus mode, this pin functions as the hold acknowledge output (HAK
) pin. When the HDE bit in the EPCR register is set to “0”, this
pin functions as a general purpose I/O port.
This is a general purpose I/O port. In external bus mode, when the
P56
D
(CMOS)
RDY
RYE bit in the EPCR register is set to “1”, this pin functions as the RDY
pin.
In external bus mode, this pin functions as the external ready (RDY)
input pin. When the RYE bit in the EPCR register is set to “0”, this pin
functions as a general purpose I/O port.
This is a general purpose I/O port. In external bus mode, when the
P57
D
(CMOS)
CLK
CKE bit in the EPCR register is set to “1”, this pin functions as the CLK
pin.
In external bus mode, this pin functions as the machine cycle clock
(CLK) output pin. When the CKE bit in the EPCR register is set to
“0”, this pin functions as a general purpose I/O port.
P60 to P63
AN0 to AN3These are the analog input pins for A/D converter.
H
(CMOS)
These are general purpose I/O ports.
43 to
46
41 to 44
2725
2826
2927
3028
3129
P64 to P67
AN4 to AN7These are the analog input pins for A/D converter.
P70
SIN0This is the UART serial data input pin.
P71
SOT0This is the UART serial data output pin.
P72
SCK0This is the UART serial communication clock I/O pin.
P73
TIN0This is the 16-bit reload timer event input pin.
P74
TOT0This is the 16-bit reload timer output pin.
H
(CMOS)
G
(
CMOS/H)
F
(CMOS)
G
CMOS/H)
(
G
(
CMOS/H)
F
(CMOS)
These are general purpose I/O ports.
This is a general purpose I/O port.
This is a general purpose I/O port.
This is a general purpose I/O port.
This is a general purpose I/O port.
This is a general purpose I/O port.
(Continued)
11
MB90480/485 Series
Pin No.
1
QFP*
LQFP*
3230
3331
3432
47, 4845, 46
I/O
2
Pin name
P75
P75
PWC2*
P76
P76
4
SCL*
4
circuit
3
type*
F
(CMOS)
G
CMOS/H)
(
F
(CMOS)
I
(NMOS/H)
MB90480
series
MB90485
series
MB90480
series
MB90485
series
This is a general purpose I/O port.
This is a general purpose I/O port.
This is a PWC input pin.
This is a general purpose I/O port.
This is a general purpose I/O port.
Serves as the I2C interface data I/O pin. During operation of the I
impedance state.
P77
P77
SDA*
4
F
(CMOS)
I
(NMOS/H)
MB90480
series
MB90485
series
This is a general purpose I/O port.
This is a general purpose I/O port.
Serves as the I2C interface data I/O pin. During operation of the I
impedance state.
P80, P81
IRQ0, IRQ1External interrupt input pins.
E
(
CMOS/H)
These are general purpose I/O ports.
Function
2
C interface, leave the port output in a high
2
C interface, leave the port output in a high
52 to 57 50 to 55
5856
5957
6058
6159
6260
P82 to P87
IRQ2 to IRQ7External interrupt input pins.
E
CMOS/H)
(
P90
SIN1Extended I/O serial interface data input pin.
E
CMOS/H)
(
These are general purpose I/O ports.
This is a general purpose I/O port.
CS0Chip select 0.
P91
SOT1Extended I/O serial interface data output pin.
D
(CMOS)
This is a general purpose I/O port.
CS1Chip select 1.
P92
SCK1Extended I/O serial interface clock input/output pin.
E
(
CMOS/H)
This is a general purpose I/O port.
CS2Chip select 2.
P93
FRCK
ADTG
E
(
CMOS/H)
This is a general purpose I/O port.
When the free run timer is in use, this pin functions as the external
clock input pin.
When the A/D converter is in use, this pin functions as the external
trigger input pin.
CS3Chip select 3.
P94
PPG4PPG timer output pin.
D
(CMOS)
This is a general purpose I/O port.
(Continued)
12
(Continued)
Pin No.
1
QFP*
LQFP*
2
Pin name
I/O
circuit
type*
MB90480/485 Series
Function
3
6361
6462
6563
66 to 69 64 to 67
OUT0 to OUT3
3533AV
P95
PPG5PPG timer output pin.
P96
IN0Input capture ch.0 trigger input pin.
P97
IN1Input capture ch.1 trigger input pin.
PA0 to PA3
D
(CMOS)
E
(
CMOS/H)
E
(
CMOS/H)
D
(CMOS)
CC⎯A/D converter analog power supply input pin.
This is a general purpose I/O port.
This is a general purpose I/O port.
This is a general purpose I/O port.
These are general purpose I/O ports.
Output compare event output pins.
3634AVRH⎯A/D converter reference voltage input pin.
3735AV
49 to 51 47 to 49MD0 to MD2
8482V
SS⎯A/D converter GND pin.
J
CMOS/H)
(
CC3⎯3.3 V ± 0.3 V power supply pins (VCC3) .
Operating mode selection input pins.
MB90480
series
3.3 V ± 0.3 V power supply pin.
Usually, use VCC= VCC3 = VCC5 as a 3 V power supply.
3 V/5 V power supply pin.
2321V
CC5⎯
MB90485
series
5 V power supply pin when P20 to P27, P30 to P37,
P40 to P47, P70 to P77 are used as 5 V I/F pins.
Usually, use V
CC= VCC3 = VCC5 as a 3 V power supply
(when the 3 V power supply is used alone) .
11, 42, 819, 40,
79
SS⎯GND pins.
V
*1 : QFP : FPT-100P-M06
*2 : LQFP : FPT-100P-M05
*3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPES”.
*4 : As for MB90V485B, input pins become CMOS input.
13
MB90480/485 Series
■ I/O CIRCUIT TYPES
TypeCircuitRemarks
• Feedback resistance
X1, X1A
X0, X0A
• With standby control
A
Standby
control signal
Hysteresis input with pull-up resistance
X1, X0 : approx. 1 MΩ
X1A, X0A : approx. 10 MΩ
B
Hysteresis input
• With input pull-up resistance
CTL
P-chP-ch
C
N-ch
CMOS
control
• CMOS level input/output
CMOS level input/output
P-ch
N-ch
D
CMOS
14
• Hysteresis input
P-ch
N-ch
• CMOS level output
E
CMOS
(Continued)
MB90480/485 Series
(Continued)
TypeCircuitRemarks
• CMOS level input/output
P-ch
Open drain
control signal
F
N-ch
P-ch
CMOS
Open drain
control signal
G
N-ch
Hysteresis input
• With open drain control
• CMOS level output
• Hysteresis input
• With open drain control
• CMOS level input/output
P-ch
N-ch
• Analog input
H
CMOS
Analog input
• Hysteresis input
N-ch
Digital output
• N-ch open drain output
I
(Flash memory product)
(Flash memory product)
• CMOS level input
• With high voltage control for flash
testing
Control signal
J
Mode input
Diffusion resistance
(MASK ROM product)
(MASK ROM product)
Hysteresis input
Hysteresis input
15
MB90480/485 Series
■ HANDLING DEVICES
1.Be careful never to exceed maximum rated voltages (preventing latch-up)
In CMOS IC devices, a condition known as latch-up may occur if voltages higher than VCC or lower than VSS are
applied to input or output pins other than medium-or high-voltage pins, or if the voltage applied between V
V
SS pins exceeds the rated voltage level.
When latch-up occurs, the power supply current increases rapidly causing the possibility of thermal damage to
circuit elements. Therefore it is necessary to ensure that maximum ratings are not exceeded in circuit operation.
Similarly, when turning the analog power supply on or off, it is necessary to ensure that the analog power supply
voltages (AV
2.Treatment of unused pins
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent
damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused
input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused
input pins.
3.Treatment of Power Supply Pins (VCC/VSS)
When multiple VCC/VSS pins are present, device design considerations for prevention of latch-up and unwanted
electromagnetic interference, abnormal strobe signal operation due to ground level rise, and conformity with
total output current ratings require that all power supply pins must be externally connected to power supply or
ground.
Consideration should be given to connecting power supply sources to the V
impedance as possible. It is also recommended that a bypass capacitor of approximately 0.1 µF be placed
between the V
CC and AVRH) and analog input voltages do not exceed the digital power supply (VCC) .
CC/VSS pins of this device with as low
CC and VSS lines as close to this device as possible.
CC and
4.Crystal Oscillator Circuits
Noise around the X0/X1, or X0A/X1A pins may cause this device to operate abnormally. In the interest of stable
operation it is strongly recommended that printed circuit board artwork places ground bypass capacitors as close
as possible to the X0/X1, X0A/X1A and crystal oscillator (or ceramic oscillator) and that oscillator lines do not
cross the lines of other circuits.
5.Precautions when turning the power supply on
In order to prevent abnormal operation in the chip’s internal step-down circuits, a voltage rise time during poweron of 50 µs (0.2 V to 2.7 V) or greater should be assured.
6.Supply Voltage Stabilization
Even within the operating range of VCC supply voltage, rapid voltage fluctuations may cause abnormal operation.
As a standard for power supply voltage stability, it is recommended that the peak-to-peak V
commercial supply frequency (50 MHz to 60 MHz) be 10 % or l es s o f V
CC, and that the transient voltage fluctuation
CC ripple voltage at
be no more than 0.1 V/ms or less when the power supply is turned on or off.
7.Proper power-on/off sequence
The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be turned on after the digital power
supply (V
off before the digital power supply (V
when pins used as analog input pins are doubled as input ports, be sure that the input voltage does not exceed
AV
CC) is turned on. The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be shut
CC) is shut off. Care should be taken that AVRH does not exceed AVCC. Even
CC.
16
MB90480/485 Series
8.Treatment of power supply pins on models with A/D converters
Even when the A/D converters are not in use, be sure to make the necessary connections AVCC= AVRH = VCC,
and AV
9.Notes on Using Power Supply
Only the MB90485 series usually uses a 3 V power supply. By setting VCC3 = 3 V power supply and VCC5 = 5 V
power supply, P20 to P27, P30 to P37, P40 to P47 and P70 to P77 can be interfaced as 5 V power supplies
separately from the main 3 V power supply. Note that the analog power supplies (such as AV
the A/D converter can be used only as 3 V power supplies.
10. Notes on Using External Clock
Even when using an external clock signal, an oscillation stabilization delay is applied after a power-on reset or
when recovering from sub-clock or stop mode. When using an external clock, 25 MHz should be the upper
frequency limit.
The following figure shows a sample use of external clock signals.
SS= VSS.
CC and AVSS) for
X0
OPEN
X1
11. Treatment of NC pins
NC (internally connected) pins should always be left open.
12. Notes on during operation of PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operation if such failure occurs.
13. When the MB90480/485 series microcontroller is used as a single system
When the MB90480/485 series microcontroller is used as a single system, use connections so the X0A = VSS,
and X1A = Open.
14. Writing to Flash memory
For writing to Flash memory, always ensure that the operating voltage VCC is between 3.0 V and 3.6 V.
17
MB90480/485 Series
■ BLOCK DIAGRAM
X0, X1, RST
X0A, X1A
MD2, MD1, MD0
SIN0
SOT0
SCK0
SIN1, SIN2
SOT1, SOT 2
SCK1, SCK2
AV
CC
AVR H
AV
SS
ADTG
AN0
to
AN7
PWC0
PWC1
PWC2
Clock control
8
Circuit
RAM
ROM
µDMAC
Communication
prescaler
UART
Extended I/O serial
interface × 2 channels
A/D converter
( 10-bit )
PWC ×3 channels
F2MC16LX series core
2
CPU
Interrupt controller
8/16-bit PPG
8/16-bit
up/down
counter/timer
µPG
MC-16LX Bus
2
F
Chip select
PPG0, PPG1
PPG2, PPG3
PPG4, PPG5
AIN0, AIN1
BIN0, BIN1
ZIN0, ZIN1
EXTC
MT00
MT01
CS0, CS1,
CS2, CS3
Input/output timer
16-bit input capture ×
2 channels
16-bit output compare
×
6 channels
16-bit free-run timer
16-bit reload timer
2
I
C interface
External interrupt
IN0, IN1
OUT0, OUT1,
OUT2, OUT3,
OUT4, OUT5
TIN0
TOT0
SCL
SDA
8
IRQ0
to
IRQ7
18
I/O port
888888888
P00
P10
P20
P30
P40
P50
P60
tototototototototototo
P07
P17
P27
P37
P47
P57
P67
P70
P77
P80
P87
8
P90
P97
4
PA 0
PA 3
: Only MB90485 series
P00 to P07 (8 pins) : with an input pull-up resistance setting register.
P10 to P17 (8 pins) : with an input pull-up resistance setting register.
P40 to P47 (8 pins) : with an open drain setting register.
P70 to P77 (8 pins) : with an open drain setting register.
MB90485 series only
2
• I
C pin P77 and P76 are N-ch open drain pin (without P-ch) . However, MB90V485B uses
the N-ch open drain pin (with P-ch) .
• P20 to P27, P30 to P37, P40 to P47 and P70 to P77 are also used as 3 V/5 V I/F pin.
• As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/
2
µPG/I
C become CMOS input.
Note : In the above diagram, I/O ports share internal function blocks and pins. However, when a
set of pins is used with an internal module, it cannot also be used as an I/O port.
004000H or 008000H,
selected by the MS bit in
the ROMM register
MB90V480 (FC0000H) 004000H
MB90V485B (FC0000H) 004000H
MB90483CFB0000H*
MB90F489BF90000H *
*1 : No memory cells from FC0000
4
2
H to FC7FFFH and FE0000H to FE7FFFH.
0080000H fixed006100H*
004000H
3
The upper part of the 00 bank is set up to mirror the image of FF bank ROM, to enable efficient use of small
model C compilers. Because the lower 16-bit address of the FF bank and the lower 16-bit address of the 00
bank are the same, enabling reference to tables in ROM without using the for specification in the pointer
declaration.
For example, in accessing address 00C000
H it is actually the contents of ROM at FFC000H that are accessed.
If the MS bit in the ROMM register is set to “0”, the ROM area in the FF bank will exceed 48 Kbytes and it is
not possible to reflect the entire area in the image in the 00 bank. Therefore the image from FF4000H to FFFFFFH
is reflected in the 00 bank and the area from FF0000
H to FF3FFFH can be seen in the FF bank only.
(Continued)
19
MB90480/485 Series
(Continued)
*2 : In MB90F489B, there is no access to F8 bank and FC bank on the single-chip mode or the internal-ROM
external-bus mode.
*3 : Because installed-RAM area is larger than MB90V485B, MB90F489B should execute emulation in an area
that is larger than 004000
*4 : In MB90483C, there is no access to F8 bank to FA bank and FC bank on the single-chip mode or the internal-
ROM external-bus mode.
H by the emulation memory area setting on the tool side.
20
• MB90F489B
MB90480/485 Series
FFFFFF
FF0000
FEFFFF
FE0000
FDFFFF
FD0000
FCFFFF
FC0000
FBFFFF
FB0000
FAFFFF
FA0000
F9FFFF
F90000
F8FFFF
F80000
F7FFFF
Single chip
H
ROM (FF bank)
H
H
ROM (FE bank)
H
H
ROM (FD bank)
H
H
H
H
ROM (FB bank)
H
H
ROM (FA bank)
H
H
ROM (F9 bank)
H
H
H
H
Internal ROM
external bus
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
External ROM
external bus
010000
00FFFF
008000
007FFF
006100
0060FF
000100
0000FF
0000D0
0000CF
000000
H
H
ROM area
FF bank image
H
H
H
H
H
H
H
H
PeripheralPeripheralPeripheral
H
: Internal : External : Access inhibited
Register
ROM area
FF bank image
RAMRAM
Register
RAM
Register
21
MB90480/485 Series
• MB90483C
FFFFFF
FF0000
FEFFFF
FE0000
FDFFFF
FD0000
FCFFFF
FC0000
FBFFFF
FB0000
FAFFFF
FA0000
F9FFFF
F90000
F8FFFF
F80000
F7FFFF
Single chip
H
ROM (FF bank)
H
H
ROM (FE bank)
H
H
ROM (FD bank)
H
H
H
H
ROM (FB bank)
H
H
H
H
H
H
H
H
Internal ROM
external bus
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FB bank)
External ROM
external bus
010000
00FFFF
004000
or
008000
004000
003FFF
000100
0000FF
0000D0
0000CF
000000
H
H
H
H
H
H
H
H
H
H
H
ROM area
FF bank image
Peripheral
ROM area
FF bank image
RAMRAM
RegisterRegister
Peripheral
RAM
Peripheral
Register
: Internal : External : Access inhibited
22
■ F2MC-16L CPU PROGRAMMING MODEL
•Dedicated registers
MB90480/485 Series
AHAL
•General purpose registers
32-bit
USP
SSP
PS
PC
16-bit
DPR
PCB
DTB
USB
SSB
ADB
8-bit
Accumulator
User stack pointer
System stack pointer
Processor status
Program counter
Direct page register
Program bank register
Data bank register
User stack bank register
System stack bank register
Additional data bank register
•Processor status
PSRPCCR
000180
H+ RP × 10H
1513
ILM
MSBLSB
128 70
16-bit
RW0
RW1
RW2
RW3
R1R0
R3R2
R5
R7R6
R4
RL0
RL1
RW4
RL2
RW5
RW6
RL3
RW7
23
MB90480/485 Series
■ I/O MAP
AddressRegister name
00
HPort 0 data registerPDR0R/WPort 0XXXXXXXXB
Abbreviated
register name
Read/
Write
Resource nameInitial value
01HPort 1 data registerPDR1R/WPort 1XXXXXXXXB
02HPort 2 data registerPDR2R/WPort 2XXXXXXXXB
03HPort 3 data registerPDR3R/WPort 3XXXXXXXXB
04HPort 4 data registerPDR4R/WPort 4XXXXXXXXB
05HPort 5 data registerPDR5R/WPort 5XXXXXXXXB
06HPort 6 data registerPDR6R/WPort 6XXXXXXXXB
XXXXXXXX
07HPort 7 data registerPDR7R/WPort 7
(MB90480 series)
11XXXXXX
(MB90485 series)
HPort 8 data registerPDR8R/WPort 8XXXXXXXXB
08
09HPort 9 data registerPDR9R/WPort 9XXXXXXXXB
0AHPort A data registerPDRAR/WPort A----XXXXB
10HPort 0 direction registerDDR0R/WPort 000000000B
11HPort 1 direction registerDDR1R/WPort 100000000B
12HPort 2 direction registerDDR2R/WPort 200000000B
13HPort 3 direction registerDDR3R/WPort 300000000B
14HPort 4 direction registerDDR4R/WPort 400000000B
15HPort 5 direction registerDDR5R/WPort 500000000B
16HPort 6 direction registerDDR6R/WPort 600000000B
00000000
17HPort 7 direction registerDDR7R/WPort 7
(MB90480 series)
XX000000
(MB90485 series)
HPort 8 direction registerDDR8R/WPort 800000000B
18
19HPort 9 direction registerDDR9R/WPort 900000000B
1AHPort A direction registerDDRAR/WPort A----0000B
21HSerial control registerSCRW, R/W00000100B
22HSerial input/output registerSIDR/SODRR/WXXXXXXXXB
Read/
Write
Resource nameInitial value
00000X00B
UART
23HSerial status registerSSRR, R/W00001000B
24H (Reserved area)
25
26H
27H00000010B
register
Serial mode control status register 0SMCS0R/W
Communication prescaler control
H
CDCRR/W
Communication
prescaler (UART)
SIO1 (ch.0)
00--0000B
----0000
28HSerial data register 0SDR0R/WXXXXXXXXB
29H
2AH
2BH00000010B
Communication prescaler control
register 0
Serial mode control status register 1SMCS1R/W
SDCR0R/W
Communication
prescaler
SIO1 (ch.0)
SIO2 (ch.1)
0---0000B
----0000
2CHSerial data register 1SDR1R/WXXXXXXXXB
Communication
prescaler
SIO2 (ch.1)
0---0000B
XXXXXXXXB
2DH
Communication prescaler control
register 1
SDCR1R/W
2EHReload register L (ch.0) PPLL0R/W
2FHReload register H (ch.0) PPLH0R/WXXXXXXXXB
30HReload register L (ch.1) PPLL1R/WXXXXXXXXB
31HReload resister H (ch.1) PPLH1R/WXXXXXXXXB
32HReload register L (ch.2) PPLL2R/WXXXXXXXXB
33HReload register H (ch.2) PPLH2R/WXXXXXXXXB
34HReload register L (ch.3) PPLL3R/WXXXXXXXXB
35HReload register H (ch.3) PPLH3R/WXXXXXXXXB
36HReload register L (ch.4) PPLL4R/WXXXXXXXXB
37HReload register H (ch.4) PPLH4R/WXXXXXXXXB
8/16-bit PPG
(ch.0 to ch.5)
38HReload register L (ch.5) PPLL5R/WXXXXXXXXB
39HReload register H (ch.5) PPLH5R/WXXXXXXXXB
3AHPPG0 operating mode control registerPPGC0R/W0X000XX1B
3BHPPG1 operating mode control registerPPGC1R/W0X000001B
3CHPPG2 operating mode control registerPPGC2R/W0X000XX1B
3DHPPG3 operating mode control registerPPGC3R/W0X000001B
3EHPPG4 operating mode control registerPPGC4R/W0X000XX1B
3FHPPG5 operating mode control registerPPGC5R/W0X000001B
40HPPG0, PPG1 output control registerPPG01R/W8/16-bit PPG00000000B
41H (Reserved area)
HPPG2, PPG3 output control registerPPG23R/W8/16-bit PPG00000000B
42
43H (Reserved area)
B
B
(Continued)
25
MB90480/485 Series
AddressRegister name
44
H
PPG4, PPG5 output control registerPPG45R/W8/16-bit PPG00000000B
56HOutput control register (ch.0) OCS0R/W0000--00B
57HOutput control register (ch.1) OCS1R/W---00000B
58HOutput control register (ch.2) OCS2R/W0000--00B
59HOutput control register (ch.3) OCS3R/W---00000B
5AHOutput control register (ch.4) OCS4R/W0000--00B
5BHOutput control register (ch.5) OCS5R/W---00000B
5CH
5DH
5EH
5FH
Input capture data register (ch.0) lower
digits
Input capture data register (ch.0) upper
digits
Input capture data register (ch.1) lower
digits
Input capture data register (ch.1) upper
digits
IPCP0
IPCP1
R
RXXXXXXXXB
16-bit
XXXXXXXX
input/output
RXXXXXXXX
timer input
capture
(ch.0, ch.1)
RXXXXXXXXB
60HInput capture control status registerICS01R/W00000000B
61H (Reserved area)
B
B
B
B
B
26
(Continued)
MB90480/485 Series
Abbreviated
AddressRegister name
HTimer counter data register lower digitsTCDTR/W
62
register
name
Read/
Write
Resource nameInitial value
00000000B
63HTimer counter data register upper digitsTCDTR/W00000000B
64HTimer control status registerTCCSR/W00000000B
65HTimer control status registerTCCSR/W0--00000B
66HCompare clear register lower digits
67HCompare clear register upper digitsXXXXXXXXB
XXXX0111B
B1HInterrupt control register 01ICR01W, R/WXXXX0111B
B2HInterrupt control register 02ICR02W, R/WXXXX0111B
B3HInterrupt control register 03ICR03W, R/WXXXX0111B
B4HInterrupt control register 04ICR04W, R/WXXXX0111B
Interrupt controller
B5HInterrupt control register 05ICR05W, R/WXXXX0111B
B6HInterrupt control register 06ICR06W, R/WXXXX0111B
B7HInterrupt control register 07ICR07W, R/WXXXX0111B
B8HInterrupt control register 08ICR08W, R/WXXXX0111B
B
B
B
28
(Continued)
MB90480/485 Series
(Continued)
Abbreviated
AddressRegister name
B9
HInterrupt control register 09ICR09W, R/W
register
name
BAHInterrupt control register 10ICR10W, R/WXXXX0111B
BBHInterrupt control register 11ICR11W, R/WXXXX0111B
BCHInterrupt control register 12ICR12W, R/WXXXX0111B
BDHInterrupt control register 13ICR13W, R/WXXXX0111B
BEHInterrupt control register 14ICR14W, R/WXXXX0111B
BFHInterrupt control register 15ICR15W, R/WXXXX0111B
C0HChip select area mask register 0CMR0R/W
C1HChip select area register 0CAR0R/W11111111B
C2HChip select area mask register 1CMR1R/W00001111B
C3HChip select area register 1CAR1R/W11111111B
C4HChip select area mask register 2CMR2R/W00001111B
C5HChip select area register 2CAR2R/W11111111B
C6HChip select area mask register 3CMR3R/W00001111B
C7HChip select area register 3CAR3R/W11111111B
C8HChip select control registerCSCRR/W----000*B
C9HChip select active level registerCALRR/W----0000B
CAH
CBH----0000B
CCH
CDH
Timer control status registerTMCSRR/W
16-bit timer register/
16-bit reload register
TMR/TMRLR
CEH (Reserved area)
CF
HPLL output control registerPLLOSW
D0H to FFH (External area)
100
H to #H (RAM area)
1FF0
1FF2
1FF3
1FF5
Program address detection register 0
H
(Low order address)
Program address detection register 0
(Middle order address)
Program address detection register 0
H
(High order address)
Program address detection register 1
H
(Low order address)
Program address detection register 1
(Middle order address)
Program address detection register 1
H
(High order address)
PADR0R/W
PADR1R/W
Read/
Write
Resource nameInitial value
XXXX0111B
Interrupt controller
00001111B
Chip select
function
00000000
16-bit reload timer
R/WXXXXXXXXB
Low-power
consumption
Address match
detection function
Address match
detection function
------X0B
XXXXXXXX
XXXXXXXX
B
B1FF1H
B1FF4H
* : These registers are only for MB90485 series.
They are used as the reserved area on MB90480 series.
(Continued)
29
MB90480/485 Series
(Continued)
Descriptions for read/write
R/W : Readable and writable
R : Read only
W : Write only
Descriptions for initial value
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
- : This bit is not used.
* : The initial value of this bit is “1” or “0”.
The value depends on the mode pin (MD2, MD1 and MD0) .
+ : The initial value of this bit is “1” or “0”.
The value depends on the RAM area of device.
30
MB90480/485 Series
■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
16-bit free run timer overflow,
16-bit reload timer underflow*
2
12#35FFFF70H
UART receiving completed7#36FFFF6CH
SIO1 (ch.0) 13#37FFFF68H
SIO2 (ch.1) 14#38FFFF64H
H⎯⎯
H⎯⎯
H⎯⎯
H
ICR000000B0H
ICR010000B1H
ICR020000B2H
ICR030000B3H
ICR040000B4H
ICR050000B5H
ICR060000B6H
H
ICR070000B7H
ICR080000B8H
ICR090000B9H
ICR100000BAH
ICR110000BBH
ICR120000BCH
ICR130000BDH
(Continued)
31
MB90480/485 Series
(Continued)
µDMAC
channel
number
Interrupt source
2
I
C interface
(MB90485 series only)
Clear of
2
EI
OS
×× #39FFFF60H
A/D conversion15#40FFFF5CH
Flash write/erase,
timebase timer, watch timer *
Delay interrupt generator
module
1
×× #41FFFF58H
×× #42FFFF54H
× : Interrupt request flag is not cleared by the interrupt clear signal.
: Interrupt request flag is cleared by the interrupt clear signal.
: Interrupt request flag is cleared by the interrupt clear signal (stop request present) .
*1 : The Flash write/erase, timebase timer, and watch timer cannot be used at the same time.
*2 : When the 16-bit reload timer underflow interrupt is changed from enable (TMCSR : INTE = 1) to disable
(TMCSR : INTE = 0) , disable the interrupt in the interrupt control register (ICR12 : IL2 to 0 : 111
the INTE bit to 0.
Interrupt vectorInterrupt control register
NumberAddressNumberAddress
ICR140000BEH
ICR150000BFH
B) , then set
Note : If there are two interrupt sources for the same interrupt number, the resource will clear both interrupt request
flags at the EI
2
OS/µDMAC interrupt clear signal. Therefore if either of the two sources uses the EI2OS/
µDMAC function, the other interrupt function cannot be used. The interrupt request enable bit for the corresponding resource should be set to “0” and interrupt requests from that resource should be handled by
software polling.
32
MB90480/485 Series
■ PERIPHERAL RESOURCES
1.I/O Ports
The I/O ports perform the functions of either sending data from the CPU to the I/O pins, or loading information
from the I/O into the CPU, according to the setting of the corresponding port data register (PDR) . The input/
output direction of each I/O pin can be set in individual bit units by the port direction register (DDR) for each I/
O port.
The MB90480/485 series has 84 input/output pins. The I/O ports are port 0 through port A.
(1) Port Data Registers
PDR0Initial value Access
Address : 000000
HUndefinedR/W*
7654 321 0
P06P07P05P04P03P02P01P00
1
PDR1
Address : 000001
PDR2
Address : 000002
PDR3
Address : 000003
PDR4
Address : 000004
PDR5
Address : 000005
PDR6
Address : 000006
PDR7
Address : 000007
PDR8
Address : 000008
7654 321 0
HUndefinedR/W*
HUndefinedR/W*
HUndefinedR/W*
HUndefinedR/W*
HUndefinedR/W*
HUndefinedR/W*
HUndefined*
HUndefinedR/W*
P16P17P15P14P13P12P11P10
7654 321 0
P26P27P25P24P23P22P21P20
7654 321 0
P36P37P35P34P33P32P31P30
7654 321 0
P46P47P45P44P43P42P41P40
7654 321 0
P56P57P55P54P53P52P51P50
7654 321 0
P66P67P65P64P63P62P61P60
7654 321 0
P76P77P75P74P73P72P71P70
7654 321 0
P86P87P85P84P83P82P81P80
2
R/W*
1
1
1
1
1
1
1
1
PDR9
Address : 000009
PDRA
Address : 00000A
HUndefinedR/W*
HUndefinedR/W*
7654 321 0
P96P97P95P94P93P92P91P90
7654 321 0
⎯⎯⎯⎯PA3PA2PA1PA0
1
1
*1 : The R/W indication for I/O ports is somewhat different than R/W access to memory, and involves the following
operations.
• Input mode
Read : Reads the corresponding signal pin level.
Write : Writes to the output latch.
• Output mode
Read : Reads the value from the data register latch.
Write : Outputs the value to the corresponding signal pin.
*2 : The initial value of this bit is “11XXXXXX
B” on MB90485 series.
33
MB90480/485 Series
(2) Port Direction Registers
DDR0Initial value Access
Address : 000010
7654321 0
H00000000BR/W
D06D07D05D04D03D02D01D00
DDR1
Address : 000011
DDR2
Address : 000012
DDR3
Address : 000013
DDR4
Address : 000014
DDR5
Address : 000015
DDR6
Address : 000016
DDR7
Address : 000017
DDR8
Address : 000018
76543210
H00000000BR/W
H00000000BR/W
H00000000BR/W
H00000000BR/W
H00000000BR/W
H00000000BR/W
H00000000B*
D77*
H00000000BR/W
D16D17D15D14D13D12D11D10
76543210
D26D27D25D24D23D22D21D20
76543210
D36D37D35D34D33D32D31D30
76543210
D46D47D45D44D43D42D41D40
76543210
D56D57D55D54D53D52D51D50
76543210
D66D67D65D64D63D62D61D60
76543210
1
76543210
1
D76*
D86D87D85D84D83D82D81D80
D75D74D73D72D71D70
2
R/W
DDR9
Address : 000019
DDRA
Address : 00001A
76543210
H00000000BR/W
H----0000BR/W
D96D97D95D94D93D92D91D90
76543210
⎯⎯⎯⎯DA3DA2DA1DA0
*1 : The value is set to “⎯” on MB90485 series only.
*2 : The initial value of this bit is “XX000000
B” on MB90485 series only.
• When a set of pins is functioning as a port, the corresponding signal pins are controlled as follows.
0 : Input mode.
1 : Output mode. Reset to “0”.
Notes : • When any of these registers are accessed using a read-modify-write type instruction (such as a bit set
instruction) , the bit specified in the instruction will be set to the indicated value. However, the contents
of output registers corresponding to any other bits having input settings will be rewritten to the input values
of those pins at that time.
For this reason, when changing any pin that has been used for input to output, first write the desired value
to the PDR register before setting the DDR register for output.
• P76, P77 (MB90485 series only)
This port has no DDR. To use P77 and P76 as I
enabled (to use P77 and P76 for general purposes, disable I
2
C pins, set the PDR value to “1” so that port data remains
2
C) . The port is an open drain output (with
no P-ch) .
To use it as an input port, therefore, set the PDR to “1” to turn off the output transistor and add a pull-up
resistor to the external output.
34
MB90480/485 Series
(3) Port Input Resistance Registers
RDR0Initial value Access
Address : 00001C
76543210
H00000000BR/W
RD06RD07RD05RD04RD03RD02RD01RD00
RDR1
Address : 00001D
76543210
H00000000BR/W
RD16RD17RD15RD14RD13RD12RD11RD10
These registers control the use of pull-up resistance in input mode.
0 : No pull-up resistance in input mode.
1 : With pull-up resistance in input mode.
In output mode, these registers have no function (no pull-up resistance) . Input/output mode settings are
controlled by the setting of port direction (DDR) registers.
In case of a stop (SPL = 1) , no pull-up resistance is applied (high impedance) . Using of this function is prohibited
when an external bus is used. Do not write to these registers.
(4) Port Output Pin Registers
ODR7Initial valueAccess
Address : 00001E
ODR4
Address : 00001B
76543210
H00000000B*
H00000000BR/W
1
OD77*
76543210
1
OD76*
OD46OD47OD45OD44OD43OD42OD41OD40
OD75OD74OD73OD72OD71OD70
2
R/W
*1 : The value is set to “⎯” on MB90485 series only.
*2 : The initial value of this bit is “XX000000
B” on MB90485 series only.
These registers control open drain settings in output mode.
0 : Standard output port functions in output mode.
1 : Open drain output port in output mode.
In input mode, these registers have no function (Hi-Z output) . Input/output mode settings are controlled by the
setting of port direction (DDR) registers. Using of this function is prohibited when an external bus is used. Do
not write to these registers.
(5) Analog Input Enable Register
ADERInitial value Access
Address : 00001F
76543210
H11111111BR/W
ADE6ADE7ADE5ADE4ADE3ADE2ADE1ADE0
This register controls the port 6 pins as follows.
0 : Port input/output mode.
1 : Analog input mode. The default value at reset is all “1”.
(6) Up/down Timer Input Enable Register
UDERInitial value Access
Address : 00000B
76543210
HXX000000BR/W
⎯⎯UDE5UDE4UDE3UDE2UDE1UDE0
This register controls the port 3 pins as follows.
0 : Port input mode.
1 : Up/down timer input mode.The default value at reset is “0”.
35
MB90480/485 Series
2.UART
The UART is a serial I/O port for asynchronous (start-stop synchronized) communication as well as CLK
synchronized communication.
• Full duplex double buffer
• Transfer modes : asynchronous (start-stop synchronized) , or CLK synchronized (no start bit or stop bit) .
The expanded I/O serial interface is an 8-bit × 1-channel serial I/O interface for clock synchronized data
transfer. A selection of LSB-first or MSB-first data transfer is provided.
There are two serial I/O operation modes.
• Internal shift clock mode : Data transfer is synchronized with the internal clock signal.
• External shift clock mode : Data transfer is synchronized with a clock signal input from the external clock
signal pin (SCK) . In this mode the general-purpose port that shares the external
clock signal pin (SCK) can be used for transfer according to CPU instructions.
(1) Register List
Serial mode control status register 0/1 (SMCS0, SMCS1)
Initial value
00000010B
Address : 000027
00002BH
H
15141312111098
SMD1SMD2SMD0SIESIRBUSYSTOPSTRT
R/WR/WR/WR/WR/WRR/WR/W
Address : 000026H
00002AH
7654
⎯⎯⎯⎯MODEBDSSOESCOE
⎯⎯⎯⎯
321 0
R/WR/WR/WR/W
Serial data register 0/1 (SDR0, SDR1)
Address : 000028H
00002CH
76543210
D6D7D5D4D3D2D1D0
R/WR/WR/WR/WR/WR/WR/WR/W
Communication prescaler control register 0/1 (SDCR0, SDCR1)
Address : 000029H
00002DH
15141312111098
MD⎯⎯DIV3DIV2DIV1DIV0
R/W
⎯
⎯⎯⎯R/WR/WR/WR/W
----0000B
XXXXXXXXB
0---0000B
39
MB90480/485 Series
(2) Block Diagram
Internal data bus
(MSB first) D0 to D7D7 to D0 (LSB first)
Transfer direction selection
SIN1, SIN2
SDR (Serial Data Register)
SOT1, SOT2
SCK1, SCK2
Control circuit
Internal clock
21 0
SMD2 SMD1 SMD0 SIESIR BUSY STOP STRT MODE BDS
Interrupt
request
Internal data bus
Initial value
Read
Write
Shift clock
counter
SOE SCOE
40
MB90480/485 Series
4.8/10-bit A/D Converter
The A/D converter converts analog input voltage to digital values, and provides the following features.
• Conversion time : minimum 3.68 µs per channel
(92 machine cycles at 25 MHz machine clock, including sampling time)
• Sampling time : minimum 1.92 µs per channel
(48 machine cycles at 25 MHz machine clock)
• RC sequential comparison conversion method, with sample & hold circuit.
• 8-bit or 10-bit resolution
• Analog input selection of 8 channels
Single conversion mode : Conversion from one selected channel.
Scan conversion mode : Conversion from multiple consecutive channels, programmable selection of up to
8 channels.
Continuous conversion mode : Repeated conversion of specified channels.
Stop conversion mode : Conversion from one channel followed by a pause until the next activation allows to
synchronize with conversion start.
• At the end of A/D conversion, an A/D conversion completed interrupt request can be generated to the CPU.
The interrupt can be used activate the µDMAC in order to transfer the results of A/D conversion to memory
for efficient continuous processing.
• The starting factor conversion may be selected from software, external trigger (falling edge) , or timer (rising
edge) .
(1) Register List
ADCS2, ADCS1 (Control status register)
ADCS1
Address : 000046
ADCS2
Address : 000047
76543210
H
MD1ANS2ANS1ANS0ANE2ANE1ANE0
0
R/W
15141312111098
H
BUSYINTEPAUSSTS1STS0STRT
0
R/W
ADCR2, ADCR1 (Data register)
ADCR1
Address : 000048
ADCR2
Address : 000049
76543210
H
D7D5D4D3D2D1D0
X
R
15141312111098
H
S10ST0CT1CT0⎯D9D8
0
W
MD0
0
R/W0R/W0R/W0R/W0R/W0R/W0R/W
W
0
X
R
X
R
Reserved
0
R/W
X
R
X
R
INT
0
R/W0R/W0R/W0R/W0R/W
D6
X
R
ST1
0
W
X
R
0
W
X
R
0
W
X
R
0
W
X
R
X
R
←Initial value
←Bit attributes
←Initial value
←Bit attributes
←Initial value
←Bit attributes
←Initial value
←Bit attributes
41
MB90480/485 Series
(2) Block Diagram
MP
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Input
circuit
Sample & hold
circuit
Comparator
AV
CC
AVRH
AVSS
D/A converter
Sequential
comparison register
Data bus
ADTG
Trigger activation
Timer
(PPG1 output)
Timer activation
φ
Data registers
ADCR1, ADCR2
Decoder
A/D control register 1
A/D control register 2
ADCS1, ADCS2
Operation clock
Prescaler
42
MB90480/485 Series
5.8/16-bit PPG
The 8/16-bit PPG is an 8-bit reload timer module that produces a PPG output using a pulse from the timer
operation. Hardware resources include 6 × 8-bit down counters, 12 × 8-bit reload timers, 3 × 16-bit control
registers, 6 × external pulse output pins, and 6 × interrupt outputs. Note that MB90480/485 series has six channels
for 8-bit PPG use, which can also be combined as PPG0 + PPG1, PPG2 + PPG3, and PPG4 + PPG5 to operate
as a three-channel 16-bit PPG. The following is a summary of functions.
• 8-bit PPG output 6-channel independent mode : Provides PPG output operation on six independent channels.
• 16-bit PPG output operation mode : Provides 16-bit PPG output on three channels. The six original channels
are used in combination as PPG0 + PPG1, PPG2 + PPG3, and PPG4 + PPG5.
•8 + 8-bit PPG output operation mode : Output from PPG0 (PPG2/PPG4) is used as clock input to PPG1 (PPG3/
PPG5) to provide to 8-bit PPG output at any desired period length.
• PPG output operation : Produces pulse waves at any desired period and duty ratio. The PPG module can also
be used with external circuits as a D/A converter.
(1) Register List
PPGC0/PPGC2/PPGC4 (PPG0/PPG2/PPG4 operation mode control register)
00003A
00003CH
00003EH
H
76543210
⎯
X
Reserved
⎯
1
PEN0PE00PIE0PUF0⎯⎯
R/W
0
⎯
⎯
R/W0R/W0R/W
X
0
⎯
X
Read/write
Initial value
PPGC1/PPGC3/PPGC5 (PPG1/PPG3/PPG5 operation mode control register)
00003B
00003DH
00003FH
H
15141312111098
PEN1PE10PIE1PUF1MD1MD0
R/W
0
⎯
⎯
R/W0R/W0R/W0R/W0R/W
X
0
Reserved
⎯
1
PPG01/PPG23/PPG45 (PPG0 to PPG5 output control register)
8/16-bit up/down counter/timer consists of up/down counter/timer circuits including six event input pins, two
8-bit up/down counters, two 8-bit reload/compare registers, as well as the related control circuits.
(1) Principal Functions
• 8-bit count register enables counting in the range 0 to 256.
(In 16-bit × 1 mode, counting is enabled in the range 0 to 65535)
• Count clock selection provides four count modes.
Count modesTimer mode
Up/down count mode
Phase differential down count mode ( × 2)
Phase differential down count mode ( × 8)
• In timer mode, there is a choice of two internal count clock signals.
• In up/down count mode, there is a choice of trigger edge detection for the input signal from external pins.
Edge detectionFalling edge detection
Rising edge detection
Both rising/falling edge detection
Edge detection disabled
• In phase differential count mode, to handle encoder counting for motors, the encoder A-phase, B-phase, and
Z-phase are each input, enabling easy and highly accurate counting of angle of rotation, speed of rotation, etc.
• The ZIN pin provides a selection of two functions.
ZIN pinCounter clear function
Gate functions
• A compare function and reload function are provided, each for use separately or in combination. Both functions
can be activated together for up/down counting in any desired bandwidth.
Compare/reload functionCompare function (output interrupt at compare events)
Compare function (output interrupt and clear counter at compare
events)
Reload function (output interrupt and reload at underflow events)
Compare/reload function
(output interrupt and clear counter at compare events, output interrupt
and reload at underflow events)
Compare/reload disabled
• Individual control over interrupts at compare, reload (underflow) and overflow events.
• Count direction flag enables identification of the last previous count direction.
• Interrupt generated when count direction changes.
46
(2) Register List
MB90480/485 Series
150
RCR1
Reserved area
CCRH0
Reserved area
CCRH1
8-bit
87
UDCR0UDCR1
RCR0
CSR0
CCRL0
CSR1
CCRL1
8-bit
CCRH0 (Counter Control Register High ch.0)
15141312111098
Address : 00006D
H00000000B
R/WR/WR/WR/WR/WR/WR/WR/W
CDCFM16ECFIECLKSCMS1CMS0CES1CES0
CCRH1 (Counter Control Register High ch.1)
15141312111098
Address : 000071H-0000000B
CDCF⎯CFIECLKSCMS1CMS0CES1CES0
R/WR/WR/WR/WR/WR/WR/W
CCRL0/1 (Counter Control Register Low ch.0/ch.1)
Address
Address
: 00006CH
: 000070H
76543210
CTUTUDMSUCRERLDEUDCC CGSCCGE1CGE0
R/WWR/WR/WWR/WR/WR/W
CSR0/1 (Counter Status Register ch.0/ch.1)
Address
Address
: 000072H
: 000074H
76543210
CITECSTRUDIECMPFOVFFUDFFUDF1UDF0
R/WR/WR/WR/WR/WR/WRR
UDCR0/1 (Up Down Count Register ch.0/ch.1)
15141312111098
Address : 000069
H00000000B
D16D17D15D14D13D12D11D10
RRRRRRRR
Initial value
Initial value
Initial value
0X00X000
Initial value
00000000
Initial value
B
B
76543210
Address : 000068
H00000000B
D06D07D05D04D03D02D01D00
RRRRRRRR
RCR0/1 (Reload/Compare Register ch.0/ch.1)
15141312111098
Address : 00006BH00000000B
WWWWWWWW
Address : 00006AH00000000B
WWWWWWWW
D16D17D15D14D13D12D11D10
76543210
D06D07D05D04D03D02D01D00
Initial value
Initial value
Initial value
47
MB90480/485 Series
(3) Block Diagram
CGE1 CGE0 CGSC
Data bus
8-bit
RCR0 (Reload/ compare register 0)
ZIN0
AIN0
BIN0
Edge/level detection
UDCC
CES1CES0
CMS1CMS0
UDMS
Up/down
count
clock selection
Prescaler
CLKS
CTUT
UCRE
Reload control
RLDE
Counter clear
8-bit
UDCR0 (Up/down count register 0)
Count
clock
UDF1 UDF0 CDCF CFIE
Interrupt
CSTR
output
UDFF OVFF
CITEUDIE
Carry
CMPF
48
MB90480/485 Series
7.DTP/External Interrupt
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16LX
CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the
requests to the F
MC-16LX CPU to activate the extended intelligent µDMAC or interrupt processing.
76543210
H00000000B
R/WR/WR/WR/WR/WR/WR/WR/W
15141312111098
HXXXXXXXXB
R/WR/WR/WR/WR/WR/WR/WR/W
H00000000B
R/WR/WR/WR/WR/WR/WR/WR/W
EN6EN7EN5EN4EN3EN2EN1EN0
ER6ER7ER5ER4ER3ER2ER1ER0
76543210
LA3LB3LB2LA2LB1LA1LB0LA0
Initial value
Address : 00000F
(2) Block Diagram
F2MC-16 bus
15141312111098
H00000000B
R/WR/WR/WR/WR/WR/WR/WR/W
4
4
4
8
Interrupt/DTP enable register
Gate
Interrupt/DTP source register
Interrupt level setting register
LA7LB7LB6LA6LB5LA5LB4LA4
Source F/F
Edge detection
circuit
4
Initial value
Request input
49
MB90480/485 Series
8.16-bit Input/Output Timer
The 16-bit input/output timer module is composed of one 16-bit free run timer, six output compare and two input
capture modules. These functions can be used to output six independent waveforms based on the 16-bit free
run timer, enabling input pulse width measurement and external clock frequency measurement.
• Register List
• 16-bit free run timer
150
000066/67H
CPCLR
Compare-clear register
000062/63H
000064/65H
• 16-bit output compare
00004A, 4C, 4E, 50, 52, 54H
00004B, 4D, 4F, 51, 53, 55H
000056, 58, 5AH
000057, 59, 5BH
• 16-bit input capture
00005C, 5EH
00005D, 5FH
000060H
TCDT
TCCS
150
OCCP0 to OCCP5
OCS0/2/4OCS1/3/5
150
IPCP0, IPCP1
ICS01
Timer counter data register
Control status register
Output compare register
Output compare
control registers
Input capture data register
Input capture control
status register
50
•Block Diagram
MB90480/485 Series
Control logic
16-bit free run timer
Output
compare 0
Output
Bus
compare 1
Output
compare 2
Output
compare 3
Output
compare 4
Output
compare 5
Interrupt
16-bit timer
Compare register 0
Compare register 1
Compare register 2
Compare register 3
Compare register 4
Compare register 5
Clear
To
each
block
TQ
TQ
TQ
TQ
TQ
TQ
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
Input
capture 0
Input
capture 1
Capture data register 0
Capture data register 1
Edge
selection
Edge
selection
IN0
IN1
51
MB90480/485 Series
(1) 16-bit Free Run Timer
The 16-bit free run timer is composed of a 16-bit up-down counter and control status register.
The counter value of this timer is used as the base timer for the input capture and output compare.
• The counter operation provides a choice of eight clock types.
• A counter overflow interrupt can be produced.
• A mode setting is available to initialize the counter value whenever the output compare value matches the
value in the compare clear register.
• Register List
Compare clear register (CPCLR)
Initial value
000067
15141312111098
HXXXXXXXXB
R/WR/WR/WR/WR/WR/WR/WR/W
CL14CL15CL13CL12CL11CL10CL09CL08
76543210
000066HXXXXXXXXB
R/WR/WR/WR/WR/WR/WR/WR/W
CL06CL07CL05CL04CL03CL02CL01CL00
Timer counter data register (TCDT)
15141312111098
000063H00000000B
R/WR/WR/WR/WR/WR/WR/WR/W
000062
H00000000B
R/WR/WR/WR/WR/WR/WR/WR/W
T14T15T13T12T11T10T09T08
76543210
Timer control status register (TCCS)
15141312111098
000065
000064
H0--00000B
R/WR/WR/WR/WR/WR/WR/WR/W
76543210
H00000000B
R/WR/WR/WR/WR/WR/WR/WR/W
Initial value
Initial value
Initial value
T06T07T05T04T03T02T01T00
Initial value
⎯ECKE⎯MSI2MSI1MSI0ICLRICRE
Initial value
IVFEIVFSTOPMODESCLRCLK2CLK1CLK0
52
•Block Diagram
MB90480/485 Series
Bus
Interrupt
request
IVFIVFE STOP MODE SCLRCLK1 CLK0
CLK2
16-bit free run timer
Count value output T15 to T00
16-bit compare clear register
Compare circuit
MSI2 to MSI0
ICLR
ICRE
φ
Prescaler
Clock
Interrupt request
A/D activation
53
MB90480/485 Series
(2) Output Compare
The output compare module is composed of a 16-bit compare register, compare output pin unit, and control
register. When the value in the compare register in this module matches the 16-bit free run timer, the pin output
levels can be inverted and an interrupt generated.
• There are six compare registers in all, each operating independently. A setting is available to allow two compare
registers to be used to control output.
• Interrupts can be set in terms of compare match events.
• Register List
Output compare registers (OCCP0 to OCCP5)
Initial value
00000000B
00004B
00004DH
00004FH
000051H
000053H
000055H
15141312111098
H
R/WR/WR/WR/WR/WR/WR/WR/W
C14C15C13C12C11C10C09C08
7654321
00004A
00004CH
00004EH
H
R/WR/WR/WR/WR/WR/WR/WR/W
C06C07C05C04C03C02C01C00
000050H
000052H
000054H
Output control registers (OCS1/OCS3/OCS5)
15141312111098
000057H
000059H
00005BH
⎯⎯⎯R/WR/WR/WR/WR/W
⎯⎯⎯CMODOTE1OTE0OTD1OTD0
Output control registers (OCS0/OCS2/OCS4)
76543210
000056
000058H
00005AH
H
R/WR/WR/WR/W⎯⎯R/WR/W
ICP0ICPICICE1ICE0⎯⎯CST1CST0
0
Initial value
00000000B
Initial value
---00000B
Initial values
0000--00B
54
•Block Diagram
16-bit timer counter value (T15 to T00)
MB90480/485 Series
Compare control
Compare register 0 (2, 4)
16-bit timer counter value (T15 to T00)
Bus
Compare control
Compare register 1 (3, 5)
ICP1 ICP0 ICE0 ICE0
Control unit
Individual
control blocks
TQ
CMOD
TQ
OTE0
OTE1
OUT0 (2) (4)
OUT1 (3) (5)
Compare 1 (3) (5) interrupt
Compare 0 (2) (4) interrupt
55
MB90480/485 Series
(3) Input Capture
The input capture module performs the functions of detecting the rising edge, falling edge, or both edges of
signal input from external circuits, and saving the 16-bit free run timer value at that moment to a register. An
interrupt can also be generated at the instant of edge detection.
The input capture module consists of input capture registers and a control register. Each input capture module
has its own external input pin.
• Selection of three types of valid edge for external input signals.
Rising edge, falling edge, both edges.
• An interrupt can be generated when a valid edge is detected in the external input signal.
• Register List
Input capture data register (IPCP0, IPCP1)
Initial value
XXXXXXXXB
00005D
00005FH
15141312111098
H
CP14CP15CP13CP12CP11CP10CP09CP08
RRRRRRRR
76543210
00005C
00005EH
H
CP06CP07CP05CP04CP03CP02CP01CP00
RRRRRRRR
Input capture control status register (ICS01)
76543210
000060
H00000000B
R/WR/WR/WR/WR/WR/WR/WR/W
ICP0ICP1ICE1ICE0EG11EG10EG01EG00
•Block Diagram
Capture data register 0
Bus
16-bit timer counter value (T15 to T00)
Edge detection
EG11 EG10 EG01 EG00
Initial value
XXXXXXXXB
Initial value
IN0
56
Capture data register 1
ICP1 ICP0 ICE1 ICE0
Edge detection
IN1
Interrupt
Interrupt
MB90480/485 Series
9.I2C Interface (MB90485 series only)
The I2C interface is a serial I/O port supporting the Inter IC BUS. Serves as a master/slave device on the I2C bus.
2
The I
C interface has the following functions.
• Master/slave transmit/receive
• Arbitration function
• Clock synchronization
• Slave address/general call address detection function
• Forwarding direction detection function
• Start condition repeated generation and detection
• Bus error detection function
(1) Register List
Bus Status Register (IBSR)
Initial value
Initial value
000088
H00000000B
Bus control register (IBCR)
000089
H00000000B
BER BEIE SCC MSS ACK GCAA INTE INT
R/WR/W R/WR/W R/WR/WR/WR/W
765 43210
BBRSC ALLRB TRX AAS GCA FBT
RRR RRRRR
15141312111098
Clock control register (ICCR)
00008A
H--0XXXXXB
Address register (IADR)
00008B
H-XXXXXXXB
15141312111098
Data register (IDAR)
00008C
HXXXXXXXXB
765 43210
ENCS4 CS3 CS2 CS1 CS0
R/WR/W R/WR/WR/WR/W
A6A5A4A3A2A1A0
R/W R/WR/W R/WR/WR/WR/W
765 43210
D7D6D5D4D3D2D1D0
R/WR/W R/WR/W R/WR/WR/WR/W
Initial value
Initial value
Initial value
57
MB90480/485 Series
(2) Block Diagram
ICCR
2
C enable
EN
ICCR
I
Clock dividing 1
56 78
Peripheral clock
CS4
CS3
MC-16LX Bus
2
F
CS2
CS1
CS0
IBSR
BB
RSC
LRB
TRX
FBT
AL
IBCR
BER
BEIE
INTE
Busbusy
Repeat start
Last Bit
Clock selection 1
Clock dividing 2
248 16 3264128 256
Clock selection 2
Start/stop condition detection
Tr ansmission/
Reception
First Byte
Arbitration lost detection
Interrupt request
Sync
Change timing
of shift clock edge
Error
IRQ
Shift clock generation
SCL
SDA
58
INT
IBCR
SCC
MSS
ACK
GCAA
IBSR
AAS
GCA
Start
Master
ACK enable
GC-ACK enable
Slave
Global call
End
Start/stop condition
detection
IDAR
Slave address
comparison
IADR
MB90480/485 Series
10. 16-bit Reload Timer
The 16-bit reload timer provides a choice of functions, including internal clock signals that count down in
synchronization with three types of internal clock, as well as an event count mode that counts down at specified
edge detection events in pulse signals input from external pins. This timer defines an underflow as a change in
count value from 0000
setting value + 1”. The choice of counting operations includes reload mode, in which the count setting values is
reloaded and counting continues following an underflow event, and one-shot mode, in which an underflow event
causes counting to stop. An interrupt can be generated at counter underflow, and the timer is DTC compatible.
(1) Register List
• TMCSR (Timer control status register)
Timer control status register (high) (TMCSR)
0000CB
Timer control status register (low) (TMCSR)
0000CA
H to FFFFH. Thus an underflow will occur when counting from the value “reload register
15141312111098
H
⎯⎯⎯CSL1CSL0MOD2MOD1
⎯
⎯
76543210
H
MOD0OUTLRELDINTEUFCNTETRG
R/W
0
⎯
⎯
⎯
OUTE
R/W0R/W0R/W0R/W0R/W0R/W0R/W
⎯
⎯
⎯
⎯
R/W0R/W0R/W0R/W
0
0
Read/Write
Initial value
Read/Write
Initial value
• 16-bit timer register/16-bit reload register
TMR/TMRLR (high)
15141312111098
0000CD
H
D15D13D12D11D10D09D08
R/W
D14
R/WXR/WXR/WXR/WXR/WXR/WXR/W
X
TMR/TMRLR (low)
76543210
0000CC
H
D07D05D04D03D02D01D00
R/W
D06
R/WXR/WXR/WXR/WXR/WXR/WXR/W
X
Read/Write
X
Initial value
Read/Write
X
Initial value
59
MB90480/485 Series
(2) Block Diagram
Internal data bus
TMRLR
16-bit reload register
TMR
16-bit timer register
(down counter)
CLK
Count clock generator circuit
Machine
clock φ
Pin
(TIN0)
Prescaler
Input control
circuit
3
Clear
External clock
UF
Gate
input
detection circuit
Reload signal
Valid clock
CLK
Clock
selector
Wait signal
Output signal
generation circuit
Inverted
Output signal
generation circuit
Reload
control
circuit
To A/D
converter
Pin
(TOT0)
EN
Function
selection
3
Select signal
2
Timer control status register (TMCSR)
RELDOUTL
Operation
control circuit
OUTE
60
11. µPG Timer (MB90485 series only)
The µPG timer performs pulse output in response to the external input.
(1) Register List
µPG control status register (PGCSR)
00008E
(2) Block Diagram
H00000---B
76543210
PEN0PE1PE0PMT1 PMT0
R/WR/WR/WR/WR/W
MB90480/485 Series
Initial value
MT00
MT00
Output latch
Control circuit
MT01
Output latch
MT01
Output enable
EXTC
61
MB90480/485 Series
12. PWC Timer (MB90485 series only)
The PWC timer is a 16-bit multifunction up-count timer capable of measuring the pulse width of the input signal.
A total of three channels are provided, each consisting of a 16-bit up-count timer, an input pulse divider & divide
ratio control register, a measurement input pin, and a 16-bit control register. These components provide the
following functions.
Timer function : • Capable of generating an interrupt request at fixed intervals specified.
• The internal clock used as the reference clock can be selected from
among three types.
Pulse width measurement function : • Measures the time between arbitrary events based on external pulse
inputs.
• The internal clock used as the reference clock can be selected from
among three types.
• Measurement modes
- “H” pulse width (↑ to ↓) /“L” pulse width (↑ to ↓)
- Rising cycle (↑ to ↑) /Falling cycle (↓ to ↓)
- Measurement between edges (↑ or ↓ to ↓ or ↑)
• The 8-bit input divider can be used for division measurement by dividing
the input pulse by 22 × n (n = 1, 2, 3, 4) .
• An interrupt can be generated upon completion of measurement.
• One-time measurement or fast measurement can be selected.
62
(1) Register list
PWC control/status register (PWCSR0 to PWCSR2)
000077
00007BH
00007FH
H
15141312111098
STRT STOPEDIR EDIEOVIROVIEERR
R/WR/WRR/WR/WR/WR
PWC control/status register (PWCSR0 to PWCSR2)
000076H
00007AH
00007EH
76543210
CKS1 CKS0PIS1PIS0S/CMOD2 MOD1 MOD0
R/WR/WR/WR/WR/WR/WR/WR/W
PWC data buffer register (PWCR0 to PWCR2)
000079H
00007DH
000081H
15141312111098
D15D14D13D12D11D10D9D8
R/WR/WR/WR/WR/WR/WR/WR/W
MB90480/485 Series
Initial value
Reserved
0000000X
Initial value
00000000
Initial value
00000000
B
B
B
PWC data buffer register (PWCR0 to PWCR2)
000078H
00007CH
000080H
76543210
D7D6D5D4D3D2D1D0
R/WR/WR/WR/WR/WR/WR/WR/W
Dividing ratio control register (DIVR0 to DIVR2)
000082H
76543210
000084H
000086H
DIV1DIV0
R/WR/W
Initial value
00000000B
Initial value
------00B
63
MB90480/485 Series
(2) Block Diagram
PWCR read
Error detection
ERR
MC-16 Bus
2
F
Flag set etc.
Reload
Data transfer
Overflow
16-bit up count timer
Control circuit
Start edge selection
Start of
measurement
edge
Completion of
measurement edge
Control bit output
Completion of
measurement interrupt request
Overflow interrupt request
Completion edge selection
Edge detection
PWCR
16
PIS0/PIS1
ERR
16
Dividing ON/OFF
CKS0/
CKS1
Clock
Timer clear
CKS1/CKS0
Count enable
8-bit divider
Internal clock (machine clock/4)
2
2
Clock divider
3
2
Divider clear
Input
waveform
comparator
PWC0
PWC1
64
15
PWCSR
2
Dividing ratio selection
DIVR
MB90480/485 Series
13. Watch Timer
The watch timer is a 15-bit timer using the sub clock. This circuit can generate interrupts at predetermined
intervals. Also a setting is available to enable it to be used as the clock source for the watchdog timer.
(1) Register List
Watch timer control register (WTC)
76543210
0000AA
(2) Block Diagram
Watch timer control register (WTC)
H
WDCSWTIEWTOFWTR WTC2 WTC1 WTC0
R/W
SCE
R
R/W0R/W0R/W
1
0
R/W0R/W0R/W
1
0
Read/write
Initial value
WDCSSCEWTIEWTOFWTRWTC2WTC1WTC0
Clear
8
2
9
Sub clock
Watch counter
2102132142
2
10
2
11
2
12
2
13
2
14
15
2
Interval
selector
Interrupt
generator
circuit
Watch timer
interrupt
To watchdog timer
65
MB90480/485 Series
14. Watchdog timer
The watchdog timer is a 2-bit counter that uses the output from the timebase timer or watch timer as a count
clock signal, and will reset the CPU if not cleared within a predetermined time interval after it is activated.
(1) Register List
Watchdog timer control register (WDTC)
76543210
0000A8
(2) Block Diagram
H
PONRWRSTERSTSRST WTEWT1 WT0
R
X
Reserved
⎯
X
R
X
R
X
R
X
W
1
W
1
W
1
Read/write
Initial value
Watch mode start
Timebase timer
mode start
Sleep mode start
Hold status start
The timebase timer is an 18-bit free run counter (timebase counter) that counts up in synchronization with the
internal count clock signal (base oscillator × 2) , and functions as an interval timer with a choice of four types of
time intervals. Other functions provided by this module include timer output for the oscillator stabilization wait
period, and operating clock signal feed for other timer circuits such as the watchdog timer.
To clock control
module oscillator
stabilization wait
time selector
Timebase timer control register (TBTC)
RESVTBIE TBOF TBR TBC1 TBC0
⎯⎯
Timebase timer interrupt signal
OF : Overflow
HCLK : Oscillator clock
*1 : Switch machine clock from main clock or sub clock to PLL clock.
*2 : Switch machine clock from sub clock to main clock.
67
MB90480/485 Series
16. Clock
The clock generator module controls the operation of the internal clock circuits that serve as the operating clock
for the CPU and peripheral devices. This internal clock is referred to as the machine clock, and one cycle is referred
to as a machine cycle. Also, the clock signals from the base oscillator are called the oscillator clock, and those from
the PLL oscillator are called the PLL clock.
(1) Register List
Clock select register (CKSCR)
15141312111098
0000A1
PLL output select register (PLLOS)
0000CF
H
SCMWS1WS0SCS MCSCS1CS0
H
MCM
R
R
1
15141312111098
⎯⎯⎯⎯ ⎯⎯PLL2
⎯
⎯
⎯
⎯
⎯
R/W1R/W1R/W1R/W1R/W0R/W
1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Read/write
Initial value
0
W
X
W
0
Read/write
Initial value
68
(2) Block Diagram
Low-power consumption mode control register (LPMCR)
pin
RST
Standby control circuit
STP SLP SPL RST TMD CG1 CG0
Re-
served
MB90480/485 Series
Pin high-impedance
control circuit
Internal reset
generator circuit
Pin
high-impedance
control
Internal reset
Interrupt release
Clock generator module
SCLK
× 4
Sub clock
generator
circuit
pin
X0A
pin
X1A
pin
X0
pin
X1
CPU intermittent
operation selec
Standby control
circuit
Machine clock
Clock
selector
PLL multiplier
circuit
SCM
Clock select register (CKSCR)
System
clock
generator
circuit
HCLK
× 2
MCLK
Timebase
timer
HCLK : Oscillator clock
MCLK : Main clock
SCLK : Sub clock
tor
CPU clock
control circuit
Peripheral
clock control
circuit
Oscillator stabilization wait release
PLL output select register (PLLOS)
⎯⎯⎯⎯⎯⎯⎯PLL2
2
2
MCM WS1WS0 SCS MCS CS1CS0
×
1024
× 2 × 4 × 4 × 4 × 2
To watchdog timer
Intermittent cycle selection
CPU clock
Stop, sleep signals
Stop signal
Peripheral
clock
Oscillator
stabilization
wait period
selector
69
MB90480/485 Series
(3) Clock Feed Map
Clock generator module
X0A
pin
X1A
pin
X0
pin
X1
pin
Sub clock
generator
circuit
System clock
generator
circuit
HCLK
PLL multiplier
× 4
× 2
MCLK
Watch timer
Timebase
timer
123 4
circuit
SCLK
PCLK
Clock
selector
CPU, µDMAC
Peripheral functions
4
Watchdog timer
4
8/16-bit PPG
timer 0
8/16-bit PPG
timer 1
8/16-bit PPG
timer 2
16-bit reload
φ
timer 0
PPG0, PPG1
pins
PPG2, PPG3
pins
PPG4, PPG5
pins
TIN0
pin
TOT0
pin
SCK0, SIN0
pins
UART0
SOT0
pin
SCK1, SCK2
SIN1, SIN2
Extended I/O
serial interface,
2 channels
8/16-bit
up/down counter
pins
SOT1, SOT2
pins
AIN0, AIN1
BIN0, BIN1
ZIN0, ZIN1
pins
70
HCLK : Oscillator clock
MCLK : Main clock
SCLK : Sub clock
PCLK : PLL clock
φ : Machine clock
Chip select
16-bit output
compare
16-bit free run
timer
16-bit input
capture
10-bit A/D
converter
External interrupt
Oscillator
3
stabilization
wait control
CS0, CS1,
CS2, CS3
pins
OUT0, OUT1, OUT2,
OUT3, OUT4, OUT5
pins
FRCK
pin
IN0, IN1
pins
AN0 to AN7, ADTG
pins
IRQ0 to IRQ7
pin
MB90480/485 Series
17. Low-power Consumption Mode
The MB90480/485 series uses operating clock selection and clock operation controls to provide the following
CPU operating modes :
• Clock modes
(PLL clock mode, main clock mode, sub clock mode)
• CPU intermittent operating modes
(PLL clock intermittent mode, main clock intermittent mode, sub clock intermittent mode)
The external bus pin control circuit controls the external bus pins used to expand the CPU address/data bus
connections to external circuits.
(1) Register List
• Auto ready function select register (ARSR)
Address : 0000A5H0011--00B
15141312111098
IOR1HMR1HMR0⎯⎯LMR1LMR0
IOR0
W
WWW ⎯⎯WW
• External address output control register (HACR)
Address : 0000A6
H********B
76543210
E23E21E20E19E18E17E16
W
E22
WW W W WWW
• Bus control signal select register (EPCR)
Address : 0000A7
15141312111098
H1000*10-B
CKEHDEIOBSHMBSWRELMBS⎯
RYE
W
WWW W WW⎯
Initial value
Initial value
Initial value
W
−
*
(2) Block Diagram
: Write only
: Not used
: May be either “1” or “0”
P0 data
P0 direction
RB
Data control
Address control
P0
P1
P2
P3
P5
P4
P5
P0
74
Access control
Access control
MB90480/485 Series
19. Chip Select Function Description
The chip select module generates a chip select signals, which are used to facilitate connections to external
memory devices. The MB90480/485 series has four chip select output pins, each having a chip select area
register setting that specifies the corresponding hardware area and select signal that is output when access to
the corresponding external address is detected.
• Chip select function features
The chip select function uses two 8-bit registers for each output pin. One of these registers (CARx) is able to
detect memory areas in 64 Kbytes units by specifying the upper 8-bit of the address for match detection. The
other register (CMRx) can be used to expand the detection area beyond 64 Kbytes by masking bits for match
detection.
Note that during external bus holds, the CS output is set to high impedance.
(1) Register List
150
CAR1
CAR3
Chip select area mask register (CMRx)
0000C0
0000C2H
0000C4H
0000C6H
H
76543210
M7M5M4M3M2M1M0
R/W
M6
R/W0R/W0R/W0R/W1R/W1R/W1R/W
0
Chip select area register (CARx)
0000C1
0000C3H
0000C5H
0000C7H
H
15141312111098
A7A5A4A3A2A1A0
R/W
1
A6
R/W1R/W1R/W1R/W1R/W1R/W1R/W
Chip select control register (CSCR)
76543210
0000C8
H
⎯⎯⎯OPL3OPL2OPL1OPL0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
8 7
CMR0CAR0
CMR1
CMR2CAR2
CMR3
CSCRR/WCALR
R/W0R/W0R/W0R/W
1
1
*
R/W
R/W
R/W
R/W
Read/write
Initial value
Read/write
Initial value
Read/write
Initial value
Chip select active level register (CALR)
15141312111098
0000C9
H
⎯⎯⎯ACTL3 ACTL2 ACTL1 ACTL0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R/W0R/W0R/W0R/W
* : The initial value of this bit is “1” or “0”.
The value depends on the mode pin (MD2, MD1 and MD0) .
0
Read/write
Initial value
75
MB90480/485 Series
(2) Block Diagram
CMRx
MC-16LX Bus
2
F
CARx
A23 to A16
Chip select output pins
76
MB90480/485 Series
20. ROM Mirror Function Select Module
The ROM mirror function selection module sets the data in ROM assigned to FF bank so that the data is read
by access to 00 bank.
(1) Register List
• ROM mirror function select register (ROMM)
Initial value
( + ) : MB90F489B : Read only, fixed at “1”
Other : Selectable, Initial value 0
Address : 00006F
- : Not used
(2) Block Diagram
15141312111098
H------+1B
F
⎯⎯⎯⎯⎯⎯MSMI
2
MC-16LX bus
R/WR/W
(+)
ROM mirror function select
Addressarea
FF bank
00 bank
ROM
Note : Do not access ROM mirror function selection register (ROMM) on using the area of address 004000
00FFFF
H (008000H to 00FFFFH) .
H to
77
MB90480/485 Series
21. Interrupt Controller
The interrupt control register is built in interrupt controller, and is supported for all I/O of interrupt function.
This register sets corresponding peripheral interrupt level.
(1) Register List
Interrupt control registers
Address : ICR01
ICR03
ICR05
ICR07
ICR09
ICR11
ICR13
ICR15
0000B1
H
0000B3H
0000B5H
0000B7H
0000B9H
0000BBH
0000BDH
0000BFH
Read/write→
Initial value→
15141312111098
⎯⎯⎯
W
X
⎯
W
ReservedIL2IL1IL0
X
W
X
W
R/W
X
R/W1R/W1R/W
0
1
ICR01,
03, 05,
07, 09,
11, 13, 15
Interrupt control registers
Address : ICR00
ICR02
ICR04
ICR06
ICR08
ICR10
ICR12
ICR14
0000B0
H
0000B2H
0000B4H
0000B6H
0000B8H
0000BAH
0000BCH
0000BEH
Read/write→
Initial value→
76543210
⎯⎯⎯
W
X
⎯
W
ReservedIL2IL1IL0
X
W
X
W
X
R/W0R/W1R/W1R/W
1
ICR00,
02, 04,
06, 08,
10, 12, 14
Note : The use of access involving read-modify-write instructions may lead to abnormal operation, and should be
avoided.
78
(2) Block Diagram
MC-16LX Bus
2
F
IL2
IL1
IL0
MB90480/485 Series
Interrupt priority setting
Interrupt requests
3233
(Peripheral resources)
3
(CPU)
Interrupt level
79
MB90480/485 Series
22. µDMAC
The µDMAC is a simplified DMA module with functions equivalent to EI2OS. The µDMAC has 16 DMA data
transfer channels, and provides the following functions.
• Automatic data transfer between peripheral resources (I/O) and memory.
• CPU program execution stops during DMA operation.
• Incremental addressing for transfer source and destination can be turned on/off.
• DMA transfer control from the µDMAC enable register, µDMAC stop status register, µDMAC status register,
and descriptor.
• Stop requests from resources can stop DMA transfer.
• When DMA transfer is completed, the µDMAC status register sets a flag in the bit for the corresponding channel
on which transfer was completed, and outputs a completion interrupt to the interrupt controller.
When the address is equal to a value set in the address detection register, the instruction code loaded into the
CPU is replaced forcibly with the INT9 instruction code (01
the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program patching function
to be implemented.
Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value
set in the address detection register matches an address and if the interrupt enable bit is set at “1”, the instruction
code loaded into the CPU is replaced forcibly with the INT9 instruction code.
(1) Register List
• Program address detection register 0 (PADR0)
H). As a result, when the CPU executes a set instruction,
Address
PADR0 (Low order address) : 001FF0
Address
PADR0 (Middle order address) : 001FF1
Address
PADR0 (High order address) : 001FF2H
76543210
H
R/WR/WR/WR/WR/WR/WR/WR/W
76543210
H
R/WR/WR/WR/WR/WR/WR/WR/W
76543210
R/WR/WR/WR/WR/WR/WR/WR/W
• Program address detection register 1 (PADR1)
Address
PADR1 (Low order address) : 001FF3H
Address
PADR1 (Middle order address) : 001FF4H
Address
PADR1 (High order address) : 001FF5H
76543210
R/WR/WR/WR/WR/WR/WR/WR/W
76543210
R/WR/WR/WR/WR/WR/WR/WR/W
76543210
R/WR/WR/WR/WR/WR/WR/WR/W
• Program address detection control status register (PACSR)
Address
00009EH
76543210
RESV RESV RESV RESV AD1E RESV AD0E RESV
R/WR/WR/WR/WR/WR/WR/WR/W
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
00000000
B
B
B
B
B
B
B
82
R/W : Readable and writable
X : Undefined
RESV : Reserved bit
(2) Block Diagram
MB90480/485 Series
Address latch
Address detection
register
Enable bit
Internal databus
Compare
INT9
instruction
2
F
MC-16LX
CPU core
83
MB90480/485 Series
■ ELECTRICAL CHARACTERISTICS
1.Absolute Maximum Ratings
ParameterSymbol
VCC3VSS− 0.3VSS+ 4.0V
CC5VSS− 0.3VSS+ 7.0V
Power supply voltage*
1
V
AV
Rating
UnitRemarks
MinMax
CCVSS− 0.3VSS+ 4.0V*2
AVRHV
Input voltage*
Output voltage*
Maximum clamp currentI
1
1
CLAMP−2.0+2.0mA*7
Total maximum clamp currentΣ⏐I
“L” level maximum output currentI
“L” level average output currentI
OLAV⎯3mA*5
“L” level maximum total output currentΣI
“L” level total average output currentΣI
“H” level maximum output currentI
“H” level average output currentI
OHAV⎯−3mA*5
“H” level maximum total output currentΣI
“H” level total average output currentΣI
Power consumptionP
Operating temperatureT
VI
VO
CLAMP⏐⎯20mA*7
OL⎯10mA*4
OL⎯60mA
OLAV⎯30mA*6
OH⎯−10mA*4
OH⎯−60mA
OHAV⎯−30mA*6
D⎯320mW
A−40+85 °C
SS− 0.3VSS+ 4.0V*2
VSS− 0.3VSS+ 4.0V*3
SS− 0.3VSS+ 7.0V*3, *8, *9
V
VSS− 0.3VSS+ 4.0V*3
SS− 0.3VSS+ 7.0V*3, *8, *9
V
Storage temperatureTstg−55+150 °C
*1 : This parameter is based on VSS= AVSS= 0.0 V.
*2 : AV
*3 : V
CC and AVRH must not exceed VCC. Also, AVRH must not exceed AVCC.
I and V0 must not exceed VCC+ 0.3 V. However, if the maximum current to/from and input is limited by some
means with external components, the I
CLAMP rating supersedes the VI rating.
*4 : Maximum output current is defined as the peak value for one of the corresponding pins.
*5 : Average output current is defined as the average current flow in a 100 ms interval at one of the corresponding
pins.
*6 : Average total output current is defined as the average current flow in a 100 ms interval at all corresponding pins.
*7 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P90 to P97, PA0 to PA3
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
(Continued)
84
MB90480/485 Series
(Continued)
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the V
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input.
• Sample recommended circuits:
• Input/Output Equivalent circuits
Protective diode
Limiting
resistance
+B input (0 V to 16 V)
CC pin, and this may affect
V
CC
P-ch
N-ch
R
*8 : MB90485 series only
P20 to P27, P30 to P37, P40 to P47, P70 to P77 pins can be used as 5 V I/F pin on applied 5 V to V
CC5 pin.
P76 and P77 is N-ch open drain pin.
*9 : As for P76 and P77 (N-ch open drain pin) , even if using at 3 V simplicity (VCC3 = VCC5) , the ratings are applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
85
MB90480/485 Series
2.Recommended Operating Conditions
ParameterSymbol
MinMax
(VSS= AVSS= 0.0 V)
Value
UnitRemarks
CC3
V
1.83.6VTo maintain RAM state in stop mode
Power supply voltage
2.75.5VDuring normal operation*
2.73.6VDuring normal operation
V
CC5
1.85.5VTo maintain RAM state in stop mode*
All pins other than VIH2, VIHS, VIHM and
V
IHX
MB90485 series only
P76, P77 pins (N-ch open drain pins)
“H” level input voltage
IH0.7 VCCVCC+ 0.3V
V
VIH20.7 VCCVSS+ 5.8V
VIHS0.8 VCCVCC+ 0.3VHysteresis input pins
V
IHMVCC− 0.3VCC+ 0.3VMD pin input
V
IHX0.8 VCCVCC+ 0.3VX0A pin, X1A pin
VILVSS− 0.30.3 VCCVAll pins other than VILS, VILM and VILX
VILSVSS− 0.30.2 VCCVHysteresis input pins
“L” level input voltage
V
ILMVSS− 0.3VSS+ 0.3VMD pin input
VILXVSS− 0.30.1VX0A pin, X1A pin
Operating temperatureT
A−40+85 °C
* : MB90485 series only
P20 to P27, P30 to P37, P40 to P47, P70 to P77 pins can be used as 5 V I/F pin on applied 5 V to V
CC5 pin.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
86
3.DC Characteristics
ParameterSymbol Pin nameCondition
V
CC= 2.7 V,
I
“H” level
output voltage
“L” level
output voltage
Input leakage
current
Pull-up
resistance
Open drain
output current
V
R
I
All output
OH
pins
All output
V
OL
pins
All input
IL
I
pins
PULL⎯
P40 to P47,
leak
I
P70 to P77
CC⎯
I
CCS⎯
Power supply
current
CCL⎯
I
I
CCT⎯
ICCH⎯
Input
capacitance
IN
C
Other than
AV
VCC, VSS
Notes :•MB90485 series only
• P40 to P47 and P70 to P77 are N-ch open drain pins with control, which are usually used as CMOS.
• P76 and P77 are open drain pins without P-ch.
• For use as a single 3 V power supply products, set V
• When the device is used with dual power supplies, P20 to P27, P30 to P37, P40 to P47 and
P70 to P77 serve as 5 V pins while the other pins serve as 3 V I/O pins.
CC, AVSS,
OH=−1.6 mA
VCC= 4.5 V,
I
OH=−4.0 mA
V
CC= 2.7 V,
I
OL= 2.0 mA
CC= 4.5 V,
V
I
OH= 4.0 mA
VCC= 3.3 V,
V
SS< VI< VCC
V
CC= 3.0 V,
at T
A=+25 °C
CC= 3.3 V,
At V
internal 25 MHz operation,
normal operation
CC= 3.3 V,
At V
internal 25 MHz operation,
Flash programming
CC= 3.3 V,
At V
internal 25 MHz operation,
sleep mode
CC= 3.3 V,
At V
external 32 kHz,
internal 8 kHz operation,
sub clock operation
(T
*1 : Be careful of the operating voltage.
*2 : Duty ratio should be 50 % ± 3 %.
88
• X0, X1 clock timing
X0
• X0A, X1A clock timing
MB90480/485 Series
t
C
0.8 V
CC
0.2 V
CC
P
WH
t
cf
tCL
P
WL
t
cr
X0A
0.8 VCC
0.2 VCC
PWLHPWLL
tcftcr
89
MB90480/485 Series
• Range of warranted PLL operation
Internal operating clock frequency vs. Power supply voltage
3.6
3.0
2.7
CC (V)
V
Range of warranted PLL operation
Normal operating range
Power supply voltage
41.5
16
25
Internal clock fCP (MHz)
Notes: • For A/D operating frequency, refer to “5. A/D Converter Electrical Characteristics”
• Only at 1 multiplied PLL, use with more than f
CP= 4 MHz.
Base oscillator frequency vs. Internal operating clock frequency
3
8 × *
25
24
20
18
16
12
Internal clock fCP (MHz)
1.5
3
6 × *
4 ×
1,*2
*
9
8
6
4
348
5 61040
1
3 × *
2
2 × *1,*
12.5 1625203250
1 × *
1
Base oscillator clock F
No multiplied
CH (MHz)
*1 : In setting as 1, 2, 3 and 4 multiplied PLL, when the internal clock is used at 20 MHz < fCP≤ 25 MHz, set
the PLLOS register to “DIV2 bit = 1” and “PLL2 bit = 1”.
[Example]When using the base oscillator frequency of 24 MHz at 1 multiplied PLL :
CKSCR register : CS1 bit = “0”, CS0 bit = “0”PLLOS register : PLL2 bit = “1”
[Example]When using the base oscillator frequency of 6 MHz at 3 multiplied PLL :
CKSCR register : CS1 bit = “1”, CS0 bit = “0”PLLOS register : PLL2 bit = “1”
*2 : In setting as 2 and 4 multiplied PLL, when the internal clock is used at 20 MHz < f
CP≤ 25 MHz, the following
setting is also enabled.
2 multiplied PLL : CKSCR register : CS1 bit = “0”, CS0 bit = “0”
PLLOS register : PLL2 bit = “1”
4 multiplied PLL : CKSCR register : CS1 bit = “0”, CS0 bit = “1”
PLLOS register : PLL2 bit = “1”
*3 : When using in setting as 6 and 8 multiplied PLL, set the PLLOS register to “DIV2 bit = 0” and “PLL2 bit = 1”.
[Example]When using the base oscillator frequency of 4 MHz at 6 multiplied PLL :
CKSCR register : CS1 bit = “1”, CS0 bit = “0”PLLOS register : PLL2 bit = “1”
[Example]When using the base oscillator frequency of 3 MHz at 8 multiplied PLL :
CKSCR register : CS1 bit = “1”, CS0 bit = “1”PLLOS register : PLL2 bit = “1”
90
AC standards are set at the following measurement voltage values.
MB90480/485 Series
• Input signal waveform
Hysteresis input pins
0.8 VCC
0.2 VCC
• Pins other than hysteresis input/MD input
0.7 VCC
0.3 VCC
• Output signal waveform
Output pins
2.4 V
0.8 V
91
MB90480/485 Series
(2) Clock Output Timing
ParameterSymbol Pin nameConditions
SS= 0.0 V, TA=−40 °C to +85 °C)
(V
Val ue
MinMax
UnitRemarks
Cycle timet
CYCCLK⎯tCP*⎯ns
VCC= 3.0 V to 3.6 V tCP* / 2 − 15 tCP* / 2 + 15nsat fCP= 25 MHz
CLK↑→CLK↓t
* : t
CP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
CHCLCLK
2.4 V2.4 V
CLK
VCC= 2.7 V to 3.3 V tCP* / 2 − 20 tCP* / 2 + 20nsat fCP= 16 MHz
V
CC= 2.7 V to 3.3 V tCP* / 2 − 64 tCP* / 2 + 64nsat fCP= 5 MHz
t
CYC
t
CHCL
0.8 V
92
MB90480/485 Series
(3) Reset Input Standards
CC= 2.7 V to 3.6 V, VSS= 0.0 V, TA=−40 °C to +85 °C)
(V
ParameterSymbol
Reset input timet
*1 : t
CP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
RSTLRST⎯
Pin
name
Condi-
tions
Oscillator oscillation time*
*2 : Oscillator oscillation time is the time to 90 % of amplitude. For a crystal oscillator this is on the order of several
milliseconds to tens of milliseconds. For a ceramic oscillator, this is several hundred microseconds to
several milliseconds. For an external clock signal the value is 0 ms.
• In stop mode
t
RSTL
RST
0.2 Vcc
Val ue
MinMax
1
16 t
CP*
2
+ 4 tCP*
1
0.2 Vcc
UnitRemarks
⎯nsNormal operation
⎯msStop mode
90 % of
X0
amplitude
Internal
operating
clock
Oscillator
oscillation time
Internal reset
• Condition for measurement of AC standards
C
Pin
CLK, ALE : C
AD15 to AD00 (address data bus) , RD
A23 to A00/D15 to D00 : C
CL
4 t
CP
Oscillator stabilization wait time
Instruction execution
L : Load capacitance applied to pins during testing
L= 30 pF
, WR,
L= 30 pF
93
MB90480/485 Series
(4) Power-on Reset Standards
ParameterSymbol Pin name Conditions
CC= 2.7 V to 3.6 V, VSS= 0.0 V, TA=−40 °C to +85 °C)
(V
Val ue
UnitRemarks
MinMax
Power rise timet
RVCC
0.0530ms*
⎯
Power down timet
* : Power rise time requires V
OFFVCC1⎯msIn repeated operation
CC< 0.2 V.
Notes: • The above standards are for the application of a power-on reset.
• Within the device, the power-on reset should be applied by switching the power supply off and on again.
t
R
V
CC
2.7 V
0.2 V0.2 V0.2 V
t
OFF
Note : Rapid fluctuations in power supply voltage may trigger a power-on reset in some cases. As shown below,
when changing supply voltage during operation, it is recommended that voltage changes be suppressed
and a smooth restart be applied.
Main power supply voltage
Sub power supply voltage
94
V
CC
RAM data maintenance
V
SS
The slope of voltage increase
should be kept within 50 mV/ms.
(5) Bus Read Timing
ParameterSymbol Pin nameConditions
ALE pulse widtht
Valid address→
ALE↓time
LHLLALE⎯
tAVLL
Address,
ALE
⎯
MB90480/485 Series
CC= 2.7 V to 3.6 V, VSS= 0.0 V, TA= 0 °C to +70 °C)
(V
Value
MinMax
CP* / 2 − 15⎯ns
t
tCP* / 2 − 20⎯ns
tCP* / 2 − 35⎯ns
CP* / 2 − 17⎯ns
t
tCP* / 2 − 40⎯ns
UnitRemarks
16 MHz < fCP≤
25 MHz
8 MHz < fCP≤
16 MHz
fCP≤ 8 MHz
fCP≤ 8 MHz
ALE↓→
address valid time
Valid address→
RD
↓time
Valid address→
valid data input
tLLAX
tAVRL
AVDV
t
ALE,
Address
RD,
address
Address,
Data
⎯tCP* / 2 − 15⎯ns
⎯tCP* − 25⎯ns
⎯
5 tCP* / 2 − 55
⎯
⎯
3 tCP* / 2 − 25
5 tCP* / 2 − 80
⎯ns
RD pulse widthtRLRHRD⎯
3 tCP* / 2 − 20
RD↓→
valid data input
tRLDV
RD↑→data hold timetRHDX
RD
↑→ALE↑timetRHLHRD, ALE⎯tCP* / 2 − 15⎯ns
RD
↑→
address valid time
Valid address→
CLK↑time
RD
↓→CLK↑timetRLCHRD, CLK⎯tCP* / 2 − 17⎯ns
tRHAX
tAVCH
RD,
Data
RD,
Data
Address,
RD
Address,
CLK
⎯
⎯0⎯ns
⎯tCP* / 2 − 10⎯ns
⎯tCP* / 2 − 17⎯ns
⎯
⎯
⎯ns
3 tCP* / 2 − 55
3 tCP* / 2 − 80
ns
fCP≤ 8 MHz
ns
16 MHz < fCP≤
25 MHz
8 MHz < fCP≤
16 MHz
ns
fCP≤ 8 MHz
ns
ALE↓→RD
CP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
* : t
↓timetLLRLRD, ALE⎯tCP* / 2 − 15⎯ns
95
MB90480/485 Series
CLK
ALE
RD
In multiplexed mode
A23 to A16
AD15 to AD00
In non-multiplexed mode
A23 to A00
D15 to D00
2.4 V
0.8 V
2.4 V
tAVCH
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
2.4 V
tLHLL
tAVLL
0.8 V
tLLAX
tLLRL
tAVRLtRLDV
0.8 V
tAVDV
2.4 V
Address
0.8 V
tAVDV
tRLCH
2.4 V
tRLDV
tRLRH
0.7 VCC
0.3 V
0.7 VCC
CC
0.3 V
CC
2.4 V
tRHDX
Read data
tRHDX
Read data
tRHLH
2.4 V
tRHAX
2.4 V
0.8 V
0.7 VCC
0.3 VCC
tRHAX
2.4 V
0.8 V
0.7 VCC
0.3 VCC
96
MB90480/485 Series
(6) Bus Write Timing
CC= 2.7 V to 3.6 V, VSS= 0.0 V, TA= 0 °C to +70 °C)