FUJITSU MB90473, MB90474, MB90477, MB90478 DATA SHEET

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13712-4E

16-Bit Proprietary Microcontroller

CMOS

F2MC-16LX MB90470 Series

MB90473/474/477/478/F474L/F474H

DESCRIPTIONS

■

The FUJITSU MB90470 Series is a 16-bit general-purpose microcontroller designed for consumer products and other process control applications requiring high-speed and real-time processing.

The F

MC-16LX CPU core instruction set retains the AT architecture of the F2MC*1 family, with additional instructions for use with high-level languages, expanded addressing mode, enhanced multiply and divide instructions, and full bit processing. Also included is a built-in 32-bit accumulator for long-word processing.

Peripheral resources built into the MB90470 ser ies include 8/16-bit PPG, expanded I/O serial interface, UART, 10-bit A/D converter, 16-bit input-output timer, 8/16-bit up-counter, PWC timer, I interrupt, chip select, and 16-bit reload timer.

*1 : F

MC is an abbreviation for FUJITSU Flexible Microcontroller, and is a registered trademark of FUJITSU, Ltd.

*2 : I

C license : This product includes licensing of Philips I standard specifications established by Philips.

PACKAGES

■

100-pin plastic QFP 100-pin plastic LQFP

(FPT-100P-M06) (FPT-100P-M05)

C patents if used by the customer in an I2C system subject to the I2C

2C*2

interface, DTP/exter nal

MB90470 Series

FEATURES

■

•

Clocks

Minimum instruction execution time :

50.0 ns at 5 MHz base oscillation with 4 × multiplier (internal operation at 20 MHz/3.3 V ± 0.3 V)

62.5 ns at 4 MHz base oscillation with 4 × multiplier (internal operation at 16 MHz/3.0 V ± 0.3 V) Uses PLL clock multiplier.

•

Maximum memory size

16 Mbytes

•

Instruction set optimized for control applications

Handles bit, byte, word, long-word data 23 standard addressing modes 32-bit accumulator for enhanced high-precision calculation Signed multiply-divide and expanded RETI instructions

•

Instruction system compatible with high-level language (C) multitasking

System stack pointer Instruction set correlation and barrel shift instructions

• Non-multi bus or multi-bus compatible

• Program patch function (for two address pointers)

•

Improved execution speed

4-byte queue

•

Powerful interrupt functions

8 external interrupt functions with 8-level programmable priority

•

Data transfer functions

16 channels maximum µDMA maximum assured operation frequency : 16 MHz Extended intelligent I/O service maximum assured operation frequency : 20 MHz

•

Built-in ROM

Flash versions : 256 KB, Mask ROM versions : 128 KB/256 KB

•

Built-in RAM

10 KB/16 KB

•

General purpose ports

84 ports maximum (includes 16 ports with input pull-up resistance setting, 14 ports with output open drain setting)

•A/

D converter

RC sequential comparator type, 8 channels 10-bit resolution, conversion time 4.65 µs (at 20 MHz operation)

C interface

•

1 channel

• µµµµ

1 channel

•

UART

1 channel

•I/

O expansion serial interface (SIO

2 channels

•8/16-

•16-

bit up/down timer

1 channel

bit PWC

3 channels (including 2-channel input comparison function)

(µµµµ

DMA or Extended intelligent I/O service

)

(Continued)

MB90470 Series

(Continued)

•16-

bit reload timer

1 channel (8-bit × 2-channel, 16-bit × 1-channel mode switching function provided)

•16-

bit input-output timer

2-channel input capture, 6-channel output compare, 1-channel free run timer

• 2 built-in clock generator systems

•

Low power modes

Stop, sleep, CPU intermittent mode, watch mode, etc.

•

Package options

QFP100/LQFP100

•

Process

CMOS technology

•

Supply voltage

Can operate on 3 V single supply systems (with 5 V interface provided by some pins with 3/5 V dual-supply capability)

MB90470 Series

PRODUCT LINEUP

■

Part number

Parameter

ROM capacity FLASH 256 KB FLASH 256 KB RAM capacity 16 KB 16 KB 10 KB 16 KB

CPU functions

Ports

UART Stop-start synchronized : 1 channel 8/16-bit PPG timer 8-bit 6-channel/16-bit 3-channel

8/16-bit up-down counter/timer

-bit free-run timer

16-bit input/ output timers

DTP/external interrupt circuit External interrupt pins : 8 channels (set to edge or level correlation) I/O expansion serial interface 2-channel, built-in

Time base timer

A/D converter

Watchdog timer Low power (standby) modes Sleep, stop, CPU intermittent, watch mode

Process CMOS

Notes

Emulator dedicated power supply 

Output compare

Input capture (ICU)

C interface 1-channel, built-in

(OCU)

MB90F474L MB90F474H MB90473 MB90474

MASKROM

128 KB

Basic instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time

General purpose input/output ports : 84 Max General purpose input/output ports (CMOS output) General purpose input/output ports (built-in pull-up resistance) General purpose input/output ports (N-ch open drain)

Two 8-bit up-down counters with 6 event input pins Two 8-bit reload/compare registers

Channel : 1 Overflow interrupt

Channels : 6 Pin input source : from compare register match signal

Channels : 2 Register rewritten from pin input (rising/falling/both edges)

18-bit counter Interrupt cycle : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (minimum times, at base oscillator frequency 4 MHz)

Conversion accuracy : 8/10-bit switchable Single conversion mode (converts selected channel 1 time only) Scan conversion mode (converts multiple consecutive channels, programmable up to 8 channels) Continuous conversion mode (converts selected channels continuously) Stop conversion mode (converts selected channel, stops and repeats)

Reset interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (minimum times, at base oscillator frequency 4 MHz)

Flash model, low

voltage version (f = 10 MHz or

less at V

CC = 2.4 V)

Flash model, high

voltage version

(f = 20 MHz)

: 351 : 8-bit, 16-bit : 1 byte to 7 bytes : 1-bit, 8-bit, 16-bit : 62.5 ns (with 16 MHz machine clock)

Mask version Mask version

MASKROM

256 KB

(Continued)

MB90470 Series

(Continued)

Part number

Parameter

ROM capacity RAM capacity 8 KB 8 KB 16 KB

Basic instructions Instruction bit length

CPU functions

Ports

UART Stop-start synchronized : 1 channel 8/16-bit PPG timer 8-bit 6-channel/16-bit 3-channel

8/16-bit up-down counter/timer

16-bit free-run timer

16-bit input/ output timers

DTP/external interrupt circuit External interrupt pins : 8 channels (set to edge or level correlation) I/O expansion serial interface 2-channel, built-in

C interface 1-channel, built-in

Time base timer

A/D converter

Watchdog timer Low power (standby) modes Sleep, stop, CPU intermittent, watch mode

Process CMOS

Notes Mask version

Emulator dedicated power supply Included

Output compare (OCU)

Input capture (ICU)

Instruction length Data bit length Minimum instruction execution time

Two 8-bit up-down counters with 6 event input pins Two 8-bit reload/compare registers

Channel : 1 Overflow interrupt

Channels : 6 Pin input source : from compare register match signal

Channels : 2 Register rewritten from pin input (rising/falling/both edges)

18-bit counter Interrupt cycle : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (minimum times, at base oscillator frequency 4 MHz)

Reset interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (minimum times, at base oscillator frequency 4 MHz)

MB90477 MB90478 MB90V470B

MASKROM

256 KB

MASKROM

256 KB

Mask version without

built-in interface



: 351 : 8-bit, 16-bit : 1 byte to 7 bytes : 1-bit, 8-bit, 16-bit : 50 ns (with 20 MHz

machine clock)

EVA function

User pin

MB90470 Series

PIN ASSIGNMENTS

■

(TOP VIEW)

P21/A17 P22/A18

P23/A19 P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3

P30/A00/AIN0 P31/A01/BIN0

P32/A02/ZIN0 P33/A03/AIN1 P34/A04/BIN1

P35/A05/ZIN1 P36/A06/PWC0 P37/A07/PWC1

P40/A08/SIN2

P41/A09/SOT2 P42/A10/SCK2

P43/A11/MT00 P44/A12/MT01

P45/A13/EXTC P46/A14/OUT4 P47/A15/OUT5

VSS

CC5

P70/SIN0 P71/SOT0 P72/SCK0

P73/TIN0

P17/AD15/D15

P16/AD14/D14

P15/AD13/D13

P14/AD12/D12

P13/AD11/D11

P12/AD10/D10

P11/AD09/D09

P10/AD08/D08

P07/AD07/D07

P06/AD06/D06

P05/AD05/D05

P04/AD04/D04

P03/AD03/D03

P02/AD02/D02

99989796959493929190898887868584838281

100

1P20/A16 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

32333435363738394041424344454647484950

31P74/TOT0

CC3

P01/AD01/D01

P00/AD00/D00

X1X0VSS

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

X0A X1A P57/CLK RST P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE PA3/OUT3 PA2/OUT2 PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/PPG5 P94/PPG4 P93/FRCK/ADTG/CS3 P92/SCK1/CS2 P91/SOT1/CS1 P90/SIN1/CS0 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2 MD2

AVCC

P76/SCL

P77/SDA

P75/PWC2

AVSS

AVRH

P60/AN0

P61/AN1

P62/AN2

Vss

P63/AN3

P64/AN4

P65/AN5

P66/AN6

P67/AN7

P80/IRQ0

P81/IRQ1

MD0

MD1

(FPT-100P-M06)

(TOP VIEW)

MB90470 Series

P22/A18

P23/A19 P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3

P30/A00/AIN0 P31/A01/BIN0

P32/A02/ZIN0 P33/A03/AIN1 P34/A04/BIN1

P35/A05/ZIN1 P36/A06/PWC0 P37/A07/PWC1

P40/A08/SIN2

P41/A09/SOT2 P42/A10/SCK2

P43/A11/MT00 P44/A12/MT01

CC5

V P45/A13/EXTC P46/A14/OUT4 P47/A15/OUT5

P70/SIN0

P21/A17

P20/A16

P17/AD15/D15

P16/AD14/D13

P15/AD13/D13

P14/AD12/D12

P13/AD11/D11

P12/AD10/D10

P11/AD09/D09

P10/AD08/D08

P07/AD07/D07

P06/AD06/D06

P05/AD05/D05

P04/AD04/D04

P03/AD03/D03

9998979695949392919089888786858483828180797877

100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

26272829303132333435363738394041424344454647484950

CC3

P02/AD02/D02

P01/AD01/D01

P00/AD00/D00

X1X0V

X0A

X1A

P57/CLK

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

RST P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE PA3/OUT3 PA2/OUT2 PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/PPG5 P94/PPG4 P93/FRCK/ADTG/CS3 P92/SCK1/CS2 P91/SOT1/CS1 P90/SIN1/CS0 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3

P73/TIN0

P71/SOT0

P72/SCK0

P76/SCL

P74/TOT0

P75/PWC2

AVRH

P77/SDA

P60/AN0

(FPT-100P-M05)

P61/AN1

P62/AN2

P63/AN3

P64/AN4

P65/AN5

P66/AN6

P67/AN7

MD0

P80/IRQ0

P81/IRQ1

MD1

MD2

P82/IRQ2

MB90470 Series

PIN DESCRIPTION

■

Pin no.

LQFP QFP

80 82 X0 A Oscillator pin 81 83 X1 A Oscillator pin 78 80 X0A A 32 kHz oscillator pin 77 79 X1A A 32 kHz oscillator pin 75 77 RST

83 to 90 85 to 92

91 to 98

100

1 2

3 to 6 5 to 8

93 to

100

1 to 4

Pin name

P00 to P07

AD00 to AD07

D00 to D07

P10 to P17

AD08 to AD15

D08 to D15

P20 to P23

A16 to A19

P24 to P27

A20 to A23

PPG0 to PPG3 PPG timer output pins.

Circuit

type

B Reset input pin

General purpose input/output ports. Set the pull-up resistance setting register (RDR0) to add pull-up resistance (RD00-RD07 = “1” ) . (Not valid when set for output)

(CMOS)

(CMOS/H)

In multiplex mode, these pins function as external address/ data bus lower input/output pins.

In non-multiplex mode, these pins function as external data bus lower output pins.

General purpose input/output ports. Set the pull-up resistance setting register (RDR1) to add pull-up resistance (RD10-RD17 = “1” ) . (Not valid when set for output)

In multiplex mode, these pins function as external address/ data bus higher input/output pins.

In non-multiplex mode, these pins function as external data bus higher output pins.

General purpose input/output ports. In external bus mode, pins for which the corresponding bit in the external address output control register (HACR) is “1” function as the general purpose input/output ports.

In multiplex mode, pins for which the corresponding bit in the external address output control register (HACR) is “0” function as the upper address output pins (A16 to A19) .

In non-multiplex mode, pins for which the corresponding bit in the external address output control register (HACR) is “0” function as the upper address output pins (A16 to A19) .

In multiplex mode, pins for which the corresponding bit in the external address output control register (HACR) is “0” function as the upper address output pins (A20 to A23) .

In non-multiplex mode, pins for which the corresponding bit in the external address output control register (HACR) is “0” function as the upper address output pins (A20 to A23) .

Description

LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package

(Continued)

MB90470 Series

Pin no.

LQFP QFP

810

10 12

11 13

12 14

Pin name

P30 A00

AIN0 8/16-bit up-down timer input pin. (ch0)

P31 A01

BIN0 8/16-bit up-down timer input pin. (ch0)

P32 A02

ZIN0 8/16-bit up-down timer input pin. (ch0)

P33 A03

AIN1 8/16-bit up-down timer input pin. (ch1)

P34 A04

BIN1 8/16-bit up-down timer input pin. (ch1)

Circuit

type

(CMOS/H)

Description

General purpose input/output port. In non-multibus bus mode, this pin functions as an external

address pin.

General purpose input/output port. In non-multibus bus mode, this pin functions as an external

address pin.

General purpose input/output port. In non-multibus bus mode, this pin functions as an external

address pin.

General purpose input/output port. In non-multibus bus mode, this pin functions as an external

address pin.

General purpose input/output port. In non-multibus bus mode, this pin functions as an external

address pin.

P35

13 15

14 15

16 18

17 19

LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package

16 17

A05

ZIN1 8/16-bit up-down timer input pin. (ch1)

P36, P37 A06, A07

PWC0, PWC1 Functions as PWC input pin.

P40 A08

SIN2 Single serial I/O input pin

P41 A09

SOT2 Single serial I/O output pin

(CMOS/H)

(CMOS)

General purpose input/output port. In non-multibus bus mode, this pin functions as an external

address pin.

General purpose input/output ports. In non-multibus bus mode, this pin functions as an external

address pin.

General purpose input/output port. In non-multibus bus mode, this pin functions as an external

address pin.

General purpose input/output port. In non-multibus bus mode, this pin functions as an external

address pin.

(Continued)

MB90470 Series

Pin no.

LQFP QFP

18 20

19 20

22 24

23 24

68 70

69 71

21 22

25 26

Pin name

P42 A10

SCK2 Single serial I/O clock input/output pin

P43, P44 A11, A12

MT00, MT01 µPG input pins

P45 A13

EXTC µPG input pin

P46, P47 A14, A15

OUT4/OUT5 Output compare event output pins

P50

ALE

P51

Circuit

type

(CMOS/H)

(CMOS)

(CMOS/H)

(CMOS)

Description

General purpose input/output port. In non-multibus bus mode, this pin functions as an external

address pin.

General purpose input/output ports. In non-multibus bus mode, this pin functions as an external

address pin.

General purpose input/output ports. In non-multibus bus mode, this pin functions as an external

address pin.

General purpose input/output ports. In non-multibus bus mode, this pin functions as an external

address pin.

General purpose input/output port. In external bus mode, this pin functions as the ALE pin

In external bus mode, this pin functions as the address load enable signal (ALE) pin

General purpose input/output port. In external bus mode, this pin functions as the RD

In external bus mode, this pin functions as the read strobe output (RD

) pin.

pin.

70 72

71 73

LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package

P52

WRL

P53

WRH

(CMOS)

General purpose input/output port. In external bus mode, this pin functions as the WRL register is set to “1”.

In external bus mode, this pin functions as the lower data write strobe output (WRL register is set to “0”,this pin functions as a general purpose input/output port.

General purpose input/output port. In external bus mode with 16-bit bus width, this pin functions as the WRH WRE bit in the EPCR register is set to “1”.

In external bus mode with 16-bit bus width, this pin functions as the higher data write strobe output (WRH WRE bit in the EPCR register is set to “0”,this pin functions as a general purpose input/output port.

pin when the WRE bit in the EPCR

) pin. When the WRE bit in the EPCR

pin when the

) pin. When the

(Continued)

MB90470 Series

Pin no.

LQFP QFP

72 74

73 75

74 76

76 78

36 to 39 38 to 41

41 to 44 43 to 46

25 27

26 28

27 29

28 30

29 31

Pin name

P54

HRQ

P55

HAK

P56

RDY

P57

CLK

P60 to P63

AN0 to AN3 Analog input pins.

P64 to P67

AN4 to AN7 Analog input pins.

P70

SIN0 UART data input pin.

P71

SOT0 UART data output pin.

P72

SCK0 UART clock input pin.

P73

TIN0 16-bit reload timer event input pin.

P74

TOT0 16-bit reload timer output pin.

Circuit

type

(CMOS)

(CMOS/H)

(CMOS)

(CMOS/H)

(CMOS)

Description

General purpose input/output port. In external bus mode, this pin functions as the HRQ pin when the HDE bit in the EPCR register is set to “1”.

In external bus mode, this pin functions as the hold request input (HRQ) pin. When the HDE bit in the EPCR register is set to “0”,this pin functions as a general purpose input/output port.

General purpose input/output port. In external bus mode, this pin functions as the HAK register is set to “1”.

In external bus mode, this pin functions as the hold acknowledge output (HAK is set to “0”,this pin functions as a general purpose input/output port.

General purpose input/output port. In external bus mode, this pin functions as the DRY pin when the RYE bit in the EPCR register is set to “1”.

In external bus mode, this pin functions as the external ready input (RDY) pin. When the RYE bit in the EPCR register is set to “0”,this pin functions as a general purpose input/output port.

General purpose input/output port. In external bus mode, this pin functions as the CLK pin when the CKE bit in the EPCR register is set to “1”.

In external bus mode, this pin functions as the machine cycle clock output (CLK) pin. When the CKE bit in the EPCR register is set to “0”,this pin functions as a general purpose input/output port.

General purpose input/output ports.

General purpose input/output port.

) pin. When the HDE bit in the EPCR register

pin when the HDE bit in the EPCR

LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package

(Continued)

MB90470 Series

Pin no.

LQFP QFP

30 32

31 33

32 34

45 46

50 to 55 52 to 57

56 58

57 59

47 48

Pin name

P75

PWC2 PWC input pin.

P76

SCL

P77

SDA

P80, P81

IRQ0, IRQ1 External interrupt input pins.

P82 to P87

IRQ2 to IRQ7 External interrupt input pins.

P90

SIN1 Single serial I/O data input pin.

CS0 Chip select 0.

P91

SOT1 Single serial I/O data output pin.

CS1 Chip select 1.

Circuit

type

(CMOS/H)

(NMOS/H)

(CMOS/H)

(CMOS)

Description

General purpose input/output port.

C interface data input/output pin. During I2C interface

I operation, the port output should be set to High-Z level.

General purpose input/output port.

C interface clock input/output pin. During I2C interface

operation, the port output should be set to High-Z level. General purpose input/output ports.

General purpose input/output ports.

General purpose input/output port.

P92

58 60

59 61

60 62

61 63

62 64

LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package

SCK1 Single serial I/O clock input/output pin.

CS2 Chip select 2.

P93

FRCK

ADTG

CS3 Chip select 3.

P94

PPG4 PPG timer output pin.

P95

PPG5 PPG timer output pin.

P96

IN0 Functions as input capture ch 0 trigger input.

(CMOS/H)

(CMOS)

(CMOS/H)

General purpose input/output port.

General purpose input/output port. In free run timer operation, this pin functions as the external

clock input pin. In A/D converter operation, this pin functions as the external

trigger input pin.

General purpose input/output port.

(Continued)

Pin no.

LQFP QFP

Pin name

Circuit

type

MB90470 Series

Description

63 65

64 to 67 66 to 69

OUT0 to OUT3 Output compare event output pins.

33 35 AV

P97

IN1 Functions as input capture ch 1 trigger input.

PA0 to PA3

(CMOS/H)

(CMOS)

CC  A/D converter power supply pin.

General purpose input/output port.

General purpose input/output ports.

34 36 AVRH  A/D converter external reference power pin. 35 37 AV

47 to 49 49 to 51 MD0 to MD2

82 84 V

SS  A/D converter power supply pin.

(CMOS/H)

CC3  3.3 V ± 0.3 V power supply pin (VCC3) .

Input pins for specifying operating mode.

21 23 VCC5  3.3 V ± 0.3 V/5.0 V ± 0.5 V dual power supply pin (VCC5) .

9 40 79

11 42 81

SS  Power supply input pins (GND) .

LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package

Notes : • For use as a 3.3 V single supply de vice, apply the same v oltage to the V

• For use with a dual power supply, apply the respective voltages to the V

CC3 and VCC5 power supply pins. CC3 and VCC5 power supply pins.

• In use with a dual power supply, a total of 32 pins (P20/A16 to P27/A23/PPG3, P30/A00/AIN0 to P37/ A07/PWC1, P40/A08/SIN2 to P47/A15/OUT5 and P70/SIN0 to P77/SDA) can be used in a 5 V interf ace . Note that all other pins must be used in 3 V interface.

• In use with a dual power supply, it is not possible to turn on only the 5 V or the 3 V power supply independently . Alw ays turn on both power supplies simultaneously. (It is recommended that the 3 V power to the MB90470 series be turned on first.)

MB90470 Series

I/O CIRCUIT TYPES

■

Type Circuit Remarks

X1, X1A

Oscillator feedback resistance :

X0, X0A

Includes standby control

Standby control signal

X1,X0 1 MΩ approx. X1A,X0A 10 MΩ approx.

HYS

CTL

Hysteresis with pull-up resistance Input resistance 50 kΩ approx.

Includes input pull-up resistance control

CMOS level input/output Resistance : 50 kΩ approx.

CMOS

D CMOS level input/output

CMOS

Hysteresis input CMOS level input/output

(Continued)

MB90470 Series

(Continued)

Type Circuit Remarks

Open drain control signal

CMOS

Open drain control signal

HYS

CMOS level input/output Includes open drain control

CMOS level output Hysteresis input Includes open drain control

CMOS

Analog input

Digital output

HYS

CMOS level input/output Analog input

Hysteresis input N-ch open drain output

(Flash model)

Flash model CMOS level input

Control signal

Mode input

Spreading resistance

Includes high voltage control for FLASH test

(Mask version)

HYS

Mask version Hysteresis input port

MB90470 Series

HANDLING DEVICES

■

(1) Strictly observe maximum rated voltages (prevent latchup)

When CMOS integrated circuit devices are subjected to applied voltages higher than V pins other than medium- and high-withstand voltage pins, or to voltages lower than V excess of rated le vels are applied between V

CC and VSS, a phenomenon known as latchup can occur . In a latchup

condition, supply current can increase dramatically and may destroy semiconductor elements. In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings.

Also care must be taken when power to analog systems is switched on or off, to ensure that the analog power supply (AV

CC, AVRH) and analog input do not exceed the digital power supply (VCC) .

(2) Treatment of unused pins

If unused input pins are left open, abnormal operation or latchup may cause permanent damage to the semiconductor. Any such pins should be pulled up or pulled down through resistance of at least 2 kΩ.

Also any unused input/output pins should be left open in output status, or if set to input status should be treated in the same way as input pins.

(3) Precautions for use of external clock signals

CC at input and output

SS, or when voltages in

Even when an external clock is used, a stabilization period is required following a power-on reset or release from sub clock mode or stop mode. Also, when an e xternal clock is used 20 MHz should be used as a guideline for an upper frequency limit. The following figure shows a sample use of external clock signals.

X1OPEN

(4) Power supply pins

When using multiple V

CC/VSS sources, always mak e sure to design devices with e xternal connections of all power

supply pins to supply or ground elements, in order to prevent latchup, reduce unwanted radiation, and prevent abnormal strobe signal operation due to rise in ground level, as well as to maintain total rated output current. In addition, care must be given to connecting the V

CC and VSS pins of this device to a current source with as little

impedance as possible. It is recommended that a bypass capacitor of 1.0 µF be connected between V V

SS as close to the pins as possible.

CC and

(5) Crystal oscillator circuits

Abnormal operation of this device can result from noise in the proximity of the X0/X1 and X0A/X1A pins. For stable operation, it is strongly recommended that the printed circuit artwork provide capacitors placed as close as possible between the X0/X1, X0A/X1A and crystal oscillator (or ceramic oscillator) as well as ground, and be wired so as to avoid crossing other wiring wherever possible.

MB90470 Series

(6) Precautions for use of external oscillators (crystals)

The target value for the upper limit of oscillator (crystals) frequencies should be 20 MHz. Also, when operating at internal frequencies of 16 MHz, the PLL multiplier should be used.

(7) Proper power-on/off sequence

The A/D converter power (A V supply (V

CC) is turned on. The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be shut

off before the digital power supply (V

CC, A VRH) and analog input (AN0 to AN7) must be turned on after the digital power

CC) is shut off. Care should be taken that AVRH does not exceed AVCC. Even

when pins used as analog input pins are doubled as input ports, be sure that the input voltage does not exceed AV

CC.

Note : VCC = VCC3 = VCC5

(8) Treatment of A/D converter power supply pins

Even if the A/D converter is not used, pins should be connected so that AV

CC = AVRH = VCC, and AVSS = VSS.

(9) Power-on procedures

In order to prevent abnormal operation of the internal built-in step-down circuits, voltage r ise during power-on should be attained within 50 µs (0.2 V to 2.7 V) .

(10) Stable power supply

Even within the operating range of the V

CC supply voltage, rapid changes in supply v oltage may cause abnormal

operation. As a basis for stab le operation, it is recommended that v oltage variation be restricted in order to limit V

CC ripple fluctuations (P-P values) to 10% at commercial frequencies of 50 Hz to 60 Hz, and transient fluctuations

to 0.1 V/ms at instantaneous points such as power switching.

(11) Precautions for use of two power supplies

The MB90470 series usually uses the 3-V power supply as the main power source. With V V

CC5 = 5 V, however, it can interface with P20/A16 to P27/A23/PPG3, P30/A00/AIN0 to P37/A07/PWC1,

CC3 = 3 V and

P40/A08/SIN2 to P47/A15/OUT5, P70/SIN0 to P77/SDA f or the 5-V power supply separetely from the 3-V pow er supply at all operation mode.

(Caution) The analog power supply for the A/D conver ter (AV

CC, AVSS etc.) can only operate with the

3 V system.

(12) Crystal oscillator circuits during power-saving operation

When the power supply is lower than 2.0 V, the external crystal oscillator may not operate even when power is on. For this reason, the use of an external clock signal is recommended.

(13) Caution : low-voltage flash models (2.4 V to 3.6 V/10 MHz) do not have security functions

(14) Treatment of unused input pins

N.C. (internally connected) pins should always be left open.

(15) When the dual-supply MB90470 series is used as a 1-supply device, use connections so that

X0A

====

, and X1A

====

Open.

MB90470 Series

(16) For serial writing to flash memory, always make sure that the operating voltage V

and 3.6 V. For normal writing to flash memory, always make sure that the operating voltage V

3.0 V and 3.6 V.

(17) Caution on Operations during PLL Clock Mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit ev en when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.

is between 3.13 V

is between

BLOCK DIAGRAM

■

MB90470 Series

X0, X1, RST X0A, X1A MD2, MD1, MD0

SIN0 SOT0 SCK0

SIN1, SIN2 SOT1, SOT 2 SCK1, SCK2

AVCC AVRH AVSS ADTG AN0 to AN7

Communication prescaler

I/O expansion serial

interface × 2 channels

Clock

control circuit

RAM

ROM

µDMA

UART

A/D converter

(10-bit)

CPU FMC-16LX series core

Interrupt controller

PPG0, PPG1

8/16-bit PPG

8/16-bit

up/down counter

MC-16LX BUS

16-bit input capture × 2

16-bit output compare × 6

µPG

Chip select

Input/output timer

16-bit free-run timer

16-bit reload timer

PPG2, PPG3 PPG4, PPG5

AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1

EXTC MT00 MT01

CS0, CS1, CS2, CS3

IN0, IN1 OUT0, OUT1,

OUT2, OUT3, OUT4, OUT5

TIN0 TOT0

PWC0 PWC1 PWC2

16-bit PWC 3 channels

External interrupt

I/O ports

888888888

P00

P10

P20

P30

P40

P50

P60

P70

∼

P07

∼

P17

∼

P27

∼

P37

∼

P47

∼

P57

∼

P67

∼

P77

P80

∼

P87

C interface

P90

∼

P97

PA0 PA3

∼

SCL SDA

IRQ0 to IRQ7

P00 to P07 (8 pins) : Input pull-up resistance setting register provided. P10 to P17 (8 pins) : Input pull-up resistance setting register provided. P40 to P47 (8 pins) : Open drain setting register provided. P70 to P75 (6 pins) : Open drain setting register provided. P76, P77 (2 pins) : Open drain

Note : In the above diagram, I/O ports are shown sharing pin numbers with the built-in function blocks. However

pins may not be used as I/O ports when they are in use as pins for build-in function modules.

MB90470 Series

MEMORY MAP

■

FFFFFFH

Address 1#

010000H

004000H

Address 2#

000100H

0000D0H

Single chip Internal ROM external bus

ROM area ROM area

ROM area

FF bank image

ROM area

FF bank image

RAMRAM

External ROM external bus

RAMRegisterRegister Register

Peripheral Peripheral Peripheral

000000H

: Internal : External : Access not available

* : In models where address 2# coincides with 004000H, there is no external area.

Model Address 1# Address 2#

MB90473 FE0000 MB90474 FC0000H 004000H

MB90477/478 FC0000H 002100H

MB90F474 FC0000H 004000H

MB90V470 (FC0000H) 004000H

The image of FF bank ROM is reflected in the top of the 00 bank, for greater efficiency in using the C compiler for small models. The lower 16-bit address on the FF bank is the same as the lower 16-bit address on the 00 bank, so that it is possible to reference tables in ROM without using the pointer for a far specification.

For example, when accessing 00C000

H, it is actually the content of ROM at FFC000H that is accessed. Here,

because the ROM area on the FF bank exceeds 48 KB, it is not possib le to vie w the entire area in the image on the 00 bank. Therefore, the image from FF4000

H to FFFFFFH is visible on the 00 bank, and FF0000H to FF3FFFH

is visible only on the FF bank.

H 002900H

MC-16L CPU PROGRAMMING MODEL

■

•

Special purpose registers

MB90470 Series

AH AL

USP SSP

PS PC

16 bit

32 bit

DPR

PCB DTB USB SSB

ADB

8 bit

Accumulator

User stack pointer System stack pointer Processor status Program counter

Direct page register

Program bank register Data bank register User stack bank register System stack bank register

Additional data bank register

•

General purpose registers

000180

•

Processor status

15 13

PS RP CCR

ILM

MSB LSB

H + RP × 10H

12 8 70

16 bit

RW0 RW1 RW2

RW3 R1 R0 R3 R2 R5 R7 R6

RL0

RL1

RW4

RL2

RW5 RW6

RL3

RW7

MB90470 Series

O MAP

■I/

Address Register name Symbol Access Resource name Default

H Port 0 data register PDR0 R/W Port 0 XXXXXXXX

H Port 1 data register PDR1 R/W Port 1 XXXXXXXX

H Port 2 data register PDR2 R/W Port 2 XXXXXXXX

H Port 3 data register PDR3 R/W Port 3 XXXXXXXX

04H Port 4 data register PDR4 R/W Port 4 XXXXXXXX 05

H Port 5 data register PDR5 R/W Port 5 XXXXXXXX

H Port 6 data register PDR6 R/W Port 6 XXXXXXXX

07H Port 7 data register PDR7 R/W Port 7 1 1XXXXXX 08

H Port 8 data register PDR8 R/W Port 8 XXXXXXXX

H Port 9 data register PDR9 R/W Port 9 XXXXXXXX

0AH Port A data register PDRA R/W Port A - - - - XXXX 0B

H Port 3 timer input enable register UDRE R/W

H Interrupt/DTP enable register ENIR R/W

0DH Interrupt/DTP enable register EIRR R/W 0 0 0 0 0 0 0 0 0E

H Demand level setting register

R/W 0 0 0 0 0 0 0 0

Up/down timer

input control

DTP/external

interrupt

XX 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ELVR

H Demand level setting register R/W 0 0 0 0 0 0 0 0

H Port 0 direction register DDR0 R/W Port 0 0 0 0 0 0 0 0 0

11H Port 1 direction register DDR1 R/W Port 1 0 0 0 0 0 0 0 0 12

H Port 2 direction register DDR2 R/W Port 2 0 0 0 0 0 0 0 0

H Port 3 direction register DDR3 R/W Port 3 0 0 0 0 0 0 0 0

14H Port 4 direction register DDR4 R/W Port 4 0 0 0 0 0 0 0 0 15

H Port 5 direction register DDR5 R/W Port 5 0 0 0 0 0 0 0 0

H Port 6 direction register DDR6 R/W Port 6 0 0 0 0 0 0 0 0

17H Port 7 direction register DDR7 R/W Port 7 - - 0 0 0 0 0 0 18

H Port 8 direction register DDR8 R/W Port 8 0 0 0 0 0 0 0 0

H Port 9 direction register DDR9 R/W Port 9 0 0 0 0 0 0 0 0

1AH Port A direction register DDRA R/W Port A - - - - 0 0 0 0 1B

H Port 4 pin register ODR4 R/W Port 4 (OD control) 0 0 0 0 0 0 0 0

H Port 0 resistance register RDR0 R/W Port 0 (pull-up) 0 0 0 0 0 0 0 0

1DH Port 1 resistance register RDR1 R/W Port 1 (pull-up) 0 0 0 0 0 0 0 0 1E

H Port 7 pin register ODR7 R/W Port 7 (OD control) - - 0 0 0 0 0 0

H Analog input enable register ADER R/W Port 5, A/D 1 1 1 1 1 1 1 1

(Continued)

MB90470 Series

Address Register name Symbol Access Resource name Default

H Serial mode register 0 SMR0 R/W

21H Serial control register 0 SCR0 R/W 0 0 0 0 0 1 0 0 22 23

Serial input register/ serial output

H Serial status register SSR0 R/W 0 0 0 0 1 0 0 0 H Reserved

SIDR/

SODR0

R/W XXXXXXXX

25H Clock divider control register CDCR R/W 26

H Serial mode control status register 0 SMCS0 R/W

UART0

Communication

prescaler (UART)

0 0 0 0 0 X 0 0

0 0 - - 0 0 0 0

- - - - 0 0 0 0

H Serial mode control status register 0 SMCS0 R/W 0 0 0 0 0 0 1 0

SCI1 (ch0)

28H Serial data register SDR0 R/W XXXXXXXX 29

H Clock divider control register SDCR0 R/W

H Serial mode control status register 1 SMCS1 R/W

2BH Serial mode control status register 1 SMCS1 R/W 0 0 0 0 0 0 1 0 2C

H Serial data register SDR1 R/W XXXXXXXX

H Clock divider control register SDCR1 R/W

2EH PPG reload register L (ch0) PRLL0 R/W 2F

H PPG reload register H (ch0) PRLH0 R/W XXXXXXXX

H PPG reload register L (ch1) PRLL1 R/W XXXXXXXX

H PPG reload register H (ch1) PRLH1 R/W XXXXXXXX

Communication

prescaler (SCI0)

SCI2 (ch1)

Communication

prescaler (SCI1)

0 - - - 0 0 0 0

- - - - 0 0 0 0

0 - - - 0 0 0 0

XXXXXXXX

32H PPG reload register L (ch2) PRLL2 R/W XXXXXXXX 33

H PPG reload register H (ch2) PRLH2 R/W XXXXXXXX

H PPG reload register L (ch3) PRLL3 R/W XXXXXXXX

35H PPG reload register H (ch3) PRLH3 R/W XXXXXXXX 36

H PPG reload register L (ch4) PRLL4 R/W XXXXXXXX

H PPG reload register H (ch4) PRLH4 R/W XXXXXXXX

8/16-bit PPG

(ch0-ch5)

38H PPG reload register L (ch5) PRLL5 R/W XXXXXXXX 39

H PPG reload register H (ch5) PRLH5 R/W XXXXXXXX

H PPG0 operating mode control register PPGC0 R/W 0 X 0 0 0XX 1

3BH PPG1 operating mode control register PPGC1 R/W 0 X 0 0 0 0 0 1 3C

H PPG2 operating mode control register PPGC2 R/W 0 X 0 0 0XX 1

H PPG3 operating mode control register PPGC3 R/W 0 X 0 0 0 0 0 1

H PPG4 operating mode control register PPGC4 R/W 0 X 0 0 0XX 1

3FH PPG5 operating mode control register PPGC5 R/W 0 X 0 0 0 0 0 1 40

H PPG0, 1 output control register PPG01 R/W 8/16-bit PPG 0 0 0 0 0 0 0 0

(Continued)

MB90470 Series

Address Register name Symbol Access Resource name Default

H Reserved

42H PPG2, 3 output control register PPG23 R/W 8/16-bit PPG 0 0 0 0 0 0 0 0 43

H Reserved

H PPG4, 5 output control register PPG45 R/W 8/16-bit PPG 0 0 0 0 0 0 0 0

H Reserved

46H

ADCS1 R/W

Control status register

H ADCS2 R/W 0 0 0 0 0 0 0 0

A/D converter

ADCR1 R XXXXXXXX

Data register

H ADCR2 R 0 0 0 0 0 XXX

49 4A

H Output compare register (ch0) low

OCCP0 R/W

H Output compare register (ch0) high XXXXXXXX

4CH Output compare register (ch1) low

OCCP1 R/W

H Output compare register (ch1) high XXXXXXXX

0 0 0 0 0 0 0 0

XXXXXXXX

H Output compare register (ch2) low

XXXXXXXX

OCCP2 R/W

4FH Output compare register (ch2) high XXXXXXXX 50

H Output compare register (ch3) low

OCCP3 R/W

H Output compare register (ch3) high XXXXXXXX

52H Output compare register (ch4) low

16-bit output timer

output compare

(ch0-ch5)

XXXXXXXX

OCCP4 R/W

H Output compare register (ch4) high XXXXXXXX

H Output compare register (ch5) low

XXXXXXXX

OCCP5 R/W

H Output compare register (ch5) high XXXXXXXX

56H Output compare control register (ch0) OCS0 R/W 0 0 0 0 - - 0 0 57

H Output compare control register (ch1) OCS1 R/W - - - 0 0 0 0 0

H Output compare control register (ch2) OCS2 R/W 0 0 0 0 - - 0 0

59H Output compare control register (ch3) OCS3 R/W  - - - 0 0 0 0 0 5A

H Output compare control register (ch4) OCS4 R/W

H Output compare control register (ch5) OCS5 R/W - - - 0 0 0 0 0

5CH Input capture register (ch0) low

16-bit output timer

OCU (ch4, 5)

0 0 0 0 - - 0 0

XXXXXXXX

IPCP0

H Input capture register (ch0) high R XXXXXXXX

H Input capture register (ch1) low

IPCP1

R XXXXXXXX

16-bit output timer Input capture (ch0, 1)

5FH Input capture register (ch1) high R XXXXXXXX

H Input capture control register ICS01 R/W 0 0 0 0 0 0 0 0

H Reserved

(Continued)

MB90470 Series

Address Register name Symbol Access Resource name Default

H Timer data register low TCDT R/W

63H Timer data register high TCDT R/W 0 0 0 0 0 0 0 0 64

H Timer control status register TCCS R/W 0 0 0 0 0 0 0 0

H Timer control status register TCCS R/W 0 - - 0 0 0 0 0

H Compare clear register low

16-bit output timer

Free run timer

CPCLR R/W

67H Compare clear register high XXXXXXXX 68

H Up down count register ch0 UDCR0 R

H Up down count register ch1 UDCR1 R 0 0 0 0 0 0 0 0

6AH Reload compare register ch0 RCR0 W 0 0 0 0 0 0 0 0 6B

H Reload compare register ch1 RCR1 W 0 0 0 0 0 0 0 0

H Counter control register low ch0 CCRL0 R/W 0 X 0 0 X 0 0 0

8/16-bit up-down

timer-counter

6DH Counter control register high ch0 CCRH0 R/W 0 0 0 0 0 0 0 0 6E

H Reserved

0 0 0 0 0 0 0 0

XXXXXXXX

0 0 0 0 0 0 0 0

H ROM mirror function select register ROMM W ROM mirror function - - - - - - - 1

70H Counter control register low ch1 CCRL1 R/W 71

H Counter control register high ch1 CCRH1 R/W - 0 0 0 0 0 0 0

H Count status register ch0 CSR0 R/W 0 0 0 0 0 0 0 0

8/16-bit up-down

timer-counter

0 X 0 0 X 0 0 0

73H Reserved 74

H Count status register ch1 CSR1 R/W 8/16-bit UDC 0 0 0 0 0 0 0 0

H Reserved

0 0 0 0 0 0 0 0

PWC0 control status register PWCSR0 R/W

H 0 0 0 0 0 0 0 X

16-bit PWC timer

(ch0)

0 0 0 0 0 0 0 0

PWC0 data buffer register PWCR0 R/W

H 0 0 0 0 0 0 0 0

7AH

0 0 0 0 0 0 0 0

PWC1 control status register PWCSR1 R/W

H 0 0 0 0 0 0 0 X

16-bit PWC timer

(ch1)

0 0 0 0 0 0 0 0

PWC1 data buffer register PWCR1 R/W

H 0 0 0 0 0 0 0 0

7D 7E

0 0 0 0 0 0 0 0

PWC2 control status register PWCSR2 R/W

H 0 0 0 0 0 0 0 X

80H

16-bit PWC timer

(ch2)

0 0 0 0 0 0 0 0

PWC2 data buffer register PWCR2 R/W

H 0 0 0 0 0 0 0 0

H PWC0 division ratio register DIVR0 R/W PWC (ch0) - - - - - - 0 0

H Reserved

84H PWC1 division ratio register DIVR1 R/W PWC (ch1) - - - - - - 0 0 85

H Reserved

(Continued)

MB90470 Series

Address Register name Symbol Access Resource name Default

H PWC2 division ratio register DIVR2 R/W PWC (ch2) - - - - - - 0 0

87H Reserved 88

89 8A 8BH I 8C 8D 8EH µPG control register PGCSR R/W µPG 0 0 0 0 0 - - -

H to 9BH Prohibited

9C 9DH µDMA status register DSRH R/W µDMA 0 0 0 0 0 0 0 0

H I H I

H I

H I H Reserved

H µDMA status register DSRL R/W µDMA 0 0 0 0 0 0 0 0

C bus status register IBSR R

C bus control register IBCR R/W 0 0 0 0 0 0 0 0

C bus clock select register ICCR R/W - - 0XXXXX

C bus address register IADR R/W - XXXXXXX

C bus data register IDAR R/W XXXXXXXX

C functions

0 0 0 0 0 0 0 0

Program address detection control

status resister Delay interrupt source generate/

release register

PACSR R/W

DIRR R/W

Address Match

Detection Function

Delay interrupt

generator module

0 0 0 0 0 0 0 0

- - - - - - - - 0

A0H Low power mode register LPMCR R/W Low power modes 0 0 0 1 1 0 0 0 A1

H Clock select register CKSCR R/W Low power modes 1 1 1 1 1 1 0 0

H, A3H Reserved

H µDMA stop status register DSSR R/W µDMA 0 0 0 0 0 0 0 0

A5H Auto ready function select register ARSR W External pins 0 0 1 1 - - 0 0 A6 A7

External address output control

H Bus control signal control register EPCR W External pins 1 0 0 0 * 1 0 -

HACR W External pins 0 0 0 0 0 0 0 0

A8H Watchdog control register WDTC R/W Watchdog timer XXXXX 1 1 1 A9

H Time base timer control register TBTC R/W Time base timer 1 X X 0 0 1 0 0

H Watch timer control register WTC R/W Watch timer 1 0 0 0 1 0 0 0

ABH Reserved AC

H µDMA control register DERL R/W µDMA 0 0 0 0 0 0 0 0

H µDMA control register DERH R/W µDMA 0 0 0 0 0 0 0 0

AEH Flash memory control status register FMCR R/W

Flash memory

interface

0 0 0 X 0 0 0 0

H Prohibited

H Interrupt control register 00 ICR00 R/W  XXXX 0 1 1 1

H Interrupt control register 01 ICR01 R/W  XXXX 0 1 1 1

B2H Interrupt control register 02 ICR02 R/W  XXXX 0 1 1 1 B3

H Interrupt control register 03 ICR03 R/W  XXXX 0 1 1 1

(Continued)

MB90470 Series

Address Register name Symbol Access Resource name Default

H Interrupt control register 04 ICR04 R/W  XXXX 0 1 1 1

H Interrupt control register 05 ICR05 R/W  XXXX 0 1 1 1

H Interrupt control register 06 ICR06 R/W  XXXX 0 1 1 1

H Interrupt control register 07 ICR07 R/W  XXXX 0 1 1 1

B8H Interrupt control register 08 ICR08 R/W  XXXX 0 1 1 1 B9

H Interrupt control register 09 ICR09 R/W  XXXX 0 1 1 1

H Interrupt control register 10 ICR10 R/W  XXXX 0 1 1 1

BBH Interrupt control register 11 ICR11 R/W  XXXX 0 1 1 1

H Interrupt control register 12 ICR12 R/W  XXXX 0 1 1 1

H Interrupt control register 13 ICR13 R/W  XXXX 0 1 1 1

BEH Interrupt control register 14 ICR14 R/W  XXXX 0 1 1 1

H Interrupt control register 15 ICR15 R/W  XXXX 0 1 1 1

H Chip select MASK register 0 CMR0 R/W Chip select functions 0 0 0 0 1 1 1 1

C1H Chip select area register 0 CAR0 R/W  1 1 1 1 1 1 1 1 C2

H Chip select MASK register 1 CMR1 R/W  0 0 0 0 1 1 1 1

H Chip select area register 1 CAR1 R/W  1 1 1 1 1 1 1 1

C4H Chip select MASK register 2 CMR2 R/W  0 0 0 0 1 1 1 1 C5

H Chip select area register 2 CAR2 R/W  1 1 1 1 1 1 1 1

H Chip select MASK register 3 CMR3 R/W  0 0 0 0 1 1 1 1

H Chip select area register 3 CAR3 R/W  1 1 1 1 1 1 1 1

C8H Chip select control register CSCR R/W  - - - - 0 0 0 * C9

H Chip select control active level register CALR R/W  - - - - 0 0 0 0

0 0 0 0 0 0 0 0

Timer control status registers TMCSR R/W

H - - - - 0 0 0 0

16-bit reload timer

16-bit timer register 16-bit reload register

TMR/

TMRLR

R/W XXXXXXXX

CEH, CFH Reserved

H to FFH External area

100

H to #H RAM area

1FF0

Program address detection resister0

(Low order address)

Program address detection resister0

(Middle order address)

PADR0 R/W

Address Match

Detection Function

XXXXXXXX1FF1

1FF2

Program address detection resister0

(High order address)

(Continued)

MB90470 Series

(Continued)

Address Register name Symbol Access Resource name Default

1FF3

1FF5

Interrupt symbols : R/W : Read/write enabled R : Read only W : Write only

Default value symbols : 0 : This bit initialized to “0” 1 : This bit initialized to “1” * : This bit initialized to “0” or “1” X : Default value undefined

- : This bit is not used.

Program address detection resister1

(Low order address)

Program address detection resister1

(Middle order address)

Program address detection resister1

(High order address)

PADR1 R/W

Address Match

Detection Function

XXXXXXXX1FF4

MB90470 Series

INTERRUPT SOURCES, INTERRUPT VECTORS & INTERRUPT CONTROL REGISTERS

■

Interrupt control

Interrupt source

support

µµµµ

DMA

channel no.

Interrupt vector

No. Address No. Address

Reset #08 FFFFDC INT9 instruction #09 FFFFD8

H 

Exception #10 FFFFD4H  INT0 0 #11 FFFFD0

ICR00 0000B0H

INT1 × #12 FFFFCCH INT2 × #13 FFFFC8H

ICR01 0000B1H

INT3 × #14 FFFFC4H INT4 × #15 FFFFC0H

ICR02 0000B2H

INT5 × #16 FFFFBCH INT6 × #17 FFFFB8H

ICR03 0000B3H

INT7 × #18 FFFFB4H PWC1 × #19 FFFFB0H

ICR04 0000B4H

PWC2 × #20 FFFFACH PWC0 1 #21 FFFFA8H

ICR05 0000B5H

PPG0/PPG1 counter borrow 2 #22 FFFFA4H PPG2/PPG3 counter borrow 3 #23 FFFFA0H PPG4/PPG5 counter borrow 4 #24 FFFF9CH 8/16-bit

up/down counter timer compare/ underflow /overflow/

× #25 FFFF98

amp down inversion (ch0, 1) Input capture (ch0) load 5 #26 FFFF94H Input capture (ch1) load 6 #27 FFFF90H Output compare (ch0) match 8 #28 FFFF8CH Output compare (ch1) match 9 #29 FFFF88H Output compare (ch2) match 10 #30 FFFF84H Output compare (ch3) match × #31 FFFF80H Output compare (ch4) match × #32 FFFF7CH Output compare (ch5) match × #33 FFFF78H UART send end 11 #34 FFFF74H 16-bit free run timer/

16-bit reload timer overflow

12 #35 FFFF70

UART receive end 7 #36 FFFF6CH

ICR06 0000B6H

ICR07 0000B7H

ICR08 0000B8H

ICR09 0000B9H

ICR10 0000BAH

ICR11 0000BBH

ICR12 0000BCH

(Continued)

MB90470 Series

(Continued)

Interrupt source

support

µµµµ

DMA

channel no.

Interrupt vector

Interrupt control

No. Address No. Address

SIO1 13 #37 FFFF68

ICR13 0000BDH

SIO2 14 #38 FFFF64H I2C interface ××#39 FFFF60H

ICR14 0000BEH

A/D 15 #40 FFFF5CH Flash write/erase, time base timer,

watch timer*

××#41 FFFF58H

ICR15 0000BFH

Delay interrupt generator module ××#42 FFFF54H

: Interrupt request flag cleared by the interrupt clear signal. The stop request is available. : Interrupt request flag cleared by the interrupt clear signal.

× : Interrupt request flag not cleared by the interrupt clear signal.

* : Note that flash write/erase cannot be used at the same time as the time base timer or watch timer.

Note : • If two or more interrupt sources have the same interrupt number, the resource will clear both interrupt

request flags at the EI

OS/DMAC interrupt clear signal. Thus when EI2OS/µDMA function of two sources is used, the other interrupt function cannot be used. The interrupt request enable bit of the corresponding resource should be set to “0” for software polling processing.

• Maximum assured operation frequency of µDMA is 16 MHz.

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