FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13712-4E
16-Bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90470 Series
MB90473/474/477/478/F474L/F474H
DESCRIPTIONS
■
The FUJITSU MB90470 Series is a 16-bit general-purpose microcontroller designed for consumer products and
other process control applications requiring high-speed and real-time processing.
2
The F
MC-16LX CPU core instruction set retains the AT architecture of the F2MC*1 family, with additional instructions for use with high-level languages, expanded addressing mode, enhanced multiply and divide instructions,
and full bit processing. Also included is a built-in 32-bit accumulator for long-word processing.
Peripheral resources built into the MB90470 ser ies include 8/16-bit PPG, expanded I/O serial interface, UART,
10-bit A/D converter, 16-bit input-output timer, 8/16-bit up-counter, PWC timer, I
interrupt, chip select, and 16-bit reload timer.
2
*1 : F
MC is an abbreviation for FUJITSU Flexible Microcontroller, and is a registered trademark of FUJITSU, Ltd.
2
*2 : I
C license :
This product includes licensing of Philips I
standard specifications established by Philips.
PACKAGES
■
100-pin plastic QFP 100-pin plastic LQFP
(FPT-100P-M06) (FPT-100P-M05)
2
C patents if used by the customer in an I2C system subject to the I2C
2C*2
interface, DTP/exter nal
MB90470 Series
FEATURES
■
•
Clocks
Minimum instruction execution time :
50.0 ns at 5 MHz base oscillation with 4 × multiplier (internal operation at 20 MHz/3.3 V ± 0.3 V)
62.5 ns at 4 MHz base oscillation with 4 × multiplier (internal operation at 16 MHz/3.0 V ± 0.3 V)
Uses PLL clock multiplier.
•
Maximum memory size
16 Mbytes
•
Instruction set optimized for control applications
Handles bit, byte, word, long-word data
23 standard addressing modes
32-bit accumulator for enhanced high-precision calculation
Signed multiply-divide and expanded RETI instructions
•
Instruction system compatible with high-level language (C) multitasking
System stack pointer
Instruction set correlation and barrel shift instructions
• Non-multi bus or multi-bus compatible
• Program patch function (for two address pointers)
•
Improved execution speed
4-byte queue
•
Powerful interrupt functions
8 external interrupt functions with 8-level programmable priority
•
Data transfer functions
16 channels maximum
µDMA maximum assured operation frequency : 16 MHz
Extended intelligent I/O service maximum assured operation frequency : 20 MHz
•
Built-in ROM
Flash versions : 256 KB, Mask ROM versions : 128 KB/256 KB
•
Built-in RAM
10 KB/16 KB
•
General purpose ports
84 ports maximum
(includes 16 ports with input pull-up resistance setting, 14 ports with output open drain setting)
•A/
D converter
RC sequential comparator type, 8 channels
10-bit resolution, conversion time 4.65 µs (at 20 MHz operation)
2
C interface
•
I
1 channel
• µµµµ
PG
1 channel
•
UART
1 channel
•I/
O expansion serial interface (SIO
2 channels
•8/16-
•16-
bit up/down timer
1 channel
bit PWC
3 channels (including 2-channel input comparison function)
(µµµµ
DMA or Extended intelligent I/O service
)
)
(Continued)
2
MB90470 Series
(Continued)
•16-
bit reload timer
1 channel (8-bit × 2-channel, 16-bit × 1-channel mode switching function provided)
•16-
bit input-output timer
2-channel input capture, 6-channel output compare, 1-channel free run timer
• 2 built-in clock generator systems
•
Low power modes
Stop, sleep, CPU intermittent mode, watch mode, etc.
•
Package options
QFP100/LQFP100
•
Process
CMOS technology
•
Supply voltage
Can operate on 3 V single supply systems (with 5 V interface provided by some pins with 3/5 V dual-supply
capability)
3
MB90470 Series
PRODUCT LINEUP
■
Part number
Parameter
ROM capacity FLASH 256 KB FLASH 256 KB
RAM capacity 16 KB 16 KB 10 KB 16 KB
CPU functions
Ports
UART Stop-start synchronized : 1 channel
8/16-bit PPG timer 8-bit 6-channel/16-bit 3-channel
8/16-bit up-down counter/timer
-bit free-run timer
16-bit
input/
output
timers
DTP/external interrupt circuit External interrupt pins : 8 channels (set to edge or level correlation)
I/O expansion serial interface 2-channel, built-in
2
I
Time base timer
A/D converter
Watchdog timer
Low power (standby) modes Sleep, stop, CPU intermittent, watch mode
Process CMOS
Notes
Emulator dedicated power supply
16
Output compare
Input capture (ICU)
C interface 1-channel, built-in
(OCU)
MB90F474L MB90F474H MB90473 MB90474
MASKROM
128 KB
Basic instructions
Instruction bit length
Instruction length
Data bit length
Minimum instruction execution time
General purpose input/output ports : 84 Max
General purpose input/output ports (CMOS output)
General purpose input/output ports (built-in pull-up resistance)
General purpose input/output ports (N-ch open drain)
Two 8-bit up-down counters with 6 event input pins
Two 8-bit reload/compare registers
Channel : 1
Overflow interrupt
Channels : 6
Pin input source : from compare register match signal
Channels : 2
Register rewritten from pin input (rising/falling/both edges)
18-bit counter
Interrupt cycle : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms
(minimum times, at base oscillator frequency 4 MHz)
Conversion accuracy : 8/10-bit switchable
Single conversion mode (converts selected channel 1 time only)
Scan conversion mode
(converts multiple consecutive channels, programmable up to 8 channels)
Continuous conversion mode (converts selected channels continuously)
Stop conversion mode (converts selected channel, stops and repeats)
Reset interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(minimum times, at base oscillator frequency 4 MHz)
Flash model, low
voltage version
(f = 10 MHz or
less at V
CC = 2.4 V)
Flash model, high
voltage version
(f = 20 MHz)
: 351
: 8-bit, 16-bit
: 1 byte to 7 bytes
: 1-bit, 8-bit, 16-bit
: 62.5 ns (with 16 MHz machine clock)
Mask version Mask version
MASKROM
256 KB
(Continued)
4
MB90470 Series
(Continued)
Part number
Parameter
ROM capacity
RAM capacity 8 KB 8 KB 16 KB
Basic instructions
Instruction bit length
CPU functions
Ports
UART Stop-start synchronized : 1 channel
8/16-bit PPG timer 8-bit 6-channel/16-bit 3-channel
8/16-bit up-down counter/timer
16-bit free-run timer
16-bit
input/
output
timers
DTP/external interrupt circuit External interrupt pins : 8 channels (set to edge or level correlation)
I/O expansion serial interface 2-channel, built-in
2
I
C interface 1-channel, built-in
Time base timer
A/D converter
Watchdog timer
Low power (standby) modes Sleep, stop, CPU intermittent, watch mode
Process CMOS
Notes Mask version
Emulator dedicated power supply Included
Output compare (OCU)
Input capture (ICU)
Instruction length
Data bit length
Minimum instruction execution time
General purpose input/output ports : 84 Max
General purpose input/output ports (CMOS output)
General purpose input/output ports (built-in pull-up resistance)
General purpose input/output ports (N-ch open drain)
Two 8-bit up-down counters with 6 event input pins
Two 8-bit reload/compare registers
Channel : 1
Overflow interrupt
Channels : 6
Pin input source : from compare register match signal
Channels : 2
Register rewritten from pin input (rising/falling/both edges)
18-bit counter
Interrupt cycle : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms
(minimum times, at base oscillator frequency 4 MHz)
Conversion accuracy : 8/10-bit switchable
Single conversion mode (converts selected channel 1 time only)
Scan conversion mode
(converts multiple consecutive channels, programmable up to 8 channels)
Continuous conversion mode (converts selected channels continuously)
Stop conversion mode (converts selected channel, stops and repeats)
Reset interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(minimum times, at base oscillator frequency 4 MHz)
MB90477 MB90478 MB90V470B
MASKROM
256 KB
MASKROM
256 KB
Mask version without
built-in interface
2
C
I
: 351
: 8-bit, 16-bit
: 1 byte to 7 bytes
: 1-bit, 8-bit, 16-bit
: 50 ns (with 20 MHz
machine clock)
EVA function
User pin
5
MB90470 Series
PIN ASSIGNMENTS
■
(TOP VIEW)
P21/A17
P22/A18
P23/A19
P24/A20/PPG0
P25/A21/PPG1
P26/A22/PPG2
P27/A23/PPG3
P30/A00/AIN0
P31/A01/BIN0
P32/A02/ZIN0
P33/A03/AIN1
P34/A04/BIN1
P35/A05/ZIN1
P36/A06/PWC0
P37/A07/PWC1
P40/A08/SIN2
P41/A09/SOT2
P42/A10/SCK2
P43/A11/MT00
P44/A12/MT01
P45/A13/EXTC
P46/A14/OUT4
P47/A15/OUT5
VSS
CC5
V
P70/SIN0
P71/SOT0
P72/SCK0
P73/TIN0
P17/AD15/D15
P16/AD14/D14
P15/AD13/D13
P14/AD12/D12
P13/AD11/D11
P12/AD10/D10
P11/AD09/D09
P10/AD08/D08
P07/AD07/D07
P06/AD06/D06
P05/AD05/D05
P04/AD04/D04
P03/AD03/D03
P02/AD02/D02
99989796959493929190898887868584838281
100
1P20/A16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32333435363738394041424344454647484950
31P74/TOT0
CC3
P01/AD01/D01
P00/AD00/D00
V
X1X0VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
X0A
X1A
P57/CLK
RST
P56/RDY
P55/HAK
P54/HRQ
P53/WRH
P52/WRL
P51/RD
P50/ALE
PA3/OUT3
PA2/OUT2
PA1/OUT1
PA0/OUT0
P97/IN1
P96/IN0
P95/PPG5
P94/PPG4
P93/FRCK/ADTG/CS3
P92/SCK1/CS2
P91/SOT1/CS1
P90/SIN1/CS0
P87/IRQ7
P86/IRQ6
P85/IRQ5
P84/IRQ4
P83/IRQ3
P82/IRQ2
MD2
AVCC
P76/SCL
P77/SDA
P75/PWC2
AVSS
AVRH
P60/AN0
P61/AN1
P62/AN2
Vss
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
P80/IRQ0
P81/IRQ1
MD0
MD1
(FPT-100P-M06)
6
(TOP VIEW)
MB90470 Series
P22/A18
P23/A19
P24/A20/PPG0
P25/A21/PPG1
P26/A22/PPG2
P27/A23/PPG3
P30/A00/AIN0
P31/A01/BIN0
V
SS
P32/A02/ZIN0
P33/A03/AIN1
P34/A04/BIN1
P35/A05/ZIN1
P36/A06/PWC0
P37/A07/PWC1
P40/A08/SIN2
P41/A09/SOT2
P42/A10/SCK2
P43/A11/MT00
P44/A12/MT01
CC5
V
P45/A13/EXTC
P46/A14/OUT4
P47/A15/OUT5
P70/SIN0
P21/A17
P20/A16
P17/AD15/D15
P16/AD14/D13
P15/AD13/D13
P14/AD12/D12
P13/AD11/D11
P12/AD10/D10
P11/AD09/D09
P10/AD08/D08
P07/AD07/D07
P06/AD06/D06
P05/AD05/D05
P04/AD04/D04
P03/AD03/D03
9998979695949392919089888786858483828180797877
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26272829303132333435363738394041424344454647484950
CC3
P02/AD02/D02
P01/AD01/D01
P00/AD00/D00
V
X1X0V
SS
X0A
X1A
P57/CLK
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RST
P56/RDY
P55/HAK
P54/HRQ
P53/WRH
P52/WRL
P51/RD
P50/ALE
PA3/OUT3
PA2/OUT2
PA1/OUT1
PA0/OUT0
P97/IN1
P96/IN0
P95/PPG5
P94/PPG4
P93/FRCK/ADTG/CS3
P92/SCK1/CS2
P91/SOT1/CS1
P90/SIN1/CS0
P87/IRQ7
P86/IRQ6
P85/IRQ5
P84/IRQ4
P83/IRQ3
P73/TIN0
P71/SOT0
P72/SCK0
P76/SCL
P74/TOT0
P75/PWC2
SS
CC
AV
AV
AVRH
P77/SDA
P60/AN0
(FPT-100P-M05)
P61/AN1
P62/AN2
P63/AN3
SS
V
P64/AN4
P65/AN5
P66/AN6
P67/AN7
MD0
P80/IRQ0
P81/IRQ1
MD1
MD2
P82/IRQ2
7
MB90470 Series
PIN DESCRIPTION
■
Pin no.
LQFP QFP
80 82 X0 A Oscillator pin
81 83 X1 A Oscillator pin
78 80 X0A A 32 kHz oscillator pin
77 79 X1A A 32 kHz oscillator pin
75 77 RST
83 to 90 85 to 92
91 to 98
99
100
1
2
3 to 6 5 to 8
93 to
100
1 to 4
Pin name
P00 to P07
AD00 to AD07
D00 to D07
P10 to P17
AD08 to AD15
D08 to D15
P20 to P23
A16 to A19
A16 to A19
P24 to P27
A20 to A23
A20 to A23
PPG0 to PPG3 PPG timer output pins.
Circuit
type
B Reset input pin
General purpose input/output ports. Set the pull-up resistance
setting register (RDR0) to add pull-up resistance (RD00-RD07
= “1” ) . (Not valid when set for output)
C
(CMOS)
C
(CMOS)
E
(CMOS/H)
E
(CMOS/H)
In multiplex mode, these pins function as external address/
data bus lower input/output pins.
In non-multiplex mode, these pins function as external data
bus lower output pins.
General purpose input/output ports. Set the pull-up resistance
setting register (RDR1) to add pull-up resistance (RD10-RD17
= “1” ) . (Not valid when set for output)
In multiplex mode, these pins function as external address/
data bus higher input/output pins.
In non-multiplex mode, these pins function as external data
bus higher output pins.
General purpose input/output ports. In external bus mode, pins
for which the corresponding bit in the external address output
control register (HACR) is “1” function as the general purpose
input/output ports.
In multiplex mode, pins for which the corresponding bit in the
external address output control register (HACR) is “0” function
as the upper address output pins (A16 to A19) .
In non-multiplex mode, pins for which the corresponding bit in
the external address output control register (HACR) is “0”
function as the upper address output pins (A16 to A19) .
General purpose input/output ports. In external bus mode, pins
for which the corresponding bit in the external address output
control register (HACR) is “1” function as the general purpose
input/output ports.
In multiplex mode, pins for which the corresponding bit in the
external address output control register (HACR) is “0” function
as the upper address output pins (A20 to A23) .
In non-multiplex mode, pins for which the corresponding bit in
the external address output control register (HACR) is “0”
function as the upper address output pins (A20 to A23) .
Description
LQFP : FPT-100P-M05 package
QFP : FPT-100P-M06 package
8
(Continued)
MB90470 Series
Pin no.
LQFP QFP
79
810
10 12
11 13
12 14
Pin name
P30
A00
AIN0 8/16-bit up-down timer input pin. (ch0)
P31
A01
BIN0 8/16-bit up-down timer input pin. (ch0)
P32
A02
ZIN0 8/16-bit up-down timer input pin. (ch0)
P33
A03
AIN1 8/16-bit up-down timer input pin. (ch1)
P34
A04
BIN1 8/16-bit up-down timer input pin. (ch1)
Circuit
type
E
(CMOS/H)
E
(CMOS/H)
E
(CMOS/H)
E
(CMOS/H)
E
(CMOS/H)
Description
General purpose input/output port.
In non-multibus bus mode, this pin functions as an external
address pin.
General purpose input/output port.
In non-multibus bus mode, this pin functions as an external
address pin.
General purpose input/output port.
In non-multibus bus mode, this pin functions as an external
address pin.
General purpose input/output port.
In non-multibus bus mode, this pin functions as an external
address pin.
General purpose input/output port.
In non-multibus bus mode, this pin functions as an external
address pin.
P35
13 15
14
15
16 18
17 19
LQFP : FPT-100P-M05 package
QFP : FPT-100P-M06 package
16
17
A05
ZIN1 8/16-bit up-down timer input pin. (ch1)
P36, P37
A06, A07
PWC0, PWC1 Functions as PWC input pin.
P40
A08
SIN2 Single serial I/O input pin
P41
A09
SOT2 Single serial I/O output pin
E
(CMOS/H)
E
(CMOS/H)
G
(CMOS/H)
F
(CMOS)
General purpose input/output port.
In non-multibus bus mode, this pin functions as an external
address pin.
General purpose input/output ports.
In non-multibus bus mode, this pin functions as an external
address pin.
General purpose input/output port.
In non-multibus bus mode, this pin functions as an external
address pin.
General purpose input/output port.
In non-multibus bus mode, this pin functions as an external
address pin.
(Continued)
9
MB90470 Series
Pin no.
LQFP QFP
18 20
19
20
22 24
23
24
68 70
69 71
21
22
25
26
Pin name
P42
A10
SCK2 Single serial I/O clock input/output pin
P43, P44
A11, A12
MT00, MT01 µPG input pins
P45
A13
EXTC µPG input pin
P46, P47
A14, A15
OUT4/OUT5 Output compare event output pins
P50
ALE
P51
RD
Circuit
type
G
(CMOS/H)
F
(CMOS)
G
(CMOS/H)
F
(CMOS)
D
(CMOS)
D
(CMOS)
Description
General purpose input/output port.
In non-multibus bus mode, this pin functions as an external
address pin.
General purpose input/output ports.
In non-multibus bus mode, this pin functions as an external
address pin.
General purpose input/output ports.
In non-multibus bus mode, this pin functions as an external
address pin.
General purpose input/output ports.
In non-multibus bus mode, this pin functions as an external
address pin.
General purpose input/output port. In external bus mode, this
pin functions as the ALE pin
In external bus mode, this pin functions as the address load
enable signal (ALE) pin
General purpose input/output port. In external bus mode, this
pin functions as the RD
In external bus mode, this pin functions as the read strobe
output (RD
) pin.
pin.
70 72
71 73
LQFP : FPT-100P-M05 package
QFP : FPT-100P-M06 package
10
P52
WRL
P53
WRH
D
(CMOS)
D
(CMOS)
General purpose input/output port. In external bus mode, this
pin functions as the WRL
register is set to “1”.
In external bus mode, this pin functions as the lower data write
strobe output (WRL
register is set to “0”,this pin functions as a general purpose
input/output port.
General purpose input/output port. In external bus mode with
16-bit bus width, this pin functions as the WRH
WRE bit in the EPCR register is set to “1”.
In external bus mode with 16-bit bus width, this pin functions
as the higher data write strobe output (WRH
WRE bit in the EPCR register is set to “0”,this pin functions as
a general purpose input/output port.
pin when the WRE bit in the EPCR
) pin. When the WRE bit in the EPCR
pin when the
) pin. When the
(Continued)
MB90470 Series
Pin no.
LQFP QFP
72 74
73 75
74 76
76 78
36 to 39 38 to 41
41 to 44 43 to 46
25 27
26 28
27 29
28 30
29 31
Pin name
P54
HRQ
P55
HAK
P56
RDY
P57
CLK
P60 to P63
AN0 to AN3 Analog input pins.
P64 to P67
AN4 to AN7 Analog input pins.
P70
SIN0 UART data input pin.
P71
SOT0 UART data output pin.
P72
SCK0 UART clock input pin.
P73
TIN0 16-bit reload timer event input pin.
P74
TOT0 16-bit reload timer output pin.
Circuit
type
D
(CMOS)
D
(CMOS)
D
(CMOS)
D
(CMOS)
H
(CMOS)
H
(CMOS)
G
(CMOS/H)
F
(CMOS)
G
(CMOS/H)
G
(CMOS/H)
F
(CMOS)
Description
General purpose input/output port. In external bus mode, this
pin functions as the HRQ pin when the HDE bit in the EPCR
register is set to “1”.
In external bus mode, this pin functions as the hold request
input (HRQ) pin. When the HDE bit in the EPCR register is set
to “0”,this pin functions as a general purpose input/output port.
General purpose input/output port. In external bus mode, this
pin functions as the HAK
register is set to “1”.
In external bus mode, this pin functions as the hold acknowledge output (HAK
is set to “0”,this pin functions as a general purpose input/output
port.
General purpose input/output port. In external bus mode, this
pin functions as the DRY pin when the RYE bit in the EPCR
register is set to “1”.
In external bus mode, this pin functions as the external ready
input (RDY) pin. When the RYE bit in the EPCR register is set
to “0”,this pin functions as a general purpose input/output port.
General purpose input/output port. In external bus mode, this
pin functions as the CLK pin when the CKE bit in the EPCR
register is set to “1”.
In external bus mode, this pin functions as the machine cycle
clock output (CLK) pin. When the CKE bit in the EPCR register
is set to “0”,this pin functions as a general purpose input/output
port.
General purpose input/output ports.
General purpose input/output ports.
General purpose input/output port.
General purpose input/output port.
General purpose input/output port.
General purpose input/output port.
General purpose input/output port.
) pin. When the HDE bit in the EPCR register
pin when the HDE bit in the EPCR
LQFP : FPT-100P-M05 package
QFP : FPT-100P-M06 package
(Continued)
11
MB90470 Series
Pin no.
LQFP QFP
30 32
31 33
32 34
45
46
50 to 55 52 to 57
56 58
57 59
47
48
Pin name
P75
PWC2 PWC input pin.
P76
SCL
P77
SDA
P80, P81
IRQ0, IRQ1 External interrupt input pins.
P82 to P87
IRQ2 to IRQ7 External interrupt input pins.
P90
SIN1 Single serial I/O data input pin.
CS0 Chip select 0.
P91
SOT1 Single serial I/O data output pin.
CS1 Chip select 1.
Circuit
type
G
(CMOS/H)
I
(NMOS/H)
I
(NMOS/H)
E
(CMOS/H)
E
(CMOS/H)
E
(CMOS/H)
D
(CMOS)
Description
General purpose input/output port.
General purpose input/output port.
2
C interface data input/output pin. During I2C interface
I
operation, the port output should be set to High-Z level.
General purpose input/output port.
2
I
C interface clock input/output pin. During I2C interface
operation, the port output should be set to High-Z level.
General purpose input/output ports.
General purpose input/output ports.
General purpose input/output port.
General purpose input/output port.
P92
58 60
59 61
60 62
61 63
62 64
LQFP : FPT-100P-M05 package
QFP : FPT-100P-M06 package
SCK1 Single serial I/O clock input/output pin.
CS2 Chip select 2.
P93
FRCK
ADTG
CS3 Chip select 3.
P94
PPG4 PPG timer output pin.
P95
PPG5 PPG timer output pin.
P96
IN0 Functions as input capture ch 0 trigger input.
E
(CMOS/H)
E
(CMOS/H)
D
(CMOS)
D
(CMOS)
E
(CMOS/H)
General purpose input/output port.
General purpose input/output port.
In free run timer operation, this pin functions as the external
clock input pin.
In A/D converter operation, this pin functions as the external
trigger input pin.
General purpose input/output port.
General purpose input/output port.
General purpose input/output port.
(Continued)
12
(Continued)
Pin no.
LQFP QFP
Pin name
Circuit
type
MB90470 Series
Description
63 65
64 to 67 66 to 69
OUT0 to OUT3 Output compare event output pins.
33 35 AV
P97
IN1 Functions as input capture ch 1 trigger input.
PA0 to PA3
E
(CMOS/H)
D
(CMOS)
CC A/D converter power supply pin.
General purpose input/output port.
General purpose input/output ports.
34 36 AVRH A/D converter external reference power pin.
35 37 AV
47 to 49 49 to 51 MD0 to MD2
82 84 V
SS A/D converter power supply pin.
J
(CMOS/H)
CC3 3.3 V ± 0.3 V power supply pin (VCC3) .
Input pins for specifying operating mode.
21 23 VCC5 3.3 V ± 0.3 V/5.0 V ± 0.5 V dual power supply pin (VCC5) .
9
40
79
11
42
81
V
SS Power supply input pins (GND) .
LQFP : FPT-100P-M05 package
QFP : FPT-100P-M06 package
Notes : • For use as a 3.3 V single supply de vice, apply the same v oltage to the V
• For use with a dual power supply, apply the respective voltages to the V
CC3 and VCC5 power supply pins.
CC3 and VCC5 power supply pins.
• In use with a dual power supply, a total of 32 pins (P20/A16 to P27/A23/PPG3, P30/A00/AIN0 to P37/
A07/PWC1, P40/A08/SIN2 to P47/A15/OUT5 and P70/SIN0 to P77/SDA) can be used in a 5 V interf ace .
Note that all other pins must be used in 3 V interface.
• In use with a dual power supply, it is not possible to turn on only the 5 V or the 3 V power supply
independently . Alw ays turn on both power supplies simultaneously. (It is recommended that the 3 V power
to the MB90470 series be turned on first.)
13
MB90470 Series
I/O CIRCUIT TYPES
■
Type Circuit Remarks
X1, X1A
Oscillator feedback resistance :
A
X0, X0A
Includes standby control
Standby control
signal
X1,X0 1 MΩ approx.
X1A,X0A 10 MΩ approx.
B
HYS
CTL
Hysteresis with pull-up resistance
Input resistance 50 kΩ approx.
Includes input pull-up resistance control
C
CMOS level input/output
Resistance : 50 kΩ approx.
CMOS
D CMOS level input/output
CMOS
14
E
CMOS
Hysteresis input
CMOS level input/output
(Continued)
MB90470 Series
(Continued)
Type Circuit Remarks
Open drain
control signal
F
CMOS
Open drain
control signal
G
HYS
CMOS level input/output
Includes open drain control
CMOS level output
Hysteresis input
Includes open drain control
H
CMOS
Analog input
Digital output
I
HYS
CMOS level input/output
Analog input
Hysteresis input
N-ch open drain output
(Flash model)
Flash model
CMOS level input
J
Control signal
Mode input
Spreading resistance
Includes high voltage control for FLASH
test
(Mask version)
HYS
Mask version
Hysteresis input port
15
MB90470 Series
HANDLING DEVICES
■
(1) Strictly observe maximum rated voltages (prevent latchup)
When CMOS integrated circuit devices are subjected to applied voltages higher than V
pins other than medium- and high-withstand voltage pins, or to voltages lower than V
excess of rated le vels are applied between V
CC and VSS, a phenomenon known as latchup can occur . In a latchup
condition, supply current can increase dramatically and may destroy semiconductor elements. In using
semiconductor devices, always take sufficient care to avoid exceeding maximum ratings.
Also care must be taken when power to analog systems is switched on or off, to ensure that the analog power
supply (AV
CC, AVRH) and analog input do not exceed the digital power supply (VCC) .
(2) Treatment of unused pins
If unused input pins are left open, abnormal operation or latchup may cause permanent damage to the
semiconductor. Any such pins should be pulled up or pulled down through resistance of at least 2 kΩ.
Also any unused input/output pins should be left open in output status, or if set to input status should be treated
in the same way as input pins.
(3) Precautions for use of external clock signals
CC at input and output
SS, or when voltages in
Even when an external clock is used, a stabilization period is required following a power-on reset or release
from sub clock mode or stop mode. Also, when an e xternal clock is used 20 MHz should be used as a guideline
for an upper frequency limit.
The following figure shows a sample use of external clock signals.
X0
X1OPEN
(4) Power supply pins
When using multiple V
CC/VSS sources, always mak e sure to design devices with e xternal connections of all power
supply pins to supply or ground elements, in order to prevent latchup, reduce unwanted radiation, and prevent
abnormal strobe signal operation due to rise in ground level, as well as to maintain total rated output current. In
addition, care must be given to connecting the V
CC and VSS pins of this device to a current source with as little
impedance as possible. It is recommended that a bypass capacitor of 1.0 µF be connected between V
V
SS as close to the pins as possible.
CC and
(5) Crystal oscillator circuits
Abnormal operation of this device can result from noise in the proximity of the X0/X1 and X0A/X1A pins. For
stable operation, it is strongly recommended that the printed circuit artwork provide capacitors placed as close
as possible between the X0/X1, X0A/X1A and crystal oscillator (or ceramic oscillator) as well as ground, and be
wired so as to avoid crossing other wiring wherever possible.
16
MB90470 Series
(6) Precautions for use of external oscillators (crystals)
The target value for the upper limit of oscillator (crystals) frequencies should be 20 MHz. Also, when operating
at internal frequencies of 16 MHz, the PLL multiplier should be used.
(7) Proper power-on/off sequence
The A/D converter power (A V
supply (V
CC) is turned on. The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be shut
off before the digital power supply (V
CC, A VRH) and analog input (AN0 to AN7) must be turned on after the digital power
CC) is shut off. Care should be taken that AVRH does not exceed AVCC. Even
when pins used as analog input pins are doubled as input ports, be sure that the input voltage does not exceed
AV
CC.
Note : VCC = VCC3 = VCC5
(8) Treatment of A/D converter power supply pins
Even if the A/D converter is not used, pins should be connected so that AV
CC = AVRH = VCC, and AVSS = VSS.
(9) Power-on procedures
In order to prevent abnormal operation of the internal built-in step-down circuits, voltage r ise during power-on
should be attained within 50 µs (0.2 V to 2.7 V) .
(10) Stable power supply
Even within the operating range of the V
CC supply voltage, rapid changes in supply v oltage may cause abnormal
operation. As a basis for stab le operation, it is recommended that v oltage variation be restricted in order to limit
V
CC ripple fluctuations (P-P values) to 10% at commercial frequencies of 50 Hz to 60 Hz, and transient fluctuations
to 0.1 V/ms at instantaneous points such as power switching.
(11) Precautions for use of two power supplies
The MB90470 series usually uses the 3-V power supply as the main power source. With V
V
CC5 = 5 V, however, it can interface with P20/A16 to P27/A23/PPG3, P30/A00/AIN0 to P37/A07/PWC1,
CC3 = 3 V and
P40/A08/SIN2 to P47/A15/OUT5, P70/SIN0 to P77/SDA f or the 5-V power supply separetely from the 3-V pow er
supply at all operation mode.
(Caution) The analog power supply for the A/D conver ter (AV
CC, AVSS etc.) can only operate with the
3 V system.
(12) Crystal oscillator circuits during power-saving operation
When the power supply is lower than 2.0 V, the external crystal oscillator may not operate even when power is
on. For this reason, the use of an external clock signal is recommended.
(13) Caution : low-voltage flash models (2.4 V to 3.6 V/10 MHz) do not have security functions
(14) Treatment of unused input pins
N.C. (internally connected) pins should always be left open.
(15) When the dual-supply MB90470 series is used as a 1-supply device, use connections so that
X0A
SS
====
V
, and X1A
====
Open.
17
MB90470 Series
CC
(16) For serial writing to flash memory, always make sure that the operating voltage V
and 3.6 V.
For normal writing to flash memory, always make sure that the operating voltage V
3.0 V and 3.6 V.
(17) Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit ev en
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
is between 3.13 V
CC
is between
18
BLOCK DIAGRAM
■
MB90470 Series
X0, X1, RST
X0A, X1A
MD2, MD1, MD0
SIN0
SOT0
SCK0
SIN1, SIN2
SOT1, SOT 2
SCK1, SCK2
AVCC
AVRH
AVSS
ADTG
AN0 to AN7
8
Communication prescaler
I/O expansion serial
interface × 2 channels
Clock
control circuit
RAM
ROM
µDMA
UART
A/D converter
(10-bit)
CPU
FMC-16LX
series core
Interrupt controller
PPG0, PPG1
8/16-bit PPG
8/16-bit
up/down counter
2
F
2
MC-16LX BUS
16-bit input capture × 2
16-bit output compare × 6
µPG
Chip select
Input/output timer
16-bit free-run timer
16-bit reload timer
PPG2, PPG3
PPG4, PPG5
AIN0, AIN1
BIN0, BIN1
ZIN0, ZIN1
EXTC
MT00
MT01
CS0, CS1,
CS2, CS3
IN0, IN1
OUT0, OUT1,
OUT2, OUT3,
OUT4, OUT5
TIN0
TOT0
PWC0
PWC1
PWC2
16-bit PWC
3 channels
External interrupt
I/O ports
888888888
P00
P10
P20
P30
P40
P50
P60
P70
∼
P07
∼
P17
∼
P27
∼
P37
∼
P47
∼
P57
∼
P67
∼
P77
P80
∼
P87
2
I
C interface
8
P90
∼
P97
4
PA0
PA3
∼
SCL
SDA
8
IRQ0 to IRQ7
P00 to P07 (8 pins) : Input pull-up resistance setting register provided.
P10 to P17 (8 pins) : Input pull-up resistance setting register provided.
P40 to P47 (8 pins) : Open drain setting register provided.
P70 to P75 (6 pins) : Open drain setting register provided.
P76, P77 (2 pins) : Open drain
Note : In the above diagram, I/O ports are shown sharing pin numbers with the built-in function blocks. However
pins may not be used as I/O ports when they are in use as pins for build-in function modules.
19
MB90470 Series
MEMORY MAP
■
FFFFFFH
Address 1#
010000H
004000H
Address 2#
000100H
0000D0H
Single chip Internal ROM external bus
ROM area ROM area
ROM area
FF bank image
ROM area
FF bank image
*
RAMRAM
External ROM external bus
RAMRegisterRegister Register
Peripheral Peripheral Peripheral
000000H
: Internal : External : Access not available
* : In models where address 2# coincides with 004000H, there is no external area.
Model Address 1# Address 2#
MB90473 FE0000
MB90474 FC0000H 004000H
MB90477/478 FC0000H 002100H
MB90F474 FC0000H 004000H
MB90V470 (FC0000H) 004000H
The image of FF bank ROM is reflected in the top of the 00 bank, for greater efficiency in using the C compiler
for small models. The lower 16-bit address on the FF bank is the same as the lower 16-bit address on the 00
bank, so that it is possible to reference tables in ROM without using the pointer for a far specification.
For example, when accessing 00C000
H, it is actually the content of ROM at FFC000H that is accessed. Here,
because the ROM area on the FF bank exceeds 48 KB, it is not possib le to vie w the entire area in the image on
the 00 bank. Therefore, the image from FF4000
H to FFFFFFH is visible on the 00 bank, and FF0000H to FF3FFFH
is visible only on the FF bank.
H 002900H
20
2
F
MC-16L CPU PROGRAMMING MODEL
■
•
Special purpose registers
MB90470 Series
AH AL
USP
SSP
PS
PC
16 bit
32 bit
DPR
PCB
DTB
USB
SSB
ADB
8 bit
Accumulator
User stack pointer
System stack pointer
Processor status
Program counter
Direct page register
Program bank register
Data bank register
User stack bank register
System stack bank register
Additional data bank register
•
General purpose registers
000180
•
Processor status
15 13
PS RP CCR
ILM
MSB LSB
H + RP × 10H
12 8 70
16 bit
RW0
RW1
RW2
RW3
R1 R0
R3 R2
R5
R7 R6
R4
RL0
RL1
RW4
RL2
RW5
RW6
RL3
RW7
21
MB90470 Series
O MAP
■I/
Address Register name Symbol Access Resource name Default
00
H Port 0 data register PDR0 R/W Port 0 XXXXXXXX
01
H Port 1 data register PDR1 R/W Port 1 XXXXXXXX
02
H Port 2 data register PDR2 R/W Port 2 XXXXXXXX
03
H Port 3 data register PDR3 R/W Port 3 XXXXXXXX
04H Port 4 data register PDR4 R/W Port 4 XXXXXXXX
05
H Port 5 data register PDR5 R/W Port 5 XXXXXXXX
06
H Port 6 data register PDR6 R/W Port 6 XXXXXXXX
07H Port 7 data register PDR7 R/W Port 7 1 1XXXXXX
08
H Port 8 data register PDR8 R/W Port 8 XXXXXXXX
09
H Port 9 data register PDR9 R/W Port 9 XXXXXXXX
0AH Port A data register PDRA R/W Port A - - - - XXXX
0B
H Port 3 timer input enable register UDRE R/W
0C
H Interrupt/DTP enable register ENIR R/W
0DH Interrupt/DTP enable register EIRR R/W 0 0 0 0 0 0 0 0
0E
H Demand level setting register
R/W 0 0 0 0 0 0 0 0
Up/down timer
input control
DTP/external
interrupt
XX 0 0 0 0 0 0
0 0 0 0 0 0 0 0
ELVR
0F
H Demand level setting register R/W 0 0 0 0 0 0 0 0
10
H Port 0 direction register DDR0 R/W Port 0 0 0 0 0 0 0 0 0
11H Port 1 direction register DDR1 R/W Port 1 0 0 0 0 0 0 0 0
12
H Port 2 direction register DDR2 R/W Port 2 0 0 0 0 0 0 0 0
13
H Port 3 direction register DDR3 R/W Port 3 0 0 0 0 0 0 0 0
14H Port 4 direction register DDR4 R/W Port 4 0 0 0 0 0 0 0 0
15
H Port 5 direction register DDR5 R/W Port 5 0 0 0 0 0 0 0 0
16
H Port 6 direction register DDR6 R/W Port 6 0 0 0 0 0 0 0 0
17H Port 7 direction register DDR7 R/W Port 7 - - 0 0 0 0 0 0
18
H Port 8 direction register DDR8 R/W Port 8 0 0 0 0 0 0 0 0
19
H Port 9 direction register DDR9 R/W Port 9 0 0 0 0 0 0 0 0
1AH Port A direction register DDRA R/W Port A - - - - 0 0 0 0
1B
H Port 4 pin register ODR4 R/W Port 4 (OD control) 0 0 0 0 0 0 0 0
22
1C
H Port 0 resistance register RDR0 R/W Port 0 (pull-up) 0 0 0 0 0 0 0 0
1DH Port 1 resistance register RDR1 R/W Port 1 (pull-up) 0 0 0 0 0 0 0 0
1E
H Port 7 pin register ODR7 R/W Port 7 (OD control) - - 0 0 0 0 0 0
1F
H Analog input enable register ADER R/W Port 5, A/D 1 1 1 1 1 1 1 1
(Continued)
MB90470 Series
Address Register name Symbol Access Resource name Default
20
H Serial mode register 0 SMR0 R/W
21H Serial control register 0 SCR0 R/W 0 0 0 0 0 1 0 0
22
23
24
Serial input register/ serial output
H
register
H Serial status register SSR0 R/W 0 0 0 0 1 0 0 0
H Reserved
SIDR/
SODR0
R/W XXXXXXXX
25H Clock divider control register CDCR R/W
26
H Serial mode control status register 0 SMCS0 R/W
UART0
Communication
prescaler (UART)
0 0 0 0 0 X 0 0
0 0 - - 0 0 0 0
- - - - 0 0 0 0
27
H Serial mode control status register 0 SMCS0 R/W 0 0 0 0 0 0 1 0
SCI1 (ch0)
28H Serial data register SDR0 R/W XXXXXXXX
29
H Clock divider control register SDCR0 R/W
2A
H Serial mode control status register 1 SMCS1 R/W
2BH Serial mode control status register 1 SMCS1 R/W 0 0 0 0 0 0 1 0
2C
H Serial data register SDR1 R/W XXXXXXXX
2D
H Clock divider control register SDCR1 R/W
2EH PPG reload register L (ch0) PRLL0 R/W
2F
H PPG reload register H (ch0) PRLH0 R/W XXXXXXXX
30
H PPG reload register L (ch1) PRLL1 R/W XXXXXXXX
31
H PPG reload register H (ch1) PRLH1 R/W XXXXXXXX
Communication
prescaler (SCI0)
SCI2 (ch1)
Communication
prescaler (SCI1)
0 - - - 0 0 0 0
- - - - 0 0 0 0
0 - - - 0 0 0 0
XXXXXXXX
32H PPG reload register L (ch2) PRLL2 R/W XXXXXXXX
33
H PPG reload register H (ch2) PRLH2 R/W XXXXXXXX
34
H PPG reload register L (ch3) PRLL3 R/W XXXXXXXX
35H PPG reload register H (ch3) PRLH3 R/W XXXXXXXX
36
H PPG reload register L (ch4) PRLL4 R/W XXXXXXXX
37
H PPG reload register H (ch4) PRLH4 R/W XXXXXXXX
8/16-bit PPG
(ch0-ch5)
38H PPG reload register L (ch5) PRLL5 R/W XXXXXXXX
39
H PPG reload register H (ch5) PRLH5 R/W XXXXXXXX
3A
H PPG0 operating mode control register PPGC0 R/W 0 X 0 0 0XX 1
3BH PPG1 operating mode control register PPGC1 R/W 0 X 0 0 0 0 0 1
3C
H PPG2 operating mode control register PPGC2 R/W 0 X 0 0 0XX 1
3D
H PPG3 operating mode control register PPGC3 R/W 0 X 0 0 0 0 0 1
3E
H PPG4 operating mode control register PPGC4 R/W 0 X 0 0 0XX 1
3FH PPG5 operating mode control register PPGC5 R/W 0 X 0 0 0 0 0 1
40
H PPG0, 1 output control register PPG01 R/W 8/16-bit PPG 0 0 0 0 0 0 0 0
(Continued)
23
MB90470 Series
Address Register name Symbol Access Resource name Default
41
H Reserved
42H PPG2, 3 output control register PPG23 R/W 8/16-bit PPG 0 0 0 0 0 0 0 0
43
H Reserved
44
H PPG4, 5 output control register PPG45 R/W 8/16-bit PPG 0 0 0 0 0 0 0 0
45
H Reserved
46H
ADCS1 R/W
Control status register
47
H ADCS2 R/W 0 0 0 0 0 0 0 0
A/D converter
48
H
ADCR1 R XXXXXXXX
Data register
H ADCR2 R 0 0 0 0 0 XXX
49
4A
H Output compare register (ch0) low
OCCP0 R/W
4B
H Output compare register (ch0) high XXXXXXXX
4CH Output compare register (ch1) low
OCCP1 R/W
4D
H Output compare register (ch1) high XXXXXXXX
0 0 0 0 0 0 0 0
XXXXXXXX
XXXXXXXX
4E
H Output compare register (ch2) low
XXXXXXXX
OCCP2 R/W
4FH Output compare register (ch2) high XXXXXXXX
50
H Output compare register (ch3) low
OCCP3 R/W
51
H Output compare register (ch3) high XXXXXXXX
52H Output compare register (ch4) low
16-bit output timer
output compare
(ch0-ch5)
XXXXXXXX
XXXXXXXX
OCCP4 R/W
53
H Output compare register (ch4) high XXXXXXXX
54
H Output compare register (ch5) low
XXXXXXXX
OCCP5 R/W
55
H Output compare register (ch5) high XXXXXXXX
56H Output compare control register (ch0) OCS0 R/W 0 0 0 0 - - 0 0
57
H Output compare control register (ch1) OCS1 R/W - - - 0 0 0 0 0
58
H Output compare control register (ch2) OCS2 R/W 0 0 0 0 - - 0 0
59H Output compare control register (ch3) OCS3 R/W - - - 0 0 0 0 0
5A
H Output compare control register (ch4) OCS4 R/W
5B
H Output compare control register (ch5) OCS5 R/W - - - 0 0 0 0 0
5CH Input capture register (ch0) low
R
16-bit output timer
OCU (ch4, 5)
0 0 0 0 - - 0 0
XXXXXXXX
IPCP0
5D
H Input capture register (ch0) high R XXXXXXXX
5E
H Input capture register (ch1) low
IPCP1
R XXXXXXXX
16-bit output timer
Input capture (ch0, 1)
5FH Input capture register (ch1) high R XXXXXXXX
24
60
H Input capture control register ICS01 R/W 0 0 0 0 0 0 0 0
61
H Reserved
(Continued)
MB90470 Series
Address Register name Symbol Access Resource name Default
62
H Timer data register low TCDT R/W
63H Timer data register high TCDT R/W 0 0 0 0 0 0 0 0
64
H Timer control status register TCCS R/W 0 0 0 0 0 0 0 0
65
H Timer control status register TCCS R/W 0 - - 0 0 0 0 0
66
H Compare clear register low
16-bit output timer
Free run timer
CPCLR R/W
67H Compare clear register high XXXXXXXX
68
H Up down count register ch0 UDCR0 R
69
H Up down count register ch1 UDCR1 R 0 0 0 0 0 0 0 0
6AH Reload compare register ch0 RCR0 W 0 0 0 0 0 0 0 0
6B
H Reload compare register ch1 RCR1 W 0 0 0 0 0 0 0 0
6C
H Counter control register low ch0 CCRL0 R/W 0 X 0 0 X 0 0 0
8/16-bit up-down
timer-counter
6DH Counter control register high ch0 CCRH0 R/W 0 0 0 0 0 0 0 0
6E
H Reserved
0 0 0 0 0 0 0 0
XXXXXXXX
0 0 0 0 0 0 0 0
6F
H ROM mirror function select register ROMM W ROM mirror function - - - - - - - 1
70H Counter control register low ch1 CCRL1 R/W
71
H Counter control register high ch1 CCRH1 R/W - 0 0 0 0 0 0 0
72
H Count status register ch0 CSR0 R/W 0 0 0 0 0 0 0 0
8/16-bit up-down
timer-counter
0 X 0 0 X 0 0 0
73H Reserved
74
H Count status register ch1 CSR1 R/W 8/16-bit UDC 0 0 0 0 0 0 0 0
75
H Reserved
76
H
0 0 0 0 0 0 0 0
PWC0 control status register PWCSR0 R/W
77
H 0 0 0 0 0 0 0 X
78
H
16-bit PWC timer
(ch0)
0 0 0 0 0 0 0 0
PWC0 data buffer register PWCR0 R/W
H 0 0 0 0 0 0 0 0
79
7AH
0 0 0 0 0 0 0 0
PWC1 control status register PWCSR1 R/W
7B
H 0 0 0 0 0 0 0 X
7C
H
16-bit PWC timer
(ch1)
0 0 0 0 0 0 0 0
PWC1 data buffer register PWCR1 R/W
H 0 0 0 0 0 0 0 0
7D
7E
H
0 0 0 0 0 0 0 0
PWC2 control status register PWCSR2 R/W
7F
H 0 0 0 0 0 0 0 X
80H
16-bit PWC timer
(ch2)
0 0 0 0 0 0 0 0
PWC2 data buffer register PWCR2 R/W
81
H 0 0 0 0 0 0 0 0
82
H PWC0 division ratio register DIVR0 R/W PWC (ch0) - - - - - - 0 0
83
H Reserved
84H PWC1 division ratio register DIVR1 R/W PWC (ch1) - - - - - - 0 0
85
H Reserved
(Continued)
25
MB90470 Series
Address Register name Symbol Access Resource name Default
86
H PWC2 division ratio register DIVR2 R/W PWC (ch2) - - - - - - 0 0
87H Reserved
88
89
8A
8BH I
8C
8D
8EH µPG control register PGCSR R/W µPG 0 0 0 0 0 - - -
8F
H to 9BH Prohibited
9C
9DH µDMA status register DSRH R/W µDMA 0 0 0 0 0 0 0 0
2
H I
H I
H I
H I
H Reserved
H µDMA status register DSRL R/W µDMA 0 0 0 0 0 0 0 0
C bus status register IBSR R
2
C bus control register IBCR R/W 0 0 0 0 0 0 0 0
2
C bus clock select register ICCR R/W - - 0XXXXX
2
C bus address register IADR R/W - XXXXXXX
2
C bus data register IDAR R/W XXXXXXXX
2
I
C functions
0 0 0 0 0 0 0 0
9E
9F
Program address detection control
H
status resister
Delay interrupt source generate/
H
release register
PACSR R/W
DIRR R/W
Address Match
Detection Function
Delay interrupt
generator module
0 0 0 0 0 0 0 0
- - - - - - - - 0
A0H Low power mode register LPMCR R/W Low power modes 0 0 0 1 1 0 0 0
A1
H Clock select register CKSCR R/W Low power modes 1 1 1 1 1 1 0 0
A2
H, A3H Reserved
A4
H µDMA stop status register DSSR R/W µDMA 0 0 0 0 0 0 0 0
A5H Auto ready function select register ARSR W External pins 0 0 1 1 - - 0 0
A6
A7
External address output control
H
register
H Bus control signal control register EPCR W External pins 1 0 0 0 * 1 0 -
HACR W External pins 0 0 0 0 0 0 0 0
A8H Watchdog control register WDTC R/W Watchdog timer XXXXX 1 1 1
A9
H Time base timer control register TBTC R/W Time base timer 1 X X 0 0 1 0 0
AA
H Watch timer control register WTC R/W Watch timer 1 0 0 0 1 0 0 0
ABH Reserved
AC
H µDMA control register DERL R/W µDMA 0 0 0 0 0 0 0 0
AD
H µDMA control register DERH R/W µDMA 0 0 0 0 0 0 0 0
AEH Flash memory control status register FMCR R/W
Flash memory
interface
0 0 0 X 0 0 0 0
26
AF
H Prohibited
B0
H Interrupt control register 00 ICR00 R/W XXXX 0 1 1 1
B1
H Interrupt control register 01 ICR01 R/W XXXX 0 1 1 1
B2H Interrupt control register 02 ICR02 R/W XXXX 0 1 1 1
B3
H Interrupt control register 03 ICR03 R/W XXXX 0 1 1 1
(Continued)
MB90470 Series
Address Register name Symbol Access Resource name Default
B4
H Interrupt control register 04 ICR04 R/W XXXX 0 1 1 1
B5
H Interrupt control register 05 ICR05 R/W XXXX 0 1 1 1
B6
H Interrupt control register 06 ICR06 R/W XXXX 0 1 1 1
B7
H Interrupt control register 07 ICR07 R/W XXXX 0 1 1 1
B8H Interrupt control register 08 ICR08 R/W XXXX 0 1 1 1
B9
H Interrupt control register 09 ICR09 R/W XXXX 0 1 1 1
BA
H Interrupt control register 10 ICR10 R/W XXXX 0 1 1 1
BBH Interrupt control register 11 ICR11 R/W XXXX 0 1 1 1
BC
H Interrupt control register 12 ICR12 R/W XXXX 0 1 1 1
BD
H Interrupt control register 13 ICR13 R/W XXXX 0 1 1 1
BEH Interrupt control register 14 ICR14 R/W XXXX 0 1 1 1
BF
H Interrupt control register 15 ICR15 R/W XXXX 0 1 1 1
C0
H Chip select MASK register 0 CMR0 R/W Chip select functions 0 0 0 0 1 1 1 1
C1H Chip select area register 0 CAR0 R/W 1 1 1 1 1 1 1 1
C2
H Chip select MASK register 1 CMR1 R/W 0 0 0 0 1 1 1 1
C3
H Chip select area register 1 CAR1 R/W 1 1 1 1 1 1 1 1
C4H Chip select MASK register 2 CMR2 R/W 0 0 0 0 1 1 1 1
C5
H Chip select area register 2 CAR2 R/W 1 1 1 1 1 1 1 1
C6
H Chip select MASK register 3 CMR3 R/W 0 0 0 0 1 1 1 1
C7
H Chip select area register 3 CAR3 R/W 1 1 1 1 1 1 1 1
C8H Chip select control register CSCR R/W - - - - 0 0 0 *
C9
H Chip select control active level register CALR R/W - - - - 0 0 0 0
CA
H
0 0 0 0 0 0 0 0
Timer control status registers TMCSR R/W
CB
H - - - - 0 0 0 0
16-bit reload timer
CC
H
CD
16-bit timer register
16-bit reload register
H
TMR/
TMRLR
R/W XXXXXXXX
CEH, CFH Reserved
D0
H to FFH External area
100
H to #H RAM area
1FF0
Program address detection resister0
(Low order address)
Program address detection resister0
(Middle order address)
PADR0 R/W
Address Match
Detection Function
XXXXXXXX1FF1
1FF2
Program address detection resister0
(High order address)
(Continued)
27
MB90470 Series
(Continued)
Address Register name Symbol Access Resource name Default
1FF3
1FF5
Interrupt symbols :
R/W : Read/write enabled
R : Read only
W : Write only
Default value symbols :
0 : This bit initialized to “0”
1 : This bit initialized to “1”
* : This bit initialized to “0” or “1”
X : Default value undefined
- : This bit is not used.
Program address detection resister1
(Low order address)
Program address detection resister1
(Middle order address)
Program address detection resister1
(High order address)
PADR1 R/W
Address Match
Detection Function
XXXXXXXX1FF4
28
MB90470 Series
INTERRUPT SOURCES, INTERRUPT VECTORS & INTERRUPT CONTROL REGISTERS
■
Interrupt control
register
Interrupt source
2
OS
EI
support
µµµµ
DMA
channel no.
Interrupt vector
No. Address No. Address
Reset #08 FFFFDC
INT9 instruction #09 FFFFD8
H
H
Exception #10 FFFFD4H
INT0 0 #11 FFFFD0
H
ICR00 0000B0H
INT1 × #12 FFFFCCH
INT2 × #13 FFFFC8H
ICR01 0000B1H
INT3 × #14 FFFFC4H
INT4 × #15 FFFFC0H
ICR02 0000B2H
INT5 × #16 FFFFBCH
INT6 × #17 FFFFB8H
ICR03 0000B3H
INT7 × #18 FFFFB4H
PWC1 × #19 FFFFB0H
ICR04 0000B4H
PWC2 × #20 FFFFACH
PWC0 1 #21 FFFFA8H
ICR05 0000B5H
PPG0/PPG1 counter borrow 2 #22 FFFFA4H
PPG2/PPG3 counter borrow 3 #23 FFFFA0H
PPG4/PPG5 counter borrow 4 #24 FFFF9CH
8/16-bit
up/down counter timer compare/
underflow /overflow/
× #25 FFFF98
amp down inversion (ch0, 1)
Input capture (ch0) load 5 #26 FFFF94H
Input capture (ch1) load 6 #27 FFFF90H
Output compare (ch0) match 8 #28 FFFF8CH
Output compare (ch1) match 9 #29 FFFF88H
Output compare (ch2) match 10 #30 FFFF84H
Output compare (ch3) match × #31 FFFF80H
Output compare (ch4) match × #32 FFFF7CH
Output compare (ch5) match × #33 FFFF78H
UART send end 11 #34 FFFF74H
16-bit free run timer/
16-bit reload timer overflow
12 #35 FFFF70
UART receive end 7 #36 FFFF6CH
ICR06 0000B6H
H
ICR07 0000B7H
ICR08 0000B8H
ICR09 0000B9H
ICR10 0000BAH
ICR11 0000BBH
H
ICR12 0000BCH
(Continued)
29
MB90470 Series
(Continued)
Interrupt source
2
OS
EI
support
µµµµ
DMA
channel no.
Interrupt vector
Interrupt control
register
No. Address No. Address
SIO1 13 #37 FFFF68
H
ICR13 0000BDH
SIO2 14 #38 FFFF64H
I2C interface ××#39 FFFF60H
ICR14 0000BEH
A/D 15 #40 FFFF5CH
Flash write/erase, time base timer,
watch timer*
××#41 FFFF58H
ICR15 0000BFH
Delay interrupt generator module ××#42 FFFF54H
: Interrupt request flag cleared by the interrupt clear signal. The stop request is available.
: Interrupt request flag cleared by the interrupt clear signal.
× : Interrupt request flag not cleared by the interrupt clear signal.
* : Note that flash write/erase cannot be used at the same time as the time base timer or watch timer.
Note : • If two or more interrupt sources have the same interrupt number, the resource will clear both interrupt
request flags at the EI
2
OS/DMAC interrupt clear signal. Thus when EI2OS/µDMA function of two sources
is used, the other interrupt function cannot be used. The interrupt request enable bit of the corresponding
resource should be set to “0” for software polling processing.
• Maximum assured operation frequency of µDMA is 16 MHz.
30
MB90470 Series
PERIPHERAL RESOURCES
■
1. I/O Ports
The I/O ports output data from the CPU to the I/O pins, and also load signals input at the I/O pins into the CPU,
according to the port register (PDR) . The ports can also control the input/output direction of the I/O pins in bit
units according to the port direction register (DDR) .
The MB90470 series has 82 input/output pins and two open drain output pins. P orts 0 through A are input/output
ports, and port 76, and 77 are the open drain ports.
(1) Port Registers
PDR0 Default value Access
Address : 000000
H Undefined R/W*
PDR1
Address : 000001
H Undefined R/W*
PDR2
Address : 000002
H Undefined R/W*
PDR3
Address : 000003
H Undefined R/W*
PDR4
Address : 000004
H Undefined R/W*
PDR5
Address : 000005
H Undefined R/W*
PDR6
Address : 000006
H Undefined R/W*
PDR7
Address : 000007
H 11XXXXXX R/W*
76543210
P06P07 P05 P04 P03 P02 P01 P00
76543210
P16P17 P15 P14 P13 P12 P11 P10
76543210
P26P27 P25 P24 P23 P22 P21 P20
76543210
P36P37 P35 P34 P33 P32 P31 P30
76543210
P46P47 P45 P44 P43 P42 P41 P40
76543210
P56P57 P55 P54 P53 P52 P51 P50
76543210
P66P67 P65 P64 P63 P62 P61 P60
76543210
P76P77 P75 P74 P73 P72 P71 P70
PDR8
Address : 000008
PDR9
Address : 000009
PDRA
Address : 00000A
76543210
H Undefined R/W*
H Undefined R/W*
H Undefined R/W*
P86P87 P85 P84 P83 P82 P81 P80
76543210
P96P97 P95 P94 P93 P92 P91 P90
76543210
PA3 PA2 PA1 PA0
* : Input/output port read/write operations are somewhat different than reading and writing to memory, and operate
as follows.
•Input mode
Read : Reads the signal level of the corresponding pin.
Write : Writes to the output latch.
•Output mode
Read : Reads the value of the data register latch.
Write : Value is output to the corresponding pin.
31
MB90470 Series
(2) Port Direction Registers
DDR0
Address : 000010
DDR1
Address : 000011H 00000000 R/W
DDR2
Address : 000012
DDR3
Address : 000013
DDR4
Address : 000014
DDR5
Address : 000015
DDR6
Address : 000016
DDR7
Address : 000017
76543210
H 00000000 R/W
H 00000000 R/W
H 00000000 R/W
H 00000000 R/W
H 00000000 R/W
H 00000000 R/W
H 00000000 R/W
D06D07 D05 D04 D03 D02 D01 D 00
76543210
D16D17 D15 D14 D13 D12 D11 D10
76543210
D26D27 D25 D24 D23 D22 D21 D20
76543210
D36D37 D35 D34 D33 D32 D31 D30
76543210
D46D47 D45 D44 D43 D42 D41 D40
76543210
D56D57 D55 D54 D53 D52 D51 D50
76543210
D66D67 D65 D64 D63 D62 D61 D60
76543210
D75 D74 D73 D72 D71 D70
Default value Access
DDR8
Address : 000018
DDR9
Address : 000019
DDRA
Address : 00001A
76543210
H 00000000 R/W
H 00000000 R/W
H - - - - 0000 R/W
D86D87 D85 D84 D83 D82 D81 D80
76543210
D96D97 D95 D94 D93 D92 D91 D90
76543210
DA3 DA2 DA1 DA0
• When a pin is functioning as a port, the corresponding pin control setting is as follows :
0 : Input mode
1 : Output mode The register value is “0” at reset.
• Port 76, 77
These ports do not have DDR registers. Data at these pins is always valid, so that when P76, P77 are used
2
as I
C pins the PDR value should be “1”. (The I2C functions should be stopped, when these pins are used as
P76,P77 .)
These ports have open drain configuration. If they are used as input ports, the output transistor is turned off,
so that the output data register must be set to “1” and pull-up resistance applied.
Note : If these registers are accessed using read-modify-write instructions (such as bit set instructions) ,the bit that
is the object of the instruction will be set to the specified value but f or other bits the value of the corresponding
output register will be rewritten to the input value of the pin at that time. F or this reason when a pin used f or
input is switched to output, first write the desired value to the PDR register, then set the DDR register to
switch the pin direction.
32
(3) Input Resistance Registers
MB90470 Series
RDR0 Default value Access
Address : 00001C
RDR1
Address : 00001D
76543210
H 00000000 R/W
H 00000000 R/W
RD06RD07 RD05 RD04 RD03 RD02 RD01 RD00
76543210
RD16RD17 RD15 RD14 RD13 RD12 RD11 RD10
These registers control pull-up resistance in input mode.
0 : No pull-up resistance in input mode.
1 : Pull-up resistance applied in input mode.
In output mode, the setting has no significance (no pull-up resistance) . The direction registers (DDR) control
switching between input and output modes.
In stop mode (SPL = 1) pull-up resistance is removed (high impedance) . When an exter nal bus is used, this
function is prohibited and no values should be written to this register.
(4) Output Pin Registers
ODR7 Default value Access
Address : 00001E
ODR4
Address : 00001B
76543210
H 00000000 R/W
76543210
H 00000000 R/W
OD75 OD74 OD73 OD72 OD71 OD70
OD46OD47 OD45 OD44 OD43 OD42 OD41 OD40
These registers control open drain operation in output mode.
0 : Operates as standard output port in output mode.
1 : Operates as open drain port in output mode.
In input mode, the setting has no significance (High-Z output) . The direction registers (DDR) control switching
between input and output modes. When an external bus is used, this function is prohibited and no v alues should
be written to this register.
(5) Analog Input Enable Register
ADER Default value Access
Address : 00001F
76543210
H 11111111 R/W
ADE6ADE7 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
This register controls the port 6 pins as follows.
0 : Port input/output mode.
1 : Analog input mode. The register value is “1” at reset.
(6) Up-down Timer Input Enable Mode
UDER Default value Access
Address : 00000B
76543210
H XX000000 R/W
UDE5 UDE4 UDE3 UDE2 UDE1 UDE0
This register controls the port 3 pins as follows.
0 : Port input mode
1 : Up-down timer input mode. The register value is “0” at reset.
In the MB90470 series, the pin functions are as follows : UDE0 : P30/AIN0, UDE1 : P31/BIN0, UDE2 : P32/
ZIN0, UDE3 : P33/AIN1, UDE4 : P34/BIN1, UDE5 : P35/ZIN1
33
MB90470 Series
2. UART
The UART is a serial I/O port for asynchronous (start-stop synchronized) communication or CLK synchronized
communication.
• Full duplex double buffer
• Asynchronous (start-stop synchronized) and CLK synchronized (no start bit or stop bit) operation
• Supports multi-processor modes
• Built-in dedicated baud rate generator
Asynchronous operation : 76923/38461/19230/9615/500 K/250 Kbps
CLK synchronized : 16 M/8 M/4 M/2 M/1 M/500 K
• Baud rate can be set independently from external clock
• Can use internal clock feed from PPG1.
• Data length : 7 bits (asynchronous normal mode only) or 8 bits
• Master-slave communication functions (in multi-processor mode) : allows 1 (master) -to-n (slave)
communications
• Error detection functions (parity, framing, overrun)
• NRZ-encoded transfer signal
• DMAC support (receiving/sending)
34
(1) Register List
MB90470 Series
15 0
SCR
8 bit 8 bit
Serial mode register (SMR)
76543210
Address : 000020
MD1 CS2 CS1 CS0
H
(R/W)
( 0 )
MD0
(R/W)
( 0 )
Serial control register (SCR)
15 14 13 12 11 10 9 8
Address : 000021
PEN SBL CL A/D REC RXE TXE
H
(R/W)
( 0 )
P
(R/W)
( 0 )
Serial input/output register (SIDR/SODR)
76543210
Address : 000022
H
D7 D5 D4 D3 D2 D1 D0
(R/W)
( X )
D6
(R/W)
( X )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( X )
87
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( X )
CDCR
SMR
SIDR (R)/SODR (W)SSR
Reserved SCKE SOE
(R/W)
( 0 )
(R/W)
(R/W)
( X )
( 0 )
(R/W)
( X )
( W )
( 1 )
(R/W)
( X )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( X )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( X )
Default value
Default value
Default value
Serial data register (SSR)
15 14 13 12 11 10 9 8
Address : 000023
H
PE FRE RDRF TDRE BDS RIE TIE
( R )
( 0 )
ORE
( R )
( 0 )
( R )
( 0 )
Communication prescaler control register (CDCR)
15 14 13 12 11 10 9 8
Address : 000025
H
(R/W)
SRST
MD DIV3 DIV2 DIV1 DIV0
( 0 )
(R/W)
( 0 )
( )
( )
( R )
( 0 )
( )
( )
( R )
( 1 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
Default value
Default value
35
MB90470 Series
(2) Block Diagram
Control
signal
Dedicated baud rate
generator
PPG1
(internal connection)
External clock
Clock
select circuit
RX clock
Receiving
control circuits
TX clock
Receiving
interrupt
(to CPU)
SCK0
Sending interrupt
(to CPU)
Sending
control circuits
SIN0
Receiving status
judgement circuit
DMAC receiving
error transmission
signal (to CPU)
Start bit
detect circuit
Receiving
bit counter
Receiving
parity counter
Receiving shifter Sending shifter
Receiving
control
circuit
SIDR
F2MC-16LX BUS
Send start
circuit
Sending
bit counter
Sending
parity counter
SOT0
Sending
control
circuit
SODR
36
SMR
register
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
SCR
register
PEN
P
SBL
CL
A/D
REC
REX
TXE
SSR
register
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
Control signal
MB90470 Series
3. Expanded I/O Serial Interface
The expended I/O serial interface is a serial I/O interface in 8-bit × 1 channel configuration allowing clock
synchronized data transmission.
The interface has two serial I/O operating modes.
• Internal shift clock mode : Data transfer is synchronized with an internal clock.
• External shift clock mode : Data transfer is synchronized with a clock input from an external pin (SCK) .
This mode allows the external clock pin (SCK) to be shared with a general
purpose port that can transfer data according to CPU instructions.
(1) Register List
Serial mode control status register (SMCS)
Initial value
0 0 0 0 0 0 1 0B
Address :
000027
00002BH
15 14 13 12 11 10 9 8
H
(R/W) (R/W) (R/W)
SMD1SMD2 SMD0 SIE SIR BUSY STOP STRT
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
76543210
Address
000026H
:
00002AH
()
MODE BDS SOE SCOE
()
()
()
Serial data register (SDR)
76543210
Address
000028H
:
00002CH
(R/W)
D6D7 D5 D4 D3 D2 D1 D0
(R/W)
(R/W) (R/W) (R/W) (R/W) (R/W)(R/W)
Communication prescaler control register (SDCR0, SDCR1)
15 14 13 12 11 10 9 8
MD DIV3 DIV2 DIV1 DIV0
(R/W)
( )( )( ) (R/W) (R/W) (R/W) (R/W)
Address :
000029
00002DH
H
(R/W)
(R/W)
Initial value
- - - - 0 0 0 0B
(R/W) (R/W)
Initial value
XXXXXXXXB
Initial value
0 - - - 0000B
37
MB90470 Series
(2) Block Diagram
Internal data bus
(MSB first) D0 to D7 D7 to D0 (LSB first)
SIN1, 2
SOT1, 2
SCK1, 2
Internal clock
SDR (Serial data register)
21 0
SMD2
SMD1 SMD0 SIE SIR BUSY STOP STRT MODE BDS
Select transfer direction
Control circuit Shift clock counter
Interrupt
request
Internal data bus
Default value
Read
Write
SOE SCOE
38
MB90470 Series
4. 8/10-bit A/D Converter
The A/D converter converts analog input voltages into digital values, and provides the following features :
• Conversion time : minimum 4.9 µs per channel
(at 98 machine cycles/machine clock 20 MHz, including sampling time)
• Sampling time : minimum 3.0 µs per channel
(at 60 machine cycles/machine clock 20 MHz)
• Uses RC sequential comparison conversion with sample & hold circuit.
• Selection of 8- or 10-bit resolution
• Analog input from 8 channels, by program selection
Single conversion mode : Convert 1 selected channel
Scan conversion mode : Con vert multiple consecutive channels. Select up to 8 channels by program selection.
Continuous conversion mode : Convert specified channel continuously.
Stop conversion mode : Con vert one channel, pause and stand by until the next start. (Simultaneous conversion
start available.)
• At the end of A/D conversion, an A/D con version end interrupt request can be sent to the CPU. This interrupt
request can start the µDMA and transfer the conversion data to memory, making it ideal for continuous
processing.
• Start sources include selection of software, external trigger (falling edge) , or timer (rising edge) .
(1) Register List
ADCS2, ADCS1 (Control status registers)
ADCS1
Address : 000046
ADCS2 bit
Address : 000047
76543210
MD1 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
H
0
R/W
15 14 13 12 11 10 9 8
H
BUSY INTE PAUS STS1 STS0 STRT
0
R/W
ADCR2, ADCR1 (Data registers)
ADCR1 bit
Address : 000048
ADCR2 bit
Address : 000049
76543210
H
D7 D5 D4 D3 D2 D1 D0
X
R
15 14 13 12 11 10 9 8
H
S10 ST0 CT1 CT0 D9 D8
0
R/W
MD0
0
R/W0R/W0R/W0R/W0R/W0R/W0R/W
W
X
R
X
R
0
Reserved
0
R/W
X
R
X
R
INT
0
R/W0R/W0R/W0R/W0R/W
D6
X
R
ST1
0
W
X
R
0
W
X
R
0
W
X
R
0
W
X
R
X
R
←Default value
←Bit attributes
←Default value
←Bit attributes
←Default value
←Bit attributes
←Default value
←Bit attributes
39
MB90470 Series
(2) Block Diagram
MP
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Input circuit
Sample & hold circuit
Comparator
CC
AV
AVRH
AVSS
D/A converter
Sequential
comparison register
Data bus
ADTG
Timer
(PPG1 output)
Trigger start
Timer start
φ
Decoder
Data register
ADCR1, ADCR2
A/D control register 1
A/D control register 2
Operating clock
Prescaler
ADCS1,
ADCS2
40
MB90470 Series
5. 8/16-bit PPG
The 8/16-bit PPG is an 8-bit reload timer module that produces a PPG output in the form of a pulse for timer
operation. The hardware configuration includes six 8-bit down counters, tw elve 8-bit reload timers, three 16-bit
control registers, six external pulse output pins, and six interrupt outputs. The MB90470 provides six 8-bit PPG
channels, which can also operate as three 16-bit PPG channels in the combination PPG0 + PPG1, PPG2 +
PPG3, PPG4 + PPG5. The following is an overview of the functions of the PPG.
• Six-channel independent 8-bit PPG output mode : Provides PPG output operation independently on six
channels.
• 16-bit PPG output operation mode : Provides 16-bit PPG output operation on three channels, using the
combination PPG0 + PPG1, PPG2 + PPG3, PPG4 + PPG5.
•8 + 8-bit PPG output operation mode :
Uses the PPG0 (PPG2/PPG4) output as the PPG1 (PPG3/PPG5) clock input, to enable 8-bit PPG output with
any desired period.
• PPG output operation :
Outputs pulse waves at a specified period and duty ratio.
Can be also used with an external circuit as a D/A converter.
41
MB90470 Series
(1) Register List
PPGC0 (PPG0/2/4 operating mode control register)
00003A
H
00003CH
00003EH
PPGC1 (PPG1/3/5 operating mode control register)
00003B
H
00003DH
00003FH
PPG01/PPG23/PPG45 (PPG0-PPG5 output control register)
000040
H
000042H
000044H
76543210
PEN0 PE00 PIE0 PUF0
(R/W)
( 0 )
15 14 13 12 11 10 9 8
PEN1 PE10 PIE1 PUF1 MD1 MD0
(R/W)
( 0 )
76543210
PCS2 PCS0 PCM2 PCM1 PCM0
(R/W)
( 0 )
( )
( X )
( )
( X )
PCS1
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
( )
( X )
(R/W)
( 0 )
(R/W)
( 0 )
( )
( X )
(R/W)
( 0 )
Reserved Reserved
(R/W)
( 0 )
Reserved
( )
( 1 )
Reserved
( )
( 1 )
(R/W)
( 0 )
Read/write
Default value
Read/write
Default value
Read/write
Default value
PPLL0 to PPLL5 (Reload register L)
00002E
000030H
000032H
000034H
000036H
H
76543210
D07 D05 D04 D03 D02 D01 D00
(R/W)
( X )
D06
(R/W)
( X )
(R/W)
( X )
000038H
PPLH0 to PPLH5 (Reload register H)
00002F
000031H
000033H
000035H
000037H
H
15 14 13 12 11 10 9 8
D15 D13 D12 D11 D10 D09 D08
(R/W)
( X )
D14
(R/W)
( X )
(R/W)
( X )
000039H
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
Read/write
Default value
Read/write
Default value
42
(2) Block Diagram
•8-
bit PPG ch 0/2/4 Block Diagram
MB90470 Series
Peripheral clock 16 divider
Peripheral clock 8 divider
Peripheral clock 4 divider
Peripheral clock 2 divider
Peripheral clock
Count
clock selection
Time base counter output
clock 512 divider
L/H selection
PCNT
(down counter)
L/H selector
PRLBHPRLL
PPG 0/2/4 output enable
PPG 0/2/4 output latch
PPG0/2/4
A/D converter
PEN0
S
R
Q
ch 1/3/5 borrow
PUF0
PPGC0 (output mode control)
PIE0
IRQ
PRLL
L data bus
H data bus
43
MB90470 Series
•8-
bit PPG ch 1/3/5 Block Diagram
Peripheral clock 16 divider
Peripheral clock 8 divider
Peripheral clock 4 divider
Peripheral clock 2 divider
Peripheral clock
Count
clock selection
Time base counter output
clock 512 divider
L/H selection
PCNT
(down counter)
L/H selector
PRLBHPRLL
PPG 1/3/5 output enable
PPG 1/3/5 output latch
PPG1/3/5
UART0
PEN1
S
Q
R
PUF1
PPGC1 (output mode control)
PIE1
IRQ
44
PRLL
L data bus
H data bus
MB90470 Series
6. 8/16-bit Up-down Counter/Timer
This block is an up-down counter/timer configured with six event input pins, two 8-bit up/down counters, two
8-bit reload/compare registers, and related control circuits.
(1) Principal functions
• 8-bit count registers for counting in the range 0 to 256.
(Also operates in 16-bit × 1 mode for counting in the range 0 to 65535.)
• Count clock selection provides four count modes.
Count mode Time mode
Up/down count mode
Phase differential count mode (2 × )
Phase differential count mode (8 × )
• In timer mode, there is a choice of two internal count clocks.
Count clock 125 ns (8 MHz : divided by 2)
(16 MHz operation) 0.5 µs (2 MHz : divided by 8)
• In up/down count mode, there is a choice of external pin input signal detection edge.
Detection edge Falling edge detection
Rising edge detection
Falling/rising edge, both edges’ detection
Edge detection disabled
• In phase differential count mode, to provide counts for encoders for motors, etc., the A phase, B phase, and
Z phase of the encoder can be input separately for highly precise counts of rotation angle, rotary speed, etc.
• The ZIN pin provides a choice of two functions.
ZIN pin Counter clear function
Gate function
• Compare and reload functions are provided, each available independently or in combination. Both can be
started together to provide any desired type of up/down count.
Compare/reload function Compare function (outputs interrupt at compare events)
Compare function (outputs interrupt and clears count at compare events)
Reload function (outputs interrupt and reloads at underflow events)
Compare/reload function
(outputs interrupt and clears count at compare events, outputs interrupt
and reloads at underflow events)
Compare/reload disabled
• Individually controllable interrupts at compare, reload (underflow) and overflow events.
• Count direction flag enables detection of immediately preceding count direction.
• Interrupt generation at change of count direction.
45
MB90470 Series
(2) Register List
15 0
RCR1
CCRH0
CCRH1
87
UDCR0UDCR1
RCR0
CSR0Reserved
CCRL0
CSR1Reserved
CCRL1
8 bit
CCRH0 (Counter control register high ch.0)
15 14 13 12 11 10 9 8
Address : 00006D
H 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
CDCFM16E CFIE CLKS CMS1 CMS0 CES1 CES0
CCRH1 (Counter control register high ch.1)
15 14 13 12 11 10 9 8
Address : 000071
H -0000000B
CDCF
CFIE CLKS CMS1 CMS0 CES1 CES0
R/W R/W R/W R/W R/W R/W R/W
CCRL0/1 (Counter control register low ch.0/1)
Address
Address
: 00006CH
: 000070H
76543210
CTUTUDMS UCRE RLDE UDCC CGSC CGE1 CGE0
R/W W R/W R/W W R/W R/W R/W
CSR0/1 (Counter status register ch. 0/1)
Address
Address
: 000072H
: 000074H
76543210
CITECSTR UDIE CMPF OVFF UDFF UDF1 UDF0
R/W R/W R/W R/W R/W R/W R R
UDCR0/1 (Up down count register ch. 0/1)
15 14 13 12 11 10 9 8
Address : 000069
H 00000000B
D16D17 D15 D14 D13 D12 D11 D10
RRRRRRRR
8 bit
Default value
Default value
Default value
0X00X000B
Default value
00000000B
Default value
Address : 000068
H 00000000B
RCR0/1 (Reload/compare register ch. 0/1)
Address : 00006B
Address : 00006A
H 00000000B
H 00000000B
46
76543210
D06D07 D05 D04 D03 D02 D01 D00
RRRRRRRR
15 14 13 12 11 10 9 8
D16D17 D15 D14 D13 D12 D11 D10
WWWWWWWW
76543210
D06D07 D05 D04 D03 D02 D01 D00
WWWWWWWW
Default value
Default value
Default value
(3) Block Diagram
CGE1 CGE0 CGSC
MB90470 Series
Data bus
8 bit
RCR0 (Reload/compare register 0)
ZIN0
AIN0
BIN0
Edge/level detection
UDCC
CES1 CES0
CMS1 CMS0
Up-down count
clock selection
Prescaler
CLKS
UDMS
CTUT
UCRE RLDE
Counter clear
8 bit
UDF1 UDF0 CDCF CFIE
CSTR
Reload control
UCDR0 (Up/down count register 0)
Count
clock
Interrupt
output
UDFF OVFF
CITE UDIE
Carry
CMPF
47
MB90470 Series
7. DTP/External Interrupts
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces exter nal peripherals to the F2MC-16L
CPU. The DTP receiv es DMA request from e xternal peripherals and passes the requests to the F
2
MC-16L CPU
to activate the extended µDMA or interrupt processing.
(1) Register Descriptions
Interrupt/DTP enable register (ENIR : Enable Interrupt Request Register)
ENIR Default value
Address : 00000C
76543210
H 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
EN6EN7 EN5 EN4 EN3 EN2 EN1 EN0
Interrupt/DTP source register (EIRR : External Interrupt Request Register)
EIRR Default value
Address : 00000D
15 14 13 12 11 10 9 8
H 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
ER6ER7 ER5 ER4 ER3 ER2 ER1 ER0
(note that both
registers relate
to different
interrupts)
Request level setting register (ELVR : External Level Register)
Default value
Address : 00000E
76543210
H 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
LA3LB3 LB2 LA2 LB1 LA1 LB0 LA0
Address : 00000F
(2) Block Diagram
2
MC-16 bus
F
4
4
4
8
15 14 13 12 11 10 9 8
H 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
Gate Source F/F Edge detection circuit Request input
LA7LB7 LB6 LA6 LB5 LA5 LB4 LA4
Interrupt/DTP enable register
4
Interrupt/DTP source register
Interrupt level setting register
Default value
48
MB90470 Series
8. 16-bit Input Output Timer
The 16-bit input/output timer is composed of one 16-bit free-run timer module, 6 output compare modules, and
2 input capture modules. These functions can be used to produce output of six independent wave forms based
on the 16-bit free-run timer, with input pulse width measurement and external clock period measurement.
•
List of Registers for All Modules
• 16-bit free-run timer
15 0
000066/67H
CPCLR
Compare clear register
000062/63H
000064/65H
• 16-bit output compare
00004A, 4C, 4E, 50, 52, 54H
00004B, 4D, 4F, 51, 53, 55H
000056, 58, 5AH
000057, 59, 5BH
• 16-bit input capture
00005C, 5EH
00005D, 5FH
000060H
TCDT
TCCS
15 0
OCCP0 to OCCP5 Compare register
OCS0/2/4OCS1/3/5
15 0
IPCP0, ICCP1 Compare register
ICS
Timer data register
Control status register
Control status register
Control status register
49
MB90470 Series
•
Overall Block Diagram
16-bit free-run timer
Output
compare 0
Output
compare 1
Output
compare 2
Bus
Control logic
Interrupt
16-bit timer
Compare register 0
Compare register 1
Compare register 2
Clear
TQ
TQ
TQ
To blocks
OUT0
OUT1
OUT2
Output
compare 3
Output
compare 4
Output
compare 5
Input
capture 0
Input
capture 1
Compare register 3
Compare register 4
Compare register 5
Capture register 0
Capture register 1
TQ
TQ
TQ
Edge selection
Edge selection
OUT3
OUT4
OUT5
IN0
IN1
50
MB90470 Series
(
)(
)(
)(
)(
)(
)(
)(
)
(1) 16-bit Free-run Timer
The 16-bit free-run timer is composed of a 16-bit up-down counter and control register.
The count value from this timer is used as the base timer for the input capture and output compare modules.
• A selection of 8 clock types for counter operation is available.
• Counter overflow interrupts can be generated.
• By a mode setting, the counter can be initialized when the timer value matches the compare register v alue f or
the output compare module.
•
Register list
Compare clear register (CPCLR)
15 14 13 12 11 10 9 8
000067
000066
H XXXXXXXXB
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
H XXXXXXXXB
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
CL14CL15 CL13 CL12 CL11 CL10 CL09 CL08
76543210
CL06CL07 CL05 CL04 CL03 CL02 CL01 CL00
Timer counter data register (TCDT)
15 14 13 12 11 10 9 8
000063
000062
H 00000000B
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
H 00000000B
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
T14T15 T13 T12 T11 T10 T09 T08
76543210
T06T07 T05 T04 T03 T02 T01 T00
Timer counter control/status register (TCCS)
15 14 13 12 11 10 9 8
000065
H 0--00000B
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
ECKE MSI2 MSI1 MSI0 ICLR ICRE
Default value
Default value
Default value
Default value
Default value
000064
76543210
H 00000000B
R/W
IVFEIVF STOP MODE SCLR CLK2 CLK1 CLK0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default value
51
MB90470 Series
•
Block Diagram
φ
Bus
Interrupt request
IVF IVFE STOP MODE SCLR CLK1 CLK0
16-bit free-run timer
16-bit compare clear register
CLK2
Count value output T15 to T00
ICLRMSI3 to 0Compare circuit ICRE
Frequency
divider
Clock
Interrupt request
A/D converter startup
52
MB90470 Series
(2) Output Compare
The output compare module consists of a 16-bit compare register, compare output pin unit, and control register.
When the value in the compare register in this module matches the value of the 16-bit free-run timer, the pin
output level can be inverted and an interrupt generated.
• There are six compare registers that can operate independently. Module settings can be used to use the two
compare registers to control the output.
• The interrupt can be set by a compare match.
•
Register List
Compare register (OCCP0 to OCCP5)
00004B
00004DH
00004FH
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
000051H
000053H
000055H
00004AH
00004CH
00004EH
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
000050H
000052H
000054H
Control register (OCS1/3/5)
000057
H
000059H
00005BH
Control register (OCS0/2/4)
15 14 13 12 11 10 9 8
C14C15 C13 C12 C11 C10 C09 C08
6543210
C06C07 C05 C04 C03 C02 C01 C00
15 14 13 12 11 10 9 8
CMOD OTE1 OTE0 OTD1 OTD0
( )( )( ) (R/W) (R/W) (R/W) (R/W) (R/W)
Default value
XXXXXXXXB
Default value
XXXXXXXXB
Default value
---00000B
000056H
000058H
00005AH
76543210
ICP0ICP1 ICE1 ICE0 CST1 CST0
(R/W) (R/W) (R/W) (R/W) ( )( ) (R/W) (R/W)
Default value
0000--00B
53
MB90470 Series
•
Block Diagram
16-bit timer counter value (T15 to T00)
Compare control
Compare register 0 (2)
16-bit timer counter value (T15 to T00)
Bus
Compare control
Compare register 1 (3)
Control unit
Control blocks
ICP1 ICP0 ICE0 ICE0
TQ
CMOD
TQ
OTE0
OTE1
Compare 1 (3) (5) interrupt
Compare 0 (2) (4) interrupt
OUT0 (2) (4)
OUT1 (3) (5)
54
MB90470 Series
(
)(
)(
)(
)(
)(
)(
)(
)
(3) Input Capture
The input capture module detects the rising edge, falling edge, or both edges of an input signal and saves the
value of the 1-bit free-run timer at that moment in a register. This module can also generate an interrupt when
an edge is detected.
The input capture module is composed of input capture registers and a control register. Each of the input captures
has a corresponding external input pin.
• Selection of three valid edges for external input :
Rising edge/falling edge/both edges
• An interrupt can be generated when the valid edge is detected.
•
Register List
Input capture data registers (IPCP0, IPCP1)
15 14 13 12 11 10 9 8
00005D
00005FH
00005C
00005EH
H
( R ) ( R ) ( R ) ( R ) ( R ) ( R ) ( R ) ( R )
H
( R ) ( R ) ( R ) ( R ) ( R ) ( R ) ( R ) ( R )
CP14CP15 CP13 CP12 CP11 CP10 CP09 CP08
76543210
CP06CP07 CP05 CP04 CP03 CP02 CP01 CP00
Control status register (ICS0, ICS1)
76543210
•
Block Diagram
000060H 00000000B
R/W
ICP0ICP1 ICE1 ICE0 EG11 EG10 EG01 EG00
Capture data register 0
R/W
R/W
R/W
R/W
R/W
Edge detection
R/W
Default value
XXXXXXXXB
Default value
XXXXXXXXB
Default value
R/W
IN0
Bus
16-bit timer counter value (T15 to T00)
Capture data register 1
ICP1 ICP0 ICE1 ICE0
EG11 EG10 EG01 EG00
Edge detection
Interrupt
Interrupt
IN1
55
MB90470 Series
9. I2C Interface
The I2C interface is a serial I/O port suppor ting Inter IC bus operation, and operates as a master/slave device
on the I
2
C bus. The following features are provided.
• Master/slave sending and receiving
• Arbitration functions
• Clock synchronization functions
• Slave address/general call address detection functions
• Transfer direction detection function
• Start condition repeat generator and detection function
• Bus error detection function
(1) Register List
IBSR (bus status register)
Address : 000088
Read/write
Default value
76543210
H
BB AL LRB TRX AAS GCA FBT
( R )
( 0 )
RSC
( R )
( 0 )
( R )
( 0 )
( R )
( 0 )
( R )
( 0 )
( R )
( 0 )
( R )
( 0 )
( R )
( 0 )
Bit no.
IBCR (bus control register)
Address : 000089
Read/write
Default value
15 14 13 12 11 10 9 8
H
BER SCC MSS ACK GCAA INTE INT
(R/W)
( 0 )
BEIE
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0)
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
Bit no.
ICCR (clock control register)
Address : 00008AH
Read/write
Default value
IADR (address register)
Address : 00008B
H
Read/write
Default value
IDAR (data register)
Address : 00008CH
Read/write
Default value
76543210
EN CS4 CS3 CS2 CS1 CS0
( )
( )
15 14 13 12 11 10 9 8
A5 A4 A3 A2 A1 A0
( )
( )
76543210
D7 D5 D4 D3 D2 D1 D0
(R/W)
( X )
( )
( )
A6
(R/W)
( X )
D6
(R/W)
( X )
(R/W)
( 0 )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
Bit no.
Bit no.
Bit no.
56
(2) Block Diagram
ICCR
EN
ICCR
I2C enable
Clock divider 1
56 7
MB90470 Series
Peripheral clock
8
MC-16 bus
2
F
CS4
CS3
CS2
CS1
CS0
IBSR
BB
RSC
LRB
TRX
FBT
AL
IBCR
BER
BEIE
INTE
Clock select 1
Clock divider 2
2 4 8 16 128
Clock select 2
Bus busy
Repeat start
Last Bit
Send/receive
Start/stop
condition detector
First Byte
Arbitration
lost detector
Interrupt request
Sync
25632 64
Shift clock
edge change timing
Error
IRQ
Shift clock generator
SCL
SDA
INT
IBCR
SCC
MSS
ACK
GCAA
IBSR
AAS
GCA
Start
Master
ACK enable
GC-ACK enable
Slave
Global call
End
Start/stop
condition generator
IDAR
Slave address
compare
IADR
57
MB90470 Series
10. 16-bit reload timer
The 16-bit reload timer provides a choice of two functions, one is an internal clock countdown synchronized with
any of 3 types of internal clock, and the other is an event count mode that counts down at detection of a given
edge of a pulse input externally. This timer defines an underflow as a transition of the count value from 0000
to FFFFH. Therefore, an underflow will occur at the count value “reload register setting count + 1”. The count
operation includes a choice of reload mode in which the count set value is reloaded at each underflow event,
and one-shot mode in which the count stops at an underflow event. An interr upt can be generated when the
counter reaches an underflow, and the timer is DTC compatible.
(1) Register List
• TMCSR (Timer control status registers)
Timer control status register (high)
15 14 13 12 11 10 9 8
0000CBH
CSL1 CSL0 MOD2 MOD1
( )
( )
Timer control status register (low)
( )
( )
( )
( )
( )
( )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
Read/write
Default value
H
76543210
0000CA
H
MOD0 OUTL RELD INTE UF CNTE TRG
(R/W)
( 0 )
OUTE
(R/W)
( 0 )
(R/W)
( 0 )
• 16-bit timer register/16-bit reload register
/TMRLR (high)
TMR
15 14 13 12 11 10 9 8
0000CD
H
D15 D13 D12 D11 D10 D09 D08
(R/W)
( X )
D14
(R/W)
( X )
(R/W)
( X )
TMR/TMRLR (low)
76543210
0000CC
H
D07 D05 D04 D03 D02 D01 D00
(R/W)
( X )
D06
(R/W)
( X )
(R/W)
( X )
(R/W)
( 0 )
(R/W)
( X )
(R/W)
( X )
(R/W)
( 0 )
(R/W)
( X )
(R/W)
( X )
(R/W)
( 0 )
(R/W)
( X )
(R/W)
( X )
(R/W)
( 0 )
(R/W)
( X )
(R/W)
( X )
(R/W)
( 0 )
(R/W)
( X )
(R/W)
( X )
Read/write
Default value
Read/write
Default value
Read/write
Default value
58
(2) Block Diagram
Count clock generator circuit
Machine
clock φ
Internal data bus
TMRLR
16-bit reload register
TMR
16-bit timer register
(down counter)
Prescaler
Clear
CLK
3
Gate
input
UF
Reload signal
Valid clock
decision circuit
CLK
MB90470 Series
Wait signal
Output signal
generator circuit
Reload
control circuit
To
A/D converter
Pin
(TIN0)
Input
control circuit
3
Clock selector
External clock
2Function select Select signal
Timer control status register (TMCSR)
Output signal
Invert
generator circuit
Pin
(TOT0)
EN
RELDOUTL
Operation
control circuit
OUTE
59
MB90470 Series
11. µµµµPG Timer
The µPG timer produces a pulse output according to an external input signal.
(1) Register List
PGCSR (PG control/status register)
Operating mode control register
76543210
00008E
(2) Block Diagram
H
PEN0 PE0 PMT1 PMT0
(R/W)
( 0 )
PE1
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
( )
( )
( )
( )
( )
( )
Read/write
Default value
MT00
output latch
Control circuit
MT00
MT01
Output enable
MT00
output latch
EXTC
60
MB90470 Series
12. PWC (Pulse Width Count) Timer
The PWC timer is a 16-bit multi-function up-count timer with an input signal pulse width measurement function.
The hardware includes a total of three channels, each with one 16-bit up-count timer, one input pulse divider
and divider ration control register, one measurement input pin, and one 16-bit control register. The following
functions are provided :
Timer functions :
An interrupt can be generated each time a set time interval elapses. A choice of three internal reference clocks
is available.
Pulse width measurement functions :
Measures the time between designated ev ents on an externally input pulse signal. The reference clock is selected
from three internal clock signals.
Measurement modes : 1) H pulse width (
2) Rise period (
3) Measurement between edges (high or low to low or high)
An 8-bit input divider can divide the input pulse into 2
An interrupt can be generated when measurement is ended. Both one-time and continuous measurement are
enabled.
↑ to ↓) /L pulse width (↑ to ↓)
↑ to ↑) /fall period (↓ to ↓)
2n
divisions (n = 1, 2, 3, 4) and measure the divisions.
61
MB90470 Series
(1) Register List
15 0
PWCSR0 to PWCSR2
87
PWC0 to PWC2
DIVR0 to DIVR2
PWCSR0 to PWCSR2 (PWC control/status registers)
000077
00007BH
00007FH
000076
00007AH
00007EH
H
H
15 14 13 12 11 10 9 8
STRT EDIR EDIE OVIR OVIE ERR
(R/W)
CKS1 PIS1 PIS0 S/C MOD2 MOD1 MOD0
(R/W)
STOP
(R/W)
( 0 )
( 0 )
( 0 )
76543210
CKS0
(R/W)
( 0 )
( R )
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
PWCR0 to PWCR2 (PWC data buffer registers)
000079
00007DH
000081H
H
15 14 13 12 11 10 9 8
D15 D13 D12 D11 D10 D9 D8
(R/W)
( 0 )
D14
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
( R )
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
Reserved
( )
( X )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
(R/W)
(R/W)
Read/write
Default value
Read/write
Default value
Read/write
Default value
000078
00007CH
000080H
H
76543210
D7 D5 D4 D3 D2 D1 D0
(R/W)
( 0 )
D6
(R/W)
( 0 )
(R/W)
( 0 )
DIVR0 to DIVR2 (Divider control register)
000082
000084H
000086H
H
76543210
DIV1 DIV0
( )
( X )
( )
( X )
( )
( X )
(R/W)
( 0 )
( )
( X )
(R/W)
( 0 )
( )
( X )
(R/W)
( 0 )
( )
( X )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
Read/write
Default value
Read/write
Default value
62
(2) Block Diagram
MB90470 Series
MC-16 bus
2
F
Flag set etc.
15
PWCR read
Overflow
Measure
start edge
Measure
end edge
Control bit output
Measurement end
interrupt request
Overflow interrupt
request
Error detector
Reload
Data transfer
Control circuit
Start edge
selection
Edge detection
ERR
PWCSR
2
ERR
PWCR
16
16
16-bit up/down timer
End edge
selection
PIS0/PIS1
CKS0/CKS1
Clock
Timer
clear
Divider on/off
Divider select
DIVR
CKS1/CKS0
Count enable
8-bit divider
Internal clock
(machine clock / 4)
2
2
Clock divider
3
2
Divider
clear
Input
waveform
comparator
PWC0
PWC1
63
MB90470 Series
13. Watch Timer
The watch timer is a 15-bit timer using a sub-clock signal. This timer can generate interval interrupts. Also, by
a register setting, it can be used as a clock source for the watchdog timer.
(1) Register List
Watch timer control register (WTC)
76543210
0000AA
H
(2) Block Diagram
Watch timer control register (WTC)
WDCS WTIE WTOF WTR WTC2 WTC1 WTC0
(R/W)
( 1 )
SCE
( R )
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 1 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
Default value
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
Clear
8
2
9
Sub-clock
Watch counter
2102132142
2
10
2
11
2
12
2
13
2
14
15
2
Interval selector
Interrupt
generator
circuit
To watchdog timer
Watch timer
interrupt
64
MB90470 Series
14. Watchdog Timer
The watchdog timer is a 2-bit counter that uses a count clock signal output by the timer base timer or watch
timer and will reset the CPU unless cleared within a specified period of time.
(1) Register List
Watchdog timer control register (WDTC)
76543210
( R )
( X )
Reserved
( )
( X )
Watchdog timer control register (WDTC)
PONR STBR WRST ERST SRST WTE WT1 WT0
Watchdog timer
( R )
( X )
( R )
( X )
2
( R )
( X )
( W )
( 1 )
( W )
( 1 )
CLR and start
( W )
( 1 )
Default value
Watch timer control register
(WT0) WDCS bit
Clock select register
(CKSCR) SCM bit
CLR
0000A8
H
(2) Block Diagram
Watch mode start
Time base timer
mode start
Sleep mode start
Hold status start
PONR WRST ERST SRST WTE WT1 WT0
Counter clear
control circuit
Stop mode start
Clear
Time base counter
HCLK signal / 2
SCLK
× 2
× 2
1
1
HCLK : Oscillator clock
SCLK : Sub-clock
× 2
× 2
Count
clock
selector
4
2
2
× 28× 29× 210× 211× 212× 213× 214× 215× 216× 217× 2
× 28× 29× 210× 211× 212× 213× 214× 215× 216× 217× 2
2-bit counter
CLR
Watchdog reset
generator circuit
4
18
18
Internal reset
generator
circuit
65
MB90470 Series
15. Time Base Timer
The time base timer is an 18-bit free-run timer that counts up in synchronization with the internal count clock
(base oscillator divided by 2) . It functions as an interval timer with a selection of four types of time intervals.
Other functions of this timer also include output of a timer signal for the oscillator stabilization wait time and an
operating clock signal for the watchdog timer.
(1) Register List
Time base timer control register (TBTC)
15 14 13 12 11 10 9 8
0000A9
(2) Block Diagram
H
RESV TBIE TBOF TBR TBC1 TBC0
(R/W)
( 1 )
( )
( X )
( )
( X )
(R/W)
( 0 )
(R/W)
( 0 )
( W )
( 1 )
(R/W)
( 0 )
(R/W)
( 0 )
Time base timer/
counter
HCLK signal /2
Power-on reset
Stop mode start
Mode start
Hold status start
CKSCR : MCR = 1 → 0
CKSCR : SCS = 0 → 1
Time base timer control register (TBTC)
Time base timer interrupt signal
: Not used
OF : Overflow
HCLK : Oscillator clock
*1 : Switches machine clock from main clock or sub-clock to PLL clock.
*2 : Switches machine clock from sub-clock to main clock.
× 21× 2
*1
*2
To PPG timer
2
Counter
clear
control
circuit
To watchdog timer
× 28× 29× 210× 211× 212× 213× 214× 215× 216× 217× 2
OF
TBOF clear
OF
Interval timer selector
OF
TBOF
set
TBIE TBOF TBRRESV TBC1 TBC0
OF
18
Clock control unit
Oscillator stabilization wait
To interval selector
66
MB90470 Series
16. Clock
The clock generator module controls the operation of the internal clocks that produce the operating cloc k signals
for the CPU and peripheral devices. This inter nal clock signal is called the machine clock, and one period is
called a machine cycle. The clock signal from the base oscillator is called the oscillator clock, and the clock
signal generated by the internal PLL module is called the PLL clock.
(1) Register List
Clock select register (CKSCR)
15 14 13 12 11 10 9 8
0000A1
SCM WS1 WS0 SCS MCS CS1 CS0
H
( R )
( 1 )
MCM
( R )
( 1 )
(R/W)
( 1 )
(R/W)
( 1 )
(R/W)
( 1 )
(R/W)
( 1 )
(R/W)
( 0 )
( R/W )
( 0 )
Default value
67
MB90470 Series
(2) Block Diagram
Standby control circuit
Low power mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0
pin
RST
Interrupt release
served
CPU intermittent
operation selector
Standby
control circuit
Re-
Pin High-Z
control circuit
Internal reset
generator circuit
Intermittent cycle selection
CPU clock
control circuit
Stop, sleep signals
Stop signal
Pin
high-impedance
control
Internal reset
CPU clock
Clock generator module
Divide
by 4
Sub-clock
generator
circuit
pin
X0A
pin
X1A
pin
X0
pin
X1
Machine clock
Clock
selector
SCLK
PLL multiplier
circuit
System
clock
generator
circuit
Divide
by 2
HCLK
HCLK : Oscillator clock
MCLK : Main clock
SCLK : Sub-clock
Oscillator stabilization wait release
SCM
MCM WS1 WS0 SCS MCS CS1 CS0
Clock select register (CKSCR)
Divide
by 1024
MCLK
Time base timer
Divide
by 2
2
Divide
by 4
Peripheral clock
control circuit
2
Divide
by 4
To watchdog timer
Divide
by 4
Peripheral clock
Oscillator
stabilization
wait period
selector
Divide
by 2
68
(3) Clock Signal Supply Map
Clock generator ratio
X0A
pin
X1A
pin
X0
pin
X1
pin
Sub-clock
generator
circuit
System clock
generator
circuit
HCLK
Divide by 4
Divide by 2
MCLK
Watch timer
Time base timer
1234
PLL
multiplier circuit
PCLK
SCLK
Clock selector
CPU, µDMA
MB90470 Series
Peripheral function
4
Watchdog timer
4
8/16-bit PPG timer 0
8/16-bit PPG timer 1
8/16-bit PPG timer 2
φ
16-bit reload timer
UART
PPG0, PPG1
pin
PPG2, PPG3
pin
PPG4, PPG5
pin
TIN0
pin
TOT0
pin
SCK0, SIN0
pin
SOT0
pin
HCLK : Oscillator clock
MCLK : Main clock
SCLK : Sub-clock
PCLK : PLL clock
φ : Machine clock
I/O expansion
serial interface
8/16-bit U/D counter
Chip select
16-bit output compare
16-bit free-run timer
16-bit input capture
10-bit A/D converter
External interrupt
µ
PG
I2C interface
16-bit PWC 3ch
Oscillator stabilization
3
wait control
2 ch
SCK1, SCK2,
SIN1, SIN2
pin
SOT1, SOT2
pin
AIN0, AIN1
BIN0, BIN1
ZIN0, ZIN1
pin
CS0, CS1,
CS2, CS3
pin
OUT0, OUT1,OUT2,
OUT3, OUT4, OUT5
pin
FRCK
pin
IN0, IN1
pin
AN0 to AN7, ADTG
pin
IRQ0 to IRQ7
pin
IN0, IN1
pin
MT00, MT01
pin
SCL, SDA
pin
PWC1, PWC2, PWC3
pin
69
MB90470 Series
17. Low Power Modes
The MB90470 series uses a selection of operating clock signals and clock operation controls to prov ide the
following CPU operating modes.
• Clock modes
(PLL clock mode, main clock mode, sub-clock mode)
• CPU intermittent operation modes
(PLL clock intermittent operation mode, main clock intermittent operation mode, sub-clock intermittent
operation mode)
• Standby mode
(Sleep mode, time base timer mode, stop mode, watch mode)
(1) Register List
Low power mode control register (LPMCR)
76543210
(R/W)
( 0 )
Reserved
(R/W)
( 0 )
Default value
0000A0
STP SPL RST TMD CG1 CG0
H
( W )
( 0 )
SLP
( W )
( 0 )
(R/W)
( 0 )
( W )
( 1 )
(R/W)
( 1 )
(R/W)
( 0 )
70
(2) Block Diagram
Standby control circuit
Low power mode control register (LPMCR)
pin
RST
Interrupt release
STP SLP SPL RST TMD CG1 CG0
CPU intermittent
operation selector
Standby
control circuit
Re-
served
MB90470 Series
Pin High-Z
control circuit
Internal reset
generator circuit
Intermittent cycle selection
CPU clock
control circuit
Stop, sleep signals
Stop signal
Pin
high-impedance
control
Internal reset
CPU clock
Clock generator module
Divide
by 4
Sub-clock
generator
circuit
pin
X0A
pin
X1A
pin
X0
pin
X1
Machine clock
Clock
selector
SCLK
PLL multiplier
circuit
System
clock
generator
circuit
Divide
by 2
HCLK
HCLK : Oscillator clock
MCLK : Main clock
SCLK : Sub-clock
Oscillator stabilization wait release
SCM
MCM WS1 WS0 SCS MCS CS1 CS0
Clock select register (CKSCR)
Divide
1024
MCLK
Time base timer
Divide
by 2
2
Divide
by 4
Peripheral clock
control circuit
2
Divide
by 4
To watchdog timer
Divide
by 4
Peripheral clock
Oscillator
stabilization
wait period
selector
Divide
by 2
71
MB90470 Series
(3) Status Transition Chart
Power on
Power-on reset
Oscillator
stabilization
wait end
Main clock mode
SLP = 1 Interrupt SLP = 1 SLP = 1
External reset, watchdog timer reset, software reset
Reset
SCS = 1
MCS = 0
MCS = 1
PLL clock mode
Interrupt
SCS = 0
SCS = 1
SCS = 0
Sub-clock mode
Interrupt
Main sleep mode
TMD = 0 TMD = 0 TMD = 0
STP = 1
Main stop mode
Interrupt
Main clock oscillator
stabilization wait
Interrupt
Time base
timer mode
Oscillator
stabilization
wait end
PLL sleep mode
Interrupt
Time base
timer mode
STP = 1 STP = 1
PLL stop mode
Interrupt
Main clock oscillator
stabilization wait
Oscillator
stabilization
wait end
Interrupt
Sub-sleep mode
Interrupt
Watch mode
Sub-stop mode
Oscillator
stabilization
wait end
Sub-clock oscillator
stabilization wait
72
MB90470 Series
18. Overview of the Chip Select Function
This module issues chip select signals in order to facilitate connection to external memory. There are four chip
select output pins, with hardware areas set using a register for each output, so that the select signal is output
from the related pin whenever access to an external address is detected.
• Features of the chip select function
The chip select function has two 8-bit registers for settings f or each of the f our output pins . One register (CARx)
is used to specify the upper 8 bits of the address for match detection, thereby pro viding memory area detection
in 64 KB units. The other register (CMRx) can be set to detect areas larger than 64 KB by masking bits in the
match detection value.
Note that the CS output is set to high impedance during a bus hold condition.
(1) Register List
15 0
CAR1
CAR3
Chip select area MASK register (CMRx)
0000C0
0000C2H
0000C4H
0000C6H
H
76543210
M7 M5 M4 M3 M2 M1 M0
(R/W)
( 0 )
M6
(R/W)
( 0 )
(R/W)
( 0 )
Chip select area register (CARx)
0000C1
0000C3H
0000C5H
0000C7H
15 14 13 12 11 10 9 8
H
A7 A5 A4 A3 A2 A1 A0
(R/W)
( 1 )
A6
(R/W)
( 1 )
(R/W)
( 1 )
Chip select control register (CSCR)
76543210
0000C8
H
OPL3 OPL2 OPL1 OPL0
( )
( )
( )
( )
( )
( )
(R/W)
( 0 )
(R/W)
( 1 )
( )
( )
87
CMR0CAR0
CMR1
CMR2CAR2
CMR3
CSCR (R/W)CALR
(R/W)
( 1 )
(R/W)
( 1 )
(R/W)
( 0 )
(R/W)
( 1 )
(R/W)
( 1 )
(R/W)
( 0 )
(R/W)
( 1)
(R/W)
( 1 )
(R/W)
( 0 )
(R/W)
( 1 )
(R/W)
( 1 )
(R/W)
( ∗ )
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Read/write
Default value
Read/write
Default value
Read/write
Default value
Chip selector active level register (CALR)
15 14 13 12 11 10 9 8
0000C9
H
ACTL3 ACTL2 ACTL1 ACTL0
( )
( )
( )
( )
( )
( )
( )
( )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
Default value
73
MB90470 Series
(2) Block Diagram
CMRx
FMC-16 bus
CARx
Chip select output pin
A23 to A16
74
MB90470 Series
19. ROM Mirror Function Select Module
The ROM mirror function select module provides a register selection that allows the FF bank in ROM to be
viewed in the 00 bank.
(1) Register List
15 14 13 12 11 10 9 8
bit Default value
ROMM Address : 00006F
W : Write only
- : Not used
(2) Block Diagram
H - - - - - - - 1B
MI
W
2
MC-16LX
F
ROM mirror function select
Address area
FF bank
00 bank
ROM
Note : Do not access this register during operations to address 004000
H to 00FFFFH.
75
MB90470 Series
20. Interrupt Controller
The interrupt control registers are located in the interrupt controller. An interrupt control register is provided for
each I/O with an interrupt function. The registers have the following functions.
• Set the interrupt level of the corresponding peripheral.
(1) Register List
Interrupt control register
Address:
Address:
: 0000B1
ICR01
: 0000B3H
ICR03
: 0000B5H
ICR05
: 0000B7H
ICR07
: 0000B9H
ICR09
: 0000BBH
ICR11
: 0000BDH
ICR13
: 0000BFH
ICR15
Read/Write→
Initial value→
: 0000B0
ICR00
: 0000B2H
ICR02
: 0000B4H
ICR04
: 0000B6H
ICR06
: 0000B8H
ICR08
: 0000BEH
ICR14
Read/Write→
Initial value→
H
bit
15 14 13 12 11 10 9 8
----
(W) (W) (W) (W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
H
bit
15 14 13 12 11 10 9 8
--
(W) (W) (W) (W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
--
Re-
served
(0)(0)
Re-
served
(0)(0)
IL2 IL1 IL0
(1)
(0)
IL2 IL1 IL0
(1)
(0)
(1)
(1)
ICR01, 03, 05,
07, 09, 11, 13,
15
(1)
ICR00, 02, 04,
26, 08, 10, 12,
14
(1)
Note : Do not access these registers using read-modify-write instructions as this can cause misoperation.
(2) Block Diagram
3
3
3
3
3
3
3
3
3
3
3
MC-16LX Bus
2
3
F
3
3
3
3
Re-
served
IL2 IL1 IL0
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Determine
priority
of interrupt
32
Interrupt request
(peripheral resource)
3
(CPU)
Interrupt level
76
MB90470 Series
21. µµµµDMA
µDMA is the simplified DMA which has the equivalent function to EI2OS function µDMA has DMA transfer channel
which consists of 16 channels and has the following functions.
• Automatic data transfer between peripheral resources (I/O) and memory.
• CPU program executing stops dring DMA operation.
• Selectable for address transfer increase/decrease .
• DMA transfer control is done at DMA enable register, DMA stop status register, DMA status register and
descriptor.
• Stop request stops DMA transfer from resources.
• After DMA transfer, flag is set to bit corresponding to DMA status register transfer stop channel and stop
interrupt is output to interrupt controller.
(1) Register List
DMA enable register
bit
DERH : 0000ADH 0 0 0 0 0 0 0 0B
15 14 13 12 11 10 9 8
EN15 EN13 EN12 EN11 EN10 EN9 EN8
(R/W)
EN14
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
DMA enable register
bit
DERL : 0000ACH 0 0 0 0 0 0 0 0B
76543210
EN7 EN5 EN4 EN3 EN2 EN1 EN0
(R/W)
EN6
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
DMA stop status register
bit
76543210
DSSR : 0000A4H 0 0 0 0 0 0 0 0B
STP6STP7 STP5 STP4 STP3 STP2 STP1 STP0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(R/W)
DMA status register
bit
15 14 13 12 11 10 9 8
DSRH : 00009DH 0 0 0 0 0 0 0 0B
DE14DE15 DE13 DE12 DE11 DE10 DE9 DE8
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(R/W)
DMA status register
bit
76543210
DSRL : 00009CH 0 0 0 0 0 0 0 0B
DE7 DE5 DE4 DE3 DE2 DE1 DE0
( R/W )
DE6
( R/W ) ( R/W ) ( R/W ) (R/W) (R/W) (R/W) (R/W)
Initial value
Initial value
Initial value
Initial value
77
MB90470 Series
(2) Block Diagram
Memory area
by IOA
I/O register
I/O register
Peripheral
functions (I/O)
Not transfer
stop
DMA
DER read
descriptor
by BAP
Buffer
by DCT
Transfer
IOA : Address pointer
BAP : Buffer address pointer
DER : DMA enable register (ENx selection is done.)
DTC : Data counter
DMA controller
CPU
DMA transfer
request
At transfer
stop
Interrupt
controller
F
2
MC-16LX Bus
78
MB90470 Series
22. External Bus Pin Control Circuit
The external bus pin control circuit controls the external bus pins used to expand the CPU address/data bus
connections to external circuits.
(1) Register List
• Auto ready function select register (ARSR)
Address : 0000A5H 0011- - 00B
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
ICR1 HMR1 HMR0 LMR1 LMR0
ICR0
W
WWWWW
• External address output control register (HACR)
Address : 0000A6
H 00000000B
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
E23 E21 E20 E19 E18 E17 E16
W
E22
WWW W WWW
• Bus control signal select register (EPCR)
Address : 0000A7
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
H 1000∗10 -B
CKE HDE ICBS HMBS WRE LMBS
RYE
W
WWWWWW
Initial value
Initial value
Initial value
W
−
*
(2) Block Diagram
: Write only
: Not used
: May be either “1” or “0”
P0 data
P0 direction
RB
Data control
Address control
P0
P1
P2
P3
P5
P4
P5
P0
Access control
Access control
79
MB90470 Series
23. Address Match Detection Function
When the address is equal to a value set in the address detection register, the instruction code loaded into the
CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set
instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program
patching function to be implemented.
Two address detection registers are supported. An interrupt enable bit is prepared for each register . If the v alue
set in the address detection register matches an address and if the interrupt enable bit is set at “1”, the instruction
code loaded into the CPU is replaced forcibly with the INT9 instruction code.
(1) Register Configuration
• Program address detection register 0 to 2 (PADR0)
Address
PADR0 (Low order address): 001FF0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
H
R/W R/W R/W R/W R/W R/W R/W R/W
Address
PADR0 (Middle order address): 001FF1
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
H
R/W R/W R/W R/W R/W R/W R/W R/W
Address
PADR0 (High order address): 001FF2
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
H
R/W R/W R/W R/W R/W R/W R/W R/W
• Program address detection register 3 to 5 (PADR1)
Address
PADR1 (Low order address): 001FF3
Address
PADR1 (Middle order address): 001FF4
Address
PADR1 (High order address): 001FF5
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
H
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
H
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
H
R/W R/W R/W R/W R/W R/W R/W R/W
• Program address detection control status register (PACSR)
Address
00009E
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
RESV RESV RESV RESV AD1E RESV AD0E RESV
H
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
XXXXXXXX
Initial value
00000000
B
B
B
B
B
B
B
80
R/W:Readable and writable
X :Undefined
RESV:Reserved bit
(2) Block Diagram
MB90470 Series
Address latch
Address detection
Enable bit
Internal data bus
register
Compare
INT9
instruction
2
F
MC-16LX
CPU core
81
MB90470 Series
ELECTRICAL CHARACTERISTICS
■
1. Absolute Maximum Ratings
Parameter Symbol
Supply voltage
(VSS = AVSS = 0.0 V)
Rating
Unit Remarks
Min Max
V
CC3VSS − 0.3 VSS + 4.0 V
VCC5VSS − 0.3 VSS + 7.0 V
AV
CC VSS − 0.3 VSS + 4.0 V *1
AVRH V
SS − 0.3 VSS + 4.0 V
VSS − 0.3 VSS + 4.0 V *2
Input voltage V
I
V
SS − 0.3 VSS + 7.0 V *2
VSS − 0.3 VSS + 4.0 V *2
Output voltage V
O
VSS − 0.3 VSS + 7.0 V *2
Maximum clamp current I
Total maximum clump current
“L” level maximum output current I
“L” level average output current I
“L” level maximum total output current ΣI
CLAMP − 2.0 + 2.0 mA *6
CLAMP |
Σ| I
OL 10 mA *3
OLAV 3mA*4
OL 60 mA
20 mA *6
“L” level average total output current ΣIOLAV 30 mA *5
“H” level maximum output current I
“H” level average output current I
“H” level maximum total output current ΣI
OH − 10 mA *3
OHAV − 3mA*4
OH − 60 mA
“H” level average total output current ΣIOHAV −30 mA *5
Power consumption P
Operating temperature T
D 410 mW
A − 40 + 85 °C
Storage temperature Tstg − 55 + 150 °C
*1:AV
CC and AVRH must not exceed VCC3. Also, AVRH must not exceed AVCC ,too.
*2:V
I, and VO must not exceed VCC (including VCC3, VCC5) plus 0.3 V.
*3:Maximum output current is defined as the peak value at one corresponding pin.
*4:Average output current is defined as the average current flowing through one corresponding pin in an interval
of 100 ms.
*5:Average total output current is defined as the total a v er age current flowing through all corresponding pins in an
interval of 100 ms.
*6: • Applicable to pins: General purpose CMOS input port (P00 to P07, P10 to P17, P20 to P27, P30 to P37,
P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA3)
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
(Continued)
82
MB90470 Series
(Continued)
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the V
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting
supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Sample recommended circuits:
• Input/output equivalent circuits
Protective diode
Vcc
P-ch
N-ch
+
B input (0 V to 16 V)
Limiting
resistance
CC pin, and this may affect
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
83
MB90470 Series
2. Recommended Operating Conditions
Parameter Symbol
V
CC3*
V
CC5*
Supply voltage
V
CC3 1.8 3.6 V Hold stop status
CC5
V
(VSS = AVSS = 0.0 V)
Value
Unit Remarks
Min Max
1.8 3.6 V MASK version
2.4 3.6 V Low voltage FLASH version
3.0 3.6 V High speed FLASH version
1.8 5.5 V MASK version
2.4 5.5 V Low voltage FLASH version
3.0 5.5 V High speed FLASH version
1.8 5.5 V
1.8 5.5 V
Hold stop status
(MASK version)
Hold stop status
(FLASH version)
All pins other than VHIS, VIHM
pins
All pins other than VILS, VILM
pins
“H” level input voltage
“L” level input voltage
V
IH 0.7 VCC VCC + 0.3 V
VIHS 0.8 VCC VCC + 0.3 V Hysteresis input pins
V
IHM VCC − 0.3 VCC + 0.3 V MD pin input
V
IL VSS − 0.3 0.3 VCC V
V
ILS VSS − 0.3 0.2 VCC V Hysteresis input pins
VILM VSS − 0.3 VSS + 0.3 V MD pin input
Operating temperature T
A − 40 + 85 °C
* : Pay attention to operating frequency.
Note : When using I
2
C functions, the voltage should be at least 2.4 V.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
84
3. DC Characteristics
(Low voltage FLASH version : VCC = 2.4 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) *
Parameter
“H” level
output
voltage
“L” level
output
voltage
Input leak
current
Sym-
bol
V
OH
OL
V
I
IL
Pin name Conditions
All pins
except
P76-P77
All output
pins
All pins
except
P76, P77
(MASK version : VCC = 1.8 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) *
(High speed FLASH version : V
V
CC = 2.7 V
I
OH = − 1.6 mA
V
CC = 4.5 V
I
OH = − 4.0 mA
V
CC = 2.7 V
I
OL = 2.0 mA
V
CC = 4.5 V
I
OL = 4.0 mA
VCC = 3.3 V
V
SS < VI < VCC
MB90470 Series
CC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) *
Value
Min Typ Max
CC3 −
V
0.3
CC5 −
V
0.5
V
V
0.4 V
0.4 V
− 10 + 10 µA
Unit Remarks
Using 5 V
system power
supply
Using 5 V
system power
supply
Pull-up
resistance
Open drain
output
current
Supply
current
R
PULL
P40 to P47,
I
leak
P70 to P77
I
CC
I
CCS
I
CCL
VCC = 3.0 V,
at T
A = + 25 °C
0.1 10 µA
at V
CC = 3.3 V,
at normal internal
20 MHz operation
CC = 3.3 V,
at V
flash write/erase
at internal 20 MHz
CC = 3.3 V,
V
sleep mode
at 20 MHz
CC = 3.3 V,
at V
sub operation,
external 32 kHz,
internal 8 kHz
operation
(T
A = + 25 °C)
20 65 200 kΩ
60 80 mA MASK version
65 85 mA
MASK version
(A/D operation)
51 66 mA FLASH version
56 71.5 mA
FLASH version
(A/D operation)
57 71.5 mA FLASH version
18 33 mA
16 140 µA
* : Pay attention to operating frequency.
(Continued)
85
MB90470 Series
(Continued)
(Low voltage FLASH version : V
(High speed FLASH version : V
Parameter
Supply
current
Input
capacitance
Sym-
bol
I
CCT
CCH
I
Pin name Conditions
All pins
except A V
IN
C
AV
V
SS
SS, VCC,
(MASK version : VCC = 1.8 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) *
CC = 2.4 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) *
CC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) *
Value
Unit Remarks
Min Typ Max
CC = 3.3 V,
at V
10 40 µA MASK version
watch operation,
external 32 kHz,
internal 8 kHz
15 40 µAFLASH version
operation
(T
A = + 25 °C)
A = + 25 °C,
T
0.1 20 µA MASK version
stop mode,
0.2 40 µAFLASH version
CC,
at V
CC = 3.3 V
515pF
* : Pay attention to operating frequency.
Notes : • Pins P40-P47 and P70-P75 are N-ch open drain pins with controls, and normally used at CMOS level.
• P76 and P77 are N-ch open drain pins.
• V
CC = VCC3 = VCC5.
• When using two power supplies, the 5 V system pins are P20 to P27, P30 to P37, P40 to P47 and
P70 to P77. All other pins are 3 V input/output pins.
86
4. AC Characteristics
(1) Clock Timing Ratings
Parameter
Sym-
bol
Pin name Conditions
MB90470 Series
(V
SS = 0.0 V, TA = −40 °C to +85 °C)
Value
Min Typ Max
Unit Remarks
Clock frequency
Clock cycle time
Input clock pulse width
Input clock rise, fall time
Internal operating clock
frequency
Internal operating clock
cycle time
3 20
F
CH X0, X1
MHz
3 40
FCL X0A, X1A 32.768 kHz
C X0, X1 25 333 ns *2
t
t
CL X0A, X1A 30.5 µs
PWH
PWL
P
WLH
PWLL
t
cr
tcf
X0 5 ns *1
X0A 15.2 µs*1
X0 5ns
1.5 20 MHz *2
f
CP
1.5 16 MHz MB90474 only
8.192 kHz
f
CPL
3 20 MHz MB90F474H
3 12 MHz MB90F474L
50.0 666 ns *2
t
CP
62.5 666 ns MB90474 only
t
CPL 122.1 µs
for crystal
oscillation*
2
for external
clock
Using
external clock
*1 : V
CC = VCC3 = VCC5
*2 : Observe the operating voltage with care.
87
MB90470 Series
•X0,
X1 clock timing
X0
•
X0A, X1A clock timing
X0A
tC
0.8 VCC
0.2 VCC
PWH PWL
tcf tcr
tCL
0.8 VCC
0.2 VCC
PWLH PWLL
tcf tcr
88
• PLL warranted operating range
Internal operating clock frequency vs. Supply voltage
3.6
3.13
3.0
(V)
2.5
CC
2.4
High speed flash model operating range
PLL warranted
operating range
MB90470 Series
1.8
Normal operating range
Supply voltage V
31.5 5 12 16
Note : Use it at f = 16 MHz for MB90474.
When using the high speed flash model at f = 20 MHz, use supply voltages of 3.13 V to 3.6 V.
For A/D operating frequencies, see the electrical characteristics of the A/D converter module.
Maximum assured operation frequency (f
Base oscillator frequency vs. Internal operating clock frequency
20
16
(MHz)
CP
12
9
8
4
Internal clock f
8
34
10 16 2420 32 40
Base oscillator clock FC (MHz)
10
Internal clock f
cp) of µDMA is 16 MHz.
Low voltage flash model operating range
20
CP
(MHz)
Note : Use PLL circuit when using internal clock at 16 MHz or more. It is recommended to use base
oscillator clock of up to 20 MHz.
AC characteristics are determined using the following measurement reference voltage values.
• Input signal waveform
Hysteresis input pins
0.8 VCC
0.2 VCC
• Output signal waveform
Output pins
2.4 V
0.8 V
Pins other than hysteresis input/MD input pins
0.7 VCC
0.3 VCC
89
MB90470 Series
(2) Clock Output Timing
Parameter
Sym-
bol
Pin name Conditions
(V
Value
Min Max
SS = 0.0 V, TA = −40 °C to +85 °C)
Unit Remarks
Cycle time t
CLK ↑→ to CLK ↓ t
Notes : • t
CP : See (1) Clock Timing Ratings.
• V
CC = VCC3 = VCC5
CYC CLK tCP ns
VCC = 3.0 V to 3.6 V tCP / 2 − 15 tCP / 2 + 15 ns at fcp = 20 MHz
CHCL CLK
2.4 V 2.4 V
CLK
VCC = 2.7 V to 3.3 V tCP / 2 − 20 tCP / 2 + 20 ns at fcp = 16 MHz
V
CC = 2.7 V to 3.3 V tCP / 2 − 64 tCP / 2 + 64 ns at fcp = 5 MHz
tCYC
CHCL
t
0.8 V
90
(3) Reset Input Ratings
Parameter Symbol Pin name Conditions
MB90470 Series
(V
CC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Min Max
Unit Remarks
In normal
operation
In stop
mode
Reset input time t
RSTL RST
16 t
CP ns
Oscillator oscillation
time* + 16 t
CP
ms
* : Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to several
dozen ms; for a F AR/ceramic oscillator, this is se veral hundred µs to a few ms, and f or an external clock this is 0 ms.
Note: t
CP : See (1) Clock Timing Ratings.
• In stop mode
tRSTL
RST
X0
0.2 Vcc
90 % of
amplitude
0.2 Vcc
Internal
operation
clock
Oscillator
oscillation time
16 tcp
Internal
reset
• Measurement conditions for AC ratings
Pin
CL
Oscillator stabilization wait time
Execution of the instruction
C
L : Load capacitance applied to pin during testing
CLK, ALE, C
AD15 to AD00 (Address, data bus) , RD
A23 to A00/D15 to D00 : C
L = 30 pF
, WR,
L = 80 pF
91
MB90470 Series
(4) Power On Ratings (Power-on reset)
Parameter
Sym-
bol
Pin
name
Condi-
tions
(V
CC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Unit Remarks
Min Max
Power rise time t
R VCC
30 ms *
Power cutoff time t
* : Power supply rise time requires V
OFF VCC 1 ms For continuous operation
CC < 0.2 V.
Notes : • VCC = VCC3 = VCC5
• The above ratings are values for power-on reset.
• A power-on reset should be applied by restarting the power supply inside the device.
tR
VCC
2.7 V
0.2 V 0.2 V0.2 V
tOFF
Extreme variations in supply voltage may activate a power-on reset. As the illustration shows below ,
when varying supply voltage during operation the use of a smooth voltage rise with suppressed fluctuation
is recommended.
Main supply voltage
VCC
Sub supply voltage
VSS
Hold RAM data
A rise slope of 50 mV
or less is recommended
92
(5) Bus read timing
Parameter
Sym-
bol
Pin name
Condi-
tions
MB90470 Series
(V
CC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Min Max
CP / 2 − 15 ns at fcp = 20 MHz
t
Unit Remarks
ALE pulse width t
LHLL ALE
t
CP / 2 − 20 ns at fcp = 16 MHz
tCP / 2 − 35 ns at fcp = 8 MHz
Valid address →
ALE ↓ time
ALE ↓ →
address valid time
Valid address →
RD
↓ time
Valid address →
valid data input
pulse width tRLRH RD
RD
↓ →
RD
valid data input
RD
↑ →
data hold time
RD
↑ → ALE ↑ time tRHLH RD, ALE tCP / 2 − 15 ns
RD ↑ →
address valid time
Address pins,
AVLL
t
tLLAX
tAVRL
AVDV Address/data
t
tRLDV
tRHDX
ALE
ALE,
Address pins
RD,
address
RD,
Data
RD,
Data
tRHAX Address, RD tCP / 2 − 10 ns
t
tCP / 2 − 15 ns
tCP − 20 ns
0 ns
CP / 2 − 20 ns
t
CP / 2 − 40 ns at fcp = 8 MHz
5 t
CP / 2 − 60 ns
5 tCP / 2 − 80 ns at fcp = 8 MHz
3 t
CP / 2 − 25 ns at fcp = 20 MHz
3 t
CP / 2 − 20 ns at fcp = 16 MHz
3 t
3 t
CP / 2 − 60 ns
CP / 2 − 80 ns at fcp = 8 MHz
Valid address →
CLK ↑ time
RD
↓ → CLK ↑ time tRLCH RD, CLK tCP / 2 − 20 ns
t
AVCH
Address,
CLK
tCP / 2 − 20 ns
ALE ↓ → RD ↓ time tLLRL RD, ALE tCP / 2 − 15 ns
Notes : • t
CP : See (1) Clock Timing Ratings.
• V
CC = VCC3 = VCC5
93
MB90470 Series
CLK
ALE
RD
Multiplex mode
A23 to A16
AD15 to
AD00
Non-multiplex mode
A23 to A00
D15 to
D00
2.4 V
0.8 V
2.4 V
tAVCH
2.4 V
2.4 V
tLHLL
tAVLL
2.4 V
0.8 V
Address Read data
2.4 V
0.8 V
0.8 V
tLLAX
tLLRL
tAVRL tRLDV
tAVDV
tAVDV
2.4 V
0.8 V
tRLCH
2.4 V
0.8 V
tRLDV
tRLRH
0.7 VCC
0.3 V
0.7 VCC
0.3 V
CC
CC
tRHLH
2.4 V
2.4 V
tRHAX
2.4 V
0.8 V
tRHDX
0.7 VCC
0.3 VCC
tRHAX
2.4 V
0.8 V
tRHDX
0.7 VCC
Read data
0.3 VCC
94
(6) Bus Write Timing
Parameter
Sym-
bol
Pin name
MB90470 Series
(V
CC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Condi-
tions
Value
Unit Remarks
Min Max
Valid address → WR
↓ time tAVWL
Address pins,
WR
tCP − 20 ns
3 tCP / 2 − 25 ns at fcp = 20 MHz
pulse width tWLWH WRL, WRH
WR
3 tCP / 2 − 20 ns at fcp = 16 MHz
Valid data output → WR
time
↑
tDVWH
Data pins,
WR
3 tCP / 2 − 20 ns
15 ns at fcp = 20 MHz
WR
↑ → data hold time tWHDX
WR,
Data pins
20 ns at fcp = 16 MHz
30 ns at f
WR
↑ → address valid time tWHAX
WR,
Address pins
tCP / 2 − 10 ns
WR ↑ → ALE ↑ time tWHLH WR , ALE tCP / 2 − 15 ns
WR
↓ → CLK ↑ time tWLCH WR , CLK tCP / 2 − 20 ns
Notes : • t
CP : See (1) Clock Timing Ratings.
• V
CC = VCC3 = VCC5
cp = 8 MHz
95
MB90470 Series
CLK
ALE
WR
(WRL, WRH)
tWLCH
2.4 V
tWHLH
2.4 V
tWLWH
2.4 V
0.8 V
Multiplex mode
A23 to A16
AD15 to
AD00
Non-multiplex mode
A23 to A00
D15 to
D00
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
tAVWL
tDVWH
Address Write data
2.4 V
0.8 V
2.4 V
0.8 V
tDVWH
Write data
tWHAX
2.4 V
0.8 V
tWHDX
2.4 V
0.8 V
tWHAX
2.4 V
0.8 V
tWHDX
2.4 V
0.8 V
96
(7) Ready Input Timing
Parameter Symbol Pin name
(V
Condi-
tions
MB90470 Series
CC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Unit Remarks
Min Max
RDY setup time t
RYHS
RDY
70 ns fcp = 8 MHz
RDY hold time tRYHH 0 ns
Notes : • If the RDY setup time is not sufficient, use the auto ready function.
45 ns
• V
CC = VCC3 = VCC5
• If input from the RDY pin, note that the AC ratings must be satisfied so that the chip will not drive recklessly.
CLK
ALE
RD/WR
RDY
wait not
applied
2.4 V 2.4 V
tRYHS
tRYHH
0.8 VCC 0.8 VCC
RDY
wait applied
(1 cycle)
0.2 V
CC0.2 VCC
tRYHS
97
MB90470 Series
(8) Hold Timing
Parameter Symbol Pin name
(V
CC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Condi-
tions
Value
Unit Remarks
Min Max
Pin floating → HAK
↓ time tXHAL HAK
30 t
CP ns
HAK
↓ → valid data time tHAHV HAK tCP 2 tCP ns
Notes : • t
CP : See (1) Clock Timing Ratings.
• V
CC = VCC3 = VCC5
• If the HRQ pin is read, at least one cycle is required before the HAK
HAK
All pins
0.8 V
tXHAL
2.4 V
0.8 V
2.4 V
High-Z
pin changes.
tHAHV
2.4 V
0.8 V
98
(9) UART Timing
Parameter
Sym-
bol
Pin
name
MB90470 Series
(V
CC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Conditions
Value
Unit Remarks
Min Max
Serial clock cycle time t
SCYC
8 t
CP ns
− 80 + 80 ns
SCK ↓ → SOT delay time t
SLOV
Internal shift clock
− 120 + 120 ns f
mode output pin
Valid SIN → SCK ↑ t
IVSH
C
L = 80 pF + 1 TTL
100 ns
200 ns f
SCK ↑ → valid SIN hold time tSHIX tCP ns
Serial clock “H” pulse width t
Serial clock “L” pulse width t
SHSL
SLSH 4 tCP ns
4 t
CP ns
150 ns
SCK ↓ → SOT delay time t
SLOV
External shift clock
200 ns f
mode output pin
Valid SIN → SCK ↑ t
IVSH
C
L = 80 pF + 1 TTL
60 ns
120 ns f
60 ns
SCK ↑ → valid SIN hold time t
SHIX
120 ns f
Notes : • These AC characteristics are for operation in CLK synchronous mode.
• C
L is the load capacitance applied to pins during testing.
• t
CP : See (1) Clock Timing Ratings.
• V
CC = VCC3 = VCC5
cp = 8 MHz
cp = 8 MHz
cp = 8 MHz
cp = 8 MHz
cp = 8 MHz
99
MB90470 Series
•
Internal Shift Clock Mode
SCK
0.8 V 0.8 V
tSLOV
SOT
SIN
•
External Shift Clock Mode
SCK
0.2 VCC 0.2 VCC
tSCYC
2.4 V
2.4 V
0.8 V
tIVSH tSHIX
0.8 V
CC
0.2 VCC
tSLSH tSHSL
0.8 VCC 0.8 VCC
0.8 VCC
0.2 VCC
SOT
SIN
tSLOV
2.4 V
0.8 V
0.8 V
0.2 VCC
tIVSH tSHIX
CC
0.8 VCC
0.2 VCC
100
Loading...