FUJITSU MB90V460, MB90F462, MB90462, MB90467 DATA SHEET

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FUJITSU SEMICONDUCTOR

DATA SHEET

16-bit Proprietary Microcontroller

CMOS

F2MC-16LX MB90460 Series

MB90462/467/F462/V460

DESCRIPTION

■■■■

The MB90460 series is a line of general-purpose, Fujitsu 16-bit microcontrollers designed for process control applications which require high-speed real-time processing, such as consumer products.

While inheriting the AT architecture of the F MB90460 series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90460 has an on-chip 32-bit accumulator which enab les processing of long-word data.

The peripheral resources integrated in the MB90460 series include : an 8/10-bit A/D converter, UARTs (SCI) 0 to 1, 16-bit PPG timer, a multi-functional timer (16-bit free-run timer, input capture units (ICUs) 0 to 3, output compare units (OCUs) 0 and 5, 16-bit PPG timer, a waveform generator) , a multi-pulse generator (16-bit PPG timer, 16-bit reload timer, waveform sequencer) , PWC 0 to 1, 16-bit reload timer and DTP/external interrupt.

MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.

* : F

2MC*

family, the instruction set for the F2MC-16LX CPU core of the

DS07-13714-1E

FEATURES

■■■■

• Minimum execution time : 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication) maximum multiplier = 4

• Maximum memory space 16 Mbyte Linear/bank access

PACKAGES

■■■■

64-pin plastic QFP 64-pin plastic LQFP 64-pin plastic SH-DIP

(FPT-64P-M06) (FPT-64P-M09) (DIP-64P-M01)

(Continued)

MB90460 Series

(Continued)

• Instruction set optimized for controller applications Supported data types : bit, byte, word, and long-word types Standard addressing modes : 23 types 32-bit accumulator enhancing high-precision operations Signed multiplication/division and extended RETI instructions

• Enhanced high level language (C) and multi-tasking support instructions Use of a system stack pointer Symmetrical instruction set and barrel shift instructions

• Program patch function (for two address pointers)

• Enhanced execution speed : 4 byte instruction queue

• Enhanced interrupt function Up to eight programmable priority levels External interrupt inputs : 8 lines

• Automatic data transmission function independent of CPU operation Up to 16 channels for the extended intelligent I/O service DTP request inputs : 8 lines

• Internal ROM FLASH : 64 Kbyte (with flash security) MASKROM : 64 Kbyte

• Internal RAM EVA : 8 Kbyte FLASH : 2 Kbyte MASKROM : 2 Kbyte

• General-purpose ports Up to 51 channels (Input pull-up resistor settable for : 16 channels)

• A/D Converter (RC) : 8 ch 8/10-bit resolution selectable Conversion time : 6.13 µs (Min) , 16 MHz operation

• UART : 2 channels

• 16 bit PPG : 3 channels Mode switching function provided (PWM mode or one-shot mode) Can be worked with a multi-functional timer, a multi-pulse generator or individually

• 16 bit reload timer : 2 channels Can be worked with multi-pulse generator or individually

• 16-bit PWC timer : 2 channels

• A multi-functional timer Input capture : 4 channels Output compare with selectable buffer : 6 channels Free-run timer with up or up/down mode selection and selectable buffer : 1 channel 16-bit PPG : 1 channel A waveform generator : (16-bit timer : 3 channels, 3-phase waveform or dead time)

• A multi-pulse generator 16-bit PPG : 1 channel 16-bit reload timer : 1 channel Waveform sequencer : (16-bit timer with buffer and compare clear function)

• Time-base counter/watchdog timer : 18-bit

• Low-power consumption mode : Sleep mode Stop mode CPU intermittent operation mode

• Package : QFP-64 (FPT-64P-M09 : 0.65 mm pitch) QFP-64 (FPT-64P-M06 : 1.00 mm pitch) SDIP-64 (DIP-64P-M01 : 1.78 mm pitch)

•CMOS technology

MB90460 Series

PRODUCT LINEUP

■■■■

Part number

Item

Classification

ROM size  64 KBytes RAM size 8 KBytes 2 KBytes

Number of Instruction : 351 Minimum execution time : 62.5 ns / 4 MHz (PLL × 4)

CPU function

I/O port I/O port (CMOS) : 51

PWC

UART

16-bit reload timer

16-bit PPG timer

Multi-functional

timer

(for AC/DC

motor control)

Multi-pulse

generator

(for DC motor control)

8/10-bit A/D

converter

DTP/External

interrupt

Lower power consumption

Addressing mode : 23 Data bit length : 1, 8, 16 bits Maximum memory space : 16 MBytes

Pulse width counter timer : 2 channels Timer function (select the counter timer from three internal clocks)

Various Pulse width measuring function (H pulse width, L pulse width, rising edge to falling edge period, falling edge to rising edge period, rising edge to rising edge period and falling edge to falling edge period)

UART : 2 channels With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively used Transmission can be one-to-one (bi-directional commuication) or one-to-n (MasterSlave communication)

Reload timer : 2 channels Reload mode, single-shot mode or event count mode selectable Can be worked with a multi-pulse generator or individually

PPG timer : 3 channels PPG timer : 2ch PWM mode or single-shot mode selectable

Can be worked with multi-functional timer / multi-pulse generator or individually 16-bit free-running timer with up or up/down mode selection and buffer : 1 channel

16-bit output compare : 6 channels 16-bit input capture : 4 channels 16-bit PPG timer : 1 channel Waveform generator (16-bit timer : 3 channels, 3-phase waveform or dead time)

16-bit PPG timer : 1 channel 16-bit reload timer operation (toggle output, one shot output selectable) Event counter function : 1 channel built-in A waveform sequencer (includes 16-bit timer with buffer and compare clear function)

8/10-bit resolution (8 channels) Conversion time : Less than 6.13 µS (16 MHz internal clock)

8 independent channels Selectable causes : Rising edge, falling edge, “L” level or “H” level

Stop mode / Sleep mode / CPU intermittent operation mode

MB90V460 MB90F462 MB90462 MB90467

Development/evaluation

product

Mass-produced

products

(Flash ROM)

Mass-produced products

(Mask ROM)

Pulse width counter timer : 1ch



(Continued)

Item

Package PGA256

Part number

MB90460 Series

MB90V460 MB90F462 MB90462 MB90467

LQFP-64 (FPT-64P-M09 : 0.65 mm pitch)

QFP-64 (FPT-64P-M06 : 1.00 mm pitch) SDIP-64 (DIP-64P-M01 : 1.78 mm pitch)

Power supply voltage for

operation*

Process CMOS

* : V aries with conditions such as the operating frequency (See section “■ ELECTRICAL CHARA CTERISTICS”) .

Assurance for the MB90V460 is giv en only for operation with a tool at a power supply voltage of 4.5 V to 5.5 V, an operating temperature of 0 to +25 °C, and an operating frequency of 1 MHz to 16 MHz.

PACKAGE AND CORRESPONDING PRODUCTS

■■■■

Package MB90V460 MB90F462 MB90462 MB90467

PGA256 FPT-64P-M09 FTP-64P-M06 DIP-64P-M01

: Available, : Not available

Note : For more information about each package, see section “■ PACKAGE DIMENSIONS”.

DIFFERENCES AMONG PRODUCTS

■■■■

Memory Size

× × ×

4.5 V to 5.5 V *

×××

In evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. The following items must be taken into consideration.

• The MB90V460 does not have an internal ROM, ho wev er, operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the development tool.

• In the MB90V460, images from FF4000 mapped to bank FF only. (This setting can be changed by configuring the development tool.)

• In the MB90462/F462/467, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFF

H are mapped to bank FF only.

H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH are

MB90460 Series

PIN ASSIGNMENT

■■■■

(TOP VIEW)

P44/SNI1* P45/SNI2*

P46/PPG2

P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7

AVR

P60/SIN1

P61/SOT1

P62/SCK1

P63/INT7

MD0

P42/SCK0

P41/SOT0

P43/SNI0*

P40/SIN0

P37/PPG0

P36/PPG1*

/RTO5 (Z)

/RTO4 (W)

/RTO3 (Y)

/RTO2 (V)

P33*

P32*

/RTO1 (X)

P31*

VCC

P35*

P34*

64636261605958575655545352

2 2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

/RTO0 (U)

P30* V

P27/IN3 P26/IN2 P25/IN1 P24/IN0 P23/PWO1 P22/PWI1 P21/TO1 P20/TIN1 P17/FRCK P16/INT6/TO0 P15/INT5/TIN0 P14/INT4 P13/INT3 P12/INT2/DTTI1* P11/INT1 P10/INT0/DTTI0 P07/PWO0*

20212223242526272829303132

*1 : Heavy current pins *2 : MB90V460, MB90F462, MB90462 only.

They do not exist on MB90467, because there are not PWC (ch 0) , 16-bit PPG (ch 1) and waveform sequencer.

RST

MD2

MD1

(FPT-64P-M06)

/OPT0*

/OPT1*

P00*

P01*

/OPT2*

/OPT3*

P02*

P03*

/OPT4*

/OPT5*

P04*

P05*

P06/PWI0*

(Continued)

(TOP VIEW)

MB90460 Series

P45/SNI2*

P46/PPG2

P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7

AVR

P60/SIN1 P61/SOT1 P62/SCK1

P43/SNI0*

P42/SCK0

P44/SNI1*

P41/SOT0

646362616059585756555453525150

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

171819202122232425262728293031

P40/SIN0

P37/PPG0

P36/PPG1*

/RTO5 (Z)

VCCP35*

/RTO4 (W)

/RTO3 (Y)

P34*

P33*

/RTO2 (V)

P32*

/RTO1 (X)

/RTO0 (U)

P31*

P30*

49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

P27/IN3 P26/IN2 P25/IN1 P24/IN0 P23/PWO1 P22/PWI1 P21/TO1 P20/TIN1 P17/FRCK P16/INT6/TO0 P15/INT5/TIN0 P14/INT4 P13/INT3 P12/INT2/DTTI1* P11/INT1 P10/INT0/DTTI0

/OPT3*

/OPT4*

P03*

P04*

/OPT5*

P06/PWI0

P05*

P07/PWO0

RST

MD0

P63/INT7

MD1

MD2

/OPT0*

/OPT1*

P00*

P01*

/OPT2*

P02*

(FPT-64P-M09) *1 : Heavy current pins *2 : MB90V460, MB90F462, MB90462 only.

They do not exist on MB90467, because there are not PWC (ch 0) , 16-bit PPG (ch 1) and waveform sequencer.

(Continued)

MB90460 Series

(Continued)

(TOP VIEW)

P36/PPG1*

P37/PPG0

P40/SIN0 P41/SOT0 P42/SCK0

P43/SNI0* P44/SNI1* P45/SNI2*

P46/PPG2

P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7

AVR

AVSS

P60/SIN1 P61/SOT1 P62/SCK1

P63/INT7

MD0

RST MD1 MD2

X0 X1

1 2 3 4 5

2 2 2

6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

P35*1/RTO5 (Z) P34*1/RTO4 (W)

P33*

/RTO3 (Y)

P32*1/RTO2 (V)

P31*

/RTO1 (X) P30*1/RTO0 (U) VSS P27/IN3 P26/IN2 P25/IN1 P24/IN0 P23/PWO1 P22/PWI1 P21/TO1 P20/TIN1 P17/FRCK P16/INT6/TO0 P15/INT5/TIN0 P14/INT4 P13/INT3 P12/INT2/DTTI1* P11/INT1 P10/INT0/DTTI0 P07/PWO0* P06/PWI0* P05*1/OPT5* P04*1/OPT4* P03*1/OPT3* P02*1/OPT2* P01*1/OPT1* P00*1/OPT0*

2 2 2 2 2 2

*1 : Heavy current pins *2 : MB90V460, MB90F462, MB90462 only.

They do not exist on MB90467, because there are not PWC (ch 0) , 16-bit PPG (ch 1) and waveform sequencer.

(DIP-64P-M01)

PIN DESCRIPTION

■■■■

MB90460 Series

Pin No.

QFP-

M06*

LQFP-

M09*

SDIP*

name

I/O

circuit

23, 24 22, 23 30, 31 X0, X1 A Oscillation input pins.

20 19 27 RST

P00 to

26 to 3125 to 3033 to

OPT0 to

OPT5

P05

B External reset input pin.

General-purpose I/O ports. Output terminals OPT0 to 5 of the waveform sequencer.

These pins output the waveforms specified at the output data

registers of the waveform sequencer circuit. Output is generated when OPE0 to 5 of OPCR is enabled.

32 31 39

33 32 40

34 33 41

P06

PWI0

P07

PWO0

P10

INT0

DTTI0

General-purpose I/O ports.

PWC 0 signal input pin. General-purpose I/O ports.

PWC 0 signal output pin. General-purpose I/O ports. Can be used as interrupt request input channels 0. Input is en-

abled when 1 is set in EN0 in standby mode. RTO0 to 5 pins for fixed-level input. This function is enabled

when the waveform generator enables its input bits.

Function

35 34 42

36 35 43

37 to 3836 to 3744 to

39 38 46

P11

INT1

P12

INT2

DTTI1

P13 to

P14

General-purpose I/O ports.

Can be used as interrupt request input channels 1. Input is enabled when 1 is set in EN1 in standby mode.

General-purpose I/O ports. Can be used as interrupt request input channels 2. Input is en-

abled when 1 is set in EN2 in standby mode. OPT0 to 5 pins for fixed-level input. This function is enabled

when the waveform sequencer enables its input bit. General-purpose I/O ports.

INT3 to

INT4

P15

INT5

Can be used as interrupt request input channels 3 to 4. Input is enabled when 1 is set in EN3 to EN4 in standby mode.

General-purpose I/O ports. Can be used as interrupt request input channel 5. Input is en-

abled when 1 is set in EN5 in standby mode.

TIN0 External clock input pin for reload timer 0.

(Continued)

MB90460 Series

Pin No.

LQFP-

M09*

SDIP*

QFP-

M06*

40 39 47

41 40 48

42 41 49

43 42 50

44 43 51

45 44 52

46 to 4945 to 4853 to

51 to 5650 to 5558 to

name

P16

INT6

I/O

circuit

Function

General-purpose I/O ports. Can be used as interrupt request input channels 6. Input is en-

abled when 1 is set in EN6 in standby mode.

TO0 Event output pin for reload timer 0.

P17

General-purpose I/O ports.

FRCK External clock input pin for free-running timer.

P20

General-purpose I/O ports.

TIN1 External clock input pin for reload timer 1.

P21

General-purpose I/O ports.

TO1 Event output pin for reload timer 1.

P22

General-purpose I/O ports.

PWI1 PWC 1 signal input pin.

P23

General-purpose I/O ports.

PWO1 PWC 1 signal output pin. P24 to

P27

IN0 to

IN3

General-purpose I/O ports. Trigger input pins for input capture channels 0 to 3.

When input capture channels 0 to 3 are used for input operation, these pins are enabled as required and must not be used for any other I/P.

P30 to

P35

RTO0 (U)

RTO5 (Z)

General-purpose I/O ports. Waveform generator output pins. These pins output the wave-

forms specified at the waveform generator. Output is generated when waveform generator output is enabled. (U) to (Z) show the coils that control 3-phase motor.

59 58 2

60 59 3

61 60 4

62 61 5

P36

PPG1

P37

PPG0

P40

SIN0

P41

SOT0

General-purpose I/O ports.

Output pins for PPG channels 1. This function is enabled when PPG channels 1 enable output.

General-purpose I/O ports.

Output pins for PPG channels 0. This function is enabled when PPG channels 0 enable output.

General-purpose I/O ports. Serial data input pin for UART channel 0. While UART channel

0 is operating for input, the input of this pin is used as required and must not be used for any other input.

General-purpose I/O ports.

Serial data output pin for UART channel 0. This function is enabled when UART channel 0 enables data output.

(Continued)

Pin No.

QFP-

M06*

LQFP-

M09*

SDIP*

MB90460 Series

(Continued)

name

I/O

circuit

Function

63 62 6

64 63 7

1648

219

3210

4 to 11 3 to 10

11 to

P42

SCK0

P43

SNI0

P44

SNI1

P45

SNI2

P46

PPG2

P50 to

P57

AN0 to

AN7

General-purpose I/O ports.

Serial clock I/O pin for UART channel 0. This function is enabled when UART channel 0 enables clock output.

General-purpose I/O ports. Trigger input pins for position detection of the waveform se-

quencer. When this pin is used for input operation, it is enabled as required and must not be used for any other I/P.

General-purpose I/O ports. Trigger input pins for position detection of the Multi-pulse gener-

ator. When this pin is used for input operation, it is enabled as required and must not be used for any other I/P.

General-purpose I/O ports. Trigger input pins for position detection of the Multi-pulse gener-

ator. When this pin is used for input operation, it is enabled as required and must not be used for any other I/P.

General-purpose I/O ports.

Output pins for PPG channel 2. This function is enabled when PPG channel 2 enables output.

General-purpose I/O ports.

A/D converter analog input pins. This function is enabled when the analog input specification is enabled. (ADER) .

12 11 19 AV

CC  VCC power input pin for analog circuits.

Reference voltage (+) input pin for the A/D converter. This volt-

13 12 20 AVR 

age must not exceed V fixed to AV

SS.

CC and AVCC. Reference voltage (−) is

14 13 21 AVSS  VSS power input pin for analog circuits.

P60

15 14 22

SIN1

General-purpose I/O ports. Serial data input pin for UART channel 1. While UART channel

1 is operating for input, the input of this pin is used as required and must not be used for any other in-put.

P61

16 15 23

SOT1

General-purpose I/O ports.

Serial data output pin for UART channel 1. This function is enabled when UART channel 1 enables data output.

(Continued)

MB90460 Series

(Continued)

QFP-

M06*

Pin No.

LQFP-

M09*

SDIP*

name

I/O

circuit

Function

P62

17 16 24

SCK1

P63

18 17 25

INT7

19 18 26 MD0 J

21, 22 20, 21 28, 29 25, 50 24, 49 32, 57 V

57 56 64 V

MD1,

MD2

SS  Power (0 V) input pin. CC  Power (5 V) input pin.

58 57 1 C 

General-purpose I/O port.

Serial clock I/O pin for UART channel 1. This function is enabled when UART channel 1 enables clock output.

General-purpose I/O port.

Usable as interrupt request input channel 7. Input is enabled when 1 is set in EN7 in standby mode.

Input pin for operation mode specification. Connect this pin directly to V

Input pin for operation mode specification. Connect this pin di-

rectly to VCC or VSS.

CC or VSS.

Capacity pin for power stabilization. Please connect to an approximately 0.1 µF ceramic capacitor.

*1 : FPT-64P-M09 *2 : FPT-64P-M06 *3 : DIP-64P-M01 *4 : MB90V460, MB90F462, MB90462 only.

They do not exist on MB90467, because there are not PWC (ch 0) , 16-bit PPG (ch 1) and w avef orm sequencer.

MB90460 Series

I/O CIRCUIT TYPE

■■■■

Classification Type Remarks

N-ch P-ch

P-ch

P-ch N-ch

Pull up control

P-ch

N-ch

Standby mode control

Pout

Nout

Xout

Main clock (main clock crystal oscillator)

• At an oscillation feedback resistor of approximately 1 MΩ

• Hysteresis input

• Pull-up resistor approximately 50 kΩ

• CMOS output

• Hysteresis input

• Selectable pull-up resistor approximately 50 kΩ

•I

OL = 4 mA

• Standby control available

Hysteresis input

Standby mode control

• CMOS output

P-ch

Pull up control

P-ch

N-ch

Pout

Nout

CMOS input

Standby mode control

• CMOS input

• Selectable pull-up resistor approximately 50 kΩ

• Standby control available

•I

OL = 12 mA

(Continued)

MB90460 Series

Classification Type Remarks

• CMOS output

P-ch

N-ch

Pull up control

P-ch

N-ch

Pout

Nout

CMOS input

Standby mode control

Pout

Nout

• CMOS input

• Selectable pull-up resistor approximately 50 kΩ

• Standby control available

•I

OL = 4 mA

• CMOS output

• Hysteresis input

• Standby control available

OL = 4 mA

•I

Hysteresis input

Standby mode control

• CMOS output

P-ch

N-ch

Pout

Nout

• CMOS input

• Standby control available

OL = 12 mA

•I

CMOS input

Standby mode control

• CMOS output

P-ch

N-ch

Pout

Nout

• CMOS input

• Standby control available

OL = 4 mA

•I

CMOS input

Standby mode control

(Continued)

MB90460 Series

(Continued)

Classification Type Remarks

• CMOS output

P-ch

N-ch

Pout

Nout

CMOS input

Analog input control Analog input

• CMOS input

• Analog input

•I

OL = 4 mA

• Hysteresis input

MB90460 Series

HANDLING DEVICES

■■■■

1. Preventing Latchup

CMOS ICs may cause latchup in the following situations :

• When a voltage higher than V

• When a voltage exceeding the rating is applied between VCC and VSS.

• When AV

CC power is supplied prior to the VCC voltage.

If latchup occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to let it occur.

For the same reason, also be careful not to let the analog power-supply v oltage e xceed the digital pow er-supply voltage.

2. Handling unused input pins

Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. Unused input pins should be pulled up or pulled down through at least 2 kΩ resistance.

Unused input/output pins may be left open in the output state, b ut if such pins are in the input state the y should be handled in the same way as input pins.

3. Use of the external clock

CC or lower than VSS is applied to input or output pins.

When the device uses an e xternal clock, drive only the X0 pin while leaving the X1 pin open (See the illustr ation below) .

MB90460 series

Open

4. Power Supply Pins (VCC/VSS)

In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However, connect the pins exter nal power and ground lines to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating.

Make sure to connect V It is recommended to provide a bypass capacitor of around 0.1 µF between V

CC and VSS pins via the lowest impedance to power lines.

CC and VSS pins near the device.

5. Crystal Oscillator Circuit

Noise around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via the shortest distance from X0, X1 pins, cr ystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.

It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with the ground area for stabilizing the operation.

6. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on the A/D converter power supply (AVCC, AVSS, AVR) and analog inputs (AN0 to AN7) after turning-on the digital power supply (V

Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage of A VR dose not exceed A V is acceptable) .

CC) .

CC (turning on/off the analog and digital power supplies simultaneously

MB90460 Series

7. Connection of Unused Pins of A/D Converter

Connect unused pin of A/D converter to AVCC = VCC, AVSS = AVR = VSS.

8. N.C. Pin

The N.C. (internally connected) pin must be opened for use.

9. Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 µs or more.

10. Initialization

In the device, there are internal registers which are initialized only by a pow er-on reset. T o initialize these registers, please turn on the power again.

11. Return from standby state

If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may fail to return from the standby state. In this case, reset the de vice via the external reset pin to return to the normal state.

MB90460 Series

BLOCK DIAGRAM

■■■■

P11/INT1

P13/INT3 to

P14/INT4

P40/SIN0

P41/SOT0 P42/SCK0

P36/PPG1

P15/INT5/TIN0

P16/INT6/TO0

P43/SNI0∗2 to

P45/SNI2 P00/OPT0 P01/OPT1 P02/OPT2 P03/OPT3 P04/OPT4 P05/OPT5

P12/INT2/DTTI1

P06/PWI0

P07/PWO0

P46/PPG2

X0 X1

RST

∗2

∗2 ∗2 ∗2 ∗2 ∗2 ∗2 ∗2 ∗2

∗2 ∗2

Clock control

circuit

Reset circuit

(Watch-dog timer)

Interrupt controller

DTP/External interrupt

UART

(Ch0)

Multi-pulse Generator

16-bit PPG

16-bit reload timer

Waveform sequencer

16-bit PPG

(Ch1)

(Ch0)

PWC (Ch0)

(Ch2)

F2MC-16LX series core

∗2

∗1

CPU

MC-16LX Bus

Timebase timer

Delayed interrupt generator

Multi-functional Timer

16-bit PPG

(Ch0)

16-bit input capture

(Ch0/1/2/3)

16-bit free-run

timer

16-bit output

compare

(Ch0 to 5)

Waveform

generator

16-bit reload timer

(Ch1)

UART

(Ch1)

CMOS I/O port 1, 2, 3, 6

Other pins

SS × 2, VCC × 1, MD0-2, C

PWC

P37/PPG0

P24/IN0 to P27/IN3

P17/FRCK

P30/RTO0 (U) P31/RTO1 (X)

P32/RTO2 (V) P33/RTO3 (Y) P34/RTO4 (W) P35/RTO5 (Z)

P10/INT0/DTTI0

P20/TIN1 P21/TO1

P22/PWI1 P23/PWO1

P60/SIN1 P61/SOT1

P62/SCK1 P63/INT7

CMOS I/O port 0, 1, 3, 4

RAM

ROM

ROM correction

ROM mirroring

CMOS I/O port 5

A/D converter

(8/10 bit)

Note : P00 to P07 (8 channels) : With registers that can be used

as input pull-up resistors P10 to P17 (8 channels) : With registers that can be used as input pull-up resistors

*1: Only MB90V460, MB90F462 and MB90462 have PWC (ch 0) , 16-bit PPG (ch 1) and w aveform sequencer .

They do not exist on MB90467.

*2: The multi-pulse generator function can be used only by MB90V460, MB90F462 and MB90462.

This function can not be used by MB90467.

P50/AN0 P51/AN1 P52/AN2 P53/AN3

P54/AN4 P55/AN5 P56/AN6 P57/AN7

AVR AV

MEMORY MAP

■■■■

Address #1

Address #2

FFFFFFH

FC0000

010000H

MB90460 Series

ROM area

(FF bank image)

: Internal access memory : Access not allowed

004000H

003FE0H

Address #3

000100H

0000C0H

000000H

Peripheral area

RAM

area

Peripheral area

In Single chip mode the mirror function is supported

Parts No. Address#1 Address#2 Address#3

MB90462/467 FF0000

H 004000H 000900H

MB90F462 FF0000H 004000H 000900H MB90V460 (FF0000H) 004000H 002100H

Note : The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C

compiler small model. The lower 16-bit is assigned to the same address, enabling ref erence of the tab le on the ROM without stating “far”. F o r e xample, if an attempt has been made to access 00C000 of the ROM at FFC000

H are accessed actually. Since the ROM area of the FF bank exceeds 48 Kbytes, the

whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000 therefore, as if it were the image f or 004000 be stored in the area of FF4000

H to FFFFFFH.

H to 00FFFFH. Thus, it is recommended that the ROM data table

H , the contents

H to FFFFFFH looks,

MB90460 Series

I/O MAP

■■■■

Address

000000

Abbrevia-

tion

H PDR0 Port 0 data register R/W R/W Port 0 XXXXXXXXB

Byte

access

Word

access

Resource

name

Initial value

000001H PDR1 Port 1 data register R/W R/W Port 1 XXXXXXXXB 000002H PDR2 Port 2 data register R/W R/W Port 2 XXXXXXXXB 000003H PDR3 Port 3 data register R/W R/W Port 3 XXXXXXXXB 000004H PDR4 Port 4 data register R/W R/W Port 4 -XXXXXXXB 000005H PDR5 Port 5 data register R/W R/W Port 5 XXXXXXXXB 000006H PDR6 Port 6 data register R/W R/W Port 6 ----XXXXB 000007H Prohibited area 000008

H PWCSL0

R/W R/W

00000000B

PWC control status register CH0

000009H PWCSH0 R/W R/W 00000000B

00000AH

PWC0 PWC data buffer register CH0  R/W

PWC timer

(CH0)

XXXXXXXX 00000BH XXXXXXXXB 00000CH DIV0 Divide ratio control register CH0 R/W R/W ------00B 00000DH

to 0F

000010

H DDR0 Port 0 direction register R/W R/W Port 0 00000000B

Prohibited area

000011H DDR1 Port 1 direction register R/W R/W Port 1 00000000B 000012H DDR2 Port 2 direction register R/W R/W Port 2 00000000B 000013H DDR3 Port 3 direction register R/W R/W Port 3 00000000B 000014H DDR4 Port 4 direction register R/W R/W Port 4 -0000000B 000015H DDR5 Port 5 direction register R/W R/W Port 5 00000000B 000016H DDR6 Port 6 direction register R/W R/W Port 6 ----0000B 000017H ADER Analog input enable register R/W R/W Port 5, A/D 11111111B 000018H Prohibited area

000019

H CDCR0 Clock division control register 0 R/W R/W

Communication

prescaler 0

0---0000B 00001AH Prohibited area 00001BH CDCR1 Clock division control register 1 R/W R/W

Communication

prescaler 1

0---0000B 00001CH RDR0 Port 0 pull-up resistor setting register R/W R/W Port 0 00000000B

00001DH RDR1 Port 1 pull-up resistor setting register R/W R/W Port 1 00000000B 00001EH

to 1F

Prohibited area

(Continued)

MB90460 Series

Address

000020

Abbrevia-

tion

H SMR0 Serial mode register 0 R/W R/W

Byte

access

Word

access

Resource

name

Initial value

00000000B

000021H SCR0 Serial control register 0 R/W R/W 00000100B 000022H

SIDR0 / SODR0

Input data register 0 / output data register 0

R/W R/W XXXXXXXXB

UART0

000023H SSR0 Serial status register 0 R/W R/W 00001000B 000024H SMR1 Serial mode register 1 R/W R/W

00000000B

000025H SCR1 Serial control register 1 R/W R/W 00000100B 000026H

SIDR1 / SODR1

Input data register 1 / output data register 1

R/W R/W XXXXXXXXB

UART1

000027H SSR1 Status register 1 R/W R/W 00001000B 000028H PWCSL1

R/W R/W

00000000B

PWC control status register CH1

000029H PWCSH1 R/W R/W 00000000B

00002AH

PWC1 PWC data buffer register CH1  R/W

PWC timer

(CH1)

XXXXXXXX 00002BH XXXXXXXXB 00002CH DIV1 Divide ratio control register CH1 R/W R/W ------00B 00002DH

to 2F

Prohibited area

000030

H ENIR Interrupt / DTP enable register R/W R/W

00000000B

000031H EIRR Interrupt / DTP cause register R/W R/W XXXXXXXXB 000032H ELVRL

000033H ELVRH

Request level setting register (Lower Byte)

Request level setting register (Higher Byte)

R/W R/W 00000000B

000034H ADCS0 A/D control status register 0 R/W R/W 000035H ADCS1 A/D control status register 1 R/W R/W 00000000B 000036H ADCR0 A/D data register 0 R R XXXXXXXXB

DTP/external

interrupt

00000000B

8/10-bit A/D

converter

000037H ADCR1 A/D data register 1 R/W R/W 00000-XXB 000038H

11111111

PDCR0 PPG0 down counter register  R

000039H 11111111B 00003AH 00003BH XXXXXXXXB

PCSR0 PPG0 period setting register  W

16-bit

XXXXXXXX

PPG timer

00003CH

PDUT0 PPG0 duty setting register  W

(CH0)

XXXXXXXX 00003DH XXXXXXXXB 00003EH PCNTL0

R/W R/W --000000B

PPG0 control status register

00003FH PCNTH0 R/W R/W 00000000B

(Continued)

MB90460 Series

Address

000040

Abbrevia-

tion

Byte

access

Word

access

Resource

name

Initial value

11111111

PDCR1 PPG1 down counter register  R

000041H 11111111B 000042H 000043H XXXXXXXXB

PCSR1 PPG1 period setting register  W

16-bit

XXXXXXXX

PPG timer

000044H

PDUT1 PPG1 duty setting register  W

(CH1)

XXXXXXXX

000045H XXXXXXXXB 000046H PCNTL1

R/W R/W --000000B

PPG1 control status register

000047H PCNTH1 R/W R/W 00000000B 000048H

11111111

PDCR2 PPG2 down counter register  R

000049H 11111111B 00004AH 00004BH XXXXXXXXB

PCSR2 PPG2 period setting register  W

16-bit

XXXXXXXX

PPG timer

00004CH

PDUT2 PPG2 duty setting register  W

(CH2)

XXXXXXXX 00004DH XXXXXXXXB 00004EH PCNTL2

R/W R/W --000000B

PPG2 control status register

00004FH PCNTH2 R/W R/W 00000000B

000050H

XXXXXXXX

TMRR0 16-bit timer register 0  R/W

000051H XXXXXXXXB 000052H

XXXXXXXX

TMRR1 16-bit timer register 1  R/W

000053H XXXXXXXXB 000054H

TMRR2 16-bit timer register 2  R/W

000055H XXXXXXXXB

Waveform

generator

XXXXXXXX

000056H DTCR0 16-bit timer control register 0 R/W R/W 00000000B 000057H DTCR1 16-bit timer control register 1 R/W R/W 00000000B 000058H DTCR2 16-bit timer control register 2 R/W R/W 00000000B

000059H SIGCR Waveform control register R/W R/W 00000000B 00005AH 00005BH 11111111B 00005CH 00005DH 00000000B

CPCLRB /

CPCLR

Compare clear buffer register / Compare clear register (lower)

 R/W

TCDT Timer data register (lower)  R/W

16-bit

free-running

timer

11111111

00000000

00005EH TCCSL Timer control status register (lower) R/W R/W 00000000B

00005FH TCCSH Timer control status register (upper) R/W R/W -0000000B

(Continued)

MB90460 Series

Address

000060

Abbrevia-

tion

Byte

access

Word

access

Resource

name

Initial value

XXXXXXXX

IPCP0 Input capture data register CH0  R

000061H XXXXXXXXB

000062H

XXXXXXXX

IPCP1 Input capture data register CH1  R

000063H XXXXXXXXB

000064H

XXXXXXXX

IPCP2 Input capture data register CH2  R

000065H XXXXXXXXB

000066H

IPCP3 Input capture data register CH3  R

000067H XXXXXXXXB

000068H PICSL01

000069H PICSH01

00006AH ICSL23

00006BH ICSH23 00006CH

to 6E

PPG output control / Input capture control status register 01 (lower)

PPG output control / Input capture control status register 01 (upper)

Input capture control status register 23 (lower)

Input capture control status register 23 (upper)

Prohibited area

R/W R/W 00000000B

R R ------00B

16-bit

input capture

(CH0 to CH3)

XXXXXXXX

00006F

000070H

000071H XXXXXXXXB

000072H

000073H XXXXXXXXB

000074H

000075H XXXXXXXXB

000076H

000077H XXXXXXXXB

000078H

000079H XXXXXXXXB 00007AH 00007BH XXXXXXXXB

H ROMM

OCCPB0/

OCCP0

OCCPB1/

OCCP1

OCCPB2/

OCCP2

OCCPB3/

OCCP3

OCCPB4/

OCCP4

OCCPB5/

OCCP5

ROM mirroring function selection register

Output compare buffer register / output compare register 0

Output compare buffer register / output compare register 1

Output compare buffer register / output compare register 2

Output compare buffer register / output compare register 3

Output compare buffer register / output compare register 4

Output compare buffer register / output compare register 5

 R/W

ROM mirroring

function

Output compare

(CH0 to CH5)

-------1B

XXXXXXXX

(Continued)

MB90460 Series

Address

00007C

Abbrevia-

tion

H OCS0 Compare control register 0 R/W R/W

Byte

access

Word

access

Resource

name

Initial value

00000000B 00007DH OCS1 Compare control register 1 R/W R/W -0000000B 00007EH OCS2 Compare control register 2 R/W R/W 00000000B

00007FH OCS3 Compare control register 3 R/W R/W -0000000B

Output compare

(CH0 to CH5)

000080H OCS4 Compare control register 4 R/W R/W 00000000B 000081H OCS5 Compare control register 5 R/W R/W -0000000B

000082H TMCSRL0

000083H TMCSRH0

Timer control status register CH0 (lower)

Timer control status register CH0 (upper)

R/W R/W

00000000B

16-bit

R/W R/W ----0000B

reload timer

(CH0)

000084H 000085H XXXXXXXXB

000086H TMCSRL1

000087H TMCSRH1 000088H

000089H XXXXXXXXB

TMR0 /

TMRD0

TMR1 /

TMRD1

16 bit timer register CH0 / 16-bit reload register CH0

Timer control status register CH1 (lower)

Timer control status register CH1 (upper)

16 bit timer register CH1 / 16-bit reload register CH1

 R/W

R/W R/W

R/W R/W ----0000B

16-bit reload

timer (CH1)

 R/W

XXXXXXXX

00000000B

XXXXXXXX

00008AH OPCLR Output control lower register R/W R/W

00000000B 00008BH OPCUR Output control upper register R/W R/W 00000000B 00008CH IPCLR Input control lower register R/W R/W 00000000B 00008DH IPCUR Input control upper register R/W R/W 00000000B

Waveform sequencer

00008EH TCSR Timer control status register R/W R/W 00000000B

00008FH NCCR Noise cancellation control register R/W R/W 00000000B 000090H

to 9D

00009E

H PACSR

00009FH DIRR

0000A0H LPMCR

Program address detect control status register

Delayed interrupt cause / clear register

Low-power consumption mode

to A7

Prohibited area

R/W R/W Rom correction 00000000B

R/W R/W

Prohibited area

Delayed interrupt

Low-power

consumption

control register

-------0B

00011000B

0000A8H WDTC Watchdog control register R/W R/W Watchdog timer X-XXX111B 0000A9H TBTC Timebase timer control register R/W R/W Timebase timer 1--00100B

(Continued)

MB90460 Series

Address

0000AA

to AD

0000AE

Abbrevia-

tion

H FMCS

Prohibited area

Flash memory control status

Byte

access

R/W R/W

Word

Resource

name

Flash memory

interface circuit

Initial value

00010000B

0000AFH Prohibited area 0000B0H ICR00 Interrupt control register 00 R/W R/W

00000111B 0000B1H ICR01 Interrupt control register 01 R/W R/W 00000111B 0000B2H ICR02 Interrupt control register 02 R/W R/W 00000111B 0000B3H ICR03 Interrupt control register 03 R/W R/W 00000111B 0000B4H ICR04 Interrupt control register 04 R/W R/W 00000111B 0000B5H ICR05 Interrupt control register 05 R/W R/W 00000111B 0000B6H ICR06 Interrupt control register 06 R/W R/W 00000111B 0000B7H ICR07 Interrupt control register 07 R/W R/W 00000111B 0000B8H ICR08 Interrupt control register 08 R/W R/W 00000111B

Interrupt

controller

0000B9H ICR09 Interrupt control register 09 R/W R/W 00000111B 0000BAH ICR10 Interrupt control register 10 R/W R/W 00000111B 0000BBH ICR11 Interrupt control register 11 R/W R/W 00000111B 0000BCH ICR12 Interrupt control register 12 R/W R/W 00000111B 0000BDH ICR13 Interrupt control register 13 R/W R/W 00000111B 0000BEH ICR14 Interrupt control register 14 R/W R/W 00000111B 0000BFH ICR15 Interrupt control register 15 R/W R/W 00000111B 0000C0H

to FF

001FF0

H PADR0L

001FF1H PADR0M

001FF2H PADR0H

Program address detection register 0 (Lower Byte)

Program address detection register 0 (Middle Byte)

Program address detection register 0 (Higher Byte)

External area

R/W R/W

R/W R/W XXXXXXXXB

XXXXXXXXB

Rom correction

001FF3H PADR1L

001FF4H PADR1M

001FF5H PADR1H

Program address detection register 1 (Lower Byte)

Program address detection register 1 (Middle Byte)

Program address detection register 1 (Higher Byte)

R/W R/W XXXXXXXXB

(Continued)

MB90460 Series

(Continued)

Address

Abbrevia-

tion

Byte

access

Word

access

Resource

name

Initial value

003FE0

00000000

OPDBR0 Output data buffer register 0  R/W

003FE1H 00000000B 003FE2H

00000000

OPDBR1 Output data buffer register 1  R/W

003FE3H 00000000B 003FE4H

00000000

OPDBR2 Output data buffer register 2  R/W

003FE5H 00000000B 003FE6H

00000000

OPDBR3 Output data buffer register 3  R/W

003FE7H 00000000B

003F78H

00000000

OPDBR4 Output data buffer register 4  R/W

003FE9H 00000000B 003FEAH

00000000

OPDBR5 Output data buffer register 5  R/W

003FEBH 00000000B 003FECH

00000000

OPEBR6 Output data buffer register 6  R/W

003FEDH 00000000B 003FEEH

OPEBR7 Output data buffer register 7  R/W

003FEFH 00000000B

Waveform sequencer

003FF0H

00000000

OPEBR8 Output data buffer register 8  R/W

003FF1H 00000000B

003FF2H

00000000

OPEBR9 Output data buffer register 9  R/W

003FF3H 00000000B 003FF4H

00000000

OPEBRA Output data buffer register A  R/W

003FF5H 00000000B 003FF6H

00000000

OPEBRB Output data buffer register B  R/W

003FF7H 00000000B 003FF8H

XXXXXXXX

OPDR Output data register  R

003FF9H 0000XXXXB 003FFAH

XXXXXXXX

CPCR Compare clear register  R/W

003FFBH XXXXXXXXB 003FFCH

00000000

TMBR Timer buffer register  R

003FFDH 00000000B 003FFEH

003FFF

Prohibited area

MB90460 Series

• Meaning of abbreviations used for reading and writing R/W : Read and write enabled R : Read only W : Write only

• Explanation of initial values 0 : The bit is initialized to 0. 1 : The bit is initialized to 1. X : The initial value of the bit is undefined.

- : The bit is not used. Its initial value is undefined.

The Instruction using IO addressing e.g. MOV A, io, is not supported for registers area 003FE0

Note : For bits that is initialized by an reset operation, the initial v alue set by the reset operation is listed as an initial

value. Note that the values are different from reading results. For LPMCR/CKSCR/WDTC, there are cases where initialization is perf ormed or not performed, depending on the types of the reset. However, initial value for resets that initializes the value is listed.

H to 003FFFH.

MB90460 Series

INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

■■■■

Interrupt control

Priority

Interrupt cause

support

Interrupt vector

Number Address ICR Address

Reset #08 08 INT9 instruction #09 09 Exception processing #10 0AH FFFFD4H  A/D converter conversion termination #11 0B

× ×

H FFFFDCH High H FFFFD8H 

H FFFFD0H

ICR00 0000B0H

Output compare channel 0 match #12 0CH FFFFCCH End of measurement by PWC0 timer /

PWC0 timer overflow

#13 0DH FFFFC8H

ICR01 0000B1H

16-bit PPG timer 0 #14 0EH FFFFC4H Output compare channel 1 match #15 0FH FFFFC0H

ICR02 0000B2H

16-bit PPG timer 1 #16 10H FFFFBCH Output compare channel 2 match #17 11H FFFFB8H

ICR03 0000B3H

16-bit reload timer 1 underflow #18 12H FFFFB4H Output compare channel 3 match #19 13H FFFFB0H DTP/ext. interrupt channels 0/1 detection

#20 14

H FFFFACH

ICR04 0000B4H

DTTI0 ∆

Output compare channel 4 match #21 15

H FFFFA8H

DTP/ext. interrupt channels 2/3 detection

#22 16

H FFFFA4H

DTTI1 ∆ Output compare channel 5 match #23 17 End of measurement by PWC1 timer /

PWC1 timer overflow

#24 18H FFFF9CH

H FFFFA0H

DTP/ext. interrupt channels 4/5 detection #25 19H FFFF98H Waveform sequencer timer compare match

/ write timing

#26 1AH FFFF94H

DTP/ext. interrupt channels 6/7 detection #27 1BH FFFF90H Waveform sequencer position detect /

compare interrupt Waveform generator 16-bit timer 0/1/2

underflow

∆ #29 1DH FFFF88H

#28 1CH FFFF8CH

16-bit reload timer 0 underflow #30 1EH FFFF84H 16-bit free-running timer zero detect ∆ #31 1FH FFFF80H 16-bit PPG timer 2 #32 20H FFFF7CH Input capture channels 0/1 #33 21H FFFF78H 16-bit free-running timer compare clear ∆ #34 22H FFFF74H

ICR05 0000B5H

ICR06 0000B6H

ICR07 0000B7H

ICR08 0000B8H

ICR09 0000B9H

ICR10 0000BAH

ICR11 0000BBH

(Continued)

Interrupt cause

EI2OS

support

MB90460 Series

Interrupt vector

Number Address ICR Address

Interrupt control

Priority

Input capture channels 2/3 #35 23

H FFFF70H

ICR12 0000BCH

Timebase timer ∆ #36 24H FFFF6CH UART1 receive #37 25H FFFF68H

ICR13 0000BDH

UART1 send ∆ #38 26H FFFF64H UART0 receive #39 27H FFFF60H

ICR14 0000BEH

UART0 send ∆ #40 28H FFFF5CH Flash memory status ∆ #41 29H FFFF58H

ICR15 0000BFH

Delayed interrupt generator module ∆ #42 2AH FFFF54H Low

: Can be used and support the EI2OS stop request. : Can be used and interrupt request flag is cleared by EI

: Cannot be used.

OS interrupt clear signal.

∆ : Usable when an interrupt cause that shares the ICR is not used.

MB90460 Series

PERIPHERAL RESOURCES

■■■■

1. Low-Power Consumption Control Circuit

The MB90460 series has the following CPU operating mode configured by selection of an operating clock and clock operation control.

• Clock mode

PLL clock mode : A PLL clock that is a multiple of the oscillation clock (HCLK) frequency is used to operate the CPU and peripheral functions. Main clock mode : The main clock, with a frequency one-half that of the oscillation clock (HCLK) , is used to operate the CPU and peripheral functions. In main clock mode, the PLL multiplier circuit is inactive.

• CPU intermittent operation mode

CPU intermittent operation mode causes the CPU to operate intermittently, while high-speed clock pulses are supplied to peripheral functions, reducing power consumption. In CPU intermittent operation mode, intermittent clock pulses are only applied to the CPU when it is accessing a register, internal memory, a peripheral function, or an external unit.

• Standby mode

In standby mode, the low pow er consumption control circuit stops supplying the clock to the CPU (sleep mode) or the CPU and peripheral functions (timebase timer mode) , or stops the oscillation clock itself (stop mode) , reducing power consumption.

• PLL sleep mode PLL sleep mode is activated to stop the CPU operating clock when the microcontroller enters PLL clock mode; other components continue to operate on the PLL clock.

• Main sleep mode Main sleep mode is activated to stop the CPU operating clock when the microcontroller enters main clock mode; other components continue to operate on the main clock.

• PLL timebase timer mode PLL timebase timer mode causes microcontroller operation, with the exception of the oscillation cloc k, PLL clock and timebase timer, to stop. All functions other than the timebase timer are deactivated.

• Main timebase timer mode Main timebase timer mode causes microcontroller operation, with the exception of the oscillation cloc k, main clock and the timebase timer, to stop. All functions other than the timebase timer are deactivated.

• Stop mode Stop mode causes the source oscillation to stop. All functions are deactivated.

Block Diagram

RST

Release reset

Cancel interrupt

Low power mode control register (LPMCR)

STP

SLP SPL RST TMD CG1

CPU intermittent

operation selecter

Standby control

CG0 RESV

circuit

RST

MB90460 Series

Pin high

impedance

control circuit Internal reset

generation

circuit

CPU clock

control circuit

Stop and sleep signals Stop signal

Pin Hi-z control

Internal reset

Select intermittent cycles

CPU clock

Clock generator

Clock selector

×1×2×3×4

PLL multipiler

circuit

System clock generation circuit

Peripheral clock

Machine clock

Oscillation stabilization wait is passed

RESV MCM WS1 WS0 RESV MCS CS1 CS0

Clock selection register (CKSCR)

Divideby-2

Main clock

Divideby-512

Divideby-2

control circuit

Divideby-4

Peripheral clock

Oscillation stabilization wait interval selector

Divideby-4

Timebase timer

Divideby-4

MB90460 Series

2. I/O Ports

(1) Outline of I/O ports

When a data register serving for control output is read, the data output from it as a control output is read regardless of the value in the direction register . Note that, if a read-modify-write instruction (such as a bit set instruction) is used to preset output data in the data register when changing its setting from input to output, the data read is not the data register latched value but the input data from the pin.

Ports 0 to 4 and 6 are input/output ports which ser ve as inputs when the direction register value is “0” or as outputs when the value is “1”.

Port 5 are input/output ports as other port when ADER is 00

Block Diagram

• Block diagram of Port 0 pins

RDR

Port data register (PDR)

Internal data bus

PDR read

PDR write Port data direction register (DDR)

DDR write

DDR read

Output latch

Direction

latch

Resource output

Direct resource input

Resource output enable

Pull-up resistor About 50 KΩ

Standby control (SPL = 1)

(Continued)

• Block diagram of Port 1 pins

MB90460 Series

RDR

Port data register (PDR)

Internal data bus

PDR read

Output latch

PDR write Port data direction register (DDR)

Direction

latch

DDR write

DDR read

• Block diagram of Port 2 pins

Resource output

Resource output enable

Resource input

Pull-up resistor About 50 KΩ

Standby control (SPL = 1)

Port data register (PDR)

Internal data bus

PDR read

PDR write Port data direction register (DDR)

DDR write

DDR read

Output latch

Direction

latch

Resource output

Resource output enable

Resource input

Standby control (SPL = 1)

(Continued)

MB90460 Series

• Block diagram of Port 3 pins

Port data register (PDR)

Internal data bus

PDR read

PDR write Port data direction register (DDR)

DDR write

DDR read

• Block diagram of Port 4 pins

Resource output

Resource output enable

Output latch

Direction

latch

Standby control (SPL = 1)

Port data register (PDR)

Internal data bus

PDR read

PDR write Port data direction register (DDR)

DDR write

DDR read

Output latch

Direction

latch

Resource output

Resource output enable

Resource input

Standby control (SPL = 1)

(Continued)

• Block diagram of Port 5 pins

ADER

Port data register (PDR)

MB90460 Series

Analog input

Internal data bus

PDR read

PDR write Port data direction register (DDR)

DDR write

DDR read

• Block diagram of Port 6 pins

Port data register (PDR)

Output latch

Direction

latch

Resource output

Standby control (SPL = 1)

Resource input

Resource output enable

Internal data bus

PDR read

PDR write Port data direction register (DDR)

DDR write

DDR read

Output latch

Direction

latch

Standby control (SPL = 1)

External interrupt enable

MB90460 Series

3. Timebase Timer

The timebase timer is an 18-bit free-running counter (timebase counter) that counts up in synchronization to the internal count clock (main oscillator clock divided by 2) .

Features of timebase timer :

• Interrupt generated when counter overflow

•EI

OS supported

• Interval timer function : An interrupt generated at four different time intervals

• Clock supply function : Four different clocks can be selected as a watchdog timer’s count clock Supply clock for oscillation stabilization

Block Diagram

Timebase timer counter

watchdog timer

Divide-by

-two HCLK

CKSCR : MCS = 1 to 0 *

Timebase timer interrupt signal #36

(24

H)*

× 22× 2

× 2

Counter clear

Power-on reset

Stop mode start

TBOF clear

Counter

clear circuit

Timebase timer interrpt register (TBTC)

× 28× 29× 210× 211× 212× 213× 214× 215× 2

TBIE TBOF TBR TBC1 TBC0

Interval

timer selector

TBOF set

OF : Overflow HCLK : Oscillation clock

*1 : Switching of the machine clock from the oscillation clock to the PLL clock *2 : Interrupt number

× 2

To the oscillation setting time selector in the clock control section

MB90460 Series

4. Watchdog Timer

The watchdog timer is a 2-bit counter that uses the timebase timer’s supply clock as the count clock. After activation, if the watchdog timer is not cleared within a given period, the CPU will be reset.

• Features of Watchdog Timer : Reset CPU at four different time intervals Status bits to indicate the reset causes

Block Diagram

Watchdog timer control register (WDTC)

PONR STBR WRST ERST SRST WTE WT1 WT0

Start of sleep mode Start of hold status mode Start of stop mode

One-half of HCLK

HCLK : Oscillation clock

Watchdog timer

Counter

clear control

circuit

Clear

(Timebase timer counter)

× 2

Activation with CLR

Count

clock

selector

CLR

× 28× 29× 210× 211× 212× 213× 214× 215× 216× 217× 2

2-bit

counter

Overflow

reset generator

CLR

Watchdog

To the internal reset generator

MB90460 Series

5. 16 bit reload timer ( ×××× 2)

The 16-bit reload timer provides two operating mode, internal clock mode and event count mode. In each operating mode, the 16-bit down counter can be reloaded (reload mode) or stopped when underflow (one-shot mode) .

Output pins TO1 - TO0 are able to output different waveform accroding to the counter operating mode. TO1 TO0 toggles when counter underflow if counter is operated as reload mode. TO1 - TO0 output specified level (H or L) when counter is counting if the counter is in one-shot mode.

Features of the 16 bit reload timer :

• Interrupt generated when timer underflow

•EI

OS supported

• Internal clock operating mode : Three internal count clocks can be selected Counter can be activated by software or exteranl trigger (singal at TIN1 - TIN0 pin) Counter can be reloaded or stopped when underflow after activated

• Event count operating mode : Counter counts down by one when specified edge at TIN1 - TIN0 pin Counter can be reloaded or stopped when underflow

Block Diagram

MC-16LX Bus

MB90460 Series

TMR0* <TMR1>

Count clock generation circuit

Machine clock

P15/TIN0* <P20/TIN1>

Prescaler

control

Function selection

TMRD0* <TMRD1>

16-bit timer register

Input

circuit

16-bit reload register

Clear

External clock

Gate input

Internal clock

CLK

Valid clock

judgment

circuit

CLK

Clock

selector

Select signal

Reload signal

control circuit

Wait signal

Output control circuit

Output signal

generation

Invert

circuit

Reload

To UART0 and UART1 * <To the A/D converter>

P16/TO0* <P21/TO1>

Operation

control

circuit

CSL1 CSL0 MOD2

Timer control status register (TMCSR0)*

MOD1MOD0OUTE OUTL RELD UFINTE CNTE TRG

Interrupt request signal #30 (1EH)* <#32 (20H)>

*1 : This register includes channel 0 and channel 1. The register enclosed in < and > indicates the

channel 1 register.

*2 : Interrupt number

MB90460 Series

6. 16-bit PPG Timer ( ×××× 3 )

The 16-bit PPG timer consists of a 16-bit down counter, prescaler, 16-bit period setting buffer register, 16-bit duty setting buffer register, 16-bit control register and a PPG output pin. This module can be used to output pulses synchronized by software trigger or GATE signal from Multi-functional timer, refer to “Multi-functional Timer”

Features of 16-bit PPG Timer :

• Two operating mode : PWM and One-shot

• 8 types of counter operation clock (φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128) can be selected

• Interrupt generated when trigger signal arrived, or counter borrow, or change of PPG output

•EI

OS supported

Block Diagram

Prescaler

CKS2 CKS1 CKS0

1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/128

Machine clock φ

MC-16LX Bus

Down Counter

GATE-from multi-functional

timer (for PPG ch. 0 only)

Period Setting

Buffer Register 0/1/2

Period Setting Register 0/1/2

CLK LOAD

16-bit

down counter

STOP

BORROWSTART

Duty Setting

Buffer Register 0/1/2

Duty Setting

Comparator

Interrupt

selection

MDSEPGMS OSEL POEN

PPG0 (multi-functional timer)

PPG1 (multi-pulse generator)

PPG2

Interrupt #14/#16/#32

P37/PPG0

P36/PPG1

P46/PPG2

Edge detection

(for PPG ch. 1 & 2)

STGR

CNTE

IRS1 IRS0 IRQFIREN

RTRG

MB90460 Series

7. Multi-functional Timer

The 16-bit multi-functional timer module consists of one 16-bit free-running timer, four input capture circuits, six output comparators and one channel of 16-bit PPG timer. This module allows six independent waveforms generated by PPG timer or waveform generator to be outputted. With the 16-bit free-run timer and the input capture circuit, a input pulse width measurement and external clock cycle measurement can be done.

(1) 16-bit free-running timer (1 channel)

• The 16-bit free-running timer consists of a 16-bit up/up-down counter, control register, 16-bit compare clear register (with buffer register) and a prescaler.

• 8 types of counter operation clock (φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128) can be selected. (φ is the machine clock)

• Two types of interrupt causes :

- Compare clear interrupt is generated when there is a comparing match with compare clear register and 16bit free-run timer.

- Zero detection interrupt is generated while 16-bit free-running timer is detected as zero in count value.

•EI

OS supported

• The compare clear register has a selectable buff er register, into which data is written f or transfer to the compare clear register. When the timer is stopped, transfer occurs immediately when the data is written to the buffer. When the timer is operation, data transfer from the buffer occurs when the timer value is detected to be zero .

• Reset, software clear, compare match with compare clear register in up-count mode will reset the counter value to “0000

• Supply clock to output compare module : The prescaler ouptut is acted as the count clock of the output compare.

H”.

(2) Output compare module (6 channels)

• The output compare module consists of six 16-bit compare registers (with selectable buff er register) , compare output latch and compare control registers. An interrupt is generated and output level is inverted when the value of 16-bit free-running timer and compare register are matched.

• 6 compare registers can be operated independently.

• Output pins and interrupt flag are corresponding to each compare register.

• Inverts output pins by using 2 compare registers together. 2 compare registers can be paired to control the output pins.

• Setting the initial value for each output pin is possible.

• Interrupt generated when there is a comparing match with output compare register and 16 bit free-run timer

•EI

OS supported

(3) Input capture module (4 channels)

Input capture consists of 4 independent external input pins, the corresponding capture register and capture control register. By detecting any edge of the input signal from the external pin, the value of the 16-bit freerunning timer can be stored in the capture register and an interrupt is generated simultaneously.

• Operation synchronized with the 16-bit free-run timer’s count clock.

• 3 types of trigger edge (rising edge, falling edge and both edge) of the external input signal can be selected and there is indication bit to show the trigger edge is rising or falling.

• 4 input captures can be operated independently.

• Two independent interrupts are generated when detecting a valid edge from external input.

•EI

OS supported

(4) 16-bit PPG timer (

××××

The 16-bit PPG timer 0 is used to provide a PPG signal for waveform generator.

MB90460 Series

(5) Waveform Generator module

The wav eform generator consists of three 16-bit timer registers, three timer control registers and 16-bit wav eform control register.

With waveform generator, it is possible to generate real time output, 16-bit PPG waveform output, non-overlap 3-phase waveform output for inverter control and DC chopper waveform output.

• It is possible to generate a non-ov erlap wav ef orm output based on dead-time of 16-bit timer . (Dead-time timer function)

• It is possible to generate a non-ov erlap wav ef orm output when realtime output is operated in 2-channel mode. (Dead-time timer function)

• By detecting realtime output compare match, GATE signal of the PPG timer operation will be generated to start or stop PPG timer operation. (GATE function)

• When a match is detected by realtime output compare, the 16-bit timer is activated. The PPG timer can be started or stopped easily by generating a GATE signal for PPG operation until the 16-bit timer stops. (GATE function)

• Forced to stop output waveform using DTTI0 pin input

• Interrupt generated when DTTI0 active or 16-bit tmer underflow

•EI

OS supported

• MCU to 3-phase Motor Interface Circuit

VCC

RTO0(U)

RTO1(X)

RTO2(V)

(U)

RTO3(Y)

RTO0 (U) , RTO2 (V) , RTO4 (W) are called “UPPER ARM”. RTO1 (X) , RTO3 (Y) , RTO5 (Z) are called “LOWER ARM”.

RTO4(W)

(V)

RTO5(Z)

(W)

RTO0 (U) and RTO1 (X) are called “non-overlapping output pair”. RTO2 (V) and RTO3 (Y) are called “non-overlapping output pair”. RTO4 (W) and RTO5 (Z) are called “non-overlapping output pair”.

(U) , (V) , (W) are the 3-phase coil connection.

• 3-phase Motor Coil Connection Circuit

Star Connection Circuit

MB90460 Series

(U)

Delta Connection Circuit

(W)

(V)

(U)

(V)

MB90460 Series

Block Diagram

• Block Diagram of Multi-functional Timer

Real time I/O

Interrupt#12 Interrupt#15 Interrupt#17 Interrupt#19 Interrupt#21

16-bit Output

Compare

buffer

transfer

Interrupt#23

counter

value

RT0 to 5

output compare 0 output compare 1 output compare 2 output compare 3 output compare 4 output compare 5

RT0 to 5

Waveform

generator

RTO0

RTO1

RTO2 RTO3

RTO4

RTO5

DTTI

P30/RTO0 (U)

P31/RTO1 (X)

P32/RTO2 (V)

P33/RTO3 (Y)

P34/RTO4 (W)

P35/RTO5 (Z)

P10/INT0/DTTI0

MC-16LX Bus

16-bit free-

running

timer

counter

value

16-bit Input

Capture

Interrupt#31 Interrupt#34

A/D trigger A/D trigger

EXCK

Interrupt #33 Interrupt #35

IN0

IN1

IN2 IN3

Zero detect Compare clear

Input capture 0/1 Input capture 2/3

Interrupt#29 16-bit timer 0/1/2

Interrupt#20 DTTI0 falling edge detect

PPG0 PPG0

GATE GATE

underflow

P17/FRCK

P24/IN0

P25/IN1

P26/IN2

P27/IN3

(Continued)

• Block diagram of 16-bit free-running timer

MB90460 Series

MC-16LX BUS

STOP MODE SCLR CLK2 CLK1 CLK0

UP/

STOP

UP-DOWN

16-bit free-running timer

16-bit compare clear register

16-bit compare clear buffer register

Mask Circuit

CLR

transfer

Selector

Compare

circuit

I0 I1

Selector

I0 I1

Selector

Zero detect

circuit

Prescaler

Zero detect (to output compare)

To Input Capture & Output Compare

Compare clear match (to output compare)

Interrupt #31 (1F

Interrupt #34 (22

MSI2 MSI1 MSI0 ICLR ICRE IRQZF IRQZE

I0 I1

Selector

A/D trigger

(Continued)

MB90460 Series

• Block diagram of 16-bit output compare

Count value from Free-running timer

MC-16LX BUS

Compare buffer

Compare register 0/2/4

Compare circuit

Compare buffer

Compare register 1/3/5

Compare circuit

transfer

BUF0

Selector

BUF1

Selector

CMOD

IOP1 IOP0 IOE1 IOE0

BTS0

I0 I1

BTS1

I0 I1

TQ RT0/2/4

Zero detect from free-running timer

Compare clear match from free-running timer

(Waveform

generator)

RT1/3/5

(Waveform

generator)

Interrupt #12, #17, #21

#15, #19, #23

• Block diagram of 16-bit input capture

Count value from Free-running timer

Capture register 0/2

MC-16LX BUS

Capture register 1/3

Edge detect

EG11 EG10 EG01 EG00 IEI1 IEI0

Edge detect

ICP0 ICP1 ICE0 ICE1

IN0/2

IN1/3

Interrupt #33, #35

#33, #35

(Continued)

• Block diagram of waveform generator

MB90460 Series

Divider

DTCR0

DTCR1

MC-16LX BUS

DCK2 DCK1 DCK0 NRSL DTIF DTIE NWS1 NWS0

PICSH01

TMD2 TMD1 TMD0

RT0 RT1

16-bit timer 0

16-bit timer register 0

TMD2 TMD1 TMD0 GTEN1 GTEN0

PICSH01

RT2 RT3

16-bit timer 1

PGEN1PGEN0

GTEN1 GTEN0

Compare circuit

PGEN3 PGEN2

Compare circuit

DTTI0 control circuit

Waveform control

Selector

Dead time generator

Waveform control

Selector

TO0

TO1

TO2

TO3

Noise Cancellation

GATE 0/1

Selector

GATE 2/3

Selector

SIGCR

DTTI0

GATE (to PPG0)

RTO0 (U)

Output ControlOutput ControlOutput Control

RTO1 (X)

RTO2 (V)

DTCR2

PPG0

16-bit timer register 1

TMD2 TMD1 TMD0

RT4 RT5

16-bit timer 2

16-bit timer register 2

PICSH01

GTEN1 GTEN0

PGEN5PGEN4

Compare circuit

Dead time generator

Waveform control

Selector

Dead time generator

V Y

TO4

TO5

GATE 4/5

Selector

RTO3 (Y)

RTO4 (W)

RTO5 (Z)

MB90460 Series

8. Multi-Pulse Generator

The Multi-pulse Generator consists of a 16-bit PPG timer, a 16-bit reload timer and a waveform sequencer. By using the wav eform sequencer, 16-bit PPG timer output signal can be directed to Multi-pulse Generator output (OPT5 to 0) according to the input signal of Multi-pulse Generator (SNI2 to 0) . Meanwhile, the OPT5 to 0 output signal can be hardware terminated by DTTI input (DTTI1) in case of emergency. The OPT5 to 0 output signals are synchronized with the PPG signal in order to eliminate the unwanted glitch.

The Multi-pulse generator has the following features :

• Output Signal Control

- 12 output data buffer registers are provided

- Output data register can be updated by any one of output data buffer registers when :

1. an effective edge detected at SNI2 - SNI0 pin

2. 16-bit reload timer underflow

3. output data buffer register OPDBR0 is written

• Output data register (OPDR) determines which OPT terminals (OPT5 - 0) output the 16-bit PPG waveform

- Waveform sequencer is provided with a 16-bit timer to measure the speed of motor

- The 16-bit timer can be used to disable the OPT output when the position detection is missing

• Input Position Detect Control

- SNI2 - SNI0 input can be used to detect the rotor position

- A controllable noise filter is provided to the SNI2 - SNI0 input

• PPG Synchronization for Output signal

- OPT output is able to synchronize the edge of PPG waveform to avoid a short pulse (or glitch) appearance

• Vaious interrupt generation causes

•EI

OS supported

Block Diagram

• Block diagram of Multi-pulse generator

MB90460 Series

MC-16LX Bus

P12/INT2/DTTI1

P45/SNI2

P44/SNI1

P43/SNI0

P15/INT5/TIN0

16-BIT PPG TIMER 1

16-BIT RELOAD TIMER 0

PPG1

TOUT

TIN

DTTI

SNI2

SNI1

SNI0

TIN0

PPG1

WIN0 TIN0O

WAVEFORM

SEQUENCER

OPT5

OPT4

OPT3

OPT2

OPT1

OPT0

Interrupt #22

Interrupt #26

Interrupt #28

P05/OPT5

P04/OPT4

P03/OPT3

P02/OPT2

P01/OPT1

P00/OPT0

INTERRUPT #22

INTERRUPT #26

INTERRUPT #28

P16/INT6/TO0

(Continued)

MB90460 Series

(Continued)

• Block diagram of waveform sequencer

Interrupt #22

DTIE DTIF NRSL OPS2 OPS1 OPS0 WTIF WTIE PDIF PDIE OPE5 OPE4 OPE3 OPE2 OPE1 OPE0

OPDBRB to 0 Registers

WRITE TIMING INTERRUPT

OPCR Register

DECODER

POSITION DETECTION INTERRUPT

OPDR Register

OP × 1/OP × 0

RDA2 to 0

COMPARE CLEAR INTERRUPT

OUTPUT

CONTROL

CIRCUIT

DTTI1 Control

Circuit

SYN Circuit

Noise

Filter

PDIRT

From PPG1 WTS1

WTS0

P00/OPT0

P01/OPT1

P02/OPT2

P03/OPT3

P04/OPT4

P05/OPT5

P12/INT2/DTTI1

D1 D0

Interrupt #26

MC-16LX Bus

OPS2 OPS1 OPS0

WTS1 WTS0 CPIF CPIE CPD2 CPD1 CPD0 CMPE CPE1 CPE0 SNC2 SNC1 SNC0

IPCR Register

NCCR Register

OUTPUT DATA BUFFER REGISTER × 12

16-BIT TIMER

DATA WRITE CONTROL UNIT

SELECTOR

TIN0O WTIN0

TIN0O

WTO

WTIN1

WTIN0

BNKF

CCIRT

WTO

WTIN1

COMPARISON CIRCUIT

COMPARE MATCH INTERRUPT

D0D1S00S01S10S11S20S21

WTIN1

PDIRT

POSITION

DETECT

CIRCUIT

SEE2

P15/INT5/TIN0

SEE1 SEE0

Interrupt #28

P43/SNI0

P44/SNI1

P45/SNI2

MB90460 Series

9. PWC Timer

The PWC (pulse width count) timer is a 16-bit multi-function up-counter with reload timer functions and inputsignal pulse-width count functions as well.

The PWC timer consists of a 16-bit counter, on input pulse divider, a divide ratio control register, a count input pin, a pulse output pin, and a 16-bit control register.

The PWC timer has the following features :

• Interrupt generated when timer overflow or end of PWC measurement.

•EI

OS supported

• Timer functions :

- Generates an interrupt request at set time intervals.

- Outputs pulse signals synchronized with the timer cycle.

- Selects the counter clock from among three internal clocks.

• Pulse-width count functions

- Counts the time between external pulse input events.

- Selects the counter clock from among three internal clocks.

- Count mode

• H pulse width (rising edge to falling edge) /L pulse width (falling edge to rising edge)

• Rising-edge cycle (rising edge to falling edge) /Falling-edge cycle (falling edge to rising edge)

• Count between edges (rising or falling edge to falling or rising edge)

Capable of counting cycles by dividing input pulses by 2 Generates an interrupt request upon the completion of count operation. Selects single or consecutive count operation.

, 24, 26, 28 using an 8-bit input divider.

MB90460 Series

Block Diagram

MC-16LX bus

PWC read

16 16

Overflow

Write enabled

Start edge selection Count end edge

Flag setting

Count bit

output

Count start edge

Count end interrupt request Overflow interrupt request

Error

detection

Reload Data transfer

Control circuit

detection

PWCS

ERR

PWC 16

16-bit up count timer

Timer clear

End edge selection

Edge

CKS0

ERR

CKS1

Overflow

Divider ON/OFF

Division rate selection

DIVR

Clock

Count enabled

F.F.

8-bit

divider

2 2

CKS1, CKS0, Divider clear

Clock

divider

Internal clock

(machine clock / 4)

P07/PWO0 P23/PWO1

P06/PWI0 P22/PWI1

MB90460 Series

10. UART

The UAR T is a serial I/O port for asynchronous (start-stop) communication or clock-synchronous communication. The UART has the following features :

• Full-duplex double buffering

• Capable of asynchronous (start-stop bit) and CLK-synchronous communications

• Support for the multiprocessor mode

• Various method of baud rate generation :

- External clock input possible

- Internal clock (a clock supplied from 16-bit reload timer can be used.)

- Embedded dedicated baud rate generator

Operation Baud rate

Asynchronous 31250/9615/4808/2404/1202 bps

CLK synchronous 2 M/1 M/500 K/250 K/125 K/62.5 Kbps

* : Assuming internal machine clock frequencies of 6, 8, 10, 12, and 16 MHz

• Error detection functions (parity, framing, overrun)

• NRZ (Non Return to Zero) Signal format

• Interrupt request :

- Receive interrupt (receive complete, receive error detection)

- Transmit interrupt (transmission complete)

- Transmit / receive conforms to extended intelligent I/O service (EI

• Flexible data length :

- 7 bit to 9 bit selective (without a parity bit)

- 6 bit to 8 bit selective (with a parity bit)

OS)

MB90460 Series

Block Diagram

Dedicated baud rate generator

16-bit reload timer

SCK0, 1

Clock

selector

Reception clock

Control bus

Reception control circuit

Start bit

detection circuit

Reception interrupt request output

Send interrupt request output

Send clock

send control circuit

Send start circuit

SIN0, 1

Reception status

determination circuit

Communication prescaler control register

DIV2 DIV1 DIV0

Serial mode register 0, 1

Reception bit

counter

Reception parity

counter

Reception

shift register

Serial input

data register (0, 1)

Internal data bus

MD1 MD0 CS2 CS1 CS0 RST SCKE SOE

Serial control register 0, 1

Send bit counter

Send parity counter

Send shift register

End of reception

Serial output

data register (0, 1)

PEN P SBL CL A/D REC RXE TXE

Serial status register 0, 1

SOT0, 1

Start of transmission

EI OS receive error generation signal (to CPU)

PE ORE FRE RDRF TDRE BDS RIE TIE

MB90460 Series

11. DTP/External Interrupts

The DTP/external interrupt circuit is activated by the signal supplied to a DTP/exter nal interr upt pin. The CPU accepts the signal using the same procedure it uses for normal hardware interrupts and generates external interrupts or activates the extended intelligent I/O service (EI

Features of DTP/External Interrupt :

• Total 8 external interrupt channels

• Two request levels (“H” and “L”) are provided for the intelligent I/O service.

• Four request le vels (rising edge, falling edge, “H” le vel and “L” level) are pro vided for external interrupt requests.

Block Diagram

Request level setting register (ELVR) LB7

LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

2 2 2 2 2 2 2 2

OS) .

Selector

Pin Pin

P63/INT7 P10/INT0/DTTI0

Pin Pin

P16/INT6/TO0 P11/INT1

Internal data bus

P15/INT5/TIN0

P14/INT4

Selector

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

Selector

P12/INT2/DTTI1

P13/INT3

Interrupt request number

#20(14H)

#22(16

#25(19

#27(1B

MB90460 Series

12. Delayed Interrupt Generation Module

The delayed interrupt generation module is used to generate a task s witching interrupt. Interrupt requests to the

MC-16LX CPU can be generated and cleared by software using this module.

Block Diagram

Delayed interrupt cause issuance/cancellation decoder

MC- 16LX bus

Interrupt cause latch

MB90460 Series

13. A/D Converter

The converter converts the analog voltage input to an analog input pin (input voltage) to a digital value. The converter has the following features :

• The minimum conversion time is 6.13 µs (for a machine clock of 16 MHz; includes the sampling time) .

• The minimum sampling time is 2.0 µs (for a machine clock of 16 MHz) .

• The converter uses the RC-type successive approximation conversion method with a sample hold circuit.

• A resolution of 10 bits or 8 bits can be selected.

• Up to eight channels for analog input pins can be selected by a program.

• Various conversion mode :

- Single conversion mode : Selectively convert one channel.

- Scan conversion mode : Continuously con vert multiple channels. Maximum of 8 program selectable channels .

- Continuous conversion mode : Repeatedly convert specified channels.

- Stop conversion mode : Con vert one channel then halt until the next activ ation. (Enab les synchronization of the conversion start timing.)

• At the end of A/D conversion, an interrupt request can be generated and EI

• In the interrupt-enabled state, the con version data protection function pre vents an y part of the data from being lost through continuous conversion.

• The conversion can be activated by software, 16-bit reload timer 1 (rising edge) and 16-bit free-running timer zero detection edge.

OS can be activated.

MB90460 Series

Block Diagram

AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7

MPX

Input circuit

Comparator

Sample and hold circuit

AVCC

D/A converter

Sequential compare register

Data register

Decoder

A/D control register 0 A/D control register 1

ADCR0/1

SSAVR

ADCS0/1

MC-16LX bus

16-bit reload timer 1

16-bit free-running timer zero detection

φ : Machine clock

Operation clock

Prescaler

MB90460 Series

14. ROM Correction Function

In the case that the address of the instruction after the one that a program is currently processing matches the address configured in the detection address configuration register, the program f orces the ne xt instruction to be processed into an INT9 instruction, and branches to the interrupt process program. Since processing can be conducted using INT9 interrupts, programs can be repaired using batch processing.

••••

Overview of the Rom correction Function

• The address of the instr uction after the one that a program is currently processing is always stored in an address latch via the internal data bus. Address match detection constantly compares the address stored in the address latch with the one configured in the detection address configuration register . If the two compared addresses match, the CPU forcibly changes this instruction into an INT9 instruction, and ex ecutes an interrupt processing program.

• There are two detection address configuration registers : PADR0 and PADR1. Each register provides an interrupt enable bit. This allows you to individually configure each register to enab le/prohibit the generation of interrupts when the address stored in the address latch matches the one configured in the detection address configuration register.

Block Diagram

Address latch

PADR0 (24 bit)

Detection address configuration register 0

Internal data bus

Detection address configuration register 1

PACSR

Reserved

Address detection control register (PACSR)

PADR1 (24 bit)

Reserved

AD1E

Comparator

Reserved

AD0E

Reserved

Reseved : Make sure this is always set to “01”

• Address latch Stores value of address output to internal data bus.

• Address detection control register (PACSR) Set this register to enable/prohibit interrupt output when an address match is detected.

• Detection address configuration register (PADR0, PADR1) Configure an address with which to compare the address latch value.

INT9 instruction

(INT9 interrupt generation)

MB90460 Series

15. ROM Mirroring Function Selection Module

The ROM mirroring function selection module can select what the FF bank allocated the ROM and see through the 00 bank according to register settings.

Block Diagram

ROM mirroring register

Address area

FF bank 00 bank

MC-16LX bus

ROM

MB90460 Series

16. 512 Kbit Flash Memory

The 512 Kbit flash memory is allocated in the FEH to FFH banks on the CPU memory map. Like masked ROM, flash memory is read-accessible and program-accessible to the CPU using the flash memory interface circuit.

The flash memory can be programmed/erased by the instruction from the CPU via the flash memory interface circuit. The flash memory can therefore be reprogrammed (updated) while still on the circuit board under integrated CPU control, allowing program code and data to be improved efficiently.

Note that sector operations such as “enable sector protect” cannot be used. Features of 512 Kbit flash memory

• 64 kwords × 8 bits/32 kwords × 16 bits (16 k + 8 k + 8 k + 32 k) sector configuration

• Automatic program algorithm (same as the Embedded Algorithm* : MBM29F400TA)

• Installation of the deletion temporary stop/delete restart function

• Write/delete completion detected by the data polling or toggle bit

• Write/delete completion detected by the CPU interrupt

• Compatibility with the JEDEC standard-type command

• Each sector deletion can be executed (Sectors can be freely combined) .

• Flash security feature

• Number of write/delete operations 10,000 times guaranteed.

• Flash reading cycle time (Min) 2 machine cycles

* : Embedded Algorithm is a trademark of Advanced Micro Devices, Inc.

(1) Register configuration

Flash Memory Control status register

76543210

Address : 0000AE

Read/write

Initial value

RDYINT

INTE WE RDY

H FMCS

R/W0R/W

R/W

Reserved LPM1 Reserved LMP0

Bit number

R/W

MB90460 Series

(2) Sector configuration of 512Kbit flash memory

The 512 Kbit flash memory has the sector configuration illustrated below. The addresses in the illustration are the upper and lower addresses of each sector.

When accessed from the CPU, SA0 to SA3 are allocated in the FF bank registers, respectively.

Flash memory CPU address *Writer address

FFFFFFH

SA3 (16 Kbytes)

FFC000H FFBFFFH

SA2 (8 Kbytes)

FFA000H FF9FFFH

SA1 (8 Kbytes)

FF8000H FF7FFFH

SA0 (32 Kbytes)

FF0000H

7FFFFH

7C000H 7BFFFH

7A000H 79FFFH

78000H 77FFFH

70000H

* : Programmer addresses correspond to CPU addresses when data is programmed in flash memory by a parallel

programmer. Programmer addresses are used to program/erase data using a general-purpose programmer.

ELECTRICAL CHARACTERISTICS

■■■■

1. Absolute Maximum Ratings

Parameter Symbol

CC VSS − 0.3 VSS + 6.0 V

Power supply voltage

AVCC VSS − 0.3 VSS + 6.0 V VCC ≥ AVCC

AVR VSS − 0.3 VSS + 6.0 V AVCC ≥ AVR, AVR ≥ AVSS Input voltage VI VSS − 0.3 VSS + 6.0 V *2 Output voltage VO VSS − 0.3 VSS + 6.0 V *2

Rating

Unit Remarks

Min Max

MB90460 Series

(VSS = AVSS = 0.0 V)

* 1

Maximum clamp current I Total maximum clamp current Σ| I “L” level maximum output

current “L” level average output

current “L” level total maximum

output current “L” level total average

output current “H” level maximum output

current “H” level average output

current “H” level total maximum

output current “H” level total average

output current Power consumption P Operating temperature T

CLAMP − 2.0 + 2.0 mA *4

CLAMP |  20 mA *4

IOL  15 mA *3

OLAV  4mA

ΣI

OL  100 mA

ΣIOLAV  50 mA

OH  − 15 mA *3

OHAV  − 4mA

ΣI

OH  − 100 mA

ΣIOHAV  − 50 mA

D  300 mW A −40 +85 °C

Storage temperature Tstg −55 +150 °C

Average output current = operating current × operating efficiency

*1 : AV *2 : V

CC shall never exceed VCC when power on.

I and VO shall never exceed VCC + 0.3 V.

*3 : The maximum output current is a peak value for a corresponding pin. *4 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P46, P60 to P63

• Use within recommended operating conditions.

• Use at DC voltage (current) .

• The +B signal should always be applied with a limiting resistance placed between the +B signal and the

microcontroller.

• The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

(Continued)

MB90460 Series

(Continued)

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the V other devices.

• Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result.

• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the +B input pin open.

• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input.

• Sample recommended circuits:

CC pin, and this may affect

• Input/Output Equivalent circuits

B input (0 V to 16 V)

Limiting

resistance

Protective diode

P-ch

N-ch

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

2. Recommended Operating Conditions

Parameter

Sym-

bol

Value

Min Max

MB90460 Series

(VSS = AVSS = 0.0 V)

Unit Remarks

Power supply

voltage

CC 3.0 5.5 V Retains status at the time of operation stop

Smoothing capacitor

Operating temperature

S 0.1 1.0 µF

A −40 +85 °C

• C pin connection circuit

3.0 5.5 V Normal operation (MB90462, MB90467, MB90V460)

4.5 5.5 V Normal operation (MB90F462)

Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be connected to the VCC pin must have a capacitance value higher than C

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.

MB90460 Series

3. DC Characteristics

Parameter

Sym-

bol

Pin name Condition

(VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Unit Remarks

Min Typ Max

“H” level output voltage

“L” level output voltage

“H” level input voltage

“L” level input voltage

OH All output pins

All pins except P00 to P05 and P30 to P35

P00 to P05, P30 to P35

P00 to P07 P30 to P37

VIH

P50 to P57

VCC = 4.5 V, I

OH = − 4.0 mA

VCC = 4.5 V, I

OL = 4.0 mA

CC = 4.5 V,

OL = 12.0 mA

VCC − 0.5 V

0.4 V

0.7 V

CC  VCC + 0.3 V

CMOS input pin

P10 to P17 P20 to P27

P40 to P46

IHS

P60 to P63, RST

IHM MD pins VCC − 0.3  VCC + 0.3 V MD pin input

P00 to P07 P30 to P37

VIL

P50 to P57

CC =

3.0 V to 5.5 V (MB90462)

CC =

4.5 V to 5.5 V (MB90F462)

0.8 VCC  VCC + 0.3 V

SS − 0.3  0.3 VCC V

CMOS hysteresis input pin

CMOS input pin

P10 to P17

ILS

P20 to P27 P40 to P46 P60 to P63,

VSS − 0.3  0.2 VCC V

CMOS hysteresis input pin

RST

Input leakage current

Power supply current*

ILM MD pins VSS − 0.3  VSS + 0.3 V MD pin input

IL All input pins

VCC = 5.5 V, V

SS < VI < VCC

− 5  5 µA

VCC = 5.0 V, Internal operation at 16 MHz,

 40 50 mA Normal operation V

CC = 5.0 V,

Internal operation at 16 MHz,

VCC

When data writ-

 45 60 mA ten in flash mode programming of erasing

VCC = 5.0 V,

CCS

Internal operation at 16 MHz,

 15 20 mA In sleep mode

(Continued)

Parameter

Power supply current*

Sym-

bol

CTS

ICCH

Pin name Condition

VCC = 5.0 V, Internal operation at 16 MHz,

VCC

In Timer mode, T

A = 25 °C

In stop mode, T

A = 25 °C

MB90460 Series

(VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Unit Remarks

Min Typ Max

 2.5 5.0 mA

 520µA

Input capacitance

Pull-up resistance

Pull-down resistance

Except AVCC,

SS, C, VCC

and V

10 80 pF

P00 to P07

P10 to P17

 25 50 100 kΩ

RST

DOWN MD2  25 50 100 kΩ

* : The current value is preliminary value and may be subject to change f or enhanced characteristics without previous

notice. The power supply current is measured with an external clock.

MB90460 Series

4. AC Characteristics

(1) Clock Timings

Parameter Symbol

name

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Unit Remarks

Min Typ Max

Clock frequency f

C X0, X1

3  16 3  32 External clock *

Crystal oscillator

MHz

Clock cycle time tHCYL X0, X1 62.5  333 ns Frequency fluctuation

rate locked*

Input clock pulse width P

Input clock rise/fall time Internal operating clock f

Internal operating clock cycle time

∆f 5 %

WH PWL X0 10 ns

tCR tCF

CP  1.5  16 MHz Main clock operation

CP  62.5  666 ns Main clock operation

X0 5 ns External clock operation

Recommened duty ratio of 30% to 70%

*1 : The frequency fluctuation rate is the maximum deviation r ate of the preset center frequency when the multiplied

PLL signal is locked.

*2 : Internal operating clock frequency must not be over 16 MHz.

 α 

∆f = × 100 (%)

Center

frequency

+α

−α

tHCYL

PWH PWL

tCF

0.8 VCC

0.2 VCC

tCR

MB90460 Series

Relationship between internal operating clock frequency and power supply voltage

Operation guarantee range of MB90F462

5.5

4.5

3.3

3.0

Operation guarantee range of MB90462, MB90467, MB90V460

Power supply voltage VCC (V)

Operation guarantee range of PLL

1 3 12 16

Internal clock f

CP (MHz)

Relationship between oscillating frequency and internal operating clock frequency

Internal clock fCP (MHz)

Multiplied-

by-4

34 8

Multiplied-

Oscillation clock f

Multiplied-

by-3

by-2

C (MHz)

Multiplied-

by-1

The AC ratings are measured for the following measurement reference voltages

Not multiplied

• Input signal waveform

Hysteresis Input Pin

0.8 VCC

0.2 VCC

Pin other than hystheresis input/MD input

0.7 V

0.3 VCC

• Output signal waveform

Output Pin

2.4 V

0.8 V

MB90460 Series

(2) Reset Input Timing

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Parameter Symbol Pin Condition

Reset input time t

RSTL RST 

Oscillation time of oscillator + 4 t

* : Oscillation time of oscillator is time that amplitude reached the 90%. In the crystal oscillator, the oscillation time

is between several ms to tens of ms. In FAR/ceramic oscillator, the oscillation time is between handreds µs to several ms. In the external clock, the oscillation time is 0 ms.

• In stop mode

tRSTL

RST

0.2 VCC 0.2 VCC

Value

Units Remarks

Min Max

4 t

CP  ns Under normal operation

 ms In stop mode

Internal operation clock

Internal reset

90% of amplitude

Oscillation time of oscillator

4 tCP

Oscillation setting time

Instruction execution

(3) Power-on Reset

Parameter Symbol Pin name Condition

MB90460 Series

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Min Max

Unit Remarks

Power supply rising time t Power supply cut-off time t

Note : V

CC must be kept lower than 0.2 V before power-on.

The above values are used for causing a power-on reset. Some registers in the device are initialized only upon a po wer-on reset. To initialize these registers, turn the power supply using the above values.

VCC

Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V or fewer per second, however, you can use the PLL clock.

R VCC

0.05 30 ms



OFF VCC 4  ms

2.7 V

0.2 V 0.2 V0.2 V

tOFF

Due to repeated operations

VCC

3.0 V VSS

RAM data Hold

It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower.

MB90460 Series

(4) UART0 to UART1

Parameter Symbol Pin name Condition

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Unit Remarks

Min Max

Serial clock cycle time t SCK ↓ → SOT delay time t

SCYC SCK0 to SCK1

SLOV

SCK0 to SCK1 SOT0 to SOT1

L = 80 pF + 1 TTL

8 t

CP  ns

−80 80 ns

for an output pin of

Valid SIN → SCK ↑ t

SCK ↑ → valid SIN hold time t Serial clock “H” pulse width t

IVSH

SHIX

SHSL SCK0 to SCK1

SCK0 to SCK1

SIN0 to SIN1

SCK0 to SCK1,

SIN0 to SIN1

internal shift clock mode

100  ns

60  ns

CP  ns

4 t

Serial clock “L” pulse width tSLSH SCK0 to SCK1 4 tCP  ns

SCK ↓ → SOT delay time t

Valid SIN → SCK ↑ t

SCK ↑ → valid SIN hold time t

SLOV

IVSH

SHIX

SCK0 to SCK1,

SOT0 to SOT1

SCK0 to SCK1,

SIN0 to SIN1

SCK0 to SCK1,

SIN0 to SIN1

L = 80 pF + 1 TTL

for an output pin of external shift clock mode

 150 ns

60  ns

Note : • These are AC ratings in the CLK synchronous mode.

• CL is the load capacitance value connected to pins while testing.

• t

CP is machine cycle time (unit : ns) .

• Internal shift clock mode

MB90460 Series

SCK

SOT

SIN

• External shift clock mode

SCK

SOT

tSCYC

2.4 V

0.8 V 0.8 V tSLOV

2.4 V

0.8 V

tIVSH tSHIX

0.8 V

0.2 VCC

tSLSH tSHSL

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC tSLOV

2.4 V

0.8 V

0.8 VCC

0.2 VCC

SIN

tIVSH tSHIX

0.8 V

0.2 VCC

0.8 VCC

0.2 VCC

MB90460 Series

(5) Resources Input Timing

Parameter Symbol Pin name Condition

Input pulse width

TIWH

tTIWL

IN0 to IN3,

SNI0 to SNI2

TIN0 to TIN1

PWI0 to PWI1

DTTI0, DTTI1

0.8 VCC

tTIWH tTIWL

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Unit Remarks

Min Max

 4 t

0.8 VCC

0.2 VCC

CP  ns

0.2 VCC

*1 : 0.7 VCC for PWI0 input pin *2 : 0.3 VCC for PWI0 Input pin

(6) Trigger Input Timimg

Parameter Symbol Pin name Condition

Input pulse width

TRGH

tTRGL

INT0 to INT7  5 tCP  ns

0.8 VCC 0.8 VCC

tTRGH tTRGL

CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Unit Remarks

Min Max

0.2 VCC 0.2 VCC

5. A/D Converter Electrical Characteristics

(3.0 V ≤ AVR − AVSS, VCC = AVCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Parameter

Sym-

bol

name

Min Typ Max

Resolution   10  bit

Value

Unit Remarks

MB90460 Series

Total error

   ±3.0 LSB For MB90F462, MB90462, MB90467    ±5.0 LSB For MB90V460

Non-linear error    ±2.5 LSB Differential

linearity

   ±1.9 LSB

error

Zero transition voltage

Full-scale transition voltage

SS −

AN0 to

AN7

1.5 LSB AVSS −

3.5 LSB AVR −

AN0 to

FST

AN7

3.5 LSB AVR −

6.5 LSB

AVSS +

0.5 LSB AVSS +

0.5 LSB AVR −

1.5 LSB AVR −

1.5 LSB

AVSS +

2.5 LSB AVSS +

4.5 LSB AVR +

0.5 LSB AVR +

1.5 LSB

mV For MB90F462, MB90462, MB90467

mV For MB90V460

mV For MB90F462, MB90462, MB90467

mV For MB90V460

Conversion time 6.125  1000 µs

Sampling period  2 µs

Actual value is specified as a sum of values specified in ADCR0 : CT1, CT0 and ADCR0 : ST1, ST0. Be sure that the setting value is greater than the min value

Actual value is specified in ADCR0 : ST1, ST0 bits. Be sure that the setting value is greater than the min value

Analog port input current

Analog input voltage

Reference voltage  AVR

AN0 to

AIN

AN7

AN0 to

AN7

10 µA

AVSS  AVR V

AVSS +

2.7

 AVCC V

 2.3 6 mA For MB90F462, MB90462, MB90467

Power supply current

AVCC

 2 5 mA For MB90V460  5 µA*  140 260 µA For MB90F462, MB90462, MB90467



AVR

AN0 to

AN7

 0.9 1.3 mA For MB90V460  5 µA*

 4LSB

Reference voltage supply current

Offset between channels

* : The current when the A/D converter is not operating or the CPU is in stop mode (for V

CC = AVCC = AVR = 5.0 V)

MB90460 Series

6. A/D Converter Glossary

Resolution : Analog changes that are identifiable with the A/D converter Linearity error : The deviation of the straight line connecting the zero transition point

(“00 0000 0000” ←→ “000000 0001”) with the full-scale transition point (“11 1111 1110” ←→ “11 1111 1111”) from actual conversion characteristics

Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the

theoretical value

Total error : The total error is defined as a difference between the actual value and the theoretical

value, which includes zero-transition error/full-scale transition error and linearity error.

Total error

3FF

3FE

3FD

004

Digital output

003

002

001

AVss

Total error for digital output N =

1 LSB = (Theoretical value)

Actual conversion value

Theoretical characteristics

0.5 LSB

Analog input

NT − {1 LSB × (N − 1) + 0.5 LSB}

1 LSB

AVR − AV

1024

[V]

VOT (Theoretical value) = AVSS + 0.5 LSB [V] V

FST (Theoretical value) = AVR − 1.5 LSB [V]

NT : Voltage at a transition of digital output from (N − 1) to N

1.5 LSB

{1 LSB × (N − 1) + 0.5 LSB}

(Measured value)

AVR

[LSB]

(Continued)

MB90460 Series

Differential linearity errorLinearity error

3FF

3FE

3FD

004

Digital output

003

002

001

Differential linearity error of digital output N

Actual conversion

value

{1 LSB × (N − 1) + VOT }

(measured value)

Actual conversion value

Theoretical characteristics

VOT (Measured value)

AVss AVR AVss AVR

Analog input Analog input

Linearity error of

digital output N

V (

FST

(Measured value)

NT − {1 LSB × (N − 1) + VOT}

1 LSB

N + 1) T − VNT

1 LSB

N + 1

Digital output

N − 1

N − 2

−1 [LSB]

Actual conversion value

(Measured value)

Actual conversion value

[LSB]

Theoretical characteristics

V (N + 1) T

(Measured value)

VNT

OT : Voltage at transition of digital output from “000H” to “001H”

FST : Voltage at transition of digital output from “3FEH” to “3FFH”

FST − VOT

1022

[V]1 LSB

MB90460 Series

7. Notes on Using A/D Converter

Select the output impedance value for the external circuit of analog input according to the following conditions. Output impedance values of the external circuit recommends about 5 kΩ or lower (sampling period = 2.0 µs

@machine clock of 16 MHz) . When capacitors are connected to external pins, the capacitance of sev eral thousand times the internal capacitor

value is recommended to minimized the eff ect of voltage distribution betw een the external capacitor and internal capacitor.

When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient.

• Analog input circuit model

Analog input

Comparator

MB90462, MB90F462, MB90467 R ≅ 2.6 KΩ, C ≅ 28 pF MB90V460 R ≅ 3.2 KΩ, C ≅ 30 pF

Note : Listed values must be considered as standards.

• Error The smaller the absolute value of | AVR − AVSS |, the greater the error would become relatively.

8. Flash Memory Program and Erase Performances

Parameter Condition

Min Typ Max

Sector erase time

Chip erase time  5  s

A = + 25 °C

CC = 3.0 V

 115s

Value

Unit Remarks

Excludes 00H programming prior erasure

Excludes 00 H programming prior erasure

Word (16 bit width) programming time

 16 3,600 µs

Erase/Program cycle  10,000 cycle

Excludes system-level overhead

EXAMPLE CHARACTERISTICS

■■■■

• Power Suppy Current of MB90462, MB90467

MB90460 Series

ICCH vs. VCC

TA = 25 °C, external clock input

ICCH (mA)

23456

VCC (V)

CC − VOH vs. IOH

FC = 16 [MHz]

FC = 12 [MHz]

FC = 10 [MHz]

FC = 8 [MHz]

FC = 4 [MHz]

FC = 2 [MHz]

TA = 25 °C, VCC = 4.5 V

CCS vs. VCC

TA = 25 °C, external clock input

20 18 16 14 12 10

ICCS (mA)

6 4 2 0

23456

CC (V)

OL vs. IOL

FC = 16 [MHz]

FC = 12 [MHz]

FC = 10 [MHz]

C = 8 [MHz]

FC = 4 [MHz]

FC = 2 [MHz]

TA = 25 °C, VCC = 4.5 V

1000

900 800 700 600 500 400

VCC −VOH (mV)

300 200 100

024681012

−

−−

IOH (mA)

−−

1000

900 800 700 600 500

VOL (V)

400 300 200 100

024681012

IOL (mA)

MB90460 Series

• Power Suppy Current of MB90F462

ICCH vs. VCC

TA = 25 °C, external clock input

CCS vs. VCC

TA = 25 °C, external clock input

ICCH (mA)

23456

VCC (V)

CC − VOH vs. IOH

FC = 16 [MHz]

FC = 12 [MHz]

FC = 10 [MHz]

FC = 8 [MHz]

FC = 4 [MHz]

FC = 2 [MHz]

TA = 25 °C, VCC = 4.5 V

1000

900 800 700 600 500 400

VCC - VOH (mV)

300 200 100

024681012

IOH (mA)

20 18

CC (V)

FC = 16 [MHz]

FC = 12 [MHz]

FC = 10 [MHz]

C = 8 [MHz]

FC = 4 [MHz]

FC = 2 [MHz]

16 14 12 10

ICCS (mA)

6 4 2 0

23456

OL vs. IOL

TA = 25 °C, VCC = 4.5 V

1000

900 800 700 600 500

VOL (V)

400 300 200 100

024681012

IOL (mA)

ORDERING INFORMATION

■■■■

Part number Package Remarks

MB90F462PFM MB90462PFM MB90467PFM

MB90F462PF MB90462PF MB90467PF

MB90460 Series

64-pin Plastic LQFP

(FPT-64P-M09)

64-pin Plastic QFP

(FPT-64P-M06)

MB90F462P-SH MB90462P-SH MB90467P-SH

64-pin Plastic SH-DIP

(DIP-64P-M01)

MB90460 Series

PACKAGE DIMENSIONS

■■■■

64-pin Plastic QFP

(FPT-64P-M06)

119

"A"

24.70±0.40(.972±.016)

20.00±0.20(.787±.008)

INDEX

1.00(.039)

0.10(.004)

0.42±0.08

(.017±.003)

Note : Pins width and pins thickness include plating thickness.

0.17±0.06

18.70±0.40

(.736±.016)

(.007±.002)

Details of "A" part

+0.35 –0.20

3.00

(Mounting height)

+.014 –.008

.118

0~8°

1.20±0.20

(.047±.008)

+0.15 –0.20

0.25

+.006 –.008

.010

(Stand off)

3351

14.00±0.20

(.551±.008)

0.20(.008)

2001 FUJITSU LIMITED F64013S-c-4-4

Dimensions in mm (inches)

MB90460 Series

64-pin Plastic LQFP

(FPT-64P-M09)

14.00±0.20(.551±.008)SQ

12.00±0.10(.472±.004)SQ

INDEX

116

0.65(.026)

0.32±0.05

(.013±.002)

Note : Pins width and pins thickness include plating thickness.

0.145±0.055

3348

0.13(.005)

(.0057±.0022)

0.10(.004)

"A"

Details of "A" part

+0.20 –0.10

1.50

+.008 –.004

.059

0.25(.010)

0~8°

0.50±0.20

(.020±.008)

0.60±0.15

(.024±.006)

(Mounting height)

0.10±0.10

(.004±.004)

(Stand off)

2001 FUJITSU LIMITED F64018S-c-2-4

Dimensions in mm (inches)

MB90460 Series

64-pin Plastic SH-DIP

(DIP-64P-M01)

INDEX-1

INDEX-2

+0.70 –0.20

4.95

+.028 –.008

.195

+0.20 –0.30

3.30

+.008

.130 –.012

1.378 .0543

+0.40 –0.20

+.016 –.008

58.00

1.778(.0700)

+0.22 –0.55

2.283

0.47±0.10

(.019±.004)

Note : Pins width and pins thickness include plating thickness.

+.009 –.022

17.00±0.25 (.669±.010)

+0.50 –0.19

0.70

+.020 –.007

.028

0.27±0.10

0.25(.010)

(.011±.004)

+0.50 –0

1.00 .039 –.0

+.020

19.05(.750) 0~15°

2001 FUJITSU LIMITED D64001S-c-4-5

Dimensions in mm (inches)

MB90460 Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS AMERICA, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608 Fax: +1-408-922-9179

http://www.fma.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS EUR OPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://www.fme.fujitsu.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220

http://www.fmal.fujitsu.com/

Korea

FUJITSU MICROELECTRONICS K OREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.

The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.

F0112

 FUJITSU LIMITED Printed in Japan

FUJITSU MB90V460, MB90F462, MB90462, MB90467 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual