FUJITSU MB90440G DATA SHEET
查询MB90440G供应商
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13716-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90440G Series
MB90443G/F443G/V440G
DESCRIPTION
■
The MB90440G series with FULL-CAN*2 and FLASH ROM is a line of general-purpose, Fujitsu 16-bit microcontrollers specially designed for automotive and industrial applications. Its main features are three on board CAN
Interfaces (generic type) , which conform to V2.0 Part A and Part B, supporting very flexible message buffering.
Thus, more functions than a normal full CAN approach is available.
While inheriting the AT architecture of the F
porates additional instructions for high-level languages, suppor ts extended addressing modes, and contains
enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation
instructions. In addition, the MB90440G series has as on-chip 32-bit accumulator, which enables processing of
long-word data.
The peripheral resources integrated in the MB90440G series include; an 8/10-bit A/D converter, UARTs (SCI) ,
I/O extended serial interface, 8/16-bit PPG timer, input/output timer (input capture (ICU) , output compare (OCU) ) .
2
*1 : F
MC stands for FUJITUS Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
*2 : Controller Area Network (CAN) is a license of Robert Bosch GmbH..
2MC*1
family, the instruction set for the F2MC-16LX CPU core incor-
PACKAGE
■
100-pin Plastic QFP
FPT-100P-M06
MB90440G Series
FEATURES
■
••••
Clock
Internal PLL clock multiplication circuit
Base oscillation divided into two or multiplied by one to four
Minimum execution time : 62.5 ns (4 MHz oscillation, PLL clock multiplication multiplier = 4, V
32 kHz subsystem clock
••••
Instruction set optimized for controller applications
Supported data types : bit, byte, word, and long-word types
Standard addressing modes : 23 types
Singed multiplication/division and extended RET1 instructions
32-bit accumulator enhancing high-precision operations
••••
Enhanced high level language (C) and multi-tasking support instructions
Use of a system stack pointer
Symmetrical instruction set and barrel shift instructions
••••
Program patch function (for two address pointers)
••••
Enhanced execution speed : 4 byte instruction queue
••••
Enhanced interrupt function : 8 priority levels programmable and 34 causes
CC = 5.0 V)
••••
Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI
••••
Internal ROM size and type
FLASH ROM : 128 Kbytes
Internal RAM size : 6 Kbyte and 14 Kbyte (evaluation chip)
••••
FLASH ROM
Supports automatic programming function, Embedded Algorithm*
Writing command/erase command/erase suspend and resume command
Algorithms completion flag
Hardwire reset vector to show the fixed boot code sector
Can be erased by each sector
Sector protection by external programming voltage
••••
Low-power consumption (stand-by) modes
Sleep mode (CPU operating clock stops)
Stop mode (Main oscillation stops)
CPU intermittent operation mode
Watch mode
Time-base timer mode
••••
General-purpose I/O ports : 81 ports
••••
Timers
2
OS)
Watchdog timer : 1 channel
8/16-bit PPG timer : 8/16-bit × 4 channels
16-bit reload timer : 2 channels
* : Embedded Algorithm is a trademark of Advanced Micro Devices, Inc.
2
(Continued)
MB90440G Series
(Continued)
••••
16-bit I/O timers
16-bit free-run timers : 1 channel
16-bit input capture : 8 channels
16-bit output compare : 4 channels
••••
Extended I/O serial interfaces : 1 channel
••••
UART0
Full-duplex, double-buffered (8 bit)
Can be used for clock synchronous and asynchronous transfer (with start/stop bit)
••••
UART1 (SCI)
Full-duplex, double-buffered (8 bit)
Can be used for clock synchronous and asynchronous serial transfer (extended I/O serial)
••••
External interrupt inputs : 8 channels
Extended intelligent I/O service (EI
••••
Delayed interrupt generation module : interrupt request for task switching
••••
8/10 bit A/D converter : 8 channels
2
OS) is started by external input and external interrupt generation module
8/10-bit resolution selectable
Can be started by external trigger input
Conversion time : 6.12 µs
••••
FULL-CAN interface
3 channels
Conform to V2.0 Part A and Part B
Supports very flexible message buffering (mail-box and FIFO buffering can be mixed)
••••
External bus interface : maximum 16 Mbyte address space
3
MB90440G Series
PRODUCT LINEUP
■
The following table provides a quick outlook of the MB90440G Series
Part number
Parameter
CPU F
System clock
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, 1/2 when PLL stops)
Minimum instruction execution time : 62.5 ns (4 MHz osc. PLL ×4)
MB90443G
(under development)
MB90F443G MB90V440G
2
MC-16LX CPU
ROM size
Mask ROM
128 Kbytes
Flash memory
128 Kbytes
External
RAM size 6 Kbytes 6 Kbytes 14 Kbytes
Operating
voltage range
*1
5 V ± 10%
Temperature range −40 °C to +105 °C
Package QFP100 PGA-256
Voltage dedicated for
emulator
*2
No
Full duplex double buffer
UART0
Supports clock asynchronous/synchronous (with start/stop bits) transfer
Baud rate : 4808/5208/9615/10417/19230/38460/62500/500000 bps (asynchronous)
500 K/1 M/2 Mbps (synchronous) at System clock = 16 MHz
Full duplex double buffer
UART1
(SCI)
Asynchronized (start/stop bits synchronized) and CLK-synchronous communication
Baud rate : 601 bps to 250 kbps (asynchronous)
31.25 kbps to 2 Mbps (synchronous)
Transfer can be started from MSB or LSB
Serial IO
Supports internal clock synchronized transfer and external clock synchronized transfer
Supports positive-edge and negative-edge clock synchronization
Baud rate : 31.25 K/62.5 K/125 K/500 K/1 M/2 Mbps at System clock = 16 MHz
8/10 bit
A/D Converter
16-bit Reload Timer
(2 channels)
10-bit or 8-bit resolution
8 input channels
Conversion time : 6.12 µs (per one channel)
Operation clock frequency : fsys/2
1
, fsys/23, fsys/25 (fsys = System clock frequency)
Supports External Event Count function
16-bit
I/O Timer
16-bit
Output Compare
(4 channels)
4
Signals an interrupt during overflow
Supports Timer Clear during a match with Output Compare (Channel 0)
Operation clock freq. : fsys/2
2
, fsys/24, fsys/26, fsys/28 (fsys = System clock freq.)
Signals an interrupt during a match with 16-bit I/O Timer
Four 16-bit compare registers
A pair of compare registers can be used to generate an output signal
(Continued)
(Continued)
Part number
Parameter
16-bit
Input Capture
(8 channels)
8/16-bit
Programmable Pulse
Generator
(4 channels)
CAN Interface
3 channels :
MB90440G Series
MB90443G
(under development)
Rising edge, falling edge or rising & falling edge sensitive
Four 16-bit capture registers
Signals an interrupt upon external event
Supports 8-bit and 16-bit operation modes
Eight 8-bit reload counters
Eight 8-bit reload registers for L pulse width
Eight 8-bit reload registers for H pulse width
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler plus 8-bit reload counter
4 output pins
Operation clock frequency. : fsys, fsys/2
(fsys = System clock frequency, fosc = Oscillation clock frequency)
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Supports prioritized 16 message buffers for data and ID
Flexible configuration of acceptance filtering :
Full bit compare / Full bit mask / Two partial bit masks
Supports up to 1 Mbps
MB90F443G MB90V440G
1
, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
External Interrupt
(8 channels)
External bus interface
I/O Ports
32 kHz Subclock Sub-clock for low power operation
Flash
Memory
*1 : V alues with conditions such as the operating frequency (See section “ ELECTRICAL CHARACTERISTICS”) .
*2 : DIP switch S2 when using emulation pad MB2145-507.
The details are referred to hardware manual of MB2145-507.
Can be programmed edge detection or level detection
The external access used selective 8-bit bus or 16-bit bus is available.
(External bus mode)
Virtually all external pins can be used as general purpose I/O
All push-pull outputs and schmitt trigger inputs
Bit-wise programmable as input/output or peripheral signal
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
Data retention time : 10 years
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
TM
5
MB90440G Series
PIN ASSIGNMENT
■
(TOP VIEW)
P20/A16
P21/A17
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23
P30/ALE
P31/RD
V
P32/WRL/WR
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SOT0
P41/SCK0
P42/SIN0
P43/SIN1
P44/SCK1
V
P45/SOT1
P46/SOT2
P47/SCK2
P50/SIN2
P51/INT4
P52/INT5
CC
SS
P17/AD15
P16/AD14
P15/AD13
P14/AD12
P13/AD11
P12/AD10
P11/AD09
P10/AD08
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
99989796959493929190898887868584838281
1
100
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
C
28
29
30
31323334353637383940414243444546474849
CC
P01/AD01
P00/AD00
V
X1X0V
SS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
X0A
X1A
PA0/INT3
RST
P97/RX1
P96/TX1
P95/INT2/RX0
P94/TX0
P93/RX2
P92/TX2
P91/INT1
P90/INT0
P87/TOT1
P87/TIN1
P85/OUT1
P84/OUT0
P83/PPG3
P82/PPG2
P81/PPG1
P80/PPG0
P77/OUT3/IN7
P76/OUT2/IN6
P75/IN5
P74/IN4
P73/IN3
P72/IN2
P71/IN1
P70/IN0
N.C.
MD2
P53/INT6
P54/INT7
P55/ADTG
CC
AV
AVR-
AVR+
SS
AV
P60/AN0
P61/AN1
SS
V
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
P56/TIN0
MD0
MD1
P57/TOT0
(FPT-100P-M06)
6
MB90440G Series
PIN DESCRIPTION
■
Pin No. Pin name Circuit type Function
82
83
X0
X1
A
(Oscillation)
High speed oscillator input pins
80
79
77 RST
52 N.C. not connected
85 to 92
93 to 100
1 to 8
9
X0A
X1A
P00 to P07
AD00 to AD07
P10 to P17
AD08 to AD15
P20 to P27
A16 to A23
P30
ALE
A
(Oscillation)
B External reset request input
H
H
H
H
Low speed oscillator input pins
General I/O port with programmable pullup. This function is enabled in the single-chip mode.
I/O pins for 8 lower bits of the external address/data bus. This function is enabled when the external bus is enabled.
General I/O port with programmable pullup. This function is enabled in the single-chip mode.
I/O pins for 8 higher bits of the external address/data bus. This function is enabled when the external bus is enabled.
General I/O port with programmable pullup. This function is enabled in the single-chip mode.
I/O pins of 8 bits for A16 to A23 ot the external address bus. This
function is enabled when the external bus is enabled.
General I/O port with programmable pullup. This function is enabled in the single-chip mode.
Address latch enable output pin. This function is enabled when the
external bus is enabled.
10
12
13
P31
RD
P32
WRL
WR
P33
WRH
General I/O port with programmable pullup. This function is en-
H
H
H
abled in the single-chip mode.
Read strobe output pin for the data bus. This function is enabled
when the external bus is enabled.
General I/O port with programmable pullup. This function is en-
abled in the single-chip mode or when the WR
disabled.
Write strobe output pin for the data bus. This function is enabled
when the external bus is in enable mode and the WR
put is enabled. WRL
bits of the data bus in 16-bit access while WR
strobe output pin for 8 bits of the data bus in 8-bit access.
General I/O port with programmable pullup. This function is enabled in the single-chip mode or external bus 8-bit mode or when
W
RH pin output is disabled.
Write strobe output pin for the 8 higher bits of the data bus. This
function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the WRH
is enabled.
is used as a write-strobe output pin for 8 lower
/WRL pin output is
/WRL pin out-
is used as a write-
output pin
(Continued)
7
MB90440G Series
Pin No. Pin name Circuit type Function
14
15
16
17
18
P34
HRQ
P35
HAK
P36
RDY
P37
CLK
P40
SOT0
General I/O port with programmable pullup. This function is enabled
H
H
H
H
G
in the single-chip mode or when hold function is disabled.
Hold request input pin. This function is enabled when the external
bus is in enable mode and the hold function is enabled.
General I/O port with programmable pullup. This function is enabled
in the single-chip mode or when hold function is disabled.
Hold acknowledge output pin. This function is enabled when the ex-
ternal bus is in enable mode and the hold function is enabled.
General I/O port with programmable pullup. This function is enabled
in the single-chip mode or when the external ready function is disabled.
Ready input pin. This function is enabled when the external bus is
in enable mode and the external ready function is enabled.
General I/O port with programmable pullup. This function is enabled
in the single-chip mode or when CLK output is disabled.
CLK output pin. This function is enabled when the external bus is in
enable mode and CLK output is enabled.
General I/O port. This function is enabled when serial data output
of UART0 is disabled.
Serial data output pin for UART0. This function is enabled when
UART0 enables serial data output.
19
20
21
22
24
P41
SCK0
P42
SIN0
P43
SIN1
P44
SCK1
P45
SOT1
General I/O port. This function is enabled when clock output of
G
G
G
G
G
UART0 is disabled.
Serial clock I/O pin for UART0. This function is enabled when
UART0 enables serial clock output.
General I/O port. This function is always enabled.
Serial data input pin for UART0. Set the corresponding DDR regis-
ter to input if this function is used.
General I/O port. This function is always enabled.
Serial data input pin for UART1. Set the corresponding DDR regis-
ter to input if this function is used.
General I/O port. This function is enabled when serial clock output
of UART1 is disabled.
Serial clock I/O pin for UART1. This function is enabled when
UART1 enables serial clock output.
General I/O port. This function is enabled when serial data output
of UART1 is disabled.
Serial data output pin for UART1. This function is enabled when
UART1 enables serial data output.
(Continued)
8
MB90440G Series
Pin No. Pin name Circuit type Function
25
26
28
29 to 32
33
38 to 41
43 to 46
P46
SOT2
P47
SCK2
P50
SIN2
P51 to P54
INT4 to INT7
P55
ADTG
P60 to P63
AN0 to AN3
P64 to P67
AN4 to AN7
General I/O port. This function is enabled when the extended serial
I/O interface disables serial data output.
G
G
D
D
D
E
E
Serial data output pin for the extended serial I/O interface. This
function is enabled when the extended serial I/O interface enables
serial data output.
General I/O port. This function is enabled when the extended serial
I/O interface disables serial clock output.
Serial clock I/O pin for the extended serial I/O interface. This function is enabled when the extended serial I/O interface enables serial clock output.
General I/O port. This function is always enabled.
Serial data input pin for the extended serial I/O interface. Set the
corresponidng DDR register to input if this function is used.
General I/O ports. This function is always enabled.
External interrupt request input pins for INT4 to INT7. Set the cor-
responding DDR register to input if this function is used.
General I/O port. This function is always enabled.
External trigger input pin for the 8/10-bit A/D converter. Set the cor-
responding DDR register to input if this function is used.
General I/O ports. The function is enabled when the analog input
enable register specifies port.
Analog input pins for the 8/10-bit A/D converter. This function is en-
abled when the analog input enable register specifies A/D.
General I/O ports. The function is enabled when the analog input
enable register specifies port.
Analog input pins for the 8/10-bit A/D converter. This function is en-
abled when the analog input enable register specifies A/D.
47
48
53 to 58
P56
TIN0
P57
TOT0
P70 to P75
IN0 to IN5
General I/O port. This function is always enabled.
D
D
D
Event input pin for the 16-bit reload timers 0. Set the corresponding
DDR register to input if this function is used.
General I/O port. This function is enabled when the 16-bit reload
timers 0 disables output.
Output pin for the 16-bit reload timers 0. This function is enabled
when the 16-bit reload timers 0 enables output.
General I/O ports. This function is always enabled.
Trigger input pins for input captures ICU0 to ICU5. Set the corre-
sponding DDR register to input if this function is used.
(Continued)
9
MB90440G Series
Pin No. Pin name Circuit type Function
59 to 60
61 to 64
65 to 66
67
68
P76 to P77
OUT2 to OUT3
IN6 to IN7
P80 to P83
PPG0 to PPG3
P84 to P85
OUT0 to OUT1
P86
TIN1
P87
TOT1
General I/O ports. This function is enabled when the OCU disables
output.
Event output pins for output compares OCU2 and OCU3. This
D
D
D
D
D
function is enabled when the OCU enables output.
Trigger input pins for input captures ICU6 and ICU7. Set the corre-
sponiding DDR register to input and prohibit the OCU output if this
function is used.
General I/O ports. This function is enabled when 8/16-bit PPG timer
disables waveform output.
Output pins for 8/16-bit PPG timer. This function is enabled when
8/16-bit PPG timer enables waveform output.
General I/O ports. This function is enabled when the OCU disables
output.
Event output pins for output compares OCU0 and OCU1. This function is enabled when the OCU enables output.
General I/O port. This function is always enabled.
Input pin for the 16-bit reload timers 1. Set the corresponding DDR
register to input if this function is used.
General I/O port. This function is enabled when the 16-bit reload
timers 0 disables output.
Output pin for the 16-bit reload timers 1. This function is enabled
when the reload timers 1 enables output.
69 to 70
71
72
73
74
P90 to P91
INT0 to INT1
P92
TX2
P93
RX2
P94
TX0
P95
INT2
RX0
General I/O ports. This function is always enabled.
D
D
D
D
D
External interrupt request input pins for INT0 to INT3. Set the corresponding DDR register to input if this function is used.
General I/O port. This function is enabled when CAN2 disables output.
TX output pin for CAN2. This function is enabled when CAN2 enables output.
General I/O port. This function is always enabled.
RX input pin for CAN2 interface. When the CAN function is used,
output from the other functions must be stopped.
General I/O port. This function is enabled when CAN0 disables out-
put.
TX output pin for CAN0. This function is enabled when CAN0 en-
ables output.
General I/O port. This function is always enabled.
External interrupt request input pin for INT2. Set the corresponding
DDR register to input if this function is used.
RX input pin for CAN0 interface. When the CAN function is used,
output from the other functions must be stopped.
(Continued)
10
MB90440G Series
(Continued)
Pin No. Pin name Circuit type Function
General I/O port. This function is enabled when CAN1 disables output.
TX output pin for CAN1. This function is enabled when CAN1 enables output.
General I/O port. This function is always enabled.
RX input pin for CAN1 interface. When the CAN function is used,
output from the other functions must be stopped.
General I/O port. This function is always enabled.
External interrupt request input pin for INT2. Set the corresponding
DDR register to input if this function is used.
75
76
78
P96
D
TX1
P97
D
RX1
PA0
D
INT3
Power supply pin for the A/D Converter. This power supply must be
34 AV
37 AV
CC Power supply
SS Power supply Dedicated ground pin for the A/D Converter
turned on or off while a voltage higher than or equal to AVCC is applied to V
CC.
External reference voltage pin for the A/D Converter. This power
35 AVRH Power supply
supply must be turned on or off while a voltage higher than or equal
to AVRH is applied to AV
CC.
36 AVRL Power supply External reference voltage pin for the A/D Converter
49
to 50
MD0
to MD1
C
Input pins for specifying the operating mode. The pins must be directly connected to V
CC or Vss.
51 MD2 F
27 C
23, 84 V
11, 42
81
INPUT LEVELS
■
CC Power supply Voltage (5.0 V) input pin
V
SS Power supply Voltage (0.0 V) input pin
Input pin for specifying the operating mode. The pin must be directly
connected to V
CC or Vss.
This is the power supply stabilization capacitor pin. It should be connected externally to an 0.1 µF ceramic capacitor.
The input level of ports P00 to P37 can be selected to be either TTL- or CMOS - level. The initial setting is TTL
- level. These settings are global for all P00 to P37, it is not possible to set different levels to each port.
The input level of ports P40 to PA0 can be selected to be either CMOS- or AUTOMOTIVE - level. The initial
setting is CMOS - level. This settings can be done for each port individually.
11
MB90440G Series
I/O CIRCUIT TYPE
■
Circuit
type
A
B
X1, X1A
X0,X0A
Circuit Remarks
• Oscillation feedback resistor :
1 MΩ approx. (High speed oscillator)
10MΩ approx. (Low speed oscillator)
osillation feedback
resistor
Standby control signal
• CMOS hysteresis input .
Pull-up resistor : 50 kΩ approx.
R (pull-up)
R
HYS
• CMOS hysteresis input
C
R
HYS
• CMOS level output
• CMOS hysteresis input
CC
V
P-ch
N-ch
• Automotive hysteresis input
(See “ INPUT LEVELS”.)
D
R
R
CMOS HYS
AUTOM. HYS
(Continued)
12
MB90440G Series
Circuit
type
E
Circuit Remarks
• CMOS level output
CC
V
P-ch
• CMOS hysteresis input
• Automotive hysteresis input
(See “ INPUT LEVELS”.)
• Analog input
N-ch
P-ch
Analog input
N-ch
R
R
CMOS HYS
AUTOM. HYS
• CMOS hysteresis input
R
CMOS HYS
• Pull-down resistor : 50 kΩ approx.
(except FLASH devices)
F
R (pull-down)
• CMOS level output
• CMOS hysteresis input
CC
V
P-ch
• Automotive hysteresis input
(See “ INPUT LEVELS”.)
• TTL input (FLASH devices in flash write
mode only)
N-ch
G
R
R
R
T
CMOS HYS
AUTOM. HYS
TTL
(Continued)
13
MB90440G Series
(Continued)
Circuit
type
Circuit Remarks
VCC
• CMOS level output
• CMOS hysteresis input
• TTL hysteresis input
CNTL
CC
V
P-ch
(See “ INPUT LEVELS”.)
• Programmable pullup resistor :
50 kΩ approx.
H
R
R
N-ch
CMOS HYS
T
TTL
14
MB90440G Series
HANDLING DEVICES
■
1. Preventing Latch-up
CMOS IC chips may suffer latch-up under the following conditions :
(1) A voltage higher than V
(2) A voltage higher than the rated voltage is applied to between V
(3) The AV
CC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
Always take sufficient precautions in using semiconductor devices to avoid this possibility.
Also be careful not to let the analog power-supply voltage (AV
(V
CC) when the analog system power-supply is turned on and off.
2. Handling Unused Input Pins
Do not leave unused input pins open, as doing so may cause misoperation of the device or latch-up leading to
permanent damage. Unused input pins should be pulled up or pulled down through at least 2 kΩ resistance.
Unused I/O pins may be left open in output state, but if such pins are in input state they should be handled in
the same way as input pins.
3. Use of the External Clock
To use the external clock, drive only the X0 pin and leave the X1 pin open.
A diagram of how to use an external clock is shown below.
CC or lower than VSS is applied to an input or output pin.
CC and Vss.
CC, A VRH) exceed the digital po wer-supply voltage
MB90440G Series
X0
X1open
4. Precautions for when not using a Sub Clock Signal
If the X0A and X1A pins are not connected to an oscillator, apply pull-do wn treatment to the X0A pin and leave
the X1A pin open.
5. Power Supply Pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to
avoid abnormal operations including latch-up. However, connect the pins exter nal power and ground lines to
lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in
the ground level, and to conform to the total current rating.
Make sure to connect V
It is recommended to provide a bypass capacitor of around 0.1 µF between V
CC and VSS pins via lowest impedance to power lines.
VCC
VSS
VSS
VCC
VCC
MB90440G
Series
VSS
VCC
CC and VSS pins near the device.
VSS
VSS
VCC
15
MB90440G Series
6. Pull-up/down resistors
The MB90440G Series does not support inter nal pull-up/down resistors (except pull-up resistors of port 0 to
port 3) . Use external components needed.
7. Crystal Oscillator Circuit
Noises around X0 or X1 pins may cause abnormal operations. Make sure to pro vide bypass capacitors via the
shortest distances from X0 and X1 pins, cr ystal oscillator (or ceramic resonator) and ground lines, and make
sure, to the utmost effort, that lines of oscillation circuits do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
8. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D and D/A converters power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to
AN7) after turning on the digital power supply (V
Turn off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that A VRH does not exceed AV
able) .
CC (turning on/off the analog and digital power supplies simultaneously is accept-
9. Connection of Unused Pins of A/D Converter
Connect unused pins of A/D and D/A converters to AVCC = VCC, AVSS = AVRH = VSS.
CC) .
10. N.C. Pin
The N.C. (internally connected) pin must be opened for use.
11. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
µs or more (0.2 V to 2.7 V) .
12. Initialization
In the device, there are internal registers which are initialized only by a pow er-on reset. T o initialize these registers,
please turn on the power again.
13. Using REALOS
The use of (EI2OS) is not possible with the REALOS real time operation system.
14. Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected in the microcontroller , it may attempt to continue the operation using the freerunning frequency of the automatic oscillating circuit in the PLL circuitly even if the oscillator is out of place or
the clock input is stopped. Performance of this operation, however, cannot be guaranteed.
16
BLOCK DIAGRAM
■
X0, X1
X0A, X1A
RST
Clock
Controller
RAM 6 K
MB90440G Series
F2MC 16LX
CPU
16 bit
I/O Timer
SOT0
SCK0
SIN0
SOT1
SCK1
SIN1
SCK2
SOT2
SIN2
AV
CC
AVSS
AN0 to AN7
AVRH
AVRL
ADTG
ROM
128 K
Prescaler
UART0
Prescaler
UART1
(SCI)
Prescaler
Serial I/O
10-bit ADC
8 ch
2
F MC-16 Bus
16 bit Input
Capture
8 ch
16 bit Output
Compare
4 ch
8/16-bit
PPG Timer
4 ch
CAN
Controller 3 ch
16-bit Reload
Timer 2 ch
External
Bus
Interface
IN0 to IN5
IN6/OUT2,
IN7/OUT3
OUT0, OUT1
PPG0 to PPG3
RX0 to RX2
TX0 to TX2
TIN0, TIN1
TOT0, T O T1
AD00 to AD15
A16 to A23
ALE
RD
WRL/WR
WRH
HRQ
HAK
RDY
CLK
External
Interrupt
Circuit 8 ch
INT0 to INT7
17
MB90440G Series
MEMORY MAP
■
MB90V440G MB90F443G/
MB90443G (under development)
FFFFFF
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
00FFFFH
004000H
003FFFH
003900H
0038FFH
001FF5H
001FF0H
000100H
0000BFH
000000H
H
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
External
Access Memory
ROM (Image of
FF bank)
Peripheral
ROM correction
RAM 14 K
External
Access Memory
Peripheral
FFFFFF
FF0000H
FEFFFFH
FE0000H
00FFFFH
004000H
003FFFH
003900H
002000H
0018FFH
000100H
0000BFH
000000H
H
ROM (FF bank)
ROM (FE bank)
External
Access Memory
ROM (Image of
FF bank)
Peripheral
External
Access Memory
RAM 6 K
External
Access Memory
Peripheral
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits are the same address, the table in ROM can be referenced
without using the far specification in the pointer declaration.
For example, an attempt to access 00C000
H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 48 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF4000
FFFFFF
of FF4000
H is visible only in bank FF. Thus, it is recommended that the ROM data table be stored in the area
H and FFFFFFH .
H and FFFFFFH is visible in bank 00, while the image between FF4000H and
18
I/O MAP
■
MB90440G Series
Address Register Abbreviation
00
H Port 0 data register PDR0 R/W Port 0 XXXXXXXXB
01H Port 1 data register PDR1 R/W Port 1 XXXXXXXXB
02H Port 2 data register PDR2 R/W Port 2 XXXXXXXXB
03H Port 3 data register PDR3 R/W Port 3 XXXXXXXXB
04H Port 4 data register PDR4 R/W Port 4 XXXXXXXXB
05H Port 5 data register PDR5 R/W Port 5 XXXXXXXXB
06H Port 6 data register PDR6 R/W Port 6 XXXXXXXXB
07H Port 7 data register PDR7 R/W Port 7 XXXXXXXXB
08H Port 8 data register PDR8 R/W Port 8 XXXXXXXXB
09H Port 9 data register PDR9 R/W Port 9 XXXXXXXXB
0AH Port A data register PDRA R/W Port A _______XB
0BH Port input levels select register PILR R/W Ports 00000000B
0CH CAN2 RX/TX pin switching register CANSWR R/W CAN1/2 ______00B
0DH to 0FH Reserved
10
H Port 0 direction register DDR0 R/W Port 0 00000000B
11H Port 1 direction register DDR1 R/W Port 1 00000000B
Read/
Write
Resource
name
Initial value
12H Port 2 direction register DDR2 R/W Port 2 00000000B
13H Port 3 direction register DDR3 R/W Port 3 00000000B
14H Port 4 direction register DDR4 R/W Port 4 00000000B
15H Port 5 direction register DDR5 R/W Port 5 00000000B
16H Port 6 direction register DDR6 R/W Port 6 00000000B
17H Port 7 direction register DDR7 R/W Port 7 00000000B
18H Port 8 direction register DDR8 R/W Port 8 00000000B
19H Port 9 direction register DDR9 R/W Port 9 00000000B
1AH Port A direction register DDRA R/W Port A _______0B
1BH Analog input enable register ADER R/W Port 6, A/D 11111111B
1CH Port 0 pullup control register PUCR0 R/W Port 0 00000000B
1DH Port 1 pullup control register PUCR1 R/W Port 1 00000000B
1EH Port 2 pullup control register PUCR2 R/W Port 2 00000000B
1FH Port 3 pullup control register PUCR3 R/W Port 3 00000000B
20H Serial mode control register 0 UMC0 R/W
21H Serial status register 0 USR0 R/W 00010000B
UART0
22H Serial input/output data register 0 UIDR0/UODR0 R/W XXXXXXXXB
23H Rate and data register 0 URD0 R/W 0000000XB
00000100B
(Continued)
19
Loading...