FUJITSU MB90435 DATA SHEET

查询MB90435供应商
FUJITSU SEMICONDUCTOR
DATA SHEET
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90435 Series
DESCRIPTION
■■■■
The MB90435 series with FLASH ROM is specially designed for industrial applications.
2
The instruction set by F instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instruc­tions, and enhanced bit manipulation instructions.The micro controller has a 32-bit accumulator for processing long word data.
MC-16LX CPU core inherits an AT architecture of the F2MC* family with additional
DS07-13727-1E
The MB90435 series has peripheral resources of 8/10-bit A/D converters, UART (SCI) , extended I/O serial interfaces, 8/16-bit timer, I/O timer (input capture (ICU) , output compare (OCU) ) .
2
* : F
MC stands for FUJITSU Flexible Microcontroller.
FEATURES
■■■■
•Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from : divided-b y-2 of oscillation or one to f our times the oscillation Minimum instruction ex ecution time : 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock,
CC of 5.0 V)
V
Subsystem Clock : 32 kHz
PACKAGES
■■■■
100-pin Plastic QFP 100-pin Plastic LQFP
(Continued)
(FPT-100P-M06) (FPT-100P-M05)
MB90435 Series
• Instruction set to optimize controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C language) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed : 4-byte Instruction queue
• Enhanced interrupt function : 8 levels, 34 factors
• Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI
• Embedded ROM size and types Mask ROM : 64 Kbytes / 128 Kbytes / 256 Kbytes Flash ROM : 128 Kbytes/256 Kbytes Embedded RAM size : 2 Kbytes/4 Kbytes/6 Kbytes/8 Kbytes (evaluation chip)
•Flash ROM Supports automatic programming, Embedded Algorithm TM* Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory Erase can be performed on each block Block protection with external programming voltage
• Low-power consumption (stand-by) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) CPU intermittent operation mode Clock mode Hardware stand-by mode
•Process
0.5 µm CMOS technology
• I/O port General-purpose I/O ports : 81 ports
•Timer Watchdog timer : 1 channel 8/16-bit PPG timer : 8/16-bit × 4 channels 16-bit re-load timer : 2 channels
• 16-bit I/O timer 16-bit free-run timer : 1 channel Input capture : 8 channels Output compare : 4 channels
• Extended I/O serial interface : 1 channel
•UART 0 With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used.
2
OS)
(Continued)
2
(Continued)
•UART 1 With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized serial (extended I/O serial) can be used.
• External interrupt circuit (8 channels) A module for starting an extended intelligent I/O service (EI is triggered by an external input.
• Delayed interrupt generation module Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels) 8/10-bit resolution can be selectively used. Starting by an external trigger input. Conversion time : 26.3 µs
• External bus interface : Maximum address space 16 Mbytes
• Package: QFP-100, LQFP-100
* : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
2
OS) and generating an external interrupt which
MB90435 Series
3
MB90435 Series
PRODUCT LINEUP
■■■■
Features MB90F438L (S) /F439 (S)
CPU F System clock
ROM
RAM
Clocks
Flash memory MB90F438L(S) : 128 Kbytes MB90F439(S) : 256 Kbytes
MB90F438L(S) : 4 Kbytes MB90F439(S) : 6 Kbytes
MB90F438L/F439 : Two clocks system MB90F438LS/F439S : One clock system
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, 1/2 when PLL stop)
Minimum instruction exection time : 62.5 ns (4 MHz osc. PLL × 4)
Mask ROM : MB90437L(S): 64 Kbytes MB90438L(S): 128 Kbytes MB90439(S): 256 Kbytes
MB90437L(S): 2 Kbytes MB90438L(S): 4 Kbytes MB90439(S): 6 Kbytes
MB90437L/438L/439 : Two clocks system MB90437LS/438LS/439S : One clock system
Operating voltage range
MB90437L (S) *
/438L (S) /439 (S)
2
MC-16LX CPU
*5
1
MB90V540G
External
8 Kbytes
Two clocks system*
Temperature range −40 °C to 105 °C Package QFP100, LQFP100 PGA-256 Emulator-specify
power supply
*3
None
Full duplex double buffer
UART0
Support asynchronous/synchronous (with start/stop bit) transfer Baud rate : 4808/5208/9615/10417/19230/38460/62500/500000 bps (asynchronous)
500 K/1 M/2 Mbps (synchronous) at System clock = 16 MHz
Full duplex double buffer UART1 (SCI)
Asynchronous (start-stop synchronized) and CLK-synchronous communication
Baud rate : 1202/2404/4808/9615/19230/31250/38460/62500 bps (asynchronous)
62.5 K/125 K/250 K/500 K/1 M/2 Mbps (synchronous) at 6, 8, 10, 12, 16 MHz
Transfer can be started from MSB or LSB Serial I/O
Supports internal clock synchronized transfer and external clock synchronized transfer
Supports positive-edge and nagative-edge clock synchronization
Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock = 16 MHz
10-bit or 8-bit resolution A/D Converter
8 input channels
Conversion time : 26.3 µs (per one channel)
2
(Continued)
4
MB90435 Series
(Continued)
Features MB90F438L (S) /F439 (S)
16-bit Reload Timer (2 channels)
16-bit I/O Timer
16-bit Output Compare (4 channels)
16-bit Input Capture (8 channels)
Operation clock frequency : fsys/2 Supports External Event Count function Signals an interrupt when overflow
Supports Timer Clear when a match with Output Compare (Channel 0) Operation clock freq. : fsys/2
Signals an interrupt when a match with 16-bit I/O Timer Four 16-bit compare registers A pair of compare registers can be used to generate an output signal
Rising edge, falling edge or rising & falling edge sensitive Four 16-bit Capture registers Signals an interrupt upon external event
MB90437L (S) *
/438L (S) /439 (S)
1
, fsys/23, fsys/25 (fsys = System clock frequency)
2
, fsys/24, fsys/26, fsys/28 (fsys = System clock freq.)
Supports 8-bit and 16-bit operation modes Eight 8-bit reload counters
8/16-bit Programmable Pulse Generator (4 channels)
Eight 8-bit reload registers for L pulse width Eight 8-bit reload registers for H pulse width A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter 4 output pins Operation clock freq. : fsys, fsys/2
1
, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
(fsys = System clock frequency, fosc = Oscillation clock frequency) 32 kHz Sub-clock Sub-clock for low power operation External Interrupt
(8 channels) External bus
interface
Can be programmed edge sensitive or level sensitive
External access using the selectable 8-bit or 16-bit bus is enabled
(external bus mode.)
Virtually all external pins can be used as general purpose I/O I/O Ports
All push-pull outputs and schmitt trigger inputs
Bit-wise programmable as input/output or peripheral signal
Supports automatic programming, Embeded Algorithm TM
Write/Erase/Erase-Suspend/Erase-Resume commands
A flag indicating completion of the algorithm Flash Memory
Number of erase cycles : 10,000 times
Data retention time : 10 years
Boot block configuration
Erase can be performed on each block
Block protection by externally programmed voltage
*1 : Under development *2 : If the one clock system is used, equip X0A and X1A with clocks from the tool side. *3 : It is setting of DIP switch S2 when Emulator pod (MB2145-507) is used.Please ref er to the MB2145-507 hardware
manual (2.7 Emulator-specific Power Pin) about details. *4 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. *5 : OPERATING VOLTAGE RANGE
Products Operation guarantee range
MB90F439 (S) /439 (S) /V540G 4.5 V to 5.5 V
1
MB90V540G
*4
MB90F438L (S) /437L (S) /438L (S) 3.5 V to 5.5 V
5
MB90435 Series
PIN ASSIGNMENT
■■■■
(TOP VIEW)
P20/A16 P21/A17 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23
P30/ALE
P31/RD
V
SS
P32/WRL/WR
P33/WRH
P34/HRQ
P35/HAK P36/RDY
P37/CLK P40/SOT0 P41/SCK0
P42/SIN0 P43/SIN1
P44/SCK1
V
CC
P45/SOT1 P46/SOT2 P47/SCK2
P50/SIN2 P51/INT4 P52/INT5
P17/AD15
P16/AD14
P15/AD13
P14/AD12
P13/AD11
P12/AD10
P11/AD09
P10/AD08
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
99989796959493929190898887868584838281
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
C
28 29 30
31323334353637383940414243444546474849
CC
P01/AD01
P00/AD00
V
X1X0V
SS
50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
X0A X1A PA0 RST P97 P96 P95 P94 P93/INT3 P92/INT2 P91/INT1 P90/INT0 P87/TOT1 P86/TIN1 P85/OUT1 P84/OUT0 P83/PPG3 P82/PPG2 P81/PPG1 P80/PPG0 P77/OUT3/IN7 P76/OUT2/IN6 P75/IN5 P74/IN4 P73/IN3 P72/IN2 P71/IN1 P70/IN0 HST MD2
P53/INT6
P54/INT7
P55/ADTG
CC
AV
AVRL
AVRH
SS
AV
P60/AN0
P61/AN1
SS
V
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
P56/TIN0
P57/TOT0
MD0
MD1
(FPT-100P-M06)
(Continued)
6
(Continued)
MB90435 Series
(TOP VIEW)
CC
P21/A17
P20/A16
P17/AD15
P16/AD14
P15/AD13
P14/AD12
P13/AD11
P12/AD10
P11/AD09
P10/AD08
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
100999897969594939291908988878685848382818079787776
X1X0VSSX0A
P00/AD00
V
X1A
PA0
P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23
P30/ALE
P31/RD
V
P32/WRL/WR
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK P40/SOT0 P41/SCK0
P42/SIN0 P43/SIN1
P44/SCK1
V P45/SOT1 P46/SOT2 P47/SCK2
SS
CC
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
C
26272829303132333435363738394041424344454647484950
P51/INT4
P52/INT5
P50/SIN2
P53/INT6
P54/INT7
P55/ADTG
CC
AV
AVRL
AVRH
SS
AV
P60/AN0
P61/AN1
SS
V
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
P56/TIN0
P57/TOT0
MD0
MD1
MD2
HST
75
RST
74
P97
73
P96
72
P95
71
P94
70
P93/INT3
69
P92/INT2
68
P91/INT1
67
P90/INT0
66
P87/TOT1
65
P86/TIN1
64
P85/OUT1
63
P84/OUT0 P83/PPG3
62 61
P82/PPG2
60
P81/PPG1
59
P80/PPG0
58
P77/OUT3/IN7
57
P76/OUT2/IN6
56
P75/IN5
55
P74/IN4
54
P73/IN3
53
P72/IN2
52
P71/IN1
51
P70/IN0
(FPT-100P-M05)
7
MB90435 Series
■■■■ PIN DESCRIPTION
Pin No.
*2
LQFP
80 81
78 80 X0A
77 79 X1A 75 77 RST
50 52 HST
83 to 90 85 to 92
91 to 98 93 to 100
99 to 6 1 to 8
QFP
82 83
*1
P00 to P07
AD00 to AD07
P10 to P17
AD08 to AD15
P20 to P27
A16 to A23
Pin name Circuit type Function
X0 X1
A
(Oscillation)
A
(Oscillation)
B External reset request input pin C Hardware standby input pin
I
I
I
High speed crystal oscillator input pins Low speed crystal oscillator input pins. For the one clock
system parts, perfom external pull-down processing. Low speed crystal oscillator input pins. For the one clock
system parts, leave it open.
General I/O port with programmable pull-up. This function is enabled in the single-chip mode.
I/O pins for 8 lower bits of the external address/data bus. This function is enabled when the external bus is enabled.
General I/O port with programmable pull-up. This function is enabled in the single-chip mode.
I/O pins for 8 higher bits of the external address/data bus. This function is enabled when the external bus is enabled.
General I/O port with programmable pull-up. In external bus mode, this function is valid when the corresponding bits in the external address output control register (HACR) are set to “1”.
8-bit output pins for A16 to A23 at the external address bus. In external bus mode, this function is valid when the correspond­ing bits in the external address output control register (HACR) are set to “0”.
79
810
10 12
8
P30
ALE
P31
RD
P32
WRL
WR
General I/O port with programmable pull-up. This function is
I
I
I
enabled in the single-chip mode. Address latch enable output pin. This function is enabled
when the external bus is enabled. General I/O port with programmable pull-up. This function is
enabled in the single-chip mode. Read strobe output pin for the data bus. This function is
enabled when the external bus is enabled. General I/O port with programmable pull-up. This function is
enabled in the single-chip mode or when the WR output is disabled.
Write strobe output pin for the data bus. This function is enabled when both the external bus and the WR output are enabled. WRL lower 8 bits of the data bus in 16-bit access. WR output pin for the 8 bits of the data bus in 8-bit access.
is write-strobe output pin for the
/WRL pin
/WRL pin
is write-strobe
(Continued)
MB90435 Series
Pin No.
*2
LQFP
11 13
12 14
13 15
14 16
15 17
QFP
*1
Pin name
P33
WRH
P34
HRQ
P35
HAK
P36
RDY
P37
CLK
Circuit
type
I
I
I
I
H
Function
General I/O port with programmable pull-up. This function is enabled in the single-chip mode, external bus 8-bit mode or when WRH
Write strobe output pin for the 8 higher bits of the data bus. This function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the WRH
General I/O port with programmable pull-up. This function is enabled in the single-chip mode or when the hold function is disabled.
Hold request input pin. This function is enabled when both the external bus and the hold functions are enabled.
General I/O port with programmable pull-up. This function is enabled in the single-chip mode or when the hold function is disabled.
Hold acknowledge output pin. This function is enabled when both the external bus and the hold functions are enabled.
General I/O port with programmable pull-up. This function is enabled in the single-chip mode or when the external ready function is disabled.
Ready input pin. This function is enabled when both the external bus and the external ready functions are enabled.
General I/O port with programmable pull-up. This function is enabled in the single-chip mode or when the CLK output is disabled.
CLK output pin. This function is enabled when both the external bus and CLK outputs are enabled.
pin output is disabled.
output pin is enabled.
16 18
17 19
18 20
19 21
P40
SOT0
P41
SCK0
P42
SIN0
P43
SIN1
General I/O port. This function is enabled when UART0
G
G
G
G
disables the serial data output. Serial data output pin for UART0. This function is enabled
when UART0 enables the serial data output. General I/O port. This function is enabled when UART0
disables serial clock output. Serial clock I/O pin for UART0. This function is enabled when
UART0 enables the serial clock output. General I/O port. This function is always enabled. Serial data input pin for UART0. Set the corresponding Port
Direction Register to input if this function is used. General I/O port. This function is always enabled. Serial data input pin for UART1. Set the corresponding Port
Direction Register to input if this function is used.
(Continued)
9
MB90435 Series
Pin No.
*2
LQFP
20 22
22 24
23 25
24 26
QFP
*1
Pin name
P44
SCK1
P45
SOT1
P46
SOT2
P47
SCK2
P50
Circuit
type
G
G
G
G
Function
General I/O port. This function is enabled when UART1 disables the clock output.
Serial clock pulse I/O pin for UART1. This function is enabled when UART1 enables the serial clock output.
General I/O port. This function is enabled when UART1 disables the serial data output.
Serial data output pin for UART1. This function is enabled when UART1 enables the serial data output.
General I/O port. This function is enabled when the Extended I/O serial interface disables the serial data output.
Serial data output pin for the Extended I/O serial interface. This function is enabled when the Extended I/O serial interface enables the serial data output.
General I/O port. This function is enabled when the Extended I/O serial interface disables the clock output.
Serial clock pulse I/O pin for the Extended I/O serial interface . This function is enabled when the Extended I/O serial interface enables the Serial clock output.
General I/O port. This function is always enabled.
26 28
27 to 30 29 to 32
31 33
36 to 39 38 to 41
41 to 44 43 to 46
45 47
SIN2
P51 to P54
INT4 to INT7
P55
ADTG
P60 to P63
AN0 to AN3
P64 to P67
AN4 to AN7
P56
TIN0
D
D
D
E
E
D
Serial data input pin for the Extended I/O serial interface . Set the corresponding Port Direction Register to input if this function is used.
General I/O port. This function is always enabled. External interrupt request input pins for INT4 to INT7. Set the
corresponding Port Direction Register to input if this function is used.
General I/O port. This function is always enabled. Trigger input pin for the A/D converter. Set the corresponding
Port Direction Register to input if this function is used. General I/O port. This function is enabled when the analog
input enable register specifies a port. Analog input pins for the 8/10-bit A/D converter. This function is
enabled when the analog input enable register specifies A/D. General I/O port. The function is enabled when the analog
input enable register specifies a port. Analog input pins for the 8/10-bit A/D converter. This function is
enabled when the analog input enable register specifies A/D. General I/O port. This function is always enabled. Event input pin for the 16-bit reload timers 0. Set the
corresponding Port Direction Register to input if this function is used.
(Continued)
10
MB90435 Series
Pin No.
*2
LQFP
46 48
51 to 56 53 to 58
57 , 58 59 , 60
59 , 62 61 to 64
QFP
*1
Pin name
P57
TOT0
P70 to P75
IN0 to IN5
P76 , P77
OUT2 , OUT3
IN6 , IN7
P80 to P83
PPG0 to
PPG3
Circuit
type
D
D
D
D
Function
General I/O port. This function is enabled when the 16-bit reload timers 0 disables the output.
Output pin for the 16-bit reload timers 0. This function is enabled when the 16-bit reload timers 0 enables the output.
General I/O ports. This function is always enabled. Trigger input pins for input captures ICU0 to ICU5. Set the
corresponding Port Direction Register to input if this function is used.
General I/O ports. This function is enabled when the OCU disables the waveform output.
Event output pins for output compares OCU2 and OCU3. This function is enabled when the OCU enables the waveform output.
Trigger input pins for input captures ICU6 and ICU7. Set the corresponding Port Direction Register to input and disable the OCU waveform output if this function is used.
General I/O ports. This function is enabled when 8/16-bit PPG disables the waveform output.
Output pins for 8/16-bit PPGs. This function is enabled when 8/16-bit PPG enables the waveform output.
P84 , P85
63 , 64 65 , 66
OUT0 , OUT1
P86
65 67
TIN1
P87
66 68
TOT1
P90 to P93
67 to 70 69 to 72
INT0 to INT3
71 73 P94 D General I/O port.
D
D
D
D
General I/O ports. This function is enabled when the OCU disables the waveform output.
Waveform output pins for output compares OCU0 and OCU1. This function is enabled when the OCU enables the waveform output.
General I/O port. This function is always enabled. Input pin for the 16-bit reload timers 1. Set the
corresponding Port Direction Register to input if this function is used.
General I/O port. This function is enabled when the 16-bit reload timers 0 disables the output.
Output pin for the 16-bit reload timers 1.This function is enabled when the 16-bit reload timers 1 enables the output.
General I/O port. This function is always enabled. External interrupt request input pins for INT0 to INT3. Set the
corresponding Port Direction Register to input if this function is used.
(Continued)
11
MB90435 Series
(Continued)
Pin No.
LQFP
*2
QFP
*1
Pin name
72 74 P95 D General I/O port. 73 75 P96 D General I/O port. 74 76 P97 D General I/O port. 76 78 PA0 D General I/O port.
32 34 AV
CC
Circuit
type
Power supply
Power supply pin for the A/D Converter. This power supply must be turned on or off while a voltage higher than or equal to AV
CC is applied to VCC.
Function
35 37 AV
SS
33 35 AVRH
34 36 AVRL 47
48
49 50
MD0 MD1
49 51 MD2 F
25 27 C
21, 82 23, 84 V
9, 40, 79
11, 42,
81
CC
V
SS
*1 : FPT-100P-M06 *2 : FPT-100P-M05
Power supply
Power supply
Power supply
C
Power supply
Power supply
Power supply pin for the A/D Converter. External reference voltage input pin for the A/D Converter.
This power supply must be turned on or off while a voltage higher than or equal to AVRH is applied to AV
CC.
External reference voltage input pin for the A/D Converter. Input pins for specifying the operating mode. The pins must be
directly connected to V
CC or VSS.
Input pin for specifying the operating mode. The pin must be directly connected to V
CC or VSS.
Power supply stabilization capacitor pin. It should be connect­ed externally to an 0.1 µF ceramic capacitor.
Input pin for power supply (5.0 V) .
Input pin for power supply (0.0 V) .
12
MB90435 Series
I/O CIRCUIT TYPE
■■■■
Circuit type Diagram Remarks
• High-speed oscillation feedback resistor
X1,X1A
Clock input
X0,X0A
A
Hard, soft
standby control
: 1 M approx.
• Low-speed oscillation feedback resistor : 10 M approx.
• Hysteresis input
• Pull-up resistor : 50 k approx.
B
R (Pull-up)
R
HYS input
• Hysteresis input
C
R
HYS input
• CMOS level output
VCC
P-ch
D
R
N-ch
HYS input
• CMOS Hysteresis input
(Continued)
13
MB90435 Series
Circuit type Diagram Remarks
• CMOS level output
CC
V
P-ch
N-ch
E
P-ch
Analog input
N-ch
R
R
HYS input
HYS input
• CMOS Hysteresis input
• Analog input
• Hysteresis input
• Pull-down Resistor : 50 k approx. (except FLASH devices)
F
R (Pull-down)
• CMOS level output
• CMOS Hysteresis input
• TTL level input (FLASH devices in
CC
V
P-ch
N-ch
FLASH writer mode only)
G
R
R
T
HYS input
TTL level input
(Continued)
14
MB90435 Series
(Continued)
Circuit type Diagram Remarks
• CMOS level output
• CMOS Hysteresis input
VCC
Pull-up ON/OFF select signal
VCC
P-chP-ch
H
N-ch
• Programmable pull-up resistor : 50 k approx.
R
HYS input
• CMOS level output
• CMOS Hysteresis input
VCC
P-ch
I
R
R
Pull-up ON/OFF select signal
CC
V
P-ch
N-ch
TTL level input
T
HYS input
• TTL level input (FLASH devices in FLASH writer mode only)
• Programmable pull-up resistor : 50 k approx.
15
MB90435 Series
HANDLING DEVICES
■■■■
(1) Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than V
• A voltage higher than the rated voltage is applied between V
• The AVcc power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, care must also be tak en in not allowing the analog po wer-supply v oltage (AV exceed the digital power-supply voltage.
(2) Handling unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Theref or the y m ust be pulled up or pulled down through resistors . In this case those resistors should be more than 2 kΩ. Unused bi-directional pins should be set to the output state and can be left open, or the input state with the above described connection.
(3) Using external clock
To use external clock, drive X0 pin only and leave X1 pin unconnected. Below is a diagram of how to use external clock.
CC or lower than VSS is applied to an input or output pin.
CC and VSS.
CC, A VRH) to
MB90435 Series
X0
Open
X1
(4) Use of the sub-clock
Use one clock system parts when the sub-clock is not used. In that case, pull-down the pin X0A and leave the pin X1A open. When using two clock system parts, a 32 kHz oscillator has to be connected to the X0A and X1A pins.
CC/VSS
(5) Power supply pins (V
In products with multiple V
)
CC or VSS pins, the pins of a same potential are internally connected in the device to
avoid abnormal operations including latch-up. However you must connect the pins to an external power and a ground line to lower the electro-magnetic emission le vel to pre v ent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect V It is recommended to provide a bypass capacitor of around 0.1 µF between V
CC and VSS pins via the lowest impedance to power lines.
CC and VSS pins near the device.
VCC VSS
VCC
VSS
VSS
16
VCC
VSS
MB90435
Series
VCC
VSS
VCC
MB90435 Series
(6) Pull-up/down resistors
The MB90435 Series does not support internal pull-up/down resistors (except Port0 Port3 : pull-up resistors) . Use external components where needed.
(7) Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via the shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuits do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground area for stabilizing the operation.
(8) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (A V turning-on the digital power supply (V
CC) .
CC, A VRH, A VRL) and analog inputs (AN0 to AN7) after
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does not exceed AVRH or AV
CC (turning on/off the analog and digital power supplies simulta-
neously is acceptable) .
(9) Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter to AV
CC = VCC, AVSS = AVRH = VSS.
(10) N.C. Pin
The N.C. (internally connected) pin must be opened for use.
(11) Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 µs or more (0.2 V to 2.7 V) .
(12) Initialization
In the device, there are internal registers which are initialized only by a pow er-on reset. T o initialize these registers, please turn on the power again.
(13) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions
In the Signed multiplication and division instructions (“DIV A, Ri” and “DIVW A, RWi”) , the value of the corresponding bank register (DTB, ADB, USB, SSB) is set in “00
If the values of the corresponding bank registers (DTB, ADB, USB, SSB) are set to other than “00
H”.
H”, the remainder
by the execution result of the instruction is not stored in the register of the instruction operand.
(14) Using REALOS
The use of EI
2
OS is not possible with the REALOS real time operating system.
(15) Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit ev en when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.
17
MB90435 Series
BLOCK DIAGRAM
■■■■
X0, X1 X0A, X1A
RST HST
Clock
Controller
F2MC 16LX
CPU
SOT0 SCK0
SIN0
SOT1 SCK1
SIN1
SOT2 SCK2
SIN2
AV
CC
AVSS AN0 to AN7
AVRH AVRL ADTG
RAM
2 K/4 K/6 K/8 K
ROM/Flash
64K/128 K/256 K
(ROM only)
Prescaler
UART0
Prescaler
UART1
(SCI)
Prescaler
Serial I/O
10-bit A/D Converter
8 ch.
FMC-16 Bus
16-bit I/O
Timer
16-bit Input
Capture
8 ch.
16-bit Output
Compare
4 ch.
8/16-bit
PPG 4 ch.
16-bit Reload
Timer 2 ch.
External
Bus
Interface
External
Interrupt
8 ch.
IN0 to IN5 IN6/OUT2,
IN7/OUT3 OUT0, OUT1
PPG0 to PPG3
TIN0, TIN1 TOT0, TOT1
AD00 to AD15 A16 to A23 ALE RD WRL WRH
HRQ HAK RDY CLK
INT0 to INT7
18
■■■■ MEMORY MAP
The memory space of the MB90435 Series is shown below.
MB90435 Series
FFFFFF
FF0000 FEFFFF
FE0000 FDFFFF
FD0000 FCFFFF
FC0000
00FFFF
004000 003FFF
003900
0020FF 001FF5
001FF0
000100
0000BF 000000
MB90V540G
H
(FF bank)
H
H
(FE bank)
H
H
(FD bank)
H
H
(FC bank)
H
H
(Image of
H
H
Peripheral
H
H H
ROM correction
H
H
H
Peripheral
H
ROM
ROM
ROM
ROM
External
ROM
FF bank)
External
RAM 8 K
External
FFFFFF
FF0000
00FFFF
004000
003FFF
003900
002000
0008FF
000100 0000BF
000000
MB90F437L (S)*
H
(FF bank)
H
External
H
(Image of
FF bank)
H H
Peripheral
H
External
H
H
RAM 2 K
H
External
H
Peripheral
H
ROM
ROM
MB90F438L (S)/438L (S)
FFFFFF
H
FF0000
H
FEFFFF
H
FE0000
H
00FFFF
H
004000
H
003FFF
H
003900
H
002000
H
0010FF
H
000100
H
0000BF
H
000000
H
ROM
(FF bank)
ROM
(FE bank)
External
ROM
(Image of
FF bank)
Peripheral
External
RAM 4 K
External
Peripheral
MB90F439 (S) /439 (S)
FFFFFF
H
FF0000
H
FEFFFF
H
FE0000
H
FDFFFF
H
FD0000
H
FCFFFF
H
FC0000
H
00FFFF
H
004000
H
003FFF
H
003900
H
002100
H
0018FF
H
000100
H
0000BF
H
000000
H
ROM
(FF bank)
ROM
(FE bank)
ROM
(FD bank)
ROM
(FC bank)
External
ROM
(Image of
FF bank)
Peripheral
External
RAM 6 K
External
Peripheral
* : Under development
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits address are the same, the table in ROM can be referenced without using the “far” specification in the pointer declaration. For e xample, an attempt to access 00C000 FF exceeds 48 Kbytes, and its entire image cannot be sho wn in bank 00.The image betw een FF4000 FFFFFF
H is visible in bank 00, while the image between FF0000H and FF3FFFH is visible only in bank FF.
H accesses the value at FFC000H in ROM.The R OM area in bank
H and
19
MB90435 Series
■■■■ I/O MAP
Address Register Abbreviation Access Resource name Initial value
00
H Port 0 data register PDR0 R/W Port 0 XXXXXXXXB
01H Port 1 data register PDR1 R/W Port 1 XXXXXXXXB 02H Port 2 data register PDR2 R/W Port 2 XXXXXXXXB 03H Port 3 data register PDR3 R/W Port 3 XXXXXXXXB 04H Port 4 data register PDR4 R/W Port 4 XXXXXXXXB 05H Port 5 data register PDR5 R/W Port 5 XXXXXXXXB 06H Port 6 data register PDR6 R/W Port 6 XXXXXXXXB 07H Port 7 data register PDR7 R/W Port 7 XXXXXXXXB 08H Port 8 data register PDR8 R/W Port 8 XXXXXXXXB 09H Port 9 data register PDR9 R/W Port 9 XXXXXXXXB
0AH Port A data register PDRA R/W Port A _ _ _ _ _ _ _XB
0BH to 0FH Reserved
10
H Port 0 direction register DDR0 R/W Port 0 0 0 0 0 0 0 0 0B
11H Port 1 direction register DDR1 R/W Port 1 0 0 0 0 0 0 0 0B 12H Port 2 direction register DDR2 R/W Port 2 0 0 0 0 0 0 0 0B 13H Port 3 direction register DDR3 R/W Port 3 0 0 0 0 0 0 0 0B 14H Port 4 direction register DDR4 R/W Port 4 0 0 0 0 0 0 0 0B 15H Port 5 direction register DDR5 R/W Port 5 0 0 0 0 0 0 0 0B 16H Port 6 direction register DDR6 R/W Port 6 0 0 0 0 0 0 0 0B 17H Port 7 direction register DDR7 R/W Port 7 0 0 0 0 0 0 0 0B 18H Port 8 direction register DDR8 R/W Port 8 0 0 0 0 0 0 0 0B
19H Port 9 direction register DDR9 R/W Port 9 0 0 0 0 0 0 0 0B 1AH Port A direction register DDRA R/W Port A _ _ _ _ _ _ _0B 1BH Analog Input Enable register ADER R/W Port 6, A/D 1 1 1 1 1 1 1 1B 1CH Port 0 pull-up control register PUCR0 R/W Port 0 0 0 0 0 0 0 0 0B 1DH Port 1 pull-up control register PUCR1 R/W Port 1 0 0 0 0 0 0 0 0B 1EH Port 2 pull-up control register PUCR2 R/W Port 2 0 0 0 0 0 0 0 0B 1FH Port 3 pull-up control register PUCR3 R/W Port 3 0 0 0 0 0 0 0 0B
20H Serial Mode Control Register 0 UMC0 R/W
21H Serial Status Register 0 USR0 R/W 0 0 0 1 0 0 0 0B
22H
Serial input data register 0/
Serial output data register 0
UIDR0/
UODR0
R/W XXXXXXXXB
UART0
0 0 0 0 0 1 0 0B
20
23H Rate and data register 0 URD0 R/W 0 0 0 0 0 0 0XB
(Continued)
MB90435 Series
Address Register
24
H Serial mode register 1 SMR1 R/W
Abbreviation
Access Resource name Initial value
0 0 0 0 0 0 0 0B
25H Serial control register 1 SCR1 R/W 0 0 0 0 0 1 0 0B 26H
Serial input data register 1/
Serial output data register 1
SIDR1/
SODR1
R/W XXXXXXXXB
UART1
27H Serial status register 1 SSR1 R/W 0 0 0 0 1_0 0B 28H UART1 prescaler control register U1CDCR R/W 0_ _ _1 1 1 1B 29H Serial Edge select register SES1 R/W _ _ _ _ _ _ _0B
2AH Prohibited
2B
H Serial I/O prescaler SCDCR R/W
0_ _ _1 1 1 1B 2CH Serial mode control register SMCS R/W _ _ _ _0 0 0 0B 2DH Serial mode control register SMCS R/W 0 0 0 0 0 0 1 0B
Extended I/O
Serial Interface
2EH Serial data register SDR R/W XXXXXXXXB 2FH Serial Edge select register SES2 R/W _ _ _ _ _ _ _0B 30H External interrupt enable register ENIR R/W
0 0 0 0 0 0 0 0B
31H External interrupt request register EIRR R/W XXXXXXXXB
External Interrupt
32H External interrupt level register ELVR R/W 0 0 0 0 0 0 0 0B 33H External interrupt level register ELVR R/W 0 0 0 0 0 0 0 0B 34H A/D control status register 0 ADCS0 R/W
0 0 0 0 0 0 0 0B
35H A/D control status register 1 ADCS1 R/W 0 0 0 0 0 0 0 0B
A/D Converter
36H A/D data register 0 ADCR0 R XXXXXXXXB 37H A/D data register 1 ADCR1 R/W 0 0 0 0 1 _ XXB 38H PPG0 operation mode control register PPGC0 R/W 39H PPG1 operation mode control register PPGC1 R/W 0 _ 0 0 0 0 0 1B 3AH PPG0/1 clock selection register PPG01 R/W 0 0 0 0 0 0 _ _B
16-bit Programmable
Pulse
Generator 0/1
0 _ 0 0 0 _ _ 1B
3BH Prohibited 3CH PPG2 operation mode control register PPGC2 R/W 3DH PPG3 operation mode control register PPGC3 R/W 0 _ 0 0 0 0 0 1B 3EH PPG2/3 Clock Selection Register PPG23 R/W 0 0 0 0 0 0 _ _B
16-bit Programmable
Pulse
Generator 2/3
0 _ 0 0 0 _ _1B
3FH Prohibited 40
H PPG4 operation mode control register PPGC4 R/W
41H PPG5 operation mode control register PPGC5 R/W 0 _ 0 0 0 0 0 1B 42H PPG4/5 clock selection register PPG45 R/W 0 0 0 0 0 0 _ _B
16-bit Programmable
Pulse
Generator 4/5
0 _ 0 0 0 _ _ 1B
43H Prohibited 44
H PPG6 operation mode control register PPGC6 R/W
45H PPG7 operation mode control register PPGC7 R/W 0 _ 0 0 0 0 0 1B 46H PPG6/7 clock selection register PPG67 R/W 0 0 0 0 0 0 _ _B
16-bit Programmable
Pulse
Generator 6/7
0 _ 0 0 0 _ _ 1B
(Continued)
21
MB90435 Series
Address Register Abbreviation Access Resource name Initial value
47
H to 4BH Prohibited
4CH 4DH 4EH 4FH
Input capture control status register 0/1 Input capture control status register 2/3 Input capture control status register 4/5 Input capture control status register 6/7
50H Timer control status register 0 TMCSR0 R/W 51H Timer control status register 0 TMCSR0 R/W _ _ _ _ 0 0 0 0B
52H Timer register 0/reload register 0
53H Timer register 0/reload register 0
ICS01 R/W Input Capture 0/1 0 0 0 0 0 0 0 0B ICS23 R/W Input Capture 2/3 0 0 0 0 0 0 0 0B ICS45 R/W Input Capture 4/5 0 0 0 0 0 0 0 0B ICS67 R/W Input Capture 6/7 0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
TMR0/
TMRLR0
TMR0/
TMRLR0
R/W XXXXXXXXB
R/W XXXXXXXXB
16-bit Reload
Timer 0
54H Timer control status register 1 TMCSR1 R/W
0 0 0 0 0 0 0 0B
55H Timer control status register 1 TMCSR1 R/W _ _ _ _ 0 0 0 0B 56H Timer register 1/reload register 1
57H Timer register 1/reload register 1 58H
59H 5AH 5BH
Output compare control status register 0 Output compare control status register 1 Output compare control status register 2 Output compare control status register 3
TMR1/
TMRLR1
TMR1/
TMRLR1
R/W XXXXXXXXB
R/W XXXXXXXXB
OCS0 R/W OCS1 R/W _ _ _0 0 0 0 0B OCS2 R/W OCS3 R/W _ _ _ 0 0 0 0 0B
16-bit Reload
Timer 1
Output Compare
0/1
Output Compare
2/3
0 0 0 0 _ _ 0 0
0 0 0 0 _ _ 0 0B
5CH to 6BH Prohibited
6CH Timer Counter Data register TCDT R/W 6DH Timer Counter Data register TCDT R/W 0 0 0 0 0 0 0 0B
I/O Timer
0 0 0 0 0 0 0 0B
6EH Timer Counter Control status register TCCS R/W 0 0 0 0 0 0 0 0B
6FH ROM mirror function selection register ROMM R/W ROM Mirror _ _ _ _ _ _ _ 1B 70H to 7FH Reserved 80
H to 8FH Reserved
90H to 9DH Prohibited
B
22
Address Match
Detection
Function
0 0 0 0 0 0 0 0B
9E
H
Program address detection
control status register
PACSR R/W
9FH Delayed interrupt/release register DIRR R/W Delayed Interrupt _ _ _ _ _ _ _ 0B
A0H Low-power mode control register LPMCR R/W
A1H Clock selection register CKSCR R/W
Low Power
Controller
Low Power
Controller
0 0 0 1 1 0 0 0B
1 1 1 1 1 1 0 0B
(Continued)
MB90435 Series
(Continued)
Address Register Abbreviation Access Resource name Initial value
A2
H to A4H Prohibited
A5 A6H A7H Bus control signal selection register ECSR W 0 0 0 0 0 0 0 _B A8H Watchdog Timer control register WDTC R/W Watchdog Timer XXXXX 1 1 1B A9H Time Base Timer Control register TBTC R/W Time Base Timer 1 - - 0 0 1 0 0B
AAH Watch timer control register WTC R/W Watch Timer 1 X 0 0 0 0 0 0B
ABH to ADH Prohibited
Automatic ready function select register
H
External address output control register
ARSR W HACR W 0 0 0 0 0 0 0 0B
External Memory
Access
0 0 1 1 _ _ 0 0B
AE
Flash memory control status register
H
(Flash only, otherwise reserved)
FMCS R/W Flash Memory 0 0 0 X 0 0 0 0B
AFH Prohibited
B0H Interrupt control register 00 ICR00 R/W
0 0 0 0 0 1 1 1B B1H Interrupt control register 01 ICR01 R/W 0 0 0 0 0 1 1 1B B2H Interrupt control register 02 ICR02 R/W 0 0 0 0 0 1 1 1B B3H Interrupt control register 03 ICR03 R/W 0 0 0 0 0 1 1 1B B4H Interrupt control register 04 ICR04 R/W 0 0 0 0 0 1 1 1B B5H Interrupt control register 05 ICR05 R/W 0 0 0 0 0 1 1 1B B6H Interrupt control register 06 ICR06 R/W 0 0 0 0 0 1 1 1B B7H Interrupt control register 07 ICR07 R/W 0 0 0 0 0 1 1 1B B8H Interrupt control register 08 ICR08 R/W 0 0 0 0 0 1 1 1B
Interrupt
controller
B9H Interrupt control register 09 ICR09 R/W 0 0 0 0 0 1 1 1B
BAH Interrupt control register 10 ICR10 R/W 0 0 0 0 0 1 1 1B BBH Interrupt control register 11 ICR11 R/W 0 0 0 0 0 1 1 1B BCH Interrupt control register 12 ICR12 R/W 0 0 0 0 0 1 1 1B BDH Interrupt control register 13 ICR13 R/W 0 0 0 0 0 1 1 1B BEH Interrupt control register 14 ICR14 R/W 0 0 0 0 0 1 1 1B BFH Interrupt control register 15 ICR15 R/W 0 0 0 0 0 1 1 1B
C0H to FFH External
Address Register Abbreviation Access Resource name Initial value
1FF0
H Program address detection register 0 PADR0 R/W
XXXXXXXXB 1FF1H Program address detection register 0 PADR0 R/W XXXXXXXXB 1FF2H Program address detection register 0 PADR0 R/W XXXXXXXXB 1FF3H Program address detection register 1 PADR1 R/W XXXXXXXXB
Address Match
Detection Function
1FF4H Program address detection register 1 PADR1 R/W XXXXXXXXB 1FF5H Program address detection register 1 PADR1 R/W XXXXXXXXB
(Continued)
23
MB90435 Series
Address Register
3900
H Reload L PRLL0 R/W
Abbreviation
Access Resource name Initial value
XXXXXXXXB 3901H Reload H PRLH0 R/W XXXXXXXXB 3902H Reload L PRLL1 R/W XXXXXXXXB 3903H Reload H PRLH1 R/W XXXXXXXXB 3904H Reload L PRLL2 R/W 3905H Reload H PRLH2 R/W XXXXXXXXB 3906H Reload L PRLL3 R/W XXXXXXXXB 3907H Reload H PRLH3 R/W XXXXXXXXB 3908H Reload L PRLL4 R/W 3909H Reload H PRLH4 R/W XXXXXXXXB 390AH Reload L PRLL5 R/W XXXXXXXXB 390BH Reload H PRLH5 R/W XXXXXXXXB
390CH Reload L PRLL6 R/W 390DH Reload H PRLH6 R/W XXXXXXXXB
390EH Reload L PRLL7 R/W XXXXXXXXB 390FH Reload H PRLH7 R/W XXXXXXXXB
3910H to
3917
H
3918H Input Capture Register 0 IPCP0 R
Reserved
16-bit Programmable Pulse
Generator 0/1
XXXXXXXXB
16-bit Programmable Pulse
Generator 2/3
XXXXXXXXB
16-bit Programmable Pulse
Generator 4/5
XXXXXXXXB
16-bit Programmable Pulse
Generator 6/7
XXXXXXXXB 3919H Input Capture Register 0 IPCP0 R XXXXXXXXB 391AH Input Capture Register 1 IPCP1 R XXXXXXXXB 391BH Input Capture Register 1 IPCP1 R XXXXXXXXB
391CH Input Capture Register 2 IPCP2 R 391DH Input Capture Register 2 IPCP2 R XXXXXXXXB
391EH Input Capture Register 3 IPCP3 R XXXXXXXXB 391FH Input Capture Register 3 IPCP3 R XXXXXXXXB 3920H Input Capture Register 4 IPCP4 R 3921H Input Capture Register 4 IPCP4 R XXXXXXXXB 3922H Input Capture Register 5 IPCP5 R XXXXXXXXB 3923H Input Capture Register 5 IPCP5 R XXXXXXXXB 3924H Input Capture Register 6 IPCP6 R 3925H Input Capture Register 6 IPCP6 R XXXXXXXXB 3926H Input Capture Register 7 IPCP7 R XXXXXXXXB 3927H Input Capture Register 7 IPCP7 R XXXXXXXXB
Input Capture 0/1
XXXXXXXXB
Input Capture 2/3
XXXXXXXXB
Input Capture 4/5
XXXXXXXXB
Input Capture 6/7
(Continued)
24
MB90435 Series
(Continued)
Address Register Abbreviation Access Resource name Initial value
3928
H Output Compare Register 0 OCCP0 R/W
3929H Output Compare Register 0 OCCP0 R/W XXXXXXXXB
Output Compare 0/1
392AH Output Compare Register 1 OCCP1 R/W XXXXXXXXB 392BH Output Compare Register 1 OCCP1 R/W XXXXXXXXB
XXXXXXXXB
392CH Output Compare Register 2 OCCP2 R/W
XXXXXXXXB
392DH Output Compare Register 2 OCCP2 R/W XXXXXXXXB
Output Compare 2/3
392EH Output Compare Register 3 OCCP3 R/W XXXXXXXXB 392FH Output Compare Register 3 OCCP3 R/W XXXXXXXXB
3930H to
39FF
H
3A00
H to
3AFF
H
3B00
H to
3BFF
H
3C00H to
3CFF
H
3D00
H to
3DFF
H
3E00
H to
3FFF
H
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
• Read/write notation R/W : Reading and writing permitted
R : Read-only
W : Write-only
• Initial value notation
0 : Initial value is “0”. 1 : Initial value is “1”.
X : Initial value is undefined.
Note : Any write access to reserved addresses in I/O map should not be performed. A read access to reserved
addresses results in reading “X”.
25
MB90435 Series
INTERRUPT MAP
■■■■
Interrupt cause
2
EI
clear
OS
Interrupt vector Interrupt control register
Number Address Number Address
Reset N/A #08 FFFFDC INT9 instruction N/A #09 FFFFD8 Exception N/A #10 FFFFD4 Reserved N/A #11 FFFFD0H Reserved N/A #12 FFFFCCH Reserved N/A #13 FFFFC8H Reserved N/A #14 FFFFC4H External Interrupt INT0/INT1 *1 #15 FFFFC0H Time Base Timer N/A #16 FFFFBCH 16-bit Reload Timer 0 *1 #17 FFFFB8H 8/10-bit A/D Converter *1 #18 FFFFB4H I/O Timer N/A #19 FFFFB0H External Interrupt INT2/INT3 *1 #20 FFFFACH Serial I/O *1 #21 FFFFA8H 8/16-bit PPG 0/1 N/A #22 FFFFA4H Input Capture 0 *1 #23 FFFFA0H External Interrupt INT4/INT5 *1 #24 FFFF9CH
H  H  H 
ICR00 0000B0H
ICR01 0000B1H
ICR02 0000B2H
ICR03 0000B3H
ICR04 0000B4H
ICR05 0000B5H
ICR06 0000B6H
Input Capture 1 *1 #25 FFFF98H 8/16-bit PPG 2/3 N/A #26 FFFF94H External Interrupt INT6/INT7 *1 #27 FFFF90H Watch Timer N/A #28 FFFF8CH 8/16-bit PPG 4/5 N/A #29 FFFF88H Input Capture 2/3 *1 #30 FFFF84H 8/16-bit PPG 6/7 N/A #31 FFFF80H Output Compare 0 *1 #32 FFFF7CH Output Compare 1 *1 #33 FFFF78H Input Capture 4/5 *1 #34 FFFF74H Output Compare 2/3 - Input Capture 6/7 *1 #35 FFFF70H 16-bit Reload Timer 1 *1 #36 FFFF6CH UART 0 RX *2 #37 FFFF68H UART 0 TX *1 #38 FFFF64H UART 1 RX *2 #39 FFFF60H UART 1 TX *1 #40 FFFF5CH Flash Memory N/A #41 FFFF58H Delayed interrupt N/A #42 FFFF54H
ICR07 0000B7H
ICR08 0000B8H
ICR09 0000B9H
ICR10 0000BAH
ICR11 0000BBH
ICR12 0000BCH
ICR13 0000BDH
ICR14 0000BEH
ICR15 0000BFH
26
2
*1 : The interrupt request flag is cleared by the EI *2 : The interrupt request flag is cleared by the EI
OS interrupt clear signal.
2
OS interrupt clear signal. A stop request is available.
Notes : N/A : The interrupt request flag is not cleared by the EI
For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags are cleared by the EI
At the end of EI interrupt number. If one interrupt flag starts the EI
2
OS interrupt clear signal.
2
OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same
2
OS and in the meantime another interrupt flag is set by a hardware ev ent, the later ev ent is lost because the flag is cleared by the EI first event. So it is recommended not to use the EI
2
OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control
If EI
2
OS for this interrupt number.
register (ICR) is asserted. This means that different interrupt sources share the same EI which should be unique for each interrupt source. For this reason, when one interrupt source uses the
2
EI
OS, the other interrupt should be disabled.
MB90435 Series
2
OS interrupt clear signal.
2
OS clear signal caused by the
2
OS Descriptor
27
MB90435 Series
ELECTRICAL CHARACTERISTICS
■■■■
1. Absolute Maximum Ratings
Parameter Symbol
Power supply voltage
Input voltage V Output voltage V
AVRH,
AVRL
Value
Min Max
V
CC VSS 0.3 VSS + 6.0 V
AV
CC VSS 0.3 VSS + 6.0 V VCC = AVCC *1
VSS 0.3 VSS + 6.0 V
I VSS 0.3 VSS + 6.0 V *2
O VSS 0.3 VSS + 6.0 V *2
Units Remarks
AVCC AVRH/AVRL, AVRH AVRL *1
(VSS = AVSS = 0.0 V)
Maximum clamp current ICLAMP 2.0 + 2.0 mA *6 Total maximum clamp current | I “L” level max output current I
CLAMP | 20 mA *6
OL 15 mA *3
“L” level avg. output current IOLAV 4mA *4 “L” level max overall output current ∑I “L” level avg. overall output current ∑I
OL 100 mA
OLAV 50 mA *5
“H” level max output current IOH −15 mA *3 “H” level avg. output current I “H” level max overall output current ∑I
OHAV −4mA *4
OH −100 mA
“H” level avg. overall output current ∑IOHAV −50 mA *5 Power consumption P Operating temperature T
Storage temperature T
*1 : AV
CC, AVRH, AVRL should not exceed VCC. Also, AVRH, AVRL should not exceed AVCC, and AVRL does not
D
A −40 +105 °C
STG −55 +150 °C
500 mW Flash device 400 mW Mask ROM
exceed AVRH.
*2 : V
I and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum
current to/from an input is limited by some means with external components, the I V
I rating.
CLAMP rating supercedes the
*3 : The maximum output current is a peak value for a corresponding pin. *4 : Average output current is an average current value observed for a 100 ms period for a corresponding pin. *5 : Total average current is an average current value observed for a 100 ms period for all corresponding pins. *6 : Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P90 to P97, PA0
Use within recommended operating conditions.
Use at DC voltage (current) .
The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the V
CC pin, and this may affect
other devices.
Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result.
Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on result.
(Continued)
28
MB90435 Series
(Continued)
Care must be taken not to leave the +B input pin open.
Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input.
Sample recommended circuits :
• Input/Output Equivalent circuits
Protective diode
VCC
Limiting
resistance
+B input (0 V to 16 V)
R
Note : Average output current = operating current × operating efficiency WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
P-ch
N-ch
29
MB90435 Series
2. Recommended Conditions
Parameter Symbol
V
Power supply voltage
AV
CC,
CC
Value
Min Typ Max
Units Remarks
4.5 5.0 5.5 V
3.5 5.0 5.5 V
Under normal operation : MB90F439 (S) /439 (S) /V540G
Under normal operation : MB90F438L (S) /437L (S) /438L (S)
(VSS = AVSS = 0.0 V)
3.0 5.5 V Maintain RAM data in stop mode
Smooth capacitor C
S 0.022 0.1 1.0 µF*
Operating temperature TA −40 +105 °C
*: Use a ceramic capacitor or a capacitor of better 4. AC characteristics. The V
CC Capacitor should be greater than
this capacitor.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
• C Pin Connection Diagram
C
C
S
30
3. DC Characteristics
(MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
(MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
Parameter
Input H voltage
Input L voltage
Output H voltage
Output L voltage
Input leak current
Pull-up resistance
Pull-down resistance
Sym-
Pin name Condition
bol
CMOS hysteresis
IHS
V
input pin TTL input
V
IH
pin MD input
V
IHM
pin CMOS
hysteresis
ILS
V
input pin TTL input
V
IL
pin MD input
V
ILM
pin All output
V
OH
pins All output
V
OL
pins
I
IL
P00 to P07, P10 to P17,
R
P20 to P27,
UP
P30 to P37, RST
R
DO
MD2 25 50 100 k
WN
VCC = 4.5 V, I
OH = 4.0 mA
VCC = 4.5 V, I
OL = 4.0 mA
VCC = 5.5 V, V
SS < VI < VCC
MB90435 Series
Value
Min Typ Max
0.8 V
CC VCC + 0.3 V
2.0 V
VCC 0.3 VCC + 0.3 V
V
CC 0.3 0.2 VCC V
0.8 V
VSS 0.3 VCC + 0.3 V
VCC 0.5 V
0.4 V
5 5 µA
25 50 100 k
Units Remarks
(Continued)
31
MB90435 Series
(Continued)
(MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
(MB90F439 (S) /439 (S) /V540G : V
Parameter
Power supply current*
Input capacity
Sym-
Pin name Condition
bol
Internal frequency : 16 MHz,
I
CC
At normal operating Internal frequency : 16 MHz,
At Flash programming/erasing
I
CCS
Internal frequency : 16 MHz, At sleep mode
VCC = 5.0 V ± 1%,
I
CTS
Internal frequency : 2 MHz, At pseudo timer mode
VCC
CCL
I
I
CCLS
I
CCT
I
CCH1 At stop, TA = 25 °C 520µA
I
CCH2
Other than AV
CC, AVSS,
AVRH,
IN
C
AVRL, C, V
CC, VSS
Internal frequency : 8 kHz, At sub operation, T
Internal frequency : 8 kHz, At sub sleep, T
Internal frequency : 8 kHz, At timer mode, T
At hardware standby mode, T
A = 25 °C
CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
Value
Min Typ Max
Units Remarks
40 55 mA
50 70 mA Flash device
12 20 mA 300 600 µA
600 1100 µA MB90F348L (S) 200 400 µA
MB90437L (S) / 438L (S)
400 750 µA MB90F438L (S)
A = 25 °C
A = 25 °C
A = 25 °C
50 100 µAMask ROM 150 300 µA Flash device
15 40 µA
72A
50 100 µA
515pF
* : The power supply current testing conditions are when using the external clock.
32
4. AC Characteristics
(1) Clock Timing
(MB90F438L (S) /437L (S) /438L (S) : V
(MB90F439 (S) /439 (S) /V540G : V
Parameter Symb ol Pin name
MB90435 Series
CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
Value
Units Remarks
Min Typ Max
Oscillation frequency
Oscillation cycle time
Input clock pulse width
Input clock rise and fall time
Machine clock frequency
Machine clock cycle time
• Clock Timing
3 16 MHz V
f
C X0, X1
3 5MHz
f
CL X0A, X1A 32.768 kHz
62.5 333 ns V
CYL X0, X1
t
200 333 ns
t
LCYL X0A, X1A 30.5 µs
WH, PWL X0 10 ns
P
P
WLH, PWLL X0A 15.2 µs
t
CR, tCF X0  5 ns When using external clock
CP 1.5 16 MHz When using main clock
f
CC = 5.0 V±10%
VCC<4.5 (MB90F438L (S) / 437L (S) /438L (S) )
CC = 5.0 V±10%
VCC<4.5 (MB90F438L (S) / 437L (S) /438L (S) )
Duty ratio is about 30% to 70%.
fLCP 8.192 kHz When using sub-clock
t
CP 62.5 666 ns When using main clock
t
LCP 122.1 µs When using sub-clock
X0
X0A
tCYL
0.8 VCC
0.2 VCC
PWH PWL
tCF tCR
tLCYL
0.8 VCC
0.2 VCC
PWLH PWLL
tCF tCR
33
MB90435 Series
• Guaranteed PLL operation range
Guaranteed operation range (MB90F439(S)/439(S)/V540G)
Guaranteed operation range (MB90F438L(S)/437L(S)/438L(S))
5.5
Power supply voltage
CC
V
(V)
4.5
3.5
1.5
Machine clock f
• External clock frequency and Machine clock frequency
×4 ×3 ×2 ×1
Machine clock
CP
(MHz)
f
16
12
9 8
Guaranteed PLL operation range (MB90F438L(S)/437L(S)/438L(S))
Guaranteed PLL operation range ( MB90F439(S)/439(S)/V540G)
816
CP
(MHz)
PLL off
34
4
34 8
External clock f
C
(MHz)
16
AC characteristics are set to the measured reference voltage values below.
MB90435 Series
• Input signal waveform
Hysteresis Input Pin
0.8 VCC
0.2 VCC
TTL Input Pin
2.0 V
0.8 V
• Output signal waveform
Output Pin
2.4 V
0.8 V
35
MB90435 Series
(2) Clock Output Timing
(MB90F438L (S) /437L (S) /438L (S) : V
(MB90F439 (S) /439 (S) /V540G : V
Parameter Symbol Pin name Condition
CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
Value
Units Remarks
Min Max
Cycle time t
CYC
CLK VCC = 5 V ± 10%
CLK↑ →CLK t
CLK
CHCL 20 ns
CHCL
t
2.4 V 2.4 V
(3) Reset and Hardware Standby Input Timing
(MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
(MB90F439 (S) /439 (S) /V540G : V
Parameter Symbol
Pin
name
62.5 ns
tCYC
0.8 V
CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
Value
Units Remarks
Min Max
4 tCP ns Under normal operation
Reset input time t
RSTL RST
Oscillation time of oscillator + 4 t
CP
100 µs
4 t
CP ns
ms In stop mode
Pseudo timer mode (MB90437L (S) /438L (S) )
Pseudo timer mode (Other than MB90437L (S) /438L (S) )
In sub clock mode, sub
2 t
CP µs
sleep mode and watch mode
Hardware standby input time t
“t
cp” represents one cycle time of the machine clock.
HSTL HST 4 tCP ns Under normal operation
Oscillation time of oscillator is time that amplitude reached the 90%. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR/ceramic oscillator, the oscillation time is between handreds of µs to several ms. In the external clock, the oscillation time is 0 ns. Any reset can not fully initialize the Flash Memory if it is performing the automatic algorithm.
36
MB90435 Series
• Under normal operation, Pseudo timer mode, Sub clock mode, Sub sleep mode, Watch mode
tRSTL, tHSTL
RST
• In stop mode
HST
RST
X0
90% of amplitude
0.2 VCC
tRSTL
0.2 VCC 0.2 VCC
0.2 VCC
Internal operation clock
Internal reset
Oscillation time of oscillator
4 tCP
Oscillation setting time
Instruction execution
37
MB90435 Series
(4) Power On Reset
(MB90F438L (S) /437L (S) /438L (S) : V
(MB90F439 (S) /439 (S) /V540G : V
Parameter Symbol
name
Pin
CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
Value
Condition
Units Remarks
Min Max
Power on rise time t
R VCC
0.05 30 ms *
Power off time t
* : V
CC must be kept lower than 0.2 V before power-on.
OFF VCC 50 ms Due to repetitive operation
Notes : The above values are used for creating a power-on reset.
Some registers in the device are initialized only upon a po wer-on reset. To initialize these register, turn on the power supply using the above values.
tR
VCC
Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V or fewer per second, however, you can use the PLL clock.
2.7 V
0.2 V 0.2 V0.2 V
tOFF
38
VCC
3.0 V VSS
RAM data being held
It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower.
(5) Bus Timing (Read)
(MB90F438L (S) /437L (S) /438L (S) : V
(MB90F439 (S) /439 (S) /V540G : V
Parameter Symbol Pin name Condition
MB90435 Series
CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
Value
Units Remarks
Min Max
ALE pulse width t
LHLL ALE
tCP/2 20 ns
ALE,
Valid address→ALE↓time tAVLL
A16 to A23,
t
CP/2 20 ns
AD00 to AD15
ALE↓→Address valid time t
LLAX
ALE, AD00 to AD15
tCP/2 15 ns
A16 toA23,
Valid address→RD
time tAVRL
AD00 to AD15,
tCP 15 ns
RD
Valid addressValid data input
RD
pulse width tRLRH RD 3 tCP/2 20 ns
RD
↓→Valid data input tRLDV
t
AVDV
A16 to A23, AD00 to AD15
RD, AD00 to AD15
5 tCP/2 60 ns
3 tCP/2 60 ns
RD,
RD
↑→Data hold time tRHDX
0 ns
AD00 to AD15
RD
↓→ALEtime tRHLH RD, ALE tCP/2 15 ns
RD
↑→Address valid time tRHAX RD, A16 to A23 tCP/2 10 ns
A16 to A23,
Valid address→CLK↑time t
AVCH
AD00 to AD15,
t
CP/2 20 ns
CLK RD↓→CLKtime tRLCH RD, CLK tCP/2 20 ns ALE↓→RD
time tLLRL ALE, RD tCP/2 15 ns
39
MB90435 Series
• Bus Timing (Read)
CLK
ALE
RD
A16 to A23
AD00 to AD15
2.4 V
0.8 V
2.4 V
tAVCH
2.4 V
2.4 V
tLHLL
tAVLL
2.4 V
0.8 V
0.8 V
tLLAX
tLLRL
tAVRL tRLDV
tAVDV
Address Read data
2.4 V
0.8 V
tRLCH
2.4 V
0.8 V
tRLRH
0.8 VCC
0.2 V
CC
tRHLH
2.4 V
2.4 V
tRHAX
2.4 V
0.8 V
tRHDX
0.8 VCC
0.2 VCC
40
MB90435 Series
(6) Bus Timing (Write)
(MB90F438L (S) /437L (S) /438L (S) : V
(MB90F439 (S) /439 (S) /V540G : V
Parameter Symbol Pin name Condition
Valid addressWR
time tAVWL
WR pulse width tWLWH WR 3 tCP/2 20 ns
CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
Value
Units Remarks
Min Max
A16 to A23 AD00 to AD15,
CP 15 ns
t
WR
Valid data output→WR
WR
↑→Data hold time tWHDX
time tDVWH
WR↑→Address valid time tWHAX WR
↑→ALEtime tWHLH WR, ALE tCP/2 15 ns
WR
↑→CLKtime tWLCH WR, CLK tCP/2 20 ns
AD00 to AD15, WR
AD00 to AD15, WR
A16 to A23, WR
3 tCP/2 20 ns
20 ns
tCP/2 10 ns
• Bus Timing (Write)
tWLCH
CLK
ALE
tAVWL
2.4 V
tWLWH
tWHLH
2.4 V
WR (WRL, WRH)
A16 to A23
AD00 to AD15
2.4 V
0.8 V
0.8 V
2.4 V
0.8 V
2.4 V
Address Write data
0.8 V
tDVWH
2.4 V
tWHAX
2.4 V
0.8 V
tWHDX
2.4 V
0.8 V
41
MB90435 Series
(7) Ready Input Timing
(MB90F438L (S) /437L (S) /438L (S) : V
(MB90F439 (S) /439 (S) /V540G : V
Parameter Symbol Pin name Condition
CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
Value
Units Remarks
Min Max
RDY setup time t
RYHS RDY
45 ns
RDY hold time tRYHH RDY 0 ns
Note : If the RDY setup time is insufficient, use the auto-ready function.
• Ready Input Timing
CLK
ALE
RD/WR
2.4 V
tRYHS tRYHH
RDY no WAIT is used.
RDY When WAIT is used (1 cycle).
42
0.8 V
CC
0.2 VCC
0.8 VCC
(8) Hold Timing
(MB90F438L (S) /437L (S) /438L (S) : V
Parameter Symbol Pin name Condition
(MB90F439 (S) /439 (S) /V540G : V
MB90435 Series
CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
Value
Units Remarks
Min Max
Pin floatingHAK
time tXHAL HAK
30 t
CP ns
HAKtimePin valid time tHAHV HAK tCP 2 tCP ns
Note : There is more than 1 cycle from the time HRQ is read to the time the HAK
is changed.
• Hold Timing
HAK
Each pin
tXHAL
2.4 V
0.8 V
0.8 V
High impedance
2.4 V
tHAHV
2.4 V
0.8 V
(9) UART0/1, Serial I/O Timing
(MB90F438L (S) /437L (S) /438L (S) : V
(MB90F439 (S) /439 (S) /V540G : V
CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
Value
Parameter Symbol Pin name Condition
Min Max
Serial clock cycle time t SCK↓→SOT delay time t
Valid SIN→SCK↑ t
SCK↑→Valid SIN hold time t
SCYC SCK0 to SCK2
SLOV
SCK0 to SCK2, SOT0 to SOT2
SCK0 to SCK2,
IVSH
SIN0 to SIN2 SCK0 to SCK2,
SHIX
SIN0 to SIN2
Internal clock opera­tion output pins are
L = 80 pF + 1 TTL.
C
8 t
CP ns
80 80 ns
100 ns
60 ns
Units Remarks
Serial clock “H” pulse width t Serial clock “L” pulse width t
SCK↓→SOT delay time tSLOV
Valid SIN→SCK↑ t
SCK↑→Valid SIN hold time t
SHSL SCK0 to SCK2 SLSH SCK0 to SCK2 4 tCP ns
SCK0 to SCK2, SOT0 to SOT2
SCK0 to SCK2,
IVSH
SIN0 to SIN2 SCK0 to SCK2,
SHIX
SIN0 to SIN2
Notes : AC characteristic in CLK synchronized mode.
C
L is load capacity value of pins when testing.
For t
CP (Machine clock cycle time) , refer to “ (1) Clock Timing”.
External clock oper­ation output pins are C
L = 80 pF + 1 TTL.
CP ns
4 t
150 ns
60 ns
60 ns
43
MB90435 Series
• Internal Shift Clock Mode
SCK
SOT
SIN
• External Shift Clock Mode
SCK
SOT
tSCYC
2.4 V
0.8 V 0.8 V tSLOV
2.4 V
0.8 V
tIVSH tSHIX
0.8 V
CC
0.2 VCC
tSLSH tSHSL
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC tSLOV
2.4 V
0.8 V
0.8 VCC
0.2 VCC
SIN
tIVSH tSHIX
0.8 V
CC
0.2 VCC
0.8 VCC
0.2 VCC
44
(10) Timer Input Timing
(MB90F438L (S) /437L (S) /438L (S) : V
(MB90F439 (S) /439 (S) /V540G : V
Parameter Symbol Pin name Condition
Input pulse width
• Timer Input Timing
TIWH TIN0, TIN1
t t
TIWL IN0 to IN7
0.8 VCC 0.8 VCC
tTIWH tTIWL
MB90435 Series
CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
Min Max
4 t
0.2 VCC 0.2 VCC
CP ns
Value
Units Remarks
(11) Timer Output Timing
(MB90F438L (S) /437L (S) /438L (S) : V
(MB90F439 (S) /439 (S) /V540G : V
Parameter Symbol Pin name Condition
CLK↑→T
OUT change time tTO
• Timer Output Timing
CLK
T
OUT
CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
TOT0 to TOT1, PPG0 to PPG3
2.4 V
t
TO
Value
Units Remarks
Min Max
30 ns
2.4 V
0.8 V
45
MB90435 Series
(12) Trigger Input Timing
(MB90F438L (S) /437L (S) /438L (S) : V
(MB90F439 (S) /439 (S) /V540G : V
Parameter Symbol Pin name Condition
Input pulse width
• Trigger Input Timing
TRGH
t tTRGL
INT0 to INT7, ADTG
0.8 VCC 0.8 VCC
tTRGH tTRGL
CC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
CC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = 40 °C to +105 °C)
Value
Units Remarks
Min Max
5 t
CP ns Under nomal operation
1 µs In stop mode
0.2 VCC 0.2 VCC
46
MB90435 Series
5. A/D Converter
• Electrical Characteristics
(
VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, 3.0 V AVRH AVRL, TA = 40 °C to +105 °C)
Parameter Symbol Pin name
Min Typ Max
Resolution    10 bit Conversion error    ±5.0 LSB Nonlinearity error   ±2.5 LSB
Value
Units Remarks
Differential nonlinearity error
Zero transition voltage V
Full scale transition voltage V
   ±1.9 LSB
OT AN0 to AN7
FST AN0 to AN7
AVRL − 3.5
LSB
AVRH − 6.5
LSB
Compare time 352 t
Sampling time 64 t
Analog port input current I Analog input voltage range V
AIN AN0 to AN7 −1 1 µA
AIN AN0 to AN7 AVRL AVRH V
AVRH AVRL + 2.7 AV
Reference voltage range
AVRL 0 AVRH 2.7 V
A AVCC 5 mA
I
Power supply current
I
AH AVCC  5 µA*
400 600 µA Flash device
R AVRH
Reference voltage supply current
Offset between input channels
I
140 260 µA Mask ROM
RH AVRH  5 µA*
I AN0 to AN7  4LSB
AVRL + 0.5
LSB
AVRH 1.5
LSB
CP ns
CP ns
AVRL + 4.5
LSB
AVRH + 1.5
LSB
CC V
mV
mV
Internal frequency : 16 MHz
Internal frequency : 16 MHz
VCC = AVCC =
5.0 V ± 1%
* : When not using an A/D converter, this is the current (V
CC = AVCC = AVRH = 5.0 V) when the CPU is stopped.
Note: The functionality of the A/D converter is only guaranteed for VCC = 5.0 V ± 10 % (also for MB90F438L (S) /
437L (S) /438L (S) ) .
47
MB90435 Series
• A/D Converter Glossary
Resolution : Analog changes that are identifiable with the A/D converter Linearity error : The deviation of the straight line connecting the zero transition point (“00 0000 0000” ←→ “00
0000 0001”) with the full-scale transition point (“11 1111 1110” conversion characteristics
Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value
Total error : The total error is defined as a difference between the actual v alue and the theoretical value, which
includes zero-transition error/full-scale transition error and linearity error.
Total error
3FF
←→ “11 1111 1111”) from actual
Actual conversion Value
0.5 LSB
1024
Analog input
[V]
Digital output
1 LSB = (Theoretical value)
3FE
3FD
004
003
002
001
AVRL AVRH
AVRH AVRL
VOT (Theoretical value) = AVRL + 0.5 LSB [V]
VFST (Theoretical value) = AVRH 1.5 LSB [V]
NT {1 LSB × (N 1) + 0.5 LSB}
Total error for digital output N =
V
(measured value)
Actual conversion characteristics
Theoretical characteristics
1 LSB
0.5 LSB
{1 LSB × (N 1) + 0.5 LSB}
V
NT
[LSB]
48
NT : Voltage at a transition of digital output from (N 1) to N
V
(Continued)
(Continued)
MB90435 Series
Linearity error Differential linearity error
3FF
3FE
3FD
004
Digital output
003
002
001
Linearity error of digital output N
Actual conversion value
{1 LSB × (N 1) + VOT }
(measured value)
VOT
AVRL AVRH AVRL AVRH
NT {1 LSB × (N 1) + VOT}
V
=
Differential linearity error of digital N
V
FST VOT
1 LSB
=
1022
[V]
Theorential characteristics
N + 1
Actual conversion value
VFST
(measured value)
N
V
NT
Actual conversion characteristics
Theoretical characteristics
Analog input Analog input
1 LSB
V (
N + 1) T VNT
=
1 LSB
1 LSB [LSB]
N 1
Digital output
N 2
[LSB]
Acturel conversion value
V (N + 1) T
(measured value)
(measured value)
VNT
V
OT : Voltage at transition of digital output from “000H” to “001H
V
FST : Voltage at transition of digital output from “3FEH” to “3FFH
• Notes on Using A/D Converter
Select the output impedance value for the e xternal circuit of analog input according to the following conditions, :
• Output impedance values of the external circuit of 15 k or lower are recommended.
• When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the eff ect of v oltage distribution between the e xternal capacitor and internal capacitor.
Note : When the output impedance of the external circuit is too high, the sampling period for analog voltages ma y
not be sufficient (sampling period = 4.00 µs @machine clock of 16 MHz) .
• Equipment of analog input circuit model
Comparator
Analog input
3.2 k Max. 30 pF Max.
•Error
The smaller the | AVRH AVRL |, the greater the error would become relatively.
49
MB90435 Series
6. Flash Memory Program/Erase Characteristics
Value
Parameter Condition
Min Typ Max
Units Remarks
Sector erase time
1 15 s Excludes 00
5 s MB90F438L (S) Excludes 00
Chip erase time
Word (16 bit width) programming time
T
A = + 25 °C
V
CC = 5.0 V
7 s MB90F439 (S)
16 3,600 µs Excludes system-level overhead
Erase/Program cycle 10,000 cycle
H programming prior erasure
H
programming prior erasure
50
EXAMPLE CHARACTERISTICS
■■■■
“H” level output voltage
MB90435 Series
“L” level output voltage
VOH – IOH
5
4.5
4
3.5
3
2.5
VOH [V]
2
1.5
1
0.5
0
0 -10-8-6-4-2
(VCC = 4.5 V, Ta = +25˚C)
IOH [mA]
“H” level input voltage/ “L” level input voltage (Hysterisis inpiut)
0.9
0.8
0.7
0.6
0.5
VOL [V]
0.4
0.3
0.2
0.1
VOL – IOL
CC = 4.5 V,Ta = +25˚C)
(V
0
0
IOL [mA]
108642
5
4
3
Vin [V]
2
1
0
3 5.554.543.5
Vin – Vcc
(Ta = +25˚C)
VIH
VIL
6 6.5
Vcc [V]
51
MB90435 Series
Power supply current (MB90439)
40
35
30
25
20
Icc [mA]
15
10
5
0
276543
Icc – Vcc
Vcc [V]
(Ta = +25˚C)
fcp = 16 MHz
fcp = 12 MHz
fcp = 10 MHz
fcp = 8 MHz
fcp = 4 MHz
fcp = 2 MHz
12
10
8
6
Icc [mA]
4
2
0
276543
Iccs – Vcc
(Ta = +25˚C)
fcp = 16 MHz
fcp = 12 MHz
fcp = 10 MHz
fcp = 8 MHz
fcp = 4 MHz
fcp = 2 MHz
Vcc [V]
600
500
400
300
ICTS [µA]
200
100
0
276543
ICTS – VCC
Vcc [V]
(Ta = +25˚C)
fcp = 2 MHz
100
90
80
70
60
50
ICCL [µA]
40
30
20
10
0
ICCL – VCC
(Ta = +25˚C)
fcp = 8 kHz
276543
Vcc [V]
52
MB90435 Series
ICCLS [µA]
40
35
30
25
20
15
10
ICCLS – VCC
(Ta = +25˚C)
25
20
15
ICCT – VCC
(Ta = +25˚C)
ICCT [µA]
10
fcp = 8 kHz
5
5
0
2
6543
Vcc [V]
0
7
2
Vcc [V]
fcp = 8 kHz
6543
7
20
15
10
ICCH1 [µA]
5
0
276543
ICCH1 – VCC
(STOP, Ta = +25˚C)
Vcc [V]
53
MB90435 Series
Power supply current (MB90F439)
Icc – Vcc
45
40
35
30
25
20
ICC [mA]
15
10
5
0
23456
VCC [V]
fcp = 16 MHz
fcp = 12 MHz
(Ta = +25 ˚C)
fcp = 10 MHz
fcp = 8 MHz
fcp = 4 MHz
fcp = 2 MHz
Iccs – Vcc
14
12
10
8
6
ICC [mA]
4
2
0
7
23456
VCC [V]
(Ta = +25 ˚C)
fcp = 16 MHz
fcp = 12 MHz
fcp = 10 MHz
fcp = 8 MHz
fcp = 4 MHz
fcp = 2 MHz
7
ICTS – VCC
600
500
400
300
ICTS [µA]
200
100
0
23456
VCC [V]
(Ta = +25 ˚C)
fcp = 2 MHz
ICCL – VCC
300
250
200
150
ICCL [µA]
100
50
0
7
23456
VCC [V]
(Ta = +25 ˚C)
fcp = 8 kHz
7
54
MB90435 Series
ICCLS – VCC
45
40
35
30
25
20
ICCLS [µA]
15
10
5
0
23456
VCC [V]
fcp = 8 MHz
(Ta = +25 ˚C)
ICCT – VCC
25
20
15
ICCT [µA]
10
5
0
7
23456
VCC [V]
(Ta = +25 ˚C)
fcp = 8 MHz
7
ICCH2 – VCC
100
90
85
70
60
50
ICCH2 [µA]
40
30
20
10
0
23456
(hardware standby, Ta = +25 ˚C)
VCC [V]
ICCH1 – VCC
20
15
10
ICCH1 [µA]
5
0
7
276543
Vcc [V]
(STOP, Ta = +25˚C)
55
MB90435 Series
ORDERING INFORMATION
■■■■
Part number Package Remarks
MB90F438LPF MB90F438LSPF MB90F439PF MB90F439SPF MB90437LPF MB90437LSPF MB90438LPF MB90438LSPF MB90439PF MB90439SPF
MB90F438LPFV MB90F438LSPFV MB90F439PFV MB90F439SPFV MB90437LPFV MB90437LSPFV MB90438LPFV MB90438LSPFV MB90439PFV MB90439SPFV
100-pin
100-pin
Plastic QFP
(FPT-100P-M06)
Plastic LQFP
(FPT-100P-M05)
56
PACKAGE DIMENSIONS
■■■■
100-pin Plastic QFP
(FPT-100P-M06)
MB90435 Series
Note: Pins width and pins thickness include plating thickness.
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
5180
100-pin
Plastic LQFP
(FPT-100P-M05)
81
INDEX
100
1 30
0.65(.026)
"A"
C
2001 FUJITSU LIMITED F100008S-c-4-4
16.00±0.20(.630±.008)SQ
14.00±0.10(.551±.004)SQ
75
0.32±0.05
(.013±.002)
50
0.10(.004)
17.90±0.40
(.705±.016)
14.00±0.20
(.551±.008)
Details of "A" part
0.13(.005)
31
(Mounting height)
M
0.17±0.06
(.007±.002)
+0.35 –0.20
3.00
+.014 –.008
.118
0~8°
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25(.010)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches)
Note : Pins width and pins thickness include plating thickness.
51
76 50
INDEX
100
125
0.50(.020)
C
2000 FUJITSU LIMITED F100007S-3c-5
0.20±0.05
(.008±.002)
0.08(.003)
0.08(.003) Details of "A" part
+.008
+0.20
.059 –.004
–0.10
1.50 (Mounting height)
26
M
"A"
0.145±0.055
(.0057±.0022)
0°~8°
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
Dimensions in mm (inches)
57
MB90435 Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.
The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0207
FUJITSU LIMITED Printed in Japan
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