MB90437L (S) /438L (S) /F438L (S)
MB90439 (S) /F439 (S) /V540G
DESCRIPTION
■■■■
The MB90435 series with FLASH ROM is specially designed for industrial applications.
2
The instruction set by F
instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions.The micro controller has a 32-bit accumulator for processing
long word data.
MC-16LX CPU core inherits an AT architecture of the F2MC* family with additional
DS07-13727-1E
The MB90435 series has peripheral resources of 8/10-bit A/D converters, UART (SCI) , extended I/O serial
interfaces, 8/16-bit timer, I/O timer (input capture (ICU) , output compare (OCU) ) .
2
* : F
MC stands for FUJITSU Flexible Microcontroller.
FEATURES
■■■■
•Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from : divided-b y-2 of oscillation or one to f our times the oscillation
Minimum instruction ex ecution time : 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock,
CC of 5.0 V)
V
Subsystem Clock : 32 kHz
PACKAGES
■■■■
100-pin Plastic QFP100-pin Plastic LQFP
(Continued)
(FPT-100P-M06) (FPT-100P-M05)
MB90435 Series
• Instruction set to optimize controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
Enhanced signed multiplication/division instruction and RETI instruction functions
Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C language) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced interrupt function : 8 levels, 34 factors
• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI
• Embedded ROM size and types
Mask ROM : 64 Kbytes / 128 Kbytes / 256 Kbytes
Flash ROM : 128 Kbytes/256 Kbytes
Embedded RAM size : 2 Kbytes/4 Kbytes/6 Kbytes/8 Kbytes (evaluation chip)
•Flash ROM
Supports automatic programming, Embedded Algorithm TM*
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory
Erase can be performed on each block
Block protection with external programming voltage
• Low-power consumption (stand-by) mode
Sleep mode (mode in which CPU operating clock is stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Clock mode
Hardware stand-by mode
Transfer can be started from MSB or LSB
Serial I/O
Supports internal clock synchronized transfer and external clock synchronized transfer
Supports positive-edge and nagative-edge clock synchronization
Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock = 16 MHz
10-bit or 8-bit resolution
A/D Converter
8 input channels
Conversion time : 26.3 µs (per one channel)
2
(Continued)
4
MB90435 Series
(Continued)
FeaturesMB90F438L (S) /F439 (S)
16-bit Reload Timer
(2 channels)
16-bit I/O Timer
16-bit Output Compare
(4 channels)
16-bit Input Capture
(8 channels)
Operation clock frequency : fsys/2
Supports External Event Count function
Signals an interrupt when overflow
Supports Timer Clear when a match with Output Compare (Channel 0)
Operation clock freq. : fsys/2
Signals an interrupt when a match with 16-bit I/O Timer
Four 16-bit compare registers
A pair of compare registers can be used to generate an output signal
Rising edge, falling edge or rising & falling edge sensitive
Four 16-bit Capture registers
Signals an interrupt upon external event
MB90437L (S) *
/438L (S) /439 (S)
1
, fsys/23, fsys/25 (fsys = System clock frequency)
2
, fsys/24, fsys/26, fsys/28 (fsys = System clock freq.)
Supports 8-bit and 16-bit operation modes
Eight 8-bit reload counters
Eight 8-bit reload registers for L pulse width
Eight 8-bit reload registers for H pulse width
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit
prescaler plus 8-bit reload counter
4 output pins
Operation clock freq. : fsys, fsys/2
1
, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
(fsys = System clock frequency, fosc = Oscillation clock frequency)
32 kHz Sub-clockSub-clock for low power operation
External Interrupt
(8 channels)
External bus
interface
Can be programmed edge sensitive or level sensitive
External access using the selectable 8-bit or 16-bit bus is enabled
(external bus mode.)
Virtually all external pins can be used as general purpose I/O
I/O Ports
All push-pull outputs and schmitt trigger inputs
Bit-wise programmable as input/output or peripheral signal
A flag indicating completion of the algorithm
Flash Memory
Number of erase cycles : 10,000 times
Data retention time : 10 years
Boot block configuration
Erase can be performed on each block
Block protection by externally programmed voltage
*1 : Under development
*2 : If the one clock system is used, equip X0A and X1A with clocks from the tool side.
*3 : It is setting of DIP switch S2 when Emulator pod (MB2145-507) is used.Please ref er to the MB2145-507 hardware
manual (2.7 Emulator-specific Power Pin) about details.
*4 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
*5 : OPERATING VOLTAGE RANGE
High speed crystal oscillator input pins
Low speed crystal oscillator input pins. For the one clock
system parts, perfom external pull-down processing.
Low speed crystal oscillator input pins. For the one clock
system parts, leave it open.
General I/O port with programmable pull-up. This function is
enabled in the single-chip mode.
I/O pins for 8 lower bits of the external address/data bus. This
function is enabled when the external bus is enabled.
General I/O port with programmable pull-up. This function is
enabled in the single-chip mode.
I/O pins for 8 higher bits of the external address/data bus. This
function is enabled when the external bus is enabled.
General I/O port with programmable pull-up. In external bus
mode, this function is valid when the corresponding bits in the
external address output control register (HACR) are set to “1”.
8-bit output pins for A16 to A23 at the external address bus. In
external bus mode, this function is valid when the corresponding bits in the external address output control register (HACR)
are set to “0”.
79
810
1012
8
P30
ALE
P31
RD
P32
WRL
WR
General I/O port with programmable pull-up. This function is
I
I
I
enabled in the single-chip mode.
Address latch enable output pin. This function is enabled
when the external bus is enabled.
General I/O port with programmable pull-up. This function is
enabled in the single-chip mode.
Read strobe output pin for the data bus. This function is
enabled when the external bus is enabled.
General I/O port with programmable pull-up. This function is
enabled in the single-chip mode or when the WR
output is disabled.
Write strobe output pin for the data bus. This function is
enabled when both the external bus and the WR
output are enabled. WRL
lower 8 bits of the data bus in 16-bit access. WR
output pin for the 8 bits of the data bus in 8-bit access.
is write-strobe output pin for the
/WRL pin
/WRL pin
is write-strobe
(Continued)
MB90435 Series
Pin No.
*2
LQFP
1113
1214
1315
1416
1517
QFP
*1
Pin name
P33
WRH
P34
HRQ
P35
HAK
P36
RDY
P37
CLK
Circuit
type
I
I
I
I
H
Function
General I/O port with programmable pull-up. This function is
enabled in the single-chip mode, external bus 8-bit mode or
when WRH
Write strobe output pin for the 8 higher bits of the data bus.
This function is enabled when the external bus is enabled,
when the external bus 16-bit mode is selected, and when the
WRH
General I/O port with programmable pull-up. This function is
enabled in the single-chip mode or when the hold function is
disabled.
Hold request input pin. This function is enabled when both the
external bus and the hold functions are enabled.
General I/O port with programmable pull-up. This function is
enabled in the single-chip mode or when the hold function is
disabled.
Hold acknowledge output pin. This function is enabled when
both the external bus and the hold functions are enabled.
General I/O port with programmable pull-up. This function is
enabled in the single-chip mode or when the external ready
function is disabled.
Ready input pin. This function is enabled when both the
external bus and the external ready functions are enabled.
General I/O port with programmable pull-up. This function is
enabled in the single-chip mode or when the CLK output is
disabled.
CLK output pin. This function is enabled when both the
external bus and CLK outputs are enabled.
pin output is disabled.
output pin is enabled.
1618
1719
1820
1921
P40
SOT0
P41
SCK0
P42
SIN0
P43
SIN1
General I/O port. This function is enabled when UART0
G
G
G
G
disables the serial data output.
Serial data output pin for UART0. This function is enabled
when UART0 enables the serial data output.
General I/O port. This function is enabled when UART0
disables serial clock output.
Serial clock I/O pin for UART0. This function is enabled when
UART0 enables the serial clock output.
General I/O port. This function is always enabled.
Serial data input pin for UART0. Set the corresponding Port
Direction Register to input if this function is used.
General I/O port. This function is always enabled.
Serial data input pin for UART1. Set the corresponding Port
Direction Register to input if this function is used.
(Continued)
9
MB90435 Series
Pin No.
*2
LQFP
2022
2224
2325
2426
QFP
*1
Pin name
P44
SCK1
P45
SOT1
P46
SOT2
P47
SCK2
P50
Circuit
type
G
G
G
G
Function
General I/O port. This function is enabled when UART1
disables the clock output.
Serial clock pulse I/O pin for UART1. This function is
enabled when UART1 enables the serial clock output.
General I/O port. This function is enabled when UART1
disables the serial data output.
Serial data output pin for UART1. This function is enabled when
UART1 enables the serial data output.
General I/O port. This function is enabled when the Extended
I/O serial interface disables the serial data output.
Serial data output pin for the Extended I/O serial interface. This
function is enabled when the Extended I/O serial interface
enables the serial data output.
General I/O port. This function is enabled when the Extended
I/O serial interface disables the clock output.
Serial clock pulse I/O pin for the Extended I/O serial interface .
This function is enabled when the Extended I/O serial interface
enables the Serial clock output.
General I/O port. This function is always enabled.
2628
27 to 3029 to 32
3133
36 to 3938 to 41
41 to 4443 to 46
4547
SIN2
P51 to P54
INT4 to INT7
P55
ADTG
P60 to P63
AN0 to AN3
P64 to P67
AN4 to AN7
P56
TIN0
D
D
D
E
E
D
Serial data input pin for the Extended I/O serial interface . Set
the corresponding Port Direction Register to input if this
function is used.
General I/O port. This function is always enabled.
External interrupt request input pins for INT4 to INT7. Set the
corresponding Port Direction Register to input if this function is
used.
General I/O port. This function is always enabled.
Trigger input pin for the A/D converter. Set the corresponding
Port Direction Register to input if this function is used.
General I/O port. This function is enabled when the analog
input enable register specifies a port.
Analog input pins for the 8/10-bit A/D converter. This function is
enabled when the analog input enable register specifies A/D.
General I/O port. The function is enabled when the analog
input enable register specifies a port.
Analog input pins for the 8/10-bit A/D converter. This function is
enabled when the analog input enable register specifies A/D.
General I/O port. This function is always enabled.
Event input pin for the 16-bit reload timers 0. Set the
corresponding Port Direction Register to input if this function is
used.
(Continued)
10
MB90435 Series
Pin No.
*2
LQFP
4648
51 to 5653 to 58
57 , 5859 , 60
59 , 6261 to 64
QFP
*1
Pin name
P57
TOT0
P70 to P75
IN0 to IN5
P76 , P77
OUT2 , OUT3
IN6 , IN7
P80 to P83
PPG0 to
PPG3
Circuit
type
D
D
D
D
Function
General I/O port. This function is enabled when the 16-bit
reload timers 0 disables the output.
Output pin for the 16-bit reload timers 0. This function is
enabled when the 16-bit reload timers 0 enables the output.
General I/O ports. This function is always enabled.
Trigger input pins for input captures ICU0 to ICU5. Set the
corresponding Port Direction Register to input if this
function is used.
General I/O ports. This function is enabled when the OCU
disables the waveform output.
Event output pins for output compares OCU2 and OCU3. This
function is enabled when the OCU enables the waveform
output.
Trigger input pins for input captures ICU6 and ICU7. Set the
corresponding Port Direction Register to input and disable the
OCU waveform output if this function is used.
General I/O ports. This function is enabled when 8/16-bit PPG
disables the waveform output.
Output pins for 8/16-bit PPGs. This function is enabled when
8/16-bit PPG enables the waveform output.
P84 , P85
63 , 6465 , 66
OUT0 , OUT1
P86
6567
TIN1
P87
6668
TOT1
P90 to P93
67 to 7069 to 72
INT0 to INT3
7173P94DGeneral I/O port.
D
D
D
D
General I/O ports. This function is enabled when the OCU
disables the waveform output.
Waveform output pins for output compares OCU0 and OCU1.
This function is enabled when the OCU enables the waveform
output.
General I/O port. This function is always enabled.
Input pin for the 16-bit reload timers 1. Set the
corresponding Port Direction Register to input if this function is
used.
General I/O port. This function is enabled when the 16-bit
reload timers 0 disables the output.
Output pin for the 16-bit reload timers 1.This function is
enabled when the 16-bit reload timers 1 enables the output.
General I/O port. This function is always enabled.
External interrupt request input pins for INT0 to INT3. Set the
corresponding Port Direction Register to input if this function is
used.
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than V
• A voltage higher than the rated voltage is applied between V
• The AVcc power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, care must also be tak en in not allowing the analog po wer-supply v oltage (AV
exceed the digital power-supply voltage.
(2) Handling unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Theref or the y m ust be pulled up or pulled down through resistors . In this case those resistors should be
more than 2 kΩ.
Unused bi-directional pins should be set to the output state and can be left open, or the input state with the
above described connection.
(3) Using external clock
To use external clock, drive X0 pin only and leave X1 pin unconnected.
Below is a diagram of how to use external clock.
CC or lower than VSS is applied to an input or output pin.
CC and VSS.
CC, A VRH) to
MB90435 Series
X0
Open
X1
(4) Use of the sub-clock
Use one clock system parts when the sub-clock is not used. In that case, pull-down the pin X0A and leave the
pin X1A open. When using two clock system parts, a 32 kHz oscillator has to be connected to the X0A and X1A
pins.
CC/VSS
(5) Power supply pins (V
In products with multiple V
)
CC or VSS pins, the pins of a same potential are internally connected in the device to
avoid abnormal operations including latch-up. However you must connect the pins to an external power and a
ground line to lower the electro-magnetic emission le vel to pre v ent abnormal operation of strobe signals caused
by the rise in the ground level, and to conform to the total current rating.
Make sure to connect V
It is recommended to provide a bypass capacitor of around 0.1 µF between V
CC and VSS pins via the lowest impedance to power lines.
CC and VSS pins near the device.
VCC
VSS
VCC
VSS
VSS
16
VCC
VSS
MB90435
Series
VCC
VSS
VCC
MB90435 Series
(6) Pull-up/down resistors
The MB90435 Series does not support internal pull-up/down resistors (except Port0 − Port3 : pull-up
resistors) . Use external components where needed.
(7) Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via the shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines,
and make sure, to the utmost effort, that lines of oscillation circuits do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
(8) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (A V
turning-on the digital power supply (V
CC) .
CC, A VRH, A VRL) and analog inputs (AN0 to AN7) after
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage does not exceed AVRH or AV
CC (turning on/off the analog and digital power supplies simulta-
neously is acceptable) .
(9) Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter to AV
CC= VCC, AVSS= AVRH = VSS.
(10) N.C. Pin
The N.C. (internally connected) pin must be opened for use.
(11) Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 µs or more (0.2 V to 2.7 V) .
(12) Initialization
In the device, there are internal registers which are initialized only by a pow er-on reset. T o initialize these registers,
please turn on the power again.
(13) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions
In the Signed multiplication and division instructions (“DIV A, Ri” and “DIVW A, RWi”) , the value of the
corresponding bank register (DTB, ADB, USB, SSB) is set in “00
If the values of the corresponding bank registers (DTB, ADB, USB, SSB) are set to other than “00
H”.
H”, the remainder
by the execution result of the instruction is not stored in the register of the instruction operand.
(14) Using REALOS
The use of EI
2
OS is not possible with the REALOS real time operating system.
(15) Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit ev en
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
17
MB90435 Series
BLOCK DIAGRAM
■■■■
X0, X1
X0A, X1A
RST
HST
Clock
Controller
F2MC 16LX
CPU
SOT0
SCK0
SIN0
SOT1
SCK1
SIN1
SOT2
SCK2
SIN2
AV
CC
AVSS
AN0 to AN7
AVRH
AVRL
ADTG
RAM
2 K/4 K/6 K/8 K
ROM/Flash
64K/128 K/256 K
(ROM only)
Prescaler
UART0
Prescaler
UART1
(SCI)
Prescaler
Serial I/O
10-bit A/D
Converter
8 ch.
FMC-16 Bus
16-bit I/O
Timer
16-bit Input
Capture
8 ch.
16-bit Output
Compare
4 ch.
8/16-bit
PPG
4 ch.
16-bit Reload
Timer 2 ch.
External
Bus
Interface
External
Interrupt
8 ch.
IN0 to IN5
IN6/OUT2,
IN7/OUT3
OUT0, OUT1
PPG0 to PPG3
TIN0, TIN1
TOT0, TOT1
AD00 to AD15
A16 to A23
ALE
RD
WRL
WRH
HRQ
HAK
RDY
CLK
INT0 to INT7
18
■■■■ MEMORY MAP
The memory space of the MB90435 Series is shown below.
MB90435 Series
FFFFFF
FF0000
FEFFFF
FE0000
FDFFFF
FD0000
FCFFFF
FC0000
00FFFF
004000
003FFF
003900
0020FF
001FF5
001FF0
000100
0000BF
000000
MB90V540G
H
(FF bank)
H
H
(FE bank)
H
H
(FD bank)
H
H
(FC bank)
H
H
(Image of
H
H
Peripheral
H
H
H
ROM correction
H
H
H
Peripheral
H
ROM
ROM
ROM
ROM
External
ROM
FF bank)
External
RAM 8 K
External
FFFFFF
FF0000
00FFFF
004000
003FFF
003900
002000
0008FF
000100
0000BF
000000
MB90F437L (S)*
H
(FF bank)
H
External
H
(Image of
FF bank)
H
H
Peripheral
H
External
H
H
RAM 2 K
H
External
H
Peripheral
H
ROM
ROM
MB90F438L (S)/438L (S)
FFFFFF
H
FF0000
H
FEFFFF
H
FE0000
H
00FFFF
H
004000
H
003FFF
H
003900
H
002000
H
0010FF
H
000100
H
0000BF
H
000000
H
ROM
(FF bank)
ROM
(FE bank)
External
ROM
(Image of
FF bank)
Peripheral
External
RAM 4 K
External
Peripheral
MB90F439 (S) /439 (S)
FFFFFF
H
FF0000
H
FEFFFF
H
FE0000
H
FDFFFF
H
FD0000
H
FCFFFF
H
FC0000
H
00FFFF
H
004000
H
003FFF
H
003900
H
002100
H
0018FF
H
000100
H
0000BF
H
000000
H
ROM
(FF bank)
ROM
(FE bank)
ROM
(FD bank)
ROM
(FC bank)
External
ROM
(Image of
FF bank)
Peripheral
External
RAM 6 K
External
Peripheral
* : Under development
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits address are the same, the table in ROM can be referenced
without using the “far” specification in the pointer declaration.
For e xample, an attempt to access 00C000
FF exceeds 48 Kbytes, and its entire image cannot be sho wn in bank 00.The image betw een FF4000
FFFFFF
H is visible in bank 00, while the image between FF0000H and FF3FFFH is visible only in bank FF.
H accesses the value at FFC000H in ROM.The R OM area in bank
H and
19
MB90435 Series
■■■■ I/O MAP
AddressRegisterAbbreviation Access Resource nameInitial value
00
HPort 0 data registerPDR0R/WPort 0XXXXXXXXB
01HPort 1 data registerPDR1R/WPort 1XXXXXXXXB
02HPort 2 data registerPDR2R/WPort 2XXXXXXXXB
03HPort 3 data registerPDR3R/WPort 3XXXXXXXXB
04HPort 4 data registerPDR4R/WPort 4XXXXXXXXB
05HPort 5 data registerPDR5R/WPort 5XXXXXXXXB
06HPort 6 data registerPDR6R/WPort 6XXXXXXXXB
07HPort 7 data registerPDR7R/WPort 7XXXXXXXXB
08HPort 8 data registerPDR8R/WPort 8XXXXXXXXB
09HPort 9 data registerPDR9R/WPort 9XXXXXXXXB
0AHPort A data registerPDRAR/WPort A_ _ _ _ _ _ _XB
AddressRegisterAbbreviation Access Resource nameInitial value
47
H to 4BHProhibited
4CH
4DH
4EH
4FH
Input capture control status register 0/1
Input capture control status register 2/3
Input capture control status register 4/5
Input capture control status register 6/7
50HTimer control status register 0TMCSR0R/W
51HTimer control status register 0TMCSR0R/W_ _ _ _ 0 0 0 0B
55HTimer control status register 1TMCSR1R/W_ _ _ _ 0 0 0 0B
56HTimer register 1/reload register 1
57HTimer register 1/reload register 1
58H
59H
5AH
5BH
Output compare control status register 0
Output compare control status register 1
Output compare control status register 2
Output compare control status register 3
*1 : The interrupt request flag is cleared by the EI
*2 : The interrupt request flag is cleared by the EI
OS interrupt clear signal.
2
OS interrupt clear signal. A stop request is available.
Notes : • N/A : The interrupt request flag is not cleared by the EI
• For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags
are cleared by the EI
• At the end of EI
interrupt number. If one interrupt flag starts the EI
2
OS interrupt clear signal.
2
OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same
2
OS and in the meantime another interrupt flag is set by
a hardware ev ent, the later ev ent is lost because the flag is cleared by the EI
first event. So it is recommended not to use the EI
2
OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control
• If EI
2
OS for this interrupt number.
register (ICR) is asserted. This means that different interrupt sources share the same EI
which should be unique for each interrupt source. For this reason, when one interrupt source uses the
2
EI
OS, the other interrupt should be disabled.
MB90435 Series
2
OS interrupt clear signal.
2
OS clear signal caused by the
2
OS Descriptor
27
MB90435 Series
ELECTRICAL CHARACTERISTICS
■■■■
1.Absolute Maximum Ratings
ParameterSymbol
Power supply voltage
Input voltageV
Output voltageV
AVRH,
AVRL
Value
MinMax
V
CCVSS− 0.3VSS+ 6.0V
AV
CCVSS− 0.3VSS+ 6.0VVCC= AVCC*1
VSS− 0.3 VSS+ 6.0V
IVSS− 0.3 VSS+ 6.0V*2
OVSS− 0.3VSS+ 6.0V*2
UnitsRemarks
AVCC≥ AVRH/AVRL,
AVRH ≥ AVRL*1
(VSS= AVSS= 0.0 V)
Maximum clamp currentICLAMP− 2.0+ 2.0mA*6
Total maximum clamp current∑| I
“L” level max output currentI
“H” level max output currentIOH−15mA*3
“H” level avg. output currentI
“H” level max overall output current∑I
OHAV−4mA*4
OH−100mA
“H” level avg. overall output current∑IOHAV−50mA*5
Power consumptionP
Operating temperatureT
Storage temperatureT
*1 : AV
CC, AVRH, AVRL should not exceed VCC. Also, AVRH, AVRL should not exceed AVCC, and AVRL does not
D
A−40+105 °C
STG−55+150 °C
500mWFlash device
400mWMask ROM
exceed AVRH.
*2 : V
I and VO should not exceed VCC+ 0.3 V. VI should not exceed the specified ratings. However if the maximum
current to/from an input is limited by some means with external components, the I
V
I rating.
CLAMP rating supercedes the
*3 : The maximum output current is a peak value for a corresponding pin.
*4 : Average output current is an average current value observed for a 100 ms period for a corresponding pin.
*5 : Total average current is an average current value observed for a 100 ms period for all corresponding pins.
*6 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P90 to P97, PA0
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the V
CC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is
provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on result.
(Continued)
28
MB90435 Series
(Continued)
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input.
• Sample recommended circuits :
• Input/Output Equivalent circuits
Protective diode
VCC
Limiting
resistance
+B input (0 V to 16 V)
R
Note : Average output current = operating current × operating efficiency
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
P-ch
N-ch
29
MB90435 Series
2.Recommended Conditions
ParameterSymbol
V
Power supply voltage
AV
CC,
CC
Value
MinTypMax
UnitsRemarks
4.55.05.5V
3.55.05.5V
Under normal operation :
MB90F439 (S) /439 (S) /V540G
Under normal operation :
MB90F438L (S) /437L (S) /438L (S)
(VSS= AVSS= 0.0 V)
3.05.5VMaintain RAM data in stop mode
Smooth capacitorC
S0.0220.11.0µF*
Operating temperatureTA−40+105°C
*: Use a ceramic capacitor or a capacitor of better 4. AC characteristics. The V
CC Capacitor should be greater than
this capacitor.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
• C Pin Connection Diagram
C
C
S
30
3.DC Characteristics
(MB90F438L (S) /437L (S) /438L (S) : VCC= 3.5 V to 5.5 V, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
(MB90F439 (S) /439 (S) /V540G : VCC= 5.0 V ± 10%, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
Parameter
Input H
voltage
Input L
voltage
Output H
voltage
Output L
voltage
Input leak
current
Pull-up
resistance
Pull-down
resistance
Sym-
Pin nameCondition
bol
CMOS
hysteresis
IHS
V
input pin
TTL input
V
IH
pin
MD input
V
IHM
pin
CMOS
hysteresis
ILS
V
input pin
TTL input
V
IL
pin
MD input
V
ILM
pin
All output
V
OH
pins
All output
V
OL
pins
I
IL
P00 to P07,
P10 to P17,
R
P20 to P27,
UP
P30 to P37,
RST
R
DO
MD22550100kΩ
WN
VCC= 4.5 V,
I
OH=−4.0 mA
VCC= 4.5 V,
I
OL= 4.0 mA
VCC= 5.5 V,
V
SS< VI< VCC
MB90435 Series
Value
MinTypMax
0.8 V
CCVCC+ 0.3V
2.0V
VCC− 0.3VCC+ 0.3V
V
CC − 0.30.2 VCCV
0.8V
VSS− 0.3VCC + 0.3V
VCC − 0.5V
0.4V
−55µA
2550100kΩ
UnitsRemarks
(Continued)
31
MB90435 Series
(Continued)
(MB90F438L (S) /437L (S) /438L (S) : VCC= 3.5 V to 5.5 V, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
(MB90F439 (S) /439 (S) /V540G : V
Parameter
Power
supply
current*
Input
capacity
Sym-
Pin nameCondition
bol
Internal frequency : 16 MHz,
I
CC
At normal operating
Internal frequency : 16 MHz,
At Flash programming/erasing
I
CCS
Internal frequency : 16 MHz,
At sleep mode
VCC= 5.0 V ± 1%,
I
CTS
Internal frequency : 2 MHz,
At pseudo timer mode
VCC
CCL
I
I
CCLS
I
CCT
I
CCH1At stop, TA= 25 °C520µA
I
CCH2
Other than
AV
CC, AVSS,
AVRH,
IN
C
AVRL, C,
V
CC, VSS
Internal frequency : 8 kHz,
At sub operation, T
Internal frequency : 8 kHz,
At sub sleep, T
Internal frequency : 8 kHz,
At timer mode, T
At hardware standby mode,
T
A = 25 °C
CC= 5.0 V ± 10%, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
Value
MinTypMax
UnitsRemarks
4055mA
5070mAFlash device
1220mA
300600µA
6001100µAMB90F348L (S)
200400µA
MB90437L (S) /
438L (S)
400750µAMB90F438L (S)
A= 25 °C
A= 25 °C
A= 25 °C
50100µAMask ROM
150300µAFlash device
1540µA
725µA
50100µA
515pF
* : The power supply current testing conditions are when using the external clock.
32
4.AC Characteristics
(1) Clock Timing
(MB90F438L (S) /437L (S) /438L (S) : V
(MB90F439 (S) /439 (S) /V540G : V
ParameterSymb olPin name
MB90435 Series
CC= 3.5 V to 5.5 V, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
CC= 5.0 V ± 10%, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
Value
UnitsRemarks
MinTypMax
Oscillation frequency
Oscillation cycle time
Input clock pulse width
Input clock rise and fall
time
Machine clock frequency
Machine clock cycle time
• Clock Timing
316MHz V
f
CX0, X1
35MHz
f
CLX0A, X1A32.768kHz
62.5333nsV
CYLX0, X1
t
200333ns
t
LCYLX0A, X1A30.5µs
WH, PWLX010ns
P
P
WLH, PWLLX0A15.2µs
t
CR, tCFX0 5nsWhen using external clock
CP1.516MHz When using main clock
f
CC= 5.0 V±10%
VCC<4.5 (MB90F438L (S) /
437L (S) /438L (S) )
CC= 5.0 V±10%
VCC<4.5 (MB90F438L (S) /
437L (S) /438L (S) )
Duty ratio is about 30% to
70%.
fLCP8.192kHzWhen using sub-clock
t
CP62.5666nsWhen using main clock
t
LCP122.1µsWhen using sub-clock
X0
X0A
tCYL
0.8 VCC
0.2 VCC
PWHPWL
tCFtCR
tLCYL
0.8 VCC
0.2 VCC
PWLHPWLL
tCFtCR
33
MB90435 Series
• Guaranteed PLL operation range
Guaranteed operation range
(MB90F439(S)/439(S)/V540G)
Guaranteed operation range
(MB90F438L(S)/437L(S)/438L(S))
5.5
Power supply voltage
CC
V
(V)
4.5
3.5
1.5
Machine clock f
• External clock frequency and Machine clock frequency
×4×3×2×1
Machine clock
CP
(MHz)
f
16
12
9
8
Guaranteed PLL operation range
(MB90F438L(S)/437L(S)/438L(S))
Guaranteed PLL operation range
( MB90F439(S)/439(S)/V540G)
816
CP
(MHz)
PLL off
34
4
348
External clock f
C
(MHz)
16
AC characteristics are set to the measured reference voltage values below.
MB90435 Series
• Input signal waveform
Hysteresis Input Pin
0.8 VCC
0.2 VCC
TTL Input Pin
2.0 V
0.8 V
• Output signal waveform
Output Pin
2.4 V
0.8 V
35
MB90435 Series
(2) Clock Output Timing
(MB90F438L (S) /437L (S) /438L (S) : V
(MB90F439 (S) /439 (S) /V540G : V
ParameterSymbolPin nameCondition
CC= 3.5 V to 5.5 V, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
CC= 5.0 V ± 10%, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
Value
UnitsRemarks
MinMax
Cycle timet
CYC
CLKVCC= 5 V ± 10%
CLK↑ →CLK↓t
CLK
CHCL20ns
CHCL
t
2.4 V2.4 V
(3) Reset and Hardware Standby Input Timing
(MB90F438L (S) /437L (S) /438L (S) : VCC= 3.5 V to 5.5 V, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
(MB90F439 (S) /439 (S) /V540G : V
ParameterSymbol
Pin
name
62.5ns
tCYC
0.8 V
CC= 5.0 V ± 10%, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
Value
UnitsRemarks
MinMax
4 tCPnsUnder normal operation
Reset input timet
RSTLRST
Oscillation time of
oscillator + 4 t
CP
100µs
4 t
CPns
msIn stop mode
Pseudo timer mode
(MB90437L (S) /438L (S) )
Pseudo timer mode
(Other than MB90437L (S)
/438L (S) )
In sub clock mode, sub
2 t
CPµs
sleep mode and watch
mode
Hardware standby input timet
“t
cp” represents one cycle time of the machine clock.
HSTLHST4 tCPnsUnder normal operation
Oscillation time of oscillator is time that amplitude reached the 90%. In the crystal oscillator, the oscillation time is
between several ms to tens of ms. In FAR/ceramic oscillator, the oscillation time is between handreds of µs to
several ms. In the external clock, the oscillation time is 0 ns.
Any reset can not fully initialize the Flash Memory if it is performing the automatic algorithm.
36
MB90435 Series
• Under normal operation, Pseudo timer mode, Sub clock mode, Sub sleep mode, Watch mode
tRSTL, tHSTL
RST
• In stop mode
HST
RST
X0
90% of
amplitude
0.2 VCC
tRSTL
0.2 VCC0.2 VCC
0.2 VCC
Internal operation clock
Internal reset
Oscillation time of
oscillator
4 tCP
Oscillation setting time
Instruction execution
37
MB90435 Series
(4) Power On Reset
(MB90F438L (S) /437L (S) /438L (S) : V
(MB90F439 (S) /439 (S) /V540G : V
ParameterSymbol
name
Pin
CC= 3.5 V to 5.5 V, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
CC= 5.0 V ± 10%, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
Value
Condition
UnitsRemarks
MinMax
Power on rise timet
RVCC
0.0530ms*
Power off timet
* : V
CC must be kept lower than 0.2 V before power-on.
OFFVCC50msDue to repetitive operation
Notes : • The above values are used for creating a power-on reset.
• Some registers in the device are initialized only upon a po wer-on reset. To initialize these register, turn on
the power supply using the above values.
tR
VCC
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to
raise the voltage smoothly to suppress fluctuations as shown below.
In this case, change the supply voltage with the PLL clock not used. If the voltage drop is
1 V or fewer per second, however, you can use the PLL clock.
2.7 V
0.2 V0.2 V0.2 V
tOFF
38
VCC
3.0 V
VSS
RAM data being held
It is recommended to keep the
rising speed of the supply voltage
at 50 mV/ms or slower.
(5) Bus Timing (Read)
(MB90F438L (S) /437L (S) /438L (S) : V
(MB90F439 (S) /439 (S) /V540G : V
ParameterSymbolPin nameCondition
MB90435 Series
CC= 3.5 V to 5.5 V, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
CC= 5.0 V ± 10%, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
Value
Units Remarks
MinMax
ALE pulse widtht
LHLLALE
tCP/2 − 20ns
ALE,
Valid address→ALE↓timetAVLL
A16 to A23,
t
CP/2 − 20ns
AD00 to AD15
ALE↓→Address valid timet
LLAX
ALE,
AD00 to AD15
tCP/2 − 15ns
A16 toA23,
Valid address→RD
↓timetAVRL
AD00 to AD15,
tCP− 15ns
RD
Valid address→Valid data
input
RD
pulse widthtRLRHRD3 tCP/2 − 20ns
RD
↓→Valid data inputtRLDV
t
AVDV
A16 to A23,
AD00 to AD15
RD,
AD00 to AD15
5 tCP/2 − 60ns
3 tCP/2 − 60ns
RD,
RD
↑→Data hold timetRHDX
0ns
AD00 to AD15
RD
↓→ALE↑timetRHLHRD, ALEtCP/2 − 15ns
RD
↑→Address valid timetRHAXRD, A16 to A23tCP/2 − 10ns
A16 to A23,
Valid address→CLK↑timet
AVCH
AD00 to AD15,
t
CP/2 − 20ns
CLK
RD↓→CLK↑timetRLCHRD, CLKtCP/2 − 20ns
ALE↓→RD
↓timetLLRLALE, RDtCP/2 − 15ns
39
MB90435 Series
• Bus Timing (Read)
CLK
ALE
RD
A16 to A23
AD00 to AD15
2.4 V
0.8 V
2.4 V
tAVCH
2.4 V
2.4 V
tLHLL
tAVLL
2.4 V
0.8 V
0.8 V
tLLAX
tLLRL
tAVRLtRLDV
tAVDV
AddressRead data
2.4 V
0.8 V
tRLCH
2.4 V
0.8 V
tRLRH
0.8 VCC
0.2 V
CC
tRHLH
2.4 V
2.4 V
tRHAX
2.4 V
0.8 V
tRHDX
0.8 VCC
0.2 VCC
40
MB90435 Series
(6) Bus Timing (Write)
(MB90F438L (S) /437L (S) /438L (S) : V
(MB90F439 (S) /439 (S) /V540G : V
ParameterSymbolPin nameCondition
Valid address→WR
↓timetAVWL
WR pulse widthtWLWHWR3 tCP/2 − 20ns
CC= 3.5 V to 5.5 V, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
CC= 5.0 V ± 10%, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
Value
Units Remarks
MinMax
A16 to A23
AD00 to AD15,
CP− 15ns
t
WR
Valid data output→WR
WR
↑→Data hold timetWHDX
↑timetDVWH
WR↑→Address valid timetWHAX
WR
↑→ALE↑timetWHLHWR, ALEtCP/2 − 15ns
WR
↑→CLK↑timetWLCHWR, CLKtCP/2 − 20ns
AD00 to AD15,
WR
AD00 to AD15,
WR
A16 to A23,
WR
3 tCP/2 − 20ns
20ns
tCP/2 − 10ns
• Bus Timing (Write)
tWLCH
CLK
ALE
tAVWL
2.4 V
tWLWH
tWHLH
2.4 V
WR (WRL, WRH)
A16 to A23
AD00 to AD15
2.4 V
0.8 V
0.8 V
2.4 V
0.8 V
2.4 V
AddressWrite data
0.8 V
tDVWH
2.4 V
tWHAX
2.4 V
0.8 V
tWHDX
2.4 V
0.8 V
41
MB90435 Series
(7) Ready Input Timing
(MB90F438L (S) /437L (S) /438L (S) : V
(MB90F439 (S) /439 (S) /V540G : V
ParameterSymbolPin nameCondition
CC= 3.5 V to 5.5 V, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
CC= 5.0 V ± 10%, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
Value
UnitsRemarks
MinMax
RDY setup timet
RYHSRDY
45ns
RDY hold timetRYHHRDY0ns
Note : If the RDY setup time is insufficient, use the auto-ready function.
• Ready Input Timing
CLK
ALE
RD/WR
2.4 V
tRYHStRYHH
RDY
no WAIT is used.
RDY
When WAIT is used
(1 cycle).
42
0.8 V
CC
0.2 VCC
0.8 VCC
(8) Hold Timing
(MB90F438L (S) /437L (S) /438L (S) : V
ParameterSymbolPin nameCondition
(MB90F439 (S) /439 (S) /V540G : V
MB90435 Series
CC= 3.5 V to 5.5 V, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
CC= 5.0 V ± 10%, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
Value
UnitsRemarks
MinMax
Pin floating→HAK
↓timetXHALHAK
30t
CPns
HAK↑time→Pin valid timetHAHVHAKtCP2 tCPns
Note : There is more than 1 cycle from the time HRQ is read to the time the HAK
is changed.
• Hold Timing
HAK
Each pin
tXHAL
2.4 V
0.8 V
0.8 V
High impedance
2.4 V
tHAHV
2.4 V
0.8 V
(9) UART0/1, Serial I/O Timing
(MB90F438L (S) /437L (S) /438L (S) : V
(MB90F439 (S) /439 (S) /V540G : V
CC= 3.5 V to 5.5 V, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
CC= 5.0 V ± 10%, VSS= AVSS= 0.0 V, TA=−40 °C to +105 °C)
Value
ParameterSymbolPin nameCondition
MinMax
Serial clock cycle timet
SCK↓→SOT delay timet
Valid SIN→SCK↑t
SCK↑→Valid SIN hold timet
SCYCSCK0 to SCK2
SLOV
SCK0 to SCK2,
SOT0 to SOT2
SCK0 to SCK2,
IVSH
SIN0 to SIN2
SCK0 to SCK2,
SHIX
SIN0 to SIN2
Internal clock operation output pins are
L= 80 pF + 1 TTL.
C
8 t
CPns
−8080ns
100ns
60ns
Units Remarks
Serial clock “H” pulse widtht
Serial clock “L” pulse widtht
SCK↓→SOT delay timetSLOV
Valid SIN→SCK↑t
SCK↑→Valid SIN hold timet
SHSLSCK0 to SCK2
SLSHSCK0 to SCK24 tCPns
SCK0 to SCK2,
SOT0 to SOT2
SCK0 to SCK2,
IVSH
SIN0 to SIN2
SCK0 to SCK2,
SHIX
SIN0 to SIN2
Notes : • AC characteristic in CLK synchronized mode.
Analog port input currentI
Analog input voltage rangeV
AINAN0 to AN7−11µA
AINAN0 to AN7AVRLAVRHV
AVRHAVRL + 2.7AV
Reference voltage range
AVRL0AVRH − 2.7V
AAVCC5mA
I
Power supply current
I
AHAVCC 5µA*
400600µAFlash device
RAVRH
Reference voltage supply
current
Offset between input
channels
I
140260µAMask ROM
RHAVRH 5µA*
I
AN0 to AN7 4LSB
AVRL + 0.5
LSB
AVRH − 1.5
LSB
CPns
CPns
AVRL + 4.5
LSB
AVRH + 1.5
LSB
CCV
mV
mV
Internal
frequency :
16 MHz
Internal
frequency :
16 MHz
VCC= AVCC =
5.0 V ± 1%
* : When not using an A/D converter, this is the current (V
CC= AVCC= AVRH = 5.0 V) when the CPU is stopped.
Note: The functionality of the A/D converter is only guaranteed for VCC = 5.0 V ± 10 % (also for MB90F438L (S) /
437L (S) /438L (S) ) .
47
MB90435 Series
• A/D Converter Glossary
Resolution : Analog changes that are identifiable with the A/D converter
Linearity error : The deviation of the straight line connecting the zero transition point (“00 0000 0000” ←→ “00
0000 0001”) with the full-scale transition point (“11 1111 1110”
conversion characteristics
Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value
Total error : The total error is defined as a difference between the actual v alue and the theoretical value, which
includes zero-transition error/full-scale transition error and linearity error.
Total error
3FF
←→ “11 1111 1111”) from actual
Actual conversion
Value
0.5 LSB
1024
Analog input
[V]
Digital output
1 LSB = (Theoretical value)
3FE
3FD
004
003
002
001
AVRLAVRH
AVRH − AVRL
VOT (Theoretical value) = AVRL + 0.5 LSB [V]
VFST (Theoretical value) = AVRH − 1.5 LSB [V]
NT− {1 LSB × (N − 1) + 0.5 LSB}
Total error for digital output N =
V
(measured value)
Actual conversion
characteristics
Theoretical
characteristics
1 LSB
0.5 LSB
{1 LSB × (N − 1) + 0.5 LSB}
V
NT
[LSB]
48
NT : Voltage at a transition of digital output from (N − 1) to N
V
(Continued)
(Continued)
MB90435 Series
Linearity errorDifferential linearity error
3FF
3FE
3FD
004
Digital output
003
002
001
Linearity error of
digital output N
Actual conversion
value
{1 LSB × (N − 1) + VOT }
(measured value)
VOT
AVRLAVRHAVRLAVRH
NT− {1 LSB × (N − 1) + VOT}
V
=
Differential linearity error
of digital N
V
FST− VOT
1 LSB
=
1022
[V]
Theorential characteristics
N + 1
Actual conversion value
VFST
(measured value)
N
V
NT
Actual conversion
characteristics
Theoretical
characteristics
Analog inputAnalog input
1 LSB
V (
N+1) T− VNT
=
1 LSB
− 1 LSB [LSB]
N − 1
Digital output
N − 2
[LSB]
Acturel conversion
value
V(N + 1) T
(measured value)
(measured value)
VNT
V
OT : Voltage at transition of digital output from “000H” to “001H”
V
FST : Voltage at transition of digital output from “3FEH” to “3FFH”
• Notes on Using A/D Converter
Select the output impedance value for the e xternal circuit of analog input according to the following conditions, :
• Output impedance values of the external circuit of 15 kΩ or lower are recommended.
• When capacitors are connected to external pins, the capacitance of several thousand times the internal
capacitor value is recommended to minimized the eff ect of v oltage distribution between the e xternal capacitor
and internal capacitor.
Note : When the output impedance of the external circuit is too high, the sampling period for analog voltages ma y
not be sufficient (sampling period = 4.00 µs @machine clock of 16 MHz) .
• Equipment of analog input circuit model
Comparator
Analog input
3.2 kΩ Max.
30 pF Max.
•Error
The smaller the | AVRH − AVRL |, the greater the error would become relatively.
Note: Pins width and pins thickness include plating thickness.
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
5180
100-pin
Plastic LQFP
(FPT-100P-M05)
81
INDEX
100
130
0.65(.026)
"A"
C
2001 FUJITSU LIMITED F100008S-c-4-4
16.00±0.20(.630±.008)SQ
14.00±0.10(.551±.004)SQ
75
0.32±0.05
(.013±.002)
50
0.10(.004)
17.90±0.40
(.705±.016)
14.00±0.20
(.551±.008)
Details of "A" part
0.13(.005)
31
(Mounting height)
M
0.17±0.06
(.007±.002)
+0.35
–0.20
3.00
+.014
–.008
.118
0~8°
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25(.010)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches)
Note : Pins width and pins thickness include plating thickness.
51
7650
INDEX
100
125
0.50(.020)
C
2000 FUJITSU LIMITED F100007S-3c-5
0.20±0.05
(.008±.002)
0.08(.003)
0.08(.003)
Details of "A" part
+.008
+0.20
.059 –.004
–0.10
1.50
(Mounting height)
26
M
"A"
0.145±0.055
(.0057±.0022)
0°~8°
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
Dimensions in mm (inches)
57
MB90435 Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0207
FUJITSU LIMITED Printed in Japan
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