FUJITSU MB90420G, MB90425G DATA SHEET

查询MB90427GCPF供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13711-4E

16-Bit Original Microcontroller

CMOS

F2MC-16LX MB90420G/425G Series

MB90423GA/423GC/F423GA/F423GC/427GA/427GC/428GA/428GC/
MB90F428GA/F428GC/V420G

DESCRIPTIONS

■

The FUJITSU MB90420G/425G Series is a 16-bit general purpose high-capacity microcontroller designed for
vehicle meter control applications etc.

The instruction set retains the same A T architecture as the FUJITSU original F
further refinements including high-level language instructions, expanded addressing mode, enhanced (signed)
multipler-divider computation and bit processing.

2

MC-8L and F2MC-16L series, with

In addition, a 32-bit accumulator is built in to enable long word processing.

FEATURES

■

• 16-bit input capture (4 channels)
Detects rising, falling, or both edges.
16-bit capture register × 4
Pin input edge detection latches the 16-bit free-run timer counter value, and generates an interrupt request.

• 16-bit reload timer (2 channels)
16-bit reload timer operation (select toggle output or one-shot output)
Event count function selection provided

PACKAGES

■

Plastic QFP, 100-pin Plastic LQFP, 100-pin

(Continued)

(FPT-100P-M06) (FPT-100P-M05)

MB90420G/425G Series

• Watch timer (main clock)
Operates directly from oscillator clock.
Compensates for oscillator deviation
Read/write enabled second/minute/hour register
Signal interrupt

• 16-bit PPG (3 channels)
Output pins (3) , external trigger input pin (1)
Output clock frequencies : f

CP, fCP/2

2

, fCP/24, fCP/2

• Delay interrupt
Generates interrupt for task switching.
Interruptions to CPU can be generated/deleted by software setting.

• External interrupts (8 channels)
8-channel independent operation
Interrupt source setting available : “L” to “H” edge/ “H” to “L” edge/ “L” level/ “H” level.

• A/D converter
10-bit or 8-bit resolution × 8 channels (input multiplexed)
Conversion time : 6.13 µs or less (at f

CP = 16 MHz)

External trigger startup available (P50/INT0/ADTG)
Internal timer startup available (16-bit reload timer 1)

• UART (2 channels)
Full duplex double buffer type
Supports asynchronous/synchronous transfer (with start/stop bits)
Internal timer can be selected as clock (16-bit reload timer 0)
Asynchronous : 4808 bps, 5208 bps, 9615 bps, 10417 bps, 19230 bps, 38460 bps, 62500 bps, 500000 bps
Synchronous : 500 Kbps, 1Mbps, 2Mbps (at f

• CAN interface *

1

Conforms to CAN specifications version 2.0 Part A and B.
Automatic resend in case of error.
Automatic transfer in response to remote frame.
16 prioritized message buffers for data and messages for data and ID
Multiple message support
Receiving filter has flexible configuration : All bit compare/all bit mask/two partial bit masks
Supports up to 1 Mbps
CAN WAKEUP function (connects RX internally to INT0)

• LCD controller/driver (1 channel)
Segment driver and command driver with direct LCD panel (display) drive capability

• Low voltage/Program Looping detect reset *
Automatic reset when low voltage is detected
Program Looping detection function

• Stepping motor controller (4 channels)
High current output for all channels × 4
Synchronized 8/10-bit PWM for all channels × 2

• Sound generator
8-bit PWM signal mixed with tone frequency from 8-bit reload counter.
PWM frequencies : 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8 kHz (at f
Tone frequencies : 1/2 PWM frequency, divided by (reload frequency +1)

6

CP = 16 MHz)

2

CP = 16MHz)

(Continued)

2

MB90420G/425G Series

(Continued)

• Input/output ports
Push-pull output and Schmitt trigger input
Programmable in bit units for input/output or peripheral signals.

•Flash memory
Supports automatic programming, Embeded Algorithm
Flag indicates algorithm completion
Minato Electronics flash writer
Boot block configuration
Erasable by blocks
Block protection by external programming voltage

*1 : MB90420G series has 2 channels built-in, MB90425G series has 1 channel built-in
*2 : Built-in to MB90420GA/425GA series only. Not built-in to MB90420GC/425GC series.

Embeded Algorithm is a registered trademark of Advanced Micro Devices Inc.

TM

, write/erase/erase pause/erase resume instructions

3

MB90420G/425G Series

PRODUCT LINEUP

■

••••

MB90420G Series

Part

number

Parameter

Configuration
CPU
Clock

System clock

ROM
RAM
CAN interface
Low voltage/

CPU operation
detection reset

Packages
Emulator

dedicated
power supply*

* : When used with emulation pod MB2145-507, use DIP switch S2 setting. For details see the MB2145-50

Hardware Manual (2.7 “Emulator Dedicated Power Supply Pin”) .

MB90F423GA MB90F423GC MB90423GA MB90423GC MB90V420G

Flash ROM model Mask ROM model Evaluation model

F2MC-16LX CPU

1 system 2 systems 1 system 2 systems 2 systems

On-chip PLL clock multiplier type ( × 1, × 2, × 3, × 4, 1/2 when PLL stopped)
Minimum instruction execution time 62.5 ns (with 4 MHz oscillator × 4)

Flash ROM 128 KB Mask ROM 128 KB External

6 KB 6 KB 6 KB

2 channels

Yes No Yes No No

QFP100, LQFP100 PGA-256

 No

••••

MB90425G Series

Part number

MB90F428GA MB90F428GC MB90427GA MB90427GC MB90428GA MB90428GC

Parameter

Configuration Flash ROM model Mask ROM model
CPU

2

F

MC-16LX CPU

Clock 1 system 2 systems 1 system 2 systems 1 system 2 systems
System clock

On-chip PLL clock multiplier type ( × 1, × 2, × 3, × 4, 1/2 when PLL stopped)

Minimum instruction execution time 62.5 ns (with 4 MHz oscillator × 4)
ROM Flash ROM 128 KB Mask ROM 64 KB Mask ROM 128 KB
RAM 6 KB 4 KB 6 KB
CAN interface 1 channel
Low voltage/CPU

operation

Yes No Yes No Yes

No

detection reset
Packages QFP100, LQFP100
Emulator

dedicated



power supply

Note : MB90V420G can be used as evaluation model for MB90420G/425G series.

4

PIN ASSIGNMENTS

■

••••

QFP 100

SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7

V

SS

SEG8

SEG9
SEG10
SEG11

P36/SEG12
P37/SEG13
P40/SEG14
P41/SEG15
P42/SEG16
P43/SEG17
P44/SEG18

V
P45/SEG19
P46/SEG20
P47/SEG21

CC

C

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

MB90420G/425G Series

(TOP VIEW)

P06/PPG0/TOT1

P11/TOT0/WOT

P07/PPG1/TIN1

P12/TIN0/IN3

P13/IN2

P14/IN1

P15/IN0

COM0

COM1

COM2

COM3

100

1
2
3
4
5
6
7
8
9

99

98

97

96

95

94

93

92

P05/SCK1/TRG

P10/PPG2

88

89

90

91

P01/SOT0/INT5

P02/SCK0/INT6

P03/SIN1/INT7

P04/SOT1

84

85

86

87

P00/SIN0/INT4

X1
81

X0
80

V

SS

79

X0A

78

83

V

CC

82

P57/SGA

X1A

76

77

RST

75

P56/SGO/FRCK

74

P55/RX0

73

P54/TX0

72

DV

71

P87/PWM2M3

70

P86/PWM2P3

69

P85/PWM1M3

68

P84/PWM1P3

67

DV

66

P83/PWM2M2

65

P82/PWM2P2

64

P81/PWM1M2

63

P80/PWM1P2

62

DV

61
60

P77/PWM2M1

59

P76/PWM2P1

58

P75/PWM1M1

57

P74/PWM1P1

56

DV

55

P73/PWM2M0

54

P72/PWM2P0

53

P71/PWM1M0

52

P70/PWM1P0

51

DV

SS

CC

SS

CC

SS

29

28

27

26

V1

V0

P91/SEG23

P90/SEG22

30

V2

31

37

36

35

34

33

32

P61/AN1

P60/AN0

AVSSP50/INT0/ADTG

AVRH

AVCCV3

(FPT-100P-M06)

40

39

38

V

P63/AN3

P62/AN2

SS

43

42

41

P66/AN6

P65/AN5

P64/AN4

48

47

46

45

44

MD1

MD0

P52/INT2 (/TX1)

P51/INT1 (/RX1)

P67/AN7

50

49

P53/INT3

MD2

5

MB90420G/425G Series

••••

LQFP 100

(TOP VIEW)

P11/TOT0/WOT

P07/PPG1/TIN1

P12/TIN0/IN3

P10/PPG2

P13/IN2

P14/IN1

P15/IN0

COM0

COM1

COM2

COM3

SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7

V

SS

SEG8

SEG9
SEG10
SEG11

P36/SEG12
P37/SEG13
P40/SEG14
P41/SEG15
P42/SEG16
P43/SEG17
P44/SEG18

V
P45/SEG19
P46/SEG20
P47/SEG21

CC

100

98

99

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

C

97

96

95

94

93

92

91

90

P06/PPG0/TOT1

P05/SCK1/TRG

88

89

P01/SOT0/INT5

P02/SCK0/INT6

P03/SIN1/INT7

P04/SOT1

84

85

86

87

P00/SIN0/INT4

X1
81

X0
80

V

SS

79

X0A

78

83

V

CC

82

P57/SGA

X1A

76

77

RST

75

P56/SGO/FRCK

74

P55/RX0

73

P54/TX0

72

DV

71

P87/PWM2M3

70

P86/PWM2P3

69

P85/PWM1M3

68

P84/PWM1P3

67

DV

66
65

P83/PWM2M2

64

P82/PWM2P2

63

P81/PWM1M2

62

P80/PWM1P2

61

DV

60

P77/PWM2M1

59

P76/PWM2P1

58

P75/PWM1M1

57

P74/PWM1P1

56

DV

55

P73/PWM2M0

54

P72/PWM2P0

53

P71/PWM1M0

52

P70/PWM1P0

51

DV

SS

CC

SS

CC

SS

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

P53/INT3

MD2

MD1

MD0

P52/INT2 (/TX1)

P51/INT1 (/RX1)

P67/AN7

P66/AN6

P65/AN5

P64/AN4

V

P63/AN3

P62/AN2

P61/AN1

P60/AN0

AVSSP50/INT0/ADTG

AVRH

AVCCV3

V2

V1

V0

P91/SEG23

P90/SEG22

SS

(FPT-100P-M05)

6

PIN DESCRIPTIONS

■

MB90420G/425G Series

Pin no.

LQFP QFP

80 82 X0
81 83 X1 High speed oscillator output pin.

78 80 X0A

77 79 X1A
75 77 RST

83 85

84 86

85 87

Symbol

P00
SIN0 UART ch.0 serial data input pin.
INT4 INT4 external interrupt input pin.

P01

SOT0 UART ch.0 serial data output pin.

INT5 INT5 external interrupt input pin.

P02

SCK0 UART ch.0 serial clock input/output pin.

INT6 INT6 external interrupt input pin.

Circuit

type

High speed oscillator input pin.

A

Low speed oscillator input pin. If no oscillator is connected, apply
pull-down processing.

A

Low speed oscillator output pin. If no oscillator is connected, leave
open.

B Reset input pin.

General purpose input/output port.

G

General purpose input/output port.

G

General purpose input/output port.

G

Description

86 88

87 89

88 90

89 91

90 92

91 93

P03
SIN1 UART ch.1 serial data input pin.
INT7 INT7 external interrupt input pin.

P04

SOT1 UART ch.1 serial data output pin.

P05

SCK1 UART ch.1 serial clock input/output pin.

TRG 16-bit PPG ch.0-2 external trigger input pin.

P06

PPG0 16-bit PPG ch.0 output pin.
TOT1 16-bit reload timer ch.1 TOT output pin.

P07

PPG1 16-bit PPG ch.1 output pin.

TIN1 16-bit reload timer ch.1 TIN output pin.

P10

PPG2 16-bit PPG ch.2 output pin.

General purpose input/output port.

G

General purpose input/output port.

G

General purpose input/output port.

G

General purpose input/output port.

G

General purpose input/output port.

G

General purpose input/output port.

G

(Continued)

7

MB90420G/425G Series

Pin no.

LQFP QFP

92 94

93 95

94 to 96 96 to 98

97 to 100

1 to 8,

10 to 13

14 to 15 16 to 17

16 to 20,

22 to 24

99 to 100,

1 to 2

3 to 10,

12 to 15

18 to 22,

24 to 26

Symbol

P11

TOT0 16-bit reload timer ch.0 TOT output pin.

WOT Real-time watch timer WOT output pin.

P12
TIN0 16-bit reload timer ch.0 TIN output pin.

IN3 Input capture ch.3 trigger input pin.

P13 to P15

IN2 to IN0 Input capture ch.0-2 trigger input pins.

COM0 to

COM3

SEG0 to

SEG11

P36 to P37

SEG12 to

SEG13

P40 to P47

SEG14 to

SEG21

Circuit

type

General purpose input/output port.

G

General purpose input/output port.

G

General purpose input/output ports.

G

I LCD controller/driver common output pins.

I LCD controller/driver segment output pins.

General purpose output ports.

E

LCD controller/driver segment output pins.
General purpose input output ports.

E

LCD controller/driver segment output pins.

Description

26 to 27 28 to 29

34 36

36 to 39,

41 to 44

45 47

46 48

50 52

38 to 41,

43 to 46

P90 to P91

SEG22 to

SEG23

P50
INT0 INT0 external interrupt input pin.

ADTG A/D converter external trigger input pin.

P60 to P67

AN0 to

AN7

P51
INT1 INT1 external interrupt input pin.

(RX1 *

(TX1 *

1

) CAN interface 1 RX intput pin.

P52
INT2 INT2 external interrupt input pin.

1

) CAN interface 1 TX output pin.

P53
INT3 INT3 external interrupt input pin.

General purpose input output ports.

E

LCD controller/driver segment output pins.
General purpose input output ports.

G

General purpose input output ports.

F

A/D converter input pins.
General purpose input output port.

G

General purpose input output port.

G

General purpose input output port.

G

(Continued)

8

MB90420G/425G Series

Pin no.

LQFP QFP

52 to 55 54 to 57

57 to 60 59 to 62

62 to 65 64 to 67

67 to 70 69 to 72

Symbol

P70 to P73

PWM1P0

PWM1M0

PWM2P0

PWM2M0

P74 to P77

PWM1P1

PWM1M1

PWM2P1

PWM2M1

P80 to P83

PWM1P2

PWM1M2

PWM2P2

PWM2M2

P84 to P87

PWM1P3

PWM1M3

PWM2P3

PWM2M3

Circuit

type

H

H

H

H

Description

General purpose input output ports.

Stepping motor controller ch.0 output pins.

General purpose input output ports.

Stepping motor controller ch.1 output pins.

General purpose input output ports.

Stepping motor controller ch.2 output pins.

General purpose input output ports.

Stepping motor controller ch.3 output pins.

72 74

P54

General purpose input output port.

G

TX0 CAN interface 0 TX output pin.

73 75

P55

General purpose output port.

G

RX0 CAN interface 0 RX input pin.

74 76

P56
SGO Sound generator SG0 output pin.

General purpose input output port.

G

FRCK Free-run timer clock input pin.

76 78

P57

General purpose input output port.

G

SGA Sound generator SGA output pin.

28 to 31 30 to 33 V0 to V3  LCD controller /driver reference power supply pins.

56, 66 58, 68 DV

51, 61, 71 53, 63, 73 DV

CC 

SS 

High current output buffer with dedicated power supply input pins
(pin numbers 54-57, 59-62, 64-67, 69-72) .

High current output buffer with dedicated power supply GND pins

(pin numbers 54-57, 59-62, 64-67, 69-72) .
32 34 AVCC  A/D converter dedicated power supply input pin.
35 37 AV

SS  A/D converter dedicated GND supply pin.

33 35 AVRH  A/D converter Vref + input pin. Vref − AVss.

(Continued)

9

MB90420G/425G Series

(Continued)

Pin no.

Symbol

LQFP QFP

47
48

49
50

MD0
MD1

49 51 MD2 C/D *

Circuit

type

C Test mode input pins. Connect to V

2

Text mode input pin. Connect to VSS.

Description

CC.

25 27 C 

21, 82 23, 84 V

CC  Power supply input pins.

External capacitor pin. Connect an 0.1 µF capacitor between this

pin and V

SS.

9, 40, 79 11, 42, 81 VSS  GND power supply pins.

*1 : MB90420G series only.
*2 : Type C in the flash ROM models, type D in the mask ROM models.

10

MB90420G/425G Series

I/O CIRCUIT TYPE

■

Type Circuit Remarks

X1/X1A

• Oscillation feedback resistance :
approx. 1 MΩ (X0, X1 : MAIN)

• Oscillation feedback resistance :
approx. 10 MΩ (X0A, X1A : SUB)

A

X0/X0A

Standby control signal

• Pull-up resistance attached :
approx. 50 kΩ, hysteresis input

B

Hysteresis input

• Hysteresis input

C

Hysteresis input

• Pull-down resistance attached :
approx. 50 kΩ, hysteresis input

Hyteresis input

D

• CMOS output

• LCDC output

• Hysteresis input

E

LCDC output
Hysteresis input

(Continued)

11

MB90420G/425G Series

(Continued)

Type Circuit Remarks

• CMOS output

• Hysteresis input

• Analog input

F

Analog input

Hysteresis input

• CMOS output

• Hysteresis input

G

Hysteresis input

• CMOS high current output

• Hysteresis input

High current

H

Hysteresis input

• LCDC output

I

LCDC output

12

HANDLING DEVICES

■

Precautions for Handling Semiconductor Devices

• Strictly observe maximum rated voltages (prevent latchup)

MB90420G/425G Series

When CMOS integrated circuit devices are subjected to applied voltages higher than V
pins other than medium- and high-withstand voltage pins, or to voltages lower than V
excess of rated le vels are applied between V

CC and VSS, a phenomenon known as latchup can occur . In a latchup

CC at input and output

SS, or when voltages in

condition, supply current can increase dramatically and may destroy semiconductor elements. In using semi­conductor devices, always take sufficient care to avoid exceeding maximum ratings.

Also care must be taken when power to analog systems is switched on or off, to ensure that the analog power
supply (AV
do not exceed the digital power supply (V

CC, AVRH) , analog input and dedicated power supply for the high current output buffer pins (DVCC)

CC) .

Once the digital power supply (VCC) is switched on, the analog po wer (AVCC,AVRH) and dedicated power supply
for the high current output buffer pins (DV

CC) may be turned on in any sequence.

• Stable supply voltage

Even within the warranted operating range of V

CC supply voltage, sudden fluctuations in supply voltage can

cause abnormal operation. The recommended stability for ripple fluctuations (P-P values) at commercial fre­quencies (50 Hz to 60 Hz) should be within 10% of the standard V

CC value, and voltage fluctuations that occur

during switching of power supplies etc. should be limited to transient fluctuation rates of 0.1 V/ms or less.

• Power-on procedures

In order to prevent abnormal operation of the internal built-in step-down circuits, v oltage rise time during power­on should be attained within 50 µs (0.2 V to 2.7 V) .

• Treatment of unused pins

If unused input pins are left open, they ma y cause abnormal operation or latchup which may lead to permanent
damage to the semiconductor. An y such pins should be pulled up or pulled do wn through resistance of at least
2 kΩ.

Any unused input/output pins should be left open in output status, or if found set to input status , they should be
treated in the same way as input pins.

Any unused output pins should be left open.

• Treatment of A/D converter power supply pins

Even if the A/D converter is not used, pins should be connected so that AV

CC = VCC, and AVSS = AVRH = VSS.

• Use of external clock signals

Even when an external clock is used, a stabilization period is required following a power-on reset or release
from sub clock mode or stop mode. Also, when an e xternal clock is used it should drive only the X0 pin and the
X1 pin should be left open, as shown in Figure 3.

X0

OPEN

X1

MB90420G/425G Series

Sample external clock connection

13

MB90420G/425G Series

• Power supply pins

Devices are designed to pre vent problems such as latchup when multiple V

CC and VSS supply pins are used, by

providing internal connections between pins having the same potential. However, in order to reduce unwanted
radiation, and to prevent abnormal operation of strobe signals due to rise in ground level, and to maintain total
output current ratings, all such pins should always be connected externally to power supplies and ground.

As shown in figure below, all V
should be handled in the same way. If there are multiple V

CC power supply pins must have the same potential. All VSS power supply pins

CC or VSS systems, the device will not operate properly

even within the warranted operating range.

VCC
VSS

VCC

VSS

VCC

VSS

VSS

VCC

VSS

VCC

Power supply input pins (VCC/VSS)

In addition, care must be given to connecting the V
impedance as possible. It is recommended that a bypass capacitor of 1.0 µF be connected between V
V

SS as close to the pins as possible.

CC and VSS pins of this device to a current source with as little

CC and

• Proper sequence of A/D converter power supply analog input

A/D converter power (AV
(V

CC) is switched on. When power is shut off, the A/D converter power supply and analog input must be cut off

before the digital power supply is switched on (V
AVRH does not exceed AV
sure that the input voltage does not exceed AV

CC, AVRH) and analog input (AN0-AN7) must be applied after the digital power supply

CC) . In both power-on and shut-off, care should be taken that

CC. Even when pins which double as analog input pins are used as input por ts, be

CC. (There is no problem if analog power supplies and digital

power supplies are turned off and on at the same time.)

CC

• Handling the power supply for high-current output buffer pins (DV

Always apply pow er to high-current output b uffer pins (DV

CC, D VSS) after the digital po w er supply (VCC) is turned

on. Also when switching power off, alw a ys shut off the power supply to the high-current output b uffer pins (DV
DV

SS) before s witching off the digital po w er supply (VCC) . (There will be no problem if high-current output buffer

, DVSS)

CC,

pins and digital power supplies are turned off and on at the same time.)
Even when high-current output buff er pins are used as gener al purpose ports, the power for high current output

buffer pins (DV

CC, DVSS) should be applied to these pins.

• Pull-up/pull-down resistance

The MB90420G/425G series does not support internal pull-up/pull-down resistance. If necessary, use external
components.

14

MB90420G/425G Series

• Precautions for when not using a sub clock signal.

If the X0A and X1A pins are not connected to an oscillator, apply pull-down treatment to the X0A pin and leav e
the X1A pin open.

• Notes on during operation of PLL clock mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit ev en
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.

15

MB90420G/425G Series

BLOCK DIAGRAM

■

X0, X1
X0A, X1A
RST

P57/SGA
P56/SGO/FRCK
P55/RX0
P54/TX0
P53/INT3
P52/INT2 (/TX1)
P51/INT1 (/RX1)
P50/INT0/ADTG

P00/SIN0/INT4
P01/SOT0/INT5
P02/SCK0/INT6
P03/SIN1/INT7
P04/SOT1
P05/SCK1/TRG
P06/PPG0/TOT1
P07/PPG1/TIN1

P10/PPG2
P11/TOT0/WOT
P12/TIN0/IN3
P13/IN2
P14/IN1
P15/IN0

Clock control

circuit

RAM

ROM

Sound generator

CAN controller

Port 5

External interrupt

(8 ch)

UART0/1

Prescaler

Port 0

PPG0/1/2

Port 1

Reload timer

Real-time

Watch timer

ICU0/1/2/3

0/1

0/1

CPU

F2MC-16LX core

MC-16LX BUS

2

F

Interrupt

controller

Low voltage/
CPU operation
detection reset

Port 8

Stepping

motor

Controller

0/1/2/3

Port 7

Port 6

A/D converter

(8 ch)

Port 9

Port 4

Port 3

P87/PWM2M3

P86/PWM2P3

P85/PWM1M3

P84/PWM1P3

P83/PWM2M2

P82/PWM2P2

P81/PWM1M2

P80/PWM1P2

P77/PWM2M1

P76/PWM2P1

P75/PWM1M1

P74/PWM1P1

P73/PWM2M0

P72/PWM2P0

P71/PWM1M0

P70/PWM1P0

P67 to P60/
AN7 to AN0

AV

CC/AVSS

AVRH

P91, P90/

SEG23, SEG22

P47 to P40/

SEG21 to SEG14

P37, P36/

SEG13 to SEG12

Free-run timer

Evaluation device (MB90V420G)
No built-in ROM
Built-in RAM is 6 KB.

LCD controller/

driver

SEG11 to SEG0

COM3 to COM0

V3 to V0

Note: MB90420G series is equipped with 2-channel CAN interface and MB90425G series is equipped with 1-channel

CAN interface. MB90F423GA, MB90423GA, MB90F428GA, MB90427GA and MB90428GA have low volt­age/CPU operation detection reset. MB90F423GC, MB90423GC , MB90F428GC, MB90427GC, MB90428GC
and MB90V420G do not have low voltage/CPU operation detection reset.
See “■ Product Lineup” for detail.

16

■■■■ MEMORY MAP

000000H

0000C0H

MB90420G/425G Series

Single chip mode

(with ROM mirror function)

Peripheral area

000100H

Address #2

003900

004000H

010000H

Address #1

FFFFFFH

Register

RAM area

H

Peripheral area

ROM area

(FF bank image)

ROM area

: Internal access memory
: Access prohibited

Parts No. Address #1 Address #2

MB90423GA/GC FE0000

H 001900H

MB90427GA/GC FF0000H 001100H

MB90428GA/GC FE0000H 001900H
MB90F423GA/GC FE0000H 001900H
MB90F428GA/GC FE0000H 001900H

MB90V420G FE0000H 001900H

Note : To select models without the ROM mirror function, see the “ROM Mirror Function Selection Module.” The

image of the ROM data in the FF bank appears at the top of the 00 bank, in order to enable efficient use of
small C compiler models. The lower 16-bit address for the FF bank will be assigned to the same address,
so that tables in ROM can be referenced without declaring a “far” indication with the pointer. For example
when accessing the address 00C000

H, the actual access is to address FFC000H in ROM. Here the FF bank

ROM area exceeds 48 KB, so that it is not possible to see the entire area in the 00 bank image. Therefore
because the ROM data from FF4000
recommended that the ROM data table be stored in the area from FF4000

H to FFFFFFH will appear in the image from 004000H to 00FFFFH, it is

H to FFFFFFH.

17

MB90420G/425G Series

I/O MAP

■

• Other than CAN Interface

Address Register name Symbol Read/write Peripheral function Initial value

00

H Port 0 data register PDR0 R/W Port 0 XXXXXXXX

01

H Port 1 data register PDR1 R/W Port 1 - - XXXXXX

02H (Disabled)
03

H Port 3 data register PDR3 R/W Port 3 XX - - - - - -

04

H Port 4 data register PDR4 R/W Port 4 XXXXXXXX

05H Port 5 data register PDR5 R/W Port 5 XXXXXXXX
06

H Port 6 data register PDR6 R/W Port 6 XXXXXXXX

07

H Port 7 data register PDR7 R/W Port 7 XXXXXXXX

08H Port 8 data register PDR8 R/W Port 8 XXXXXXXX
09

H Port 9 data register PDR9 R/W Port 9 - - - - - -XX

0A

H to

0F

H

10H Port 0 direction register DDR0 R/W Port 0 0 0 0 0 0 0 0 0

(Disabled)

11

H Port 1 direction register DDR1 R/W Port 1 - - 0 0 0 0 0 0

12

H (Disabled)

13H Port 3 direction register DDR3 R/W Port 3 0 0 - - - - - -
14

H Port 4 direction register DDR4 R/W Port 4 0 0 0 0 0 0 0 0

15

H Port 5 direction register DDR5 R/W Port 5 0 0 0 0 0 0 0 0

16

H Port 6 direction register DDR6 R/W Port 6 0 0 0 0 0 0 0 0

17H Port 7 direction register DDR7 R/W Port 7 0 0 0 0 0 0 0 0
18

H Port 8 direction register DDR8 R/W Port 8 0 0 0 0 0 0 0 0

19

H Port 9 direction register DDR9 R/W Port 9 - - - - - - 0 0

1AH Analog input enable ADER R/W Port 6, A/D 1 1 1 1 1 1 1 1

1B

H to

1F

H

20

H A/D control status register lower ADCSL R/W

(Disabled)

0 0 0 0 0 0 0 0

21H A/D control status register higher ADCSH R/W 0 0 0 0 0 0 0 0

A/D converter

22

H A/D data register lower ADCRL R XXXXXXXX

23

H A/D data register higher ADCRH R/W 0 0 1 0 1 XXX

24H

R/W

XXXXXXXX

Compare clear register CPCLR

25

H R/W XXXXXXXX

18

26

H

Timer data register TCDT

H R/W 0 0 0 0 0 0 0 0

27

R/W 0 0 0 0 0 0 0 0

16-bit free-run timer

28H Timer control status register lower TCCSL R/W 0 0 0 0 0 0 0 0
29

H Timer control status register higher TCCSH R/W 0 - - 0 0 0 0 0

(Continued)

MB90420G/425G Series

Address Register name Symbol Read/write Peripheral function Initial value

2A

H PPG0 control status register lower PCNTL0 R/W

16-bit PPG0

2BH PPG0 control status register higher PCNTH0 R/W 0 0 0 0 0 0 0 -

2C

H PPG1 control status register lower PCNTL1 R/W

16-bit PPG1

2D

H PPG1 control status register higher PCNTH1 R/W 0 0 0 0 0 0 0 -

2E

H PPG2 control status register lower PCNTL2 R/W

16-bit PPG2

2FH PPG2 control status register higher PCNTH2 R/W 0 0 0 0 0 0 0 -

30

H External interrupt enable ENIR R/W

31

H External interrupt request EIRR R/W 0 0 0 0 0 0 0 0

External interrupt

32H External interrupt level lower ELVRL R/W 0 0 0 0 0 0 0 0
33

H External interrupt level higher ELVRH R/W 0 0 0 0 0 0 0 0

34

H Serial mode register 0 SMR0 R/W

35H Serial control register 0 SCR0 R/W 0 0 0 0 0 1 0 0
36

Input data register 0/

H

Output data register 0

SIDR0/

SODR0

R/W XXXXXXXX

UART 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 - 0 0

37

H Serial status register 0 SSR0 R/W 0 0 0 0 1 0 0 0

38H Serial mode register 1 SMR1 R/W
39

H Serial control register 1 SCR1 R/W 0 0 0 0 0 1 0 0

3A
3B

Input data register 1/

H

Output data register 1

H Serial status register 1 SSR1 R/W 0 0 0 0 1 0 0 0

SIDR1/

SODR1

R/W XXXXXXXX

UART1

0 0 0 0 0 − 0 0

3CH (Disabled)
3D

H Clock division control register 0 CDCR0 R/W Prescaler 0 - - - 0 0 0 0

3E

H CAN wake-up control register CWUCR R/W CAN - - - - - - - 0

3FH Clock division control register 1 CDCR1 R/W Prescaler 0 - - - 0 0 0 0

40

H to 4FH Area reserved for CAN interface 0

50

H Timer control status register 0 lower TMCSR0L R/W

51H
52

53

Timer control status register 0 high­er

H

Timer register 0/
Reload register 0

H XXXXXXXX

TMCSR0H R/W - - - 0 0 0 0 0

16-bit reload timer 0

TMR0/

TMRLR0

R/W

54H Timer control status register 1 lower TMCSR1L R/W
55
56

57
58H Watch timer control register lower WTCRL R/W
59

Timer control status register 1 high-

H

er

H

Timer register 1/
Reload register 1

H XXXXXXXX

TMCSR1H R/W - - - 0 0 0 0 0

16-bit reload timer 1

TMR1/

TMRLR1

R/W

Real-time

H Watch timer control register higher WTCRH R/W 0 0 0 0 0 0 0 0

watch timer

0 0 0 0 0 0 0 0

XXXXXXXX

0 0 0 0 0 0 0 0

XXXXXXXX

0 0 0 - - 0 0 0

(Continued)

19

MB90420G/425G Series

Address Register name Symbol Read/write Peripheral function Initial value

5A

H Sound control register lower SGCRL R/W

5BH Sound control register higher SGCRH R/W 0 - - - - - 0 0
5C

H Frequency data register SGFR R/W XXXXXXXX

Sound generator

5D

H Amplitude data register SGAR R/W 0 0 0 0 0 0 0 0

5E

H Decrement grade register SGDR R/W XXXXXXXX

5FH Tone count register SGTR R/W XXXXXXXX

0 0 0 0 0 0 0 0

60

H

XXXXXXXX

Input capture register 0 IPCP0 R

61

H XXXXXXXX

Input capture 0/1

62H

XXXXXXXX

Input capture register 1 IPCP1 R

63

H XXXXXXXX

64

H

XXXXXXXX

Input capture register 2 IPCP2 R

65

H XXXXXXXX

Input capture 2/3

66

H

XXXXXXXX

Input capture register 3 IPCP3 R

H XXXXXXXX

67
68H Input capture control status 0/1 ICS01 R/W Input capture 0/1 0 0 0 0 0 0 0 0
69

H (Disabled)

6A

H Input capture control status 2/3 ICS23 R/W Input capture 2/3 0 0 0 0 0 0 0 0

6B

H (Disabled)

6CH LCD control register lower LCRL R/W
6D

H LCD control register higher LCRH R/W 0 0 0 0 0 0 0 0

6E

Low voltage/CPU operation

H

detection reset control register

LVRC R/W

LCD controller/

driver

Low voltage/CPU opera-

tion detection reset

0 0 0 1 0 0 0 0

1 0 1 1 1 0 0 0

6FH ROM mirror ROMM W ROM mirror XXXXXXX1

70

H to 7FH Area reserved for CAN interface 1

20

80

H PWM control register 0 PWC0 R/W

Stepping motor

controller0

0 0 0 0 0 - - 0
81H (Disabled)
82

H PWM control register 1 PWC1 R/W

83

H (Disabled)

Stepping motor

controller1

0 0 0 0 0 - - 0

84H PWM control register 2 PWC2 R/W Stepping motor controller2 0 0 0 0 0 - - 0
85

H (Disabled)

86

H PWM control register 3 PWC3 R/W Stepping motor controller3 0 0 0 0 0 - - 0

87

9D

H to

H

(Disabled)

(Continued)

MB90420G/425G Series

Address Register name Symbol Read/write Peripheral function Initial value

9E

H ROM correction control register PACSR R/W

9F

H Delay interrupt/release DIRR R/W Delayed interrupt - - - - - - - 0

A0H Power saving mode LPMCR R/W
A1

H Clock select CKSCR R/W 1 1 1 1 1 1 0 0

A2

A7

H to

H

(Disabled)

Address match

detection function

Power saving

control circuit

- - - - - 0 - 0

0 0 0 1 1 0 0 0

A8H Watchdog control WDTC R/W Watchdog timer XXXXX 1 1 1
A9

H Time base timer control register TBTC R/W Time base timer 1 - - 0 0 1 0 0

AA

H Watch timer control register WTC R/W

ABH to

AD

H

AE

H Flash control register FMCS R/W Flash interface 0 0 0 X 0 XX 0

AF

H (Disabled)

(Disabled)

B0H Interrupt control register 00 ICR00 R/W
B1

H Interrupt control register 01 ICR01 R/W 0 0 0 0 0 1 1 1

B2

H Interrupt control register 02 ICR02 R/W 0 0 0 0 0 1 1 1

B3

H Interrupt control register 03 ICR03 R/W 0 0 0 0 0 1 1 1

Watch timer

(sub-clock)

1 X 0 0 0 0 0 0

0 0 0 0 0 1 1 1

B4H Interrupt control register 04 ICR04 R/W 0 0 0 0 0 1 1 1
B5

H Interrupt control register 05 ICR05 R/W 0 0 0 0 0 1 1 1

B6

H Interrupt control register 06 ICR06 R/W 0 0 0 0 0 1 1 1

B7H Interrupt control register 07 ICR07 R/W 0 0 0 0 0 1 1 1

Interrupt controller

B8

H Interrupt control register 08 ICR08 R/W 0 0 0 0 0 1 1 1

B9

H Interrupt control register 09 ICR09 R/W 0 0 0 0 0 1 1 1

BAH Interrupt control register 10 ICR10 R/W 0 0 0 0 0 1 1 1
BB

H Interrupt control register 11 ICR11 R/W 0 0 0 0 0 1 1 1

BC

H Interrupt control register 12 ICR12 R/W 0 0 0 0 0 1 1 1

BDH Interrupt control register 13 ICR13 R/W 0 0 0 0 0 1 1 1
BE

H Interrupt control register 14 ICR14 R/W 0 0 0 0 0 1 1 1

BF

H Interrupt control register 15 ICR15 R/W 0 0 0 0 0 1 1 1

C0H to

FF

H

(Disabled)

(Continued)

21

MB90420G/425G Series

Address Register name Symbol Read/write Peripheral function Initial value

1FF0

H ROM correction address 0 PADR0 R/W

1FF1H ROM correction address 1 PADR0 R/W XXXXXXXX
1FF2

H ROM correction address 2 PADR0 R/W XXXXXXXX

1FF3

H ROM correction address 3 PADR1 R/W XXXXXXXX

1FF4

H ROM correction address 4 PADR1 R/W XXXXXXXX

Address match

detection function

1FF5H ROM correction address 5 PADR1 R/W XXXXXXXX

3900

391F

H to

H

(Disabled)

XXXXXXXX

3920

H

PPG0 down counter register PDCR0 R

3921

H 1 1 1 1 1 1 1 1

3922

H

PPG0 cycle setting register PCSR0 W

H XXXXXXXX

3923

16-bit PPG 0

3924H

PPG0 duty setting register PDUT0 W

3925

H XXXXXXXX

3926

3927

H to

H

(Disabled)

3928H

PPG1 down counter register PDCR1 R

3929

H 1 1 1 1 1 1 1 1

392A

H

PPG1 cycle setting register PCSR1 W

H XXXXXXXX

392B

16-bit PPG 1

392CH

PPG1 duty setting register PDUT1 W

392D

H XXXXXXXX

392E

392F

H to

H

(Disabled)

3930H

PPG2 down counter register PDCR2 R

3931

H 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

XXXXXXXX

XXXXXXXX

1 1 1 1 1 1 1 1

XXXXXXXX

XXXXXXXX

1 1 1 1 1 1 1 1

22

3932

H

PPG2 cycle setting register PCSR2 W

H XXXXXXXX

3933
3934

H

16 bit PPG 2

PPG2 duty setting register PDUT2 W

3935

H XXXXXXXX

3936H to

3959

H

(Disabled)

XXXXXXXX

XXXXXXXX

(Continued)

MB90420G/425G Series

Address Register name Symbol Read/write Peripheral function Initial value

395A

H

395B
395C
395D
395E

Sub second data register WTBR R/W

H XXXXXXXX
H - - - XXXXX
H Second data register WTSR R/W - - XXXXXX
H Minute data register WTMR R/W - - XXXXXX

Real time

watch timer

XXXXXXXX

395FH Hour data register WTHR R/W - - - XXXXX

3960

396B

396C

397F
3980H

H to

LCD display RAM VRAM R/W

H

H to

H

(Disabled)

LCD controller/

driver

XXXXXXXX

XXXXXXXX

PWM1 compare register 0 PWC10 R/W

3981

H - - - - - - XX

3982

H

PWM2 compare register 0 PWC20 R/W

H - - - - - - XX

3983
3984

H PWM1 select register 0 PWS10 R/W - - 0 0 0 0 0 0

3985

H PWM2 select register 0 PWS20 R/W - 0 0 0 0 0 0 0

3986H to

3987

H

(Disabled)

Stepping motor

controller 0

XXXXXXXX

3988

H

XXXXXXXX

PWM1 compare register 1 PWC11 R/W

3989

H - - - - - - XX

398A

H

PWM2 compare register 1 PWC21 R/W

H - - - - - - XX

398B
398C

H PWM1 select register 1 PWS11 R/W - - 0 0 0 0 0 0

398D

H PWM2 select register 1 PWS21 R/W - 0 0 0 0 0 0 0

398EH to

398F

H

3990

H

(Disabled)

Stepping motor

controller 1

XXXXXXXX

XXXXXXXX

PWM1 compare register 2 PWC12 R/W

3991

H - - - - - - XX

3992H

PWM2 compare register 2 PWC22 R/W

3993

H - - - - - - XX

3994

H PWM1 select register 2 PWS12 R/W - - 0 0 0 0 0 0

Stepping motor

controller 2

XXXXXXXX

3995H PWM2 select register 2 PWS22 R/W - 0 0 0 0 0 0 0

3996

3997

H to

H

(Disabled)

(Continued)

23

MB90420G/425G Series

(Continued)

Address Register name Symbol Read/write Peripheral function Initial value

3998

H

XXXXXXXX

PWM1 compare register 3 PWC13 R/W

3999

H - - - - - - XX

399A

H

PWM2 compare register 3 PWC23 R/W

399B

H - - - - - - XX

399C

H PWM1 select register 3 PWS13 R/W - - 0 0 0 0 0 0

Stepping motor

controller 3

XXXXXXXX

399DH PWM2 select register 3 PWS23 R/W - 0 0 0 0 0 0 0

399E

H to

39FF

H

3A00

H to

3AFF

H

3B00H to

3BFF

H

3C00

H to

3CFF

H

3D00

H to

3DFF

H

3E00H to

3EFF

H

Area reserved for CAN interface 0

Area reserved for CAN interface 1

Area reserved for CAN interface 0

Area reserved for CAN interface 1

(Disabled)

(Disabled)

• Initial value symbols :
“0” initial value 0.
“1” initial value 1.
“X” initial value undetermined
“-” initial value undetermined (none)

• Write/read symbols :
“R/W” read/write enabled
“R” read only
“W” write only

• Addresses in the area 0000

H to 00FFH are reserved for the principal functions of the MCU. Read access

attempts to reserved areas will result in an “X” value. Also, wr ite access to reserved areas is prohibited.

24

• I/O Map for CAN Interface

Address

CAN0 CAN1

000040

H 000070H

Message buffer valid area BVALR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

000041

H 000071H

MB90420G/425G Series

Register name Symbol

Read/

write

Initial value

000042H 000072H
000043

H 000073H

000044H 000074H
000045

H 000075H

000046H 000076H
000047

H 000077H

000048H 000078H
000049

H 000079H

00004AH 00007AH
00004B

H 00007BH

00004CH 00007CH
00004D

H 00007DH

00004EH 00007EH
00004F

H 00007FH

003C00H 003D00H
003C01

H 003D01H

003C02H 003D02H
003C03

H 003D03H

003C04H 003D04H
003C05

H 003D05H

Transmission request register TREQR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Transmission cancel register TCANR (W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Transmission completed register TCR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Receiving completed register RCR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Remote request receiving register RRTRR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Receiving overrun register ROVRR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Receiving interrupt enable register RIER (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Control status register CSR (R/W, R) 0 0 - - - 0 0 0 0 - - - - 0 - 1

Last event indicator register LEIR (R/W) - - - - - - - - 0 0 0 - 0 0 0 0

RX/TX error counter RTEC (R) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

003C06H 003D06H
003C07

H 003D07H

003C08H 003D08H
003C09

H 003D09H

003C0AH 003D0AH
003C0B

H 003D0BH

003C0CH 003D0CH
003C0D

H 003D0DH

003C0EH 003D0EH
003C0F

H 003D0FH

Bit timing register BTR (R/W) - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

IDE register IDER (R/W) XXXXXXXX XXXXXXXX

Transmission RTR register TRTRR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Remote frame receiving wait register RFWTR (R/W) XXXXXXXX XXXXXXXX

Transmission interrupt enable register TIER (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

(Continued)

25

MB90420G/425G Series

Address

CAN0 CAN1

003C10
003C11

H 003D10H
H 003D11H

003C12H 003D12H
003C13

H 003D13H

003C14H 003D14H
003C15

H 003D15H

003C16H 003D16H
003C17

H 003D17H

003C18H 003D18H
003C19

H 003D19H

003C1AH 003D1AH
003C1B

003A00H

003A1F

H 003D1BH

to

H

003B00H

to

003B1F
003A20H 003B20H
003A21

H 003B21H

003A22H 003B22H
003A23

H 003B23H

003A24H 003B24H
003A25

H 003B25H

003A26H 003B26H
003A27

H 003B27H

Register name Symbol

Read/

write

Initial value

XXXXXXXX XXXXXXXX

Acceptance mask select register AMSR (R/W)

XXXXXXXX XXXXXXXX

XXXXXXXX XXXXXXXX

Acceptance mask register 0 AMR0 (R/W)

XXXXX- - - XXXXXXXX

XXXXXXXX XXXXXXXX

Acceptance mask register 1 AMR1 (R/W)

XXXXX- - - XXXXXXXX

General purpose RAM  (R/W) XXXXXXXX to XXXXXXXX

H

XXXXXXXX XXXXXXXX

ID register 0 IDR0 (R/W)

XXXXX- - - XXXXXXXX

XXXXXXXX XXXXXXXX

ID register 1 IDR1 (R/W)

XXXXX- - - XXXXXXXX

003A28H 003B28H
003A29

H 003B29H

003A2AH 003B2AH
003A2B

H 003B2BH

003A2CH 003B2CH
003A2D

H 003B2DH

003A2EH 003B2EH
003A2F

H 003B2FH

003A30H 003B30H
003A31

H 003B31H

003A32H 003B32H
003A33

H 003B33H

26

XXXXXXXX XXXXXXXX

ID register 2 IDR2 (R/W)

XXXXX- - - XXXXXXXX

XXXXXXXX XXXXXXXX

ID register 3 IDR3 (R/W)

XXXXX- - - XXXXXXXX

XXXXXXXX XXXXXXXX

ID register 4 IDR4 (R/W)

XXXXX- - - XXXXXXXX

(Continued)