FUJITSU MB86291A DATA SHEET
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP for Graphics Control
Graphics Display Controller
MB86291A
DESCRIPTION
■■■■
The MB86291A is an evolved version of the Fujitsu MB86290A graphics controller designed for use in a car
navigation system or amusement equipment. The MB86291A is a graphics display controller with a geometr y
processor, digital video capture facility, and on-chip SDRAM.
Embedding SDRAM implements data transfer at a higher bandwidth, resulting in faster drawing. Integrating the
geometry processor reduces the CPU load, thereby improving the performance of the entire system.
DS04-31102-1E
FEATUERS
■■■■
• Operating frequency : 100 MHz (External clock of 14.32 MHz Max)
• Geometry processor : Capable of executing operations for geometric transfor mation and surface front/rear
evaluation.
• Memory block: Embedded 16-Mbit SDRAM
• Video capture block: Embedded f acility to capture digital video images, f or e xample , from TV, capab le of easily
implementing “Picture in Picture” and video graphics superimposing.
• Host interface: Enables direct connection to var ious CPUs (Fujitsu SparcLite, Hitachi SH3/4 or NEC V83x) .
(Continued)
PACKAGE
■■■■
208-pin plastic QFP
(FPT-208P-M04)
MB86291A
(Continued)
• Drawing features:
• Drawing at a peak rate of 800 Mpixels per second (at an internal operating frequency of 100 MHz)
• 2D drawing functions: Point, line, triangle, polygon, BLT, and pattern drawing
• 3D drawing functions: Point, line, and triangle drawing, and hidden surface removal by Z-buffering
• Special effects: Anti-aliasing, bold/dashed-line processing, alpha blending, Gouraud shading, texture
mapping (bilinear filtering, perspective correct) , and tiling
• Display features :
• Maximum display resolution supported : 1024×768 pixels
• Color display either with a color palette of 8 bits per pix el or directly using 5-bit RGB colors of 16 bits per pixel
• Overlaying four layers of screen, of which two lower layers can be divided into the left and right parts
• Supporting two 64×64-pixel hardware cursors
• Output of analog RGB and digital RGB signals
• Capable of superimposing using an external synchronization mode
• Power-supply voltage : Two power supplies at 2.5 V±0.2 V for internal circuits and SDRAM, and 3.3 V±0.2 V
for I/O parts
• Package: Plastic QFP with 208 pins (with a lead pitch of 0.5 mm)
• Process technology : 0.25 µm CMOS
2
■■■■ PIN ASSIGNMENT
VSS208
HSYNC206
VSYNC205
CSYNC204
VSS203
DCLKO202
VDDE201
VSS
VCC0
VCC1
VSS
VCC2
VDDE
VSS
VCC3
VDDI
VSS
VDDE
VSS
VCC4
VDDI
VSS
VCC5
VDDE
CLKSEL0
CLKSEL1
RESET
MODE0
MODE1
VSS
VCC6
MODE2
TESTL0
VCC7
VSS
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
GV207
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
VI7200
VI6199
VI5198
VI4197
VI3196
VI2195
VI1194
VI0193
VDDI192
VSS191
DCLKI190
(TOP VIEW)
EO189
RESERVE188
RESERVE187
RESERVE186
RESERVE185
RESERVE184
TESTH5183
CCLK182
VDDE181
VSS180
A24179
A23178
A22
177
A21
176
A20
175
A19
174
A18
173
A17
172
A16
171
VDDI
170
VSS
169
A15
168
A14
167
A13
166
MB86291A
A12
A11
TESTL1
VDDE
161
160
159
VDDI
158
157 VSS
A10
165A9163A8162
164
ACOMPR156
VREF155
VRO154
AVD3153
AOUTR152
AVS3151
AVS2150
AVD2149
AVS1148
AOUTG147
AVD1146
ACOMPG145
AVS0144
AOUTB143
AVD0142
ACOMPB141
VSS140
VDDI139
A7138
A6137
A5136
A4135
A3134
A2133
VDDI132
VSS131
PLLVSS130
S129
OSCOUT128
PLLVDD127
VDDE126
VSS125
CLK124
OSCCNT123
VSS122
VDDI121
WE3120
WE2119
WE1118
WE0117
RD116
BS115
CS114
BCLKI113
VDDI112
VSS111
VDDE110
OPEN109
DTACK/TC108
DRACK/DMAAK107
CKM106
TESTH4105
5355565758596061626364656667686970717273745475777879808182838485868788899091929394
D0D1D2D3D4D5D6
VSS
VDDI
TESTH0
VSS/AVS/PLLVSS
VDDH/VDDE
VDDL/AVD/PLLVDD/VCC/VDDI
AVD
PLLVDD
VCC
OPEN
TESTL0/TESTL1
TESTH0 ~ TESTH5
RESERVE
D7
VSS
VDDE
D8
D9
D10
D11
D12
D13
D14
D15
D17
D18
D19
D16
VSS
VDDI
VDDE
: Ground
: 3.3 V power supply
: 2.5 V power supply
: Analog power supply
: PLL power supply
: Internal DRAM power supply
: Do not connect anything.
: Input the low level.
: Input the high level.
: Input the high level.
D20
D21
D22
D23
D24
VSS
VDDI
D25
D26
Notes : • The AVD and PLLVDD should be separated on the board.
• Insert a bypass capacitor with a superior high-frequency characteristic between the power
supply and ground. Place the capacitor as near the pins as possible.
D27
D28
D29
VSS
VDDE
9576969899
97
D30
D31
RDY
DREQ
INT
100
VSS
101
102
VDDI
TESTH1
103
104
TESTH2
TESTH3
3
MB86291A
PIN DESCRIPTION
■■■■
Host CPU
interface
Clock
D0-D31
A2-A24
BCLKI
RESET
CS
RD
WE0-WE3
RDY
BS
DREQ
DRACK
DTACK
INT
MODE0-
MODE2
TESTL, TESTH
CLK
CKM
CLKSEL0-
CLKSEL1
OSCOUT
OSCCNT
DCLKO
DCLKI
AOUTR, AOUTG,
AOUTB
HSYNC
VSYNC
CSYNC
EO
GV
MB86291A
Graphics Controller
HQFP208
S
VREF
VRO
ACOMPR, ACOMPG,
ACOMPB
R0-R7
G0-G7
B0-B7
CCLK
VI0-VI7
Vide output
interface
Vide capture
interface
4
••••
Host Interface Pins
Pin Name Input/output Function
MODE0 to MODE2 Input Host CPU mode/Ready mode select
MB86291A
RESET
D0 to D31 Input/output Host CPU bus data
A2 to A24 Input Host CPU bus address (Connect A[24] to MWR
BCLKI Input Host CPU bus clock
BS
CS
RD Input Read strobe signal
WE0
WE1
WE2 Input D16 to D23 write strobe signal
WE3
RDY
DREQ Output DMA request signal (active low with both SH and V832)
DRACK/DMAAK Input
DTACK/TC
Input Hardware reset
Input Bus cycle start signal
Input Chip select signal
Input D0 to D7 write strobe signal
Input D8 to D15 write strobe signal
Input D24 to D31 write strobe signal
Output
Tristate
Input
Wait request signal
(“0” for wait state with SH3; “1” for wait state with SH4, V832, or SPARClite)
DMA request acknowledge signal (Connect this to DMAAK in V832 mode.
Active high with both SH and V832.)
DMA transfer strobe signal (Connect this to TC in V832 mode. SH = active
high, V832 = active low)
in V832 mode.)
INT
TEST0, TEST1,
TESTH0 to TESTH5
Note : The host interface can connect the MB86291A to the SH4 (SH7750) or SH3 (SH7709) from Hitachi Ltd.
the V832 from NEC, or to the SPARClite (MB86833) from Fujitsu without any external circuit in between.
(Using the SRAM interface allows the MB86291A to use another CPU.) The host CPU is set by the
MODE0 and MODE1 pins as shown below.
MODE1 pin MODE0 pin CPU Type
LLSH3
LHSH4
HLV832
H H SPARClite
Note : The MODE2 pin can be used to set the Ready signal level to be used upon completion of the bus cycle. To
use the MODE2 signal at "H" level, set the software setting to two cycles.
MODE2 pin Ready signal mode
Output Host CPU interrupt signal (SH = active low, V832 = active high)
Input Test signal
L Set RDY
H Set RDY signal to "Ready" level upon completion of bus cycle.
signal to "Not Ready" level upon completion of bus cycle.
5
MB86291A
Notes : • The host interface transfers data signals at a fixed width of 32 bits.
• There are 23 lines for address signals handled in double words ( = 32 bits) and 32 Mbytes of address
space.
• The external bus can be used at an operating frequency of 100 MHz maximum.
• The RDY
sets the wait state in the SH3 mode. Note that the RDY
• The host interface supports DMA transfer using an external DMA controller.
• The host interface generates a host processor interrupt signal.
• The RESET
• Fix the TEST signal at high level.
• In the V832 mode, connect the following pins as specified :
••••
Vide Output Interface
Pin Name Input/output Function
DCLKO Output Display dot clock signal output
DCLKI Input Dot clock signal input
HSYNC Input/output
VSYNC Input/output
CSYNC Output Composite sync signal output
EO Input Even/odd-number field identification input
GV Output Graphics/video select signal
R0-R7 Output Digital video (R) signal output
G0-G7 Output Digital video (G) signal output
B0-B7 Output Digital video (B) signal output
AOUTR Analog output Analog video (R) signal output
AOUTG Analog output Analog video (G) signal output
AOUTB Analog output Analog video (B) signal output
VREF Analog Reference voltage input pin
ACOMPR Analog R-signal compensation pin
ACOMPG Analog G-signal compensation pin
ACOMPB Analog B-signal compensation pin
VRO Analog Reference current setting pin
signal at the low lev el sets the ready state in the SH4 or V832 mode; the signal at the lo w level
signal is a tristate output.
pin requires low lev el input of at least 300 µs after setting “S” (PLL reset signal) to high lev el.
SCARLET Pin Name V832 Signal Name
A24 MWR
DTACK TC
DRACK DMAAK
Horizontal sync signal output
Horizontal sync signal input in external synchronization mode
Vertical sync signal output
Vertical sync signal input in external synchronization mode
Notes : • The video output interface contains an 8-bit D/A converter to output analog RGB signals. Also, the
eight-bit RGB digital output pins can connect an external digital video encoder.
• Using an additional external circuit, the video output interface can generate composite video signals.
• The video output interface can provide display synchronized with external video. The mode for
synchronization with the DCLKI signal can be selected as well as the mode for synchronization with a set
dot clock as for normal display.
6
MB86291A
• The HSYNC and VSYNC signals must be pulled up outside the LSI as they enter the input state upon reset.
• Terminate the AOUTR, AOUTG, and AOUTB pins with a resistance of 75 Ω.
• Input 1.1 V to the VREF pin. Between this pin and analog ground, insert a bypass capacitor (one with a
superior high-frequency characteristic such as a laminated ceramic capacitor).
• Connect the ACOMPR, A COMPG, and ACOMPB pins to the 0.1 µF ceramic capacitor ahead of the analog
power supply.
• Connect the VRO pin to the analog ground with a 2.7 kΩ resistor.
• For noninterlaced display in external synchronization mode, input "0" to the EO pin, for example, using
a pull-down resistor.
• The GV signal serves to switch between graphics and video for chroma keying. The pin outputs a low
level signal to select video.
7
MB86291A
••••
Video Capture Interface
Pin Name Input/output Function
CCLK Input Digital video input clock signal input
VI0-VI7 Input Digital video data input
Note : The video capture interface inputs digital video signals in the ITU-RBT-656 format.
••••
Clock Input
Pin Name Input/output Function
CLK Input Clock input signal
S Input PLL reset signal
CKM Input Clock mode signal
CLKSEL1, CLKSEL0 Input Clock rate select signal
OSCOUT*
OSCCNT*
1
2
Input/output For connection of crystal oscillator (Reserved)
Input For selection of crystal oscillator (Reserved)
*1 : Do not connect anything.
*2 : Input the “H” level.
Notes : • The clock input bloc k inputs the clock signal that serves as the basis f or the reference clock f or the internal
operating clock and displa y dot clock. Usually input 4 Fsc ( = 14.31818 MHz) . The internal PLL generates
the internal operating clock signal of 100 MHz and the display reference clock signal of 200 MHz.
• The internal operating clock signal to be used can be selected between the clock signal (100 MHz)
generated by the internal PLL and the bus clock BCLKI input to the host CPU interf ace. Select the BCLKI
input to use the host CPU bus at 100 MHz.
CKM Clock Mode
L Select internal PLL output.
H Select host CPU bus clock (BCLKI)
Note : Use the CLKSEL pin to select the input clock frequency for using the internal PLL with CKM = L.
CLKSEL1 CLKSEL0 Clock Frequency
L L Input 13.5 MHz.
L H Input 14.32 MHz.
H L Input 17.73 MHz.
HHReserved
Note : Immediately after turning the power supply on, input a pulse whose low lev el period is 500 ns or more to the
S pin before setting it to high le v el. After the S signal goes high, input the RESET
µs or more
signal at low level for 300
8
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