FUJITSU MB85RS256 DATA SHEET
FUJITSU SEMICONDUCTOR
DATA SHEET
Memory FRAM
CMOS
256 K (32 K × 8) Bit SPI
MB85RS256
■ DESCRIPTION
MB85RS256 is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 32,768 words × 8 bits,
using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory
cells.
MB85RS256 adopts the Serial Peripheral Interface (SPI).
Unlike SRAM, MB85RS256 is able to retain data without back-up battery.
The memory cells used for the MB85RS256 has improved at least 10
outperforming Flash memory and E
MB85RS256 does not take long time to write data unlike Flash memories nor E
no wait time.
2
PROM in the number.
DS05-13105-2E
10
times of read/write operation significantly
2
PROM, and MB85RS256 takes
■ FEATURES
• Bit configuration : 32,768 × 8 bits
• Operating power supply voltage : 3.0 V to 3.6 V
• Operating frequency : 15 MHz (Max)
• Serial Peripheral Interface : SPI (Serial Peripheral Interface)
Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)
• Operating temperature range : −20 °C to +85 °C
• Data retention : 10 years (+55 °C)
• High endurance 10 Billion Read/writes (Min)
• Package : 8-pin plastic SOP (FPT-8P-M02)
Copyright©2005-2007 FUJITSU LIMITED All rights reserved
MB85RS256
■ PIN ASSIGNMENT
(TOP VIEW)
CS
SO
WP
VSS SI
1
2
3
(FPT-8P-M02)
8
7
6
54
■ PIN FUNCTIONAL DESCRIPTIONS
Pin No. Pin Name Functional description
Chip Select
This is an input pin to make chips select. When CS
1CS
status as long as device is not write status internally, and SO becomes High-Z. Other inputs
from pins are ignored for this time. When CS
to be “L” before inputting op-code.
is “L”, device is in select (active) status. CS has
is “H”, device is in deselect (standby)
VDD
HOLD
SCK
Write Protect
3WP
7HOLD
6SCK
5SI
2SO
8 VDD Supply Voltage
4 VSS Ground
2
This is a pin to control writing to a status register. When WP
is not operated.
Hold
This pin is used to interrupt serial input/output without making chips deselect. When HOLD
is “L”, hold operation is activated, SO becomes High-Z, SCK and SI become don’t care.
While the hold operation, CS
Serial Clock
This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising
edge, SO is output synchronously to a falling edge.
Serial Data Input
This is an input pin of serial data. This inputs op-code, address, and writing data.
Serial Data Output
This is an output pin of serial data. Reading data of FRAM memory cell array and status
register data are output. This is High-Z during standby.
is “L”, writing to a status register
has to be retained “L”.
■ BLOCK DIAGRAM
MB85RS256
SI
CS
SCK
HOLD
WP
SO
Serial-Parallel Converter
Control Circuit
Parallel-Serial Converter
FRAM Cell Array
32,768 ✕ 8
Row-Decoder
FRAM
Status Register
Address Counter
Column Decoder/Sense Amp/
Write Amp
Data Register
3
MB85RS256
■ SPI MODE
MB85RS256 is corresponding to the SPI mode 0 (CPOL = 0, CPHA = 0) , and SPI mode 3 (CPOL = 1, CPHA = 1) .
CS
SCK
CS
SCK
SI
SI
76543 210
MSBLSB
76543 210
MSBLSB
SPI Mode 0
SPI Mode 3
4
MB85RS256
■ SERIAL PERIPHERAL INTERFACE (SPI)
MB85RS256 works as a slave of SPI. More than 2 devices can be connected by using microcontroller equipped
with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus connected to use.
SCK
MOSI
MISO
SISO
SCK
SPI
Microcontroller
SCK
SISO
MB85RS256 MB85RS256
CS
SS1
SS2
HOLD1
HOLD2
HOLD
System Configuration with SPI Port
Microcontroller
CS
SCK
SISO
MB85RS256
HOLD
MOSI : Master Out Slave In
MISO : Master In Slave Out
SS : Slave Select
CS
HOLD
System Configuration without SPI Port
5
MB85RS256
■ STATUS REGISTER
Bit No. Bit Name Function
Status Register Write Protect
This is a bit composed of nonvolatile memories (FRAM). WPEN is related
7 WPEN
6 to 4 ⎯
to WP
input to protect writing to a status register (refer to “■ WRITING
PROTECT”). Writing with the WRSR command and reading with the
RDSR command are possible.
Not Used Bits
These are bits composed of nonvolatile memories, writing with the WRSR
command is possible, and “000” is written before shipment. These bits are
not used but they are read with the RDSR command.
3BP1
2BP0
1WEL
0 0 This is a bit fixed to “0”.
Block Protect
This is a bit composed of nonvolatile memory (FRAM). This defines block
size for writing protect with the WRITE command (refer to “■ BLOCK
PROTECT”). Writing with the WRSR command and reading with the
RDSR command are possible.
Write Enable Latch
This indicates FRAM memory and status register are writable. The WREN
command is for setting, and the WRDI command is for resetting. With the
RDSR command, reading is possible but writing is not possible with the
WRSR command. WEL is reset after the following operations.
The time when power is up.
The time when the WRDI command is input.
The time when the WRSR command is input.
The time when the WRITE command is input.
■ OP-CODE
MB85RS256 accepts 6 kinds of command specified in op-code. Op-code is a code composed of 8 bits shown
in the table below. When invalid codes other than codes below are input, they are ignored. If CS
inputting op-code, the command are not performed.
Name Description Op-code
is risen while
WREN Set Write Enable Latch 0000 0110
WRDI Reset Write Enable Latch 0000 0100B
RDSR Read Status Register 0000 0101B
WRSR Write Status Register 0000 0001B
READ Read Memory Code 0000 0011B
WRITE Write Memory Code 0000 0010B
6
B
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