FUJITSU MB85R1002 DATA SHEET

FUJITSU SEMICONDUCTOR

DATA SHEET

Memory FRAM

CMOS

1 M Bit (64 K × 16)

MB85R1002

■ DESCRIPTIONS

The MB85R1002 is an FRAM (Ferroelectric Random Access Memory) chip consisting of 65,536 words x 16 bits
of non-volatile memory cells created using ferroelectric process and silicon gate CMOS process technologies.
The MB85R1002 is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85R1002 can be used for at least 10
improvement over the number of read and write operations supported by Flash memory and E
The MB85R1002 uses a pseudo-SRAM interface that is compatible with conventional asynchronous SRAM.

DS05-13104-3E

10

read/write operations, which is a significant

2

PROM.

■ FEATURES

• Bit configuration : 65,536 words × 16 bits

• Read/write endurance : 10

• Operating power supply voltage : 3.0 V to 3.6 V

• Operating temperature range : − 20 °C to +85 °C

• Data retention : 10 years (+55 °C)

•LB

and UB data byte control

• Package : 48-pin plastic TSOP (1)

10

times/bit (Min)

: 48-pin plastic FBGA

Copyright©2005-2007 FUJITSU LIMITED All rights reserved

MB85R1002

■ PIN ASSIGNMENT

A15
A14
A13
A12
A11
A10

A9

A8
NC
NC

WE

CE2

GND

UB

LB

V

NC

A7

A6

A5

A4

A3

A2

A1

(

TOP VIEW)

1
2

3

4
5
6
7

8

9
10
11
12
13
14
15
16

CC

17
18
19
20
21
22
23
24

48

NC

47

NC

46

GND

45

I/O16

44

I/O8

43

I/O15

42

I/O7

41

I/O14

40

I/O6

39

I/O13

38

I/O5

37

V

CC

36

I/O12

35

I/O4

34

I/O11

33

I/O3

32

I/O10

31

I/O2

30

I/O9

29

I/O1

28

OE

27

GND

26

CE1

25

A0

(FPT-48P-M25)

(Continued)

2

(Continued)

MB85R1002

Top View Bottom View

INDEX

A

B

C

D

E

F

G

H

6543 21123 456

12 3456 654321

ALB

OE A0 A1 A2 CE2 A CE2 A2 A1 A0 OE LB

BI/O9UBA3 A4 CE1 I/O1 B I/O1 CE1 A4 A3 UB I/O9

C I/O10 I/O11 A5 A6 I/O2 I/O3 C I/O3 I/O2 A6 A5 I/O11 I/O10

D GND I/O12 NC A7 I/O4 V

EV

CC I/O13 NC NC I/O5 GND E GND I/O5 NC NC I/O13 VCC

CC DVCC I/O4 A7 NC I/O12 GND

F I/O15 I/O14 A14 A15 I/O6 I/O7 F I/O7 I/O6 A15 A14 I/O14 I/O15

G I/O16 NC A12 A13 WE I/O8 G I/O8 WE A13 A12 NC I/O16

H NC A8 A9 A10 A11 NC H NC A11 A10 A9 A8 NC

(BGA-48P-M23)

■ PIN DESCRIPTION

Pin name Function

A0 to A15 Address In

I/O1 to I/O16 Data Input/Output

CE

1 Chip Enable 1 in

CE2 Chip Enable 2 in

WE

OE

Write Enable in

Output Enable in

LB, UB Data Byte Control in

V

CC Power Supply

GND Ground

NC No Connection

3

MB85R1002

■ BLOCK DIAGRAM

A0

CE2

LB

UB

WE

OE

CE1

intCEB

to

A15

·

·

·

intCE2

Address Latch.

intCE2

Row Dec.

intOE

intWE

intCE2

intCEB

Ferro Capacitor Cell

Column Dec.

S/A

I/O1 to I/O8

I/O9 to I/O16

·

·

·

·

I/O16

to

I/O9

I/O8

to

I/O1

4

■ FUNCTION TRUTH TABLE

Mode CE1CE2 WE OE LB UB I/O1 to I/O8 I/O9 to I/O16 Supply Current

HXXXXX

MB85R1002

Standby Pre-charge

Read

Read

(Pseudo-SRAM,

OE

control*1)

Write

Write

(Pseudo-SRAM,

WE

control*2)

Notes : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance

: Latch address and latch data at falling edge, : Latch address and latch data at rising edge

XLXXXX

XXHHXX

XXXXHH

L L Dout Dout

H

L

LHH

H

L

LH H

HL

LX

L H Dout High-Z

H L High-Z Dout

L L Dout Dout

L H Dout High-Z

H L High-Z Dout

LL Din Din

L H Din High-Z

HL High-Z Din

LL Din Din

L H Din High-Z

HL High-Z Din

High-Z High-Z

Standby

(ISB)

Operation

(I

CC)

*1 : OE

*2 : WE

control of the Pseudo-SRAM means the valid address at the falling edge of OE to read.

control of the Pseudo-SRAM means the valid address and data at the falling edge of WE to write.

5