FUJITSU MB85AS8MTPF Datasheet

FUJITSU SEMICONDUCTOR

MEMORY SOLUTION DATA SHEET

Memory ReRAM

8M (1024 K  8) Bit SPI

MB85AS8MT

■ DESCRIPTION

MB85AS8MT is a ReRAM (Resistive Random Access Memory) chip in a configuration of 1,048,576
words  8 bits, using the resistance-variable memory process and silicon gate CMOS process technologies
for forming the nonvolatile memory cells.
MB85AS8MT adopts the Serial Peripheral Interf ace (SPI).
MB85AS8MT is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85AS8MT can be used for 1  10

DS501-00060-2v0-E

6

rewrite operations.

■ FEATURES

• Bit configuration : 8 Mbits (1,048,576 words  8 bits)

• Serial Peripheral Interface : SPI (Serial Peripheral Interface)
Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)

• Write buffer size : 256 bytes

• Operating frequency : 10 MHz (Max)

• Data endurance : 1  10

• Data retention : 10 years (+85 C)

• Operating power supply voltage : 1.6 V to 3.6 V

• Operating power supply current : Write current 1.5 mA (Typ)

• Operation ambient temperature range : -40 C to +85 C

• Package : 8-pin plastic SOP, 11-pin plastic WLP

6

times / 4bytes*

*4 bytes are selected by A1 to A0.

Read current 0.15 mA (Typ@5 MHz)
Standby current 60 A (Typ)
Sleep current 6 A (Typ)

RoHS compliant

Copyright 2021 FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED

2021.01

MB85AS8MT

(TOP VIEW)

8-pin SOP

(BOTTOM VIEW)

11-pin WLP Type-A

11-pin WLP Type-B
11-pin WLP Type-C

■ PIN ASSIGNMENT

VSS

CS

SO

WP

V

SS

VSS VSS

1

2

3

4

8

7

6

5

VSS

V

DD

HOLD

SCK

SI

VSS VSS

SI/SO

SCK

VSS

VSS

VSS

CS

VSSVDD

SI SO

SCK

VSS

VSS

CS

VSSVDD

2 DS501-00060-2v0-E

■ PIN FUNCTIONAL DESCRIPTIONS

Pin No. Pin Name Functional description

Chip Select pin
This is an input pin to make chips select. When CS

1CS

3WP

7HOLD

6SCK

(standby) status and SO becomes High-Z . Inp ut s fro m othe r pin s ar e ign or e d for this
time. When CS
inputting op-code.

Write Protect pin (available only for SOP package)
This is a pin to control writing to a status register. The writing of status register (see “■
STATUS REGISTER”) is protected in related with WP
PROTECT” for detail.

Hold pin (available only for SOP package)
This pin is used to interrupt serial input/output without making chips deselect. When
HOLD
do not care. See “■ HOLD OPERATION” for detail.

Serial Clock pin
This is a clock input pin to input/output serial d ata. SI is loaded synchronously t o a rising
edge, SO is output synchronously to a falling edge.

is “L” level, device is in select (active) status. CS has to be “L” level before

is “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become

is “H” level, device is in deselect

MB85AS8MT

and WPEN. See “■ WRITING

5SI

2SO

8V
4V

*: Pin No. is for SOP package.

Serial Data Input pin
This is an input pin of serial data. This inputs op-code, address, and writing dat a.

Serial Data Output pin
This is an output pin of serial data. Reading data of ReRAM memo ry cell array and status
register data are output. This is High-Z during standby.

DD Supply Voltage pin
SS Ground pin

DS501-00060-2v0-E 3

MB85AS8MT

SCK

SO

SI

Serial-Parallel Converter

ReRAM Cell Array

1,048,576 ✕ 8

Column Decoder/Sense Amp/

Write Amp

ReRAM

Status Register

Data Register

Parallel-Serial Converter

Control Circuit

Address Counter

Row Decoder

CS

WP

HOLD

SCK

SI

CS

SCK

SI

CS

76543 210

76543 210

MSBLSB

MSBLSB

SPI Mode 0

SPI Mode 3

■ BLOCK DIAGRAM

■ SPI MODE

MB85AS8MT corresponds to the SPI mode 0 ( CPOL  0, CPHA  0) , and SPI mode 3 (CPOL  1, CPHA  1) .

4 DS501-00060-2v0-E

MB85AS8MT

SCK

SS1

HOLD1

MOSI
MISO

SS2

HOLD2

SCK

CS

HOLD

SISO

SCK

CS

HOLD

SISO

MB85AS8MT MB85AS8MT

SCK

CS

HOLD

SISO

MB85AS8MT

SPI

Microcontroller

MOSI : Master Out Slave In
MISO : Master In Slave Out
SS : Slave Select

System Configuration with SPI Port

System Configuration without SPI Port

Microcontroller

■ SERIAL PERIPHERAL INTERFACE (SPI)

MB85AS8MT works as a slave of SPI. More than 2 devices can be connected by using microcontroller
equipped with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus
connected to use.

DS501-00060-2v0-E 5

MB85AS8MT

■ STATUS REGISTER

Bit No. Bit Name Function

Status Register Write Protect
This is a bit composed of nonvolatile memories (ReRAM). WPEN protects

7 WPEN

6 to 4 

3 BP1

2 BP0

writing to a status register (refer to “■ WRITING PROTECT”) relating with
WP

input. Writing with the WRSR command and reading with the RDSR

command are possible.
Not Used Bits

These are bits composed of volatile memories, writing with the WRSR
command is possible. These bits are not used b ut th ey ar e r ea d with th e
RDSR command.
Initial value is “000”.

Block Protect
This is a bit composed of nonvolatile memory. This defines size of write
protect block for the WRITE command (refer to “■ BLOCK PROTECT”).
Writing with the WRSR command and reading with t he RDSR com man d
are possible.

Write Enable Latch
This indicates ReRAM Array and status register are writable. The WREN
command is for setting, and the WRDI command is for resettin g. With the
RDSR command, reading is possible but writing is not possible with the

1WEL

0WIP

WRSR command. WEL is reset after the following operations.
After power ON.

The rising edge of CS
The end of writing process after WRSR command recognition.
The end of writing process after WRITE command recognition.

Write In Progress
This indicates ReRAM Array and status register are in writing process.
During this writing process, any commands except RDSR will not be exe­cuted (refer to “2. WIP polling”). With the RDSR command, reading is pos­sible but writing is not possible with the WRSR command.

after WRDI command recognition.

■ OP-CODE

MB85AS8MT accepts 10 kinds of command specified in op-code. Op-code is a code composed of 8 bits
shown in the table below. Do not input invalid codes other than those codes. If CS
op-code, the command are not performed.

Name Description Op-code

WREN Set Write Enable Latch 0000 0110

WRDI Reset Write Enable Latch 0000 0100B

is risen while inputting

B

RDSR Read Status Register 0000 0101B

WRSR Write Status Register 0000 0001B

READ Read Memory Code 0000 0011B

WRITE Write Memory Code 0000 0010B

RDID Read Device ID 1001 1111B
RDUID Read Device ID and Unique ID 1000 0011B
SLEEP

Enter Sleep Mode (Power Down Mode)

PWDN 1110 0010B

6 DS501-00060-2v0-E

1011 1001B

MB85AS8MT

SO

SCK

SI

CS

00000110

High-Z

76543210

InvalidInvalid

SO

SCK

SI

CS

00000100

High-Z

76543210

InvalidInvalid

■ COMMAND

 WREN

The WREN command sets WEL (Write Enable Latch) . WEL has to be set with the WREN command before
writing operation (WRSR command and WRITE command) .

 WRDI

The WRDI command resets WEL (Write Enable Latch) . Writing operation (WRSR command and WRITE
command) are not performed when WEL is reset.

DS501-00060-2v0-E 7

MB85AS8MT

SO

SCK

SI

CS

00000101

High-Z

76543210

Invalid

MSB

76543210

Data Out

LSB

Invalid

SO

SCK

SI

CS

00000001

76543210

Data In

MSB

76543210

High-Z

LSB

76543210

Instruction

 RDSR

The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input
to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. In the
RDSR command, repeated reading of status r egister is enabled by sen ding SCK continuously bef ore rising

.

of CS

 WRSR

The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR
op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable La tch) is not able to be written with WRSR
command. A SI value correspondent to bit 1 is ignored. Bit 0 of the sta tus register cannot be writ ten. The SI
value corresponding to bit 0 is ignored. WP
and do not change the WP

After rising edge of CS

signal level until the end of command sequence.

, MB85AS8MT starts writing operation to nonvolatile register and set WIP bit in status

signal level shall be fixed before performing WRSR command,

register to “1”. After this writing opera tion has fin ished, reset this WIP b it from “1” t o “0”. Although th e RDSR
command is executable for WIP polling during this writing process, any other commands will not be performed.

8 DS501-00060-2v0-E

MB85AS8MT

CS

SCK

SI

Invalid

MSB

LSB

MSB

Data Out

LSB

High-Z

Invalid

450123 26276 7 8 9 10 11 12 13 14 15 38 3928 29 30 31 32 33 34 35 36 37

00000011X

32

XXX 1817

16

54

SO

76 3

10

54 210

24-bit Address

OP-CODE

19

CS

SCK

Data In

SI

MSB

24-bit Address

OP-CODE

LSB MSB LSB

High-Z

10 110123456789

14 15 26 31 3212 13 27 28 29 30 33 34 35 36 37 38 39

0000001 30XXXX 210

SO

18 17 16 5 4 3 2 1 0765419

 READ

The READ command reads ReRAM memory cell array data. Arbitrar y 24 bits address and op-code of READ
are input to SI. The 4-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output
synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS
command is completed, but keeps on reading with automatic address increment which is enabled by con­tinuously sending clocks to SCK in unit of 8 cycles before CS

rising. When it reaches the most significant

address, it rolls over to the starting address, and reading cycle keeps on infinitely.

is risen, the READ

 WRITE

The WRITE command writes data to ReRAM memory cell array. WRITE op-code, arbitrary 24 bits of address
and 8 bits of writing data are input to SI. The 4-bit upper add ress bit is invalid.

During the CS
size is 256 bytes during this CS

is low, input writing data are temporary saved in the data register . The maximum writing data

= low period. If the input writing data are more than 8 bits, it is possible to
continue writing with automatic address increment. When it reaches the most significant address, it rolls
over to the starting address, and writing cycle can be continued up to 256 bytes (which is the size of data
register). Data exceed 256 bytes can not be written.

After rising edge of CS

, MB85AS8MT starts writing operation to nonvolatile memory and set WIP bit in status
register to “1”. After this writing opera tion has fin ished, reset this WIP b it from “1” t o “0”. Although th e RDSR
command is executable for WIP polling during this writing process, any other commands will not be performed.

DS501-00060-2v0-E 9

MB85AS8MT

SO

SCK

SI

CS

MSB

76543210

Data OutData Out

High-Z

LSB

111098

333231 393837363534

Invalid

30282931

10011111

201364578

bit

7 6 5 4 3 2 1 0Hex

Manufacturer ID 0000010004

H Fujitsu

Continuation code 011111117F

H

Proprietary use Density Hex

Product ID (1st Byte)10101010AA

H Density: 01010B  8 Mbit

Proprietary use Hex

Product ID (2nd Byte)0000001103

H

 RDID

The RDID command reads fixed Device ID. Aft er per f orming RDID op-cod e t o SI, 3 2-cycle clock is in put t o
SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. The output
is in order of Manufacturer ID (8bit)/Continuation code (8bit)/Product ID (1st Byte)/Product ID (2nd Byte).
In the RDID command, SO holds the output state of the last bit in 32-bit Device ID until CS

is risen.

10 DS501-00060-2v0-E

MB85AS8MT

SO

SCK

SI

CS

MSB

76543210

Data OutData Out

High-Z

LSB

111098

979695 1031021011009998

Invalid

94 929395

10000011

201364578

Bits Field Value Description

Device ID [95:88] Manufacture ID 04h Fujitsu
Device ID [87:80] Continuation code 7Fh

Device ID [79:72] Product ID AAh

101b: Proprietary use

01010b: Density (8 Mbit)
Device ID [71:64] Product ID 03h Proprietary use
Unique ID [63:24] Lot ID

64 bit

Unique ID

Unique ID [23:16] Wafer ID
Unique ID [15:0] Chip ID

 RDUID

The RDUID command reads (common) Device ID and (each chip-specific) Unique ID. After performing
RDUID op-code to SI, 96-cycle clock is input to SCK. The SI value is invalid for this time. SO is output
synchronously to a falling edge of SCK. The output is in order of Manufacturer ID (8bit) / Continuation code
(8bit) / Product ID (1st Byte) / Product ID (2nd Byte) as Device ID and Lot ID (40bit) / Wafer ID (8bit) / Chip
ID (16bit) as Unique ID. In the RDUID command, SO holds the output state of the last bit in 96-bit Device
ID and Unique ID until CS

is risen.

DS501-00060-2v0-E 11

MB85AS8MT

Enter Sleep Mode

CS

SCK

SI

Invalid Invalid

High-Z

Sleep Mode Entry

67012345

SO

11011100

From this time
Command input enable

 SLEEP/PWDN

The SLEEP/PWDN command shifts the LSI to a low power mode called “SLEEP mode” (“Power Down
mode”). The transition to the SLEEP mode (Power Down mode) is carried out at the rising edge of CS
operation code in the SLEEP (PWDN) command. However, when at least one SCK clock is inputted before
the rising edge of CS
is canceled.

After the SLEEP mode (Power Down mode) transition, SCK and SI inputs are ignored and SO changes to
a High-Z state.

after operation code in the SLEEP (PWDN) command, this SLEEP (PWDN) command

after

Returning to a normal operation from the SLEEP mode (Power Down mode) is carried out after t
from the falling edge of CS
However, it is prohibited to bring down CS

(see the figure below ). It is possible to retu rn CS to H level before tREC time.

to L level again during tREC period.

CS

t

CS

CSWL

REC

t

Exit Sleep Mode

Sleep Mode Exit

REC time

12 DS501-00060-2v0-E

MB85AS8MT

■ WRITING OPERATION OF NONVOLATILE MEMORY

Each input data is not written to the nonvolatile memory by unit of byte right after its data input. Multiple
bytes up to maximum 256 bytes are temporarily saved to t he data register. After the command input is finished
and rising edge of CS

1. Address counter control

In case of memory access by WRITE and READ commands, after the end of o p-code an d addr ess input, it
is possible to keep on accessing (= reading or writing) with automatic address increment which is enabled
by continuously sending clocks to SCK in unit of 8 cycles while CS
command, continuous writing is restricted by the limit of buffer size in the data register.

When it reaches the most significant addre ss, it rolls over to the starti ng address, and this automatic address
increment will be continued by the address counter control.

Over write protection to the nonvolatile memory is enabled b y BP0 and BP1 bits in status register. When the
memory address exceed it from write protected block to unprotected block by address counter control, write
to the unprotected block only. Similarly, when memory address exceed it from unpro tected block to protected
block, does not write to the protected block.

, start writing operation from this data register to the nonvolatile memory.

is low level. However, for the WRITE

Start address
Start address+1
Start address+2

Most significant address-5
Most significant address-4

Address

Most significant address-3
Most significant address-2
Most significant address-1
Most significant address

MSBLSB

bit number

6543 21

07

DS501-00060-2v0-E 13

MB85AS8MT

2. WIP polling

After the last writing data was input, writing to the nonvolatile memory needs tWC waiting time from the rising
edge of CS
condition are considered, and this maximum t
shorter than the maximum value. Therefore, MB85AS8MT supports WIP polling to improve memory access
by optimizing the waiting time.

After starting the data writing to nonvolatile memory, MB85AS8MT sets “1” to a volatile register related to
the WIP bit in status register. After finished the writing operation, reset this WIP bit from “1” to “0”. Although
the usual commands are not executable during this writing pr ocess, only the RDSR command is acceptable.
RDSR command outputs the value of status register to SO. It is possible to confirm if the internal writing
operation to nonvolatile memory is finished or not , by checking the corresponding bit to WIP in output data
from SO.

CS

WRSRRDSR

SCK

. This tWC time becomes larger than a minimum clock cycle. Production variation and operating

WC value is defined. In the usual operation, this tWC time is

SI

busy

wip

wel

SO

WPEN

XXX

(Write process situation)

(Internal volatile register for WIP)

(Internal volatile register for WEL)

BP1 BP0

XX

WPEN

X

XX

BP1

BP1

BP0

WPEN

WEL WIP

X

XX

BP0 WEL WIP

RDSR command also outputs the WPEN, BP1 and BP0 of status register to SO. In the polling after WRSR
command, MB85AS8MT outputs the WPEN, BP1 and BP0 da ta which is set before the writing to nonvolatile
memory is completed. On the other hand for WEL and WIP, MB85AS8MT outputs (WEL,WIP) =2'b11 when
the writing to nonvolatile memory is not complete d. When it is competed, outputs (WEL,WIP)=2'b00.

If continuously sending clocks to SCK during CS

= low, it is also possible to keep on outputting WPEN to
WIP bits in status register in unit of 8 cycles since 17th clock. In case the WIP polling is applied, WIP and
WEL bits in status register output to SO by RDSR command are updated regularly.

Figure shows the example of RDSR command input wi th co ntinuo usly se nding clo cks over 17 durin g CS
low, before the writing process of WRSR command is finished.

=

14 DS501-00060-2v0-E

MB85AS8MT

SCK

CS

Hold Condition

HOLD

Hold Condition

■ BLOCK PROTECT

Writing protect block for WRITE command is configu red by the value of BP0 and BP1 in the status regi ster.

BP1 BP0 Protected Block

00None
01C0000

H to FFFFFH (upper 1/4)

1 0 80000
1 1 00000

H to FFFFFH (upper 1/2)
H to FFFFFH (all)

■ WRITING PROTECT

Writing operation of the WRITE command and the WRSR co mmand are protected with the value of WEL,
WPEN, WP

WEL WPEN WP

0 X X Protected Protected Protected
1 0 X Protected Unprotected Unprotected
1 1 0 Protected Unprotected Protected
1 1 1 Protected Unprotected Unprotected

as shown in the table. In WLP package, WP is fixed to “1”.

Protected Blocks Unprotected Blocks Status Register

■ HOLD OPERATION (available only for SOP package)

Hold status is retained without aborting a comma nd if HOL D is “L” level while CS is “L” level. The timing for
starting and ending hold status depends on the SCK to be “H” level or “L” level when a HOLD
transited to the hold condition as shown in the dia gram below . In case the HO LD
when SCK is “L” level, return the HOLD
the HOLD
level. Arbitrary command operation is interrupted in hold status, SCK and SI inputs become do not care.
And, SO becomes High-Z while reading command (RDSR, READ). CS
status.

pin transited to “L” level when SCK is “H” level, return the HOLD pin to “H” level at SCK being “H”

pin to “H” level at SCK being “L” level. In the same manner, in case

shall be set to “L” level during hold

pin transited to “L” level

pin input is

DS501-00060-2v0-E 15

MB85AS8MT

■ ABSOLUTE MAXIMUM RATINGS

Parameter Symbol

Unit

Min Max

Rating

Power supply voltage* V
Input voltage* V
Output voltage* V
Operation ambient temperature T

DD  0.5  4.0 V

IN  0.5 VDD  0.5 (  4.0) V

OUT  0.5 VDD  0.5 (  4.0) V

A  40  85 C

Storage temperature Tstg  55  125 C

*:These parameters are based on the condition that VSS is 0 V.

WARNING: Semiconductor devices may be permanently damaged by application of stress (including, witho ut

limitation, voltage, current or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Parameter Symbol

Power supply voltage

*1

Operation ambient temperature

Min Typ Max

VDD 1.6  3.6 V

*2

TA  40   85 C

Value

Unit

*1: These parameters are based on the condition that VSS is 0 V.
*2: Ambient temperature when only this device is working. Please consider it to be the almost same as the

package surface temperature.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated under these conditions.

Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of
device and could result in device failure.

No warranty is made with respect to any use, operating con ditions or combinations not represented
on this data sheet. If you are considering application unde r any conditions other than listed herein,
please contact sales representatives beforehand.

16 DS501-00060-2v0-E

■ ELECTRICAL CHARACTERISTICS

1. DC Characteristics

Parameter Symbol Condition

, WP, SCK, SI,

Input leakage current |I
Output leakage current |I

I

DDR (60)

Operating power supply
current (Read)

I

DDR (85)

I

DDW (60)

Operating power supply
current (Write)

I

DDW (85)

Standby current I

Sleep current I

Input high voltage V
Input low voltage V

LI|

LO|SO  0 V to VDD  1 A

SB SCK  SI  CS  VDD  60 500 A

ZZ

IH VDD  1.6 V to 3.6 V VDD  0.7  VDD  0.5 V
IL VDD  1.6 V to 3.6 V  0.5  VDD  0.3 V

CS

HOLD

SCK = 5 MHz,

TA=0 C to 60 C,

1.6V  V
SCK = 10 MHz,

TA=  40 C to 85 C,

1.6V  V

A=0 C to 60 C,

T

1.6V  V

A=  40 C to 85 C,

T

1.6V  V

All inputs V
VDD=3.6V, TA=85 C

All inputs V

VDD=1.45V, TA=60 C

 0 V to VDD

DD  2.0V

DD  3.6V

SCK = t

SCK = t

WC,

DD  2.0V

WC,

DD  3.6V

CS  VDD

SS or VDD

 VDD

CS

SS or VDD

MB85AS8MT

(within recommended operating conditions)

Value

Unit

Min Typ Max

 1 A

 0.15 0.3

mA

0.7

 1.5 

mA

2.5

 68A

 6 A

Output high voltage V

Output low voltage V

IOH   1.5 mA @VDD  1.8 V

OH

OH   1.2 mA @VDD < 1.8 V

I

OL

IOL  1.5 mA @VDD  1.8 V

OL  1.2 mA @VDD < 1.8 V

I

DD  0.8 V

V

V

DD  0.2 V

DS501-00060-2v0-E 17

MB85AS8MT

2. AC Characteristics

Parameter Symbol

Value

Unit Condition

Min Typ Max

SCK clock frequency f
Clock high time t
Clock low time t

CK 0  10 MHz
CH 40 ns
CL 40 ns

CSUH 30 

t

Chip select set up time

CSUL 30  CS falling to SCK rising

t

CSHH 30 

t

CSHL 30  SCK rising to CS rising

Chip select hold time

Output disable time t
Output active time t
Output data valid time t
Output hold time t
Deselect time t
Data rising time t
Data falling time t
Data set up time t
Data hold time t

set uptime tHS 10 ns

HOLD

hold time tHH 10 ns

HOLD

output floating time tHZ 30 ns

HOLD

t

CSH 30  SCK falling to CS rising

t

OD 30 ns

OLZ 0 ns

ODV 35 ns

OH 0 ns

D 100 ns
R 50 ns
F 50 ns

SU 20 ns

H 20 ns

ns

CS rising to SCK rising

SCK rising to CS falling

ns

output active time tLZ 30 ns

HOLD
Write cycle time t
Recovery time from SLEEP

mode
CS

pulse width at SLEEP

mode exit

WC  5000 10000 s @100% data turn over

REC  700 1000 s

t

CSWL 100 ns

t

AC Test Condition

Power supply voltage : 1.6 V to 3.6 V
Operation ambient temperatur e :  40 C to  85 C
Input voltage magnitude : V

Input rising time : 5 ns
Input falling time : 5 ns
Input judge level : V
Output judge level : V

DD  0.7  VIH  VDD

0  VIL  VDD  0.3

DD/2
DD/2

18 DS501-00060-2v0-E

AC Load Equivalent Circuit

Output

V

MB85AS8MT

DD

1.2 kΩ

3. Pin Capacitance

Parameter Symbol Condition

Output capacitance C
Input capacitance C

30 pF

0.95 kΩ

Value

Unit

Min Max

O

I  6pF

VDD  VIN  VOUT  0 V,

f  1 MHz, T

A  +25 C

 6pF

DS501-00060-2v0-E 19

MB85AS8MT

tCSUL

CS

SCK

tCSHH

tCSHL

tCSH

Mode0

High-Z

SO

tCH

tCL

tCSUH

SI

tODV

tOH

tD

tSUtH

tOD

tCSUL

CS

SCK

tCSHH

tCSHL

tCSH

High-Z

SO

tCH

tCSUH

SI

tODV

tSUtH

㼠㻻㻰

tD

Mode3

tCL

tOLZ

tOLZ

tOH

SCK

CS

SO

t

HS tHS

tHHtHH

tHH tHH

tHZ tLZ tHZ tLZ

tHS tHS

HOLD

High-ZHigh-Z

■ TIMING DIAGRAM

 Serial Data Timing

 Hold Timing

20 DS501-00060-2v0-E

■ POWER ON/OFF SEQUENCE

V

SS

CS >VDD × 0.7V

tpd

tputrtf

V

IL

(Max)

1.0 V

V

IH

(Min)

V

DD

(Min)

V

DD

CS : don't care

CS >VDD × 0.7V

CS CS

V

SS

VIL (Max)

1.0 V

V

IH

(Min)

V

DD

(Min)

V

DD

* : CS (Max) < V DD  0.5 V

MB85AS8MT

Parameter Symbol

CS

level hold time at power OFF tpd 10  ms

CS

level hold time at power ON tpu 1  ms

Min Max

Unit

Power supply rising time tr 50 s/V
Power supply falling time tf 100 s/V

If the device does not operate within the specified conditions of read cycle, write cycle or power on/off
sequence, memory data can not be guaranteed.

■ ReRAM CHARACTERISTICS

Value

Parameter

Write Endurance 1  10

Value

Min Max

6

 Times/4bytes* Operation Ambient Temperature TA   85 C

Unit Remarks

Data Retention 10  Years Operation Ambient Temperature T
Data register size  256 byte

*: 4 bytes are selected by A1 to A0.

A   85 C

DS501-00060-2v0-E 21

MB85AS8MT

■ ESD AND LATCH-UP

Test DUT Value

ESD HBM (Human Body Model)
JESD22-A114 compliant

ESD CDM (Charged Device Model)
JESD22-C101 compliant

MB85AS8MTPF



|2000 V|

|500 V|



Latch-Up (I-test)
JESD78 compliant

|100 mA|



■ MB85AS8MTPF (8-pin plastic SOP) REFLOW CONDITIONS AND FLOOR LIFE

[ JEDEC MSL ] : Moisture Sensitivity Level 3 (IPC/JEDEC J-STD-020D)

■ CURRENT STATUS ON CONTAINED RESTRICTED SUBSTANCES

This product complies with the regulations of REACH Regulations , EU RoHS Directive and China RoHS.

22 DS501-00060-2v0-E

■ ORDERING INFORMATION

MB85AS8MT

Part number Package Shipping form

MB85AS8MTPW-G-KBAERE1 11-pin WLP Type-A Embossed Carrier Tape 10,000
MB85AS8MTPW-G-KBBERE1 11-pin WLP Type-B Embossed Carrier Tape 10,000
MB85AS8MTPW-G-KBCERE1 11-pin WLP Type-C Embossed Carrier Tape 10,000
MB85AS8MTPF-G-KBERE1 SOP 8-pin Embossed Carrier Tape 1,000

Minimum shipping

quantity

DS501-00060-2v0-E 23

MB85AS8MT

MB85AS8MTPF-G-KBERE1

■ PACKAGE DIMENSION

8-pin plastic SOP Lead pitch 1.27 mm

Package width 

package length

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 1.73 mm MAX

5.3 mm  5.65 mm

24 DS501-00060-2v0-E

MB85AS8MT

MB85AS8MTPW-G-KBAERE1
MB85AS8MTPW-G-KBBERE1

11-pin WLP Bump pitch 0.5 mm

Package width 

package length

Bump shape Soldering ball

Mounting height 0.385 mm

2.067 mm  2.877 mm

DS501-00060-2v0-E 25

MB85AS8MT

MB85AS8MTPW-G-KBCERE1

11-pin WLP Bump pitch 0.5 mm

Package width 

package length

Bump shape Soldering ball

Mounting height 0.280 mm

2.067 mm  2.877 mm

26 DS501-00060-2v0-E

■ MARKING (11-pin WLP)

$6 07

MB85AS8MT

( 

11-pin WLP Type A

AS8MT : Product name
E1 : Fixed code
1900 : Year and Week code
C00 : C (Fixed code )+00 (Trace code)

$6 07
( 



&

%



&

11-pin WLP Type B

AS8MTB : Product name+B (Fixed code)
E1 : Fixed code
1900 : Year and Week code
C00 : C (Fixed code )+00 (Trace code)

DS501-00060-2v0-E 27

MB85AS8MT

AS8MT
E1 1

900

C00

C

■ MARKING (8-pin SOP)

11-pin WLP Type C

AS8MTC : Product name+C (Fixed code)
E1 : Fixed code
1900 : Year and Week code
C00 : C (Fixed code)+00 (Trace code)

$7

(

6



/

8-pin SOP

AS8MT : Product name
E1 : Fixed code
1900 : Year and Week code
L00 : L (Fixed code)+00 (Trace code)







28 DS501-00060-2v0-E

■ PACKING FIGURE

Package

Index mark

Direction of unreeling

Unit: mm

Direction of unreeling

Emboss carrier
tape

1. Emboss carrier tape and package direction of storage

2. Reel

MB85AS8MT

DS501-00060-2v0-E 29

MB85AS8MT

■ EMBOSS CARRIER TAPE DRAWING

Unit: mm

Dimensions of Emboss carrier tape

WA0B0K0 T P0

8.0  0.3 2.25  0.05 3.25  0.05 0.60  0.05 0.25  0.05 4  0.1
P1 P2 D0 E1 F

4  0.1 2  0.05

1.5  0.1
 0

1.75  0.1 3.5  0.05

30 DS501-00060-2v0-E

MB85AS8MT

■ MAJOR CHANGES IN THIS EDITION

A change on a page is indicated by a vertical line drawn left side of that page.

Page Section Change Results

2 PIN ASSIGNMENT 11-pin WLP type-C is added.
3 PIN FUNCTIONAL DESCRIPTION HOLD

’s description is revised.
23 ORDERING INFOMATION
26 PACKAGE DIMENTION 11-pin WLP type-C is added.

28 MARKING(11-pin WLP) 11-pin WLP type-C is added.

MB85AS8MTPW-G-KBCERE1(11-pin WLP type-C) is add­ed.

MB85AS8MT

FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED

Shin-Yokohama TECH Building, 3-9-1 Shin-Yokohama,
Kohoku-ku, Yokohama, Kanagawa 222-0033, Japan

https://www.fujitsu.com/jp/fsm/en/

All Rights Reserved.

FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED, its subsidiaries and affiliates (collectively, "FUJITSU SEMI­CONDUCTOR MEMORY SOLUTION ") reserves the right to make changes to the information contained in this document without
notice. Please contact your FUJITSU SEMICONDUCTOR MEMORY SOLUTION sales representatives before order of FUJITSU
SEMICONDUCTOR MEMORY SOLUTION device.
Information contained in this document, such as descriptions of function and application circuit examples is presented solely for
reference to examples of operations and uses of FUJITSU SEMICONDUCTOR MEMORY SOLUTION device. FUJITSU SEMI­CONDUCTOR MEMORY SOLUTION disclaims any and all warranties of any kind, whether express or implied, related to such
information, including, without limitation, quality, accuracy, performance, proper operation of the device or non-infringement. If you
develop equipment or product incorporating the FUJITSU SEMICONDUCTOR MEMORY SOLUTION device based on such in­formation, you must assume any responsibility or liability arising out of or in connection with such information or any use thereof.
FUJITSU SEMICONDUCTOR MEMORY SOLUTION assumes no responsibility or liability for any damages whatsoever arising
out of or in connection with such information or any use thereof.
Nothing contained in this document shall be construed as granting or conferring any right under any patents, copyrights, or any other
intellectual property rights of FUJITSU SEMICONDUCTOR MEMORY SOLUTION or any third party by license or otherwise,
express or implied. FUJITSU SEMICONDUCTOR MEMORY SOLUTION assumes no responsibility or liability for any infringe­ment of any intellectual property rights or other rights of third parties resulting from or in connection with the information contained
herein or use thereof.
The products described in this document are designed, developed and manufactured as contemplated for general use including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and
manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high levels of safety is secured,
could lead directly to death, personal injury, severe physical damage or other loss (including, without limitation, use in nuclear
facility, aircraft flight control system, air traffic control system, mass transport control system, medical life support system and
military application), or (2) for use requiring extremely high level of reliability (including, without limitation, submersible repeater
and artificial satellite). FUJITSU SEMICONDUCTOR MEMORY SOLUTION shall not be liable for you and/or any third party for
any claims or damages arising out of or in connection with above-mentioned uses of the products.
Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs and
safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures into your
facility, equipments and products
operating conditions.
The products and technical information described in this document are subject to the Foreign Exchange and Foreign Trade Control
Law of Japan, and may be subject to export or import laws or regulations in U.S. or other countries. You are responsible for ensuring
compliance with such laws and regulations relating to export or re-export of the products and technical information described herein.
All company names, brand names and trademarks herein are property of their respective owners.

such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal

Edited: Marketing Division

32 DS501-00060-2v0-E