FUJITSU MB85AS8MTPF Datasheet

FUJITSU SEMICONDUCTOR

MEMORY SOLUTION DATA SHEET

Memory ReRAM

8M (1024 K  8) Bit SPI

MB85AS8MT

■ DESCRIPTION

MB85AS8MT is a ReRAM (Resistive Random Access Memory) chip in a configuration of 1,048,576
words  8 bits, using the resistance-variable memory process and silicon gate CMOS process technologies
for forming the nonvolatile memory cells.
MB85AS8MT adopts the Serial Peripheral Interf ace (SPI).
MB85AS8MT is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85AS8MT can be used for 1  10

DS501-00060-2v0-E

6

rewrite operations.

■ FEATURES

• Bit configuration : 8 Mbits (1,048,576 words  8 bits)

• Serial Peripheral Interface : SPI (Serial Peripheral Interface)
Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)

• Write buffer size : 256 bytes

• Operating frequency : 10 MHz (Max)

• Data endurance : 1  10

• Data retention : 10 years (+85 C)

• Operating power supply voltage : 1.6 V to 3.6 V

• Operating power supply current : Write current 1.5 mA (Typ)

• Operation ambient temperature range : -40 C to +85 C

• Package : 8-pin plastic SOP, 11-pin plastic WLP

6

times / 4bytes*

*4 bytes are selected by A1 to A0.

Read current 0.15 mA (Typ@5 MHz)
Standby current 60 A (Typ)
Sleep current 6 A (Typ)

RoHS compliant

Copyright 2021 FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED

2021.01

MB85AS8MT

(TOP VIEW)

8-pin SOP

(BOTTOM VIEW)

11-pin WLP Type-A

11-pin WLP Type-B
11-pin WLP Type-C

■ PIN ASSIGNMENT

VSS

CS

SO

WP

V

SS

VSS VSS

1

2

3

4

8

7

6

5

VSS

V

DD

HOLD

SCK

SI

VSS VSS

SI/SO

SCK

VSS

VSS

VSS

CS

VSSVDD

SI SO

SCK

VSS

VSS

CS

VSSVDD

2 DS501-00060-2v0-E

■ PIN FUNCTIONAL DESCRIPTIONS

Pin No. Pin Name Functional description

Chip Select pin
This is an input pin to make chips select. When CS

1CS

3WP

7HOLD

6SCK

(standby) status and SO becomes High-Z . Inp ut s fro m othe r pin s ar e ign or e d for this
time. When CS
inputting op-code.

Write Protect pin (available only for SOP package)
This is a pin to control writing to a status register. The writing of status register (see “■
STATUS REGISTER”) is protected in related with WP
PROTECT” for detail.

Hold pin (available only for SOP package)
This pin is used to interrupt serial input/output without making chips deselect. When
HOLD
do not care. See “■ HOLD OPERATION” for detail.

Serial Clock pin
This is a clock input pin to input/output serial d ata. SI is loaded synchronously t o a rising
edge, SO is output synchronously to a falling edge.

is “L” level, device is in select (active) status. CS has to be “L” level before

is “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become

is “H” level, device is in deselect

MB85AS8MT

and WPEN. See “■ WRITING

5SI

2SO

8V
4V

*: Pin No. is for SOP package.

Serial Data Input pin
This is an input pin of serial data. This inputs op-code, address, and writing dat a.

Serial Data Output pin
This is an output pin of serial data. Reading data of ReRAM memo ry cell array and status
register data are output. This is High-Z during standby.

DD Supply Voltage pin
SS Ground pin

DS501-00060-2v0-E 3

MB85AS8MT

SCK

SO

SI

Serial-Parallel Converter

ReRAM Cell Array

1,048,576 ✕ 8

Column Decoder/Sense Amp/

Write Amp

ReRAM

Status Register

Data Register

Parallel-Serial Converter

Control Circuit

Address Counter

Row Decoder

CS

WP

HOLD

SCK

SI

CS

SCK

SI

CS

76543 210

76543 210

MSBLSB

MSBLSB

SPI Mode 0

SPI Mode 3

■ BLOCK DIAGRAM

■ SPI MODE

MB85AS8MT corresponds to the SPI mode 0 ( CPOL  0, CPHA  0) , and SPI mode 3 (CPOL  1, CPHA  1) .

4 DS501-00060-2v0-E

MB85AS8MT

SCK

SS1

HOLD1

MOSI
MISO

SS2

HOLD2

SCK

CS

HOLD

SISO

SCK

CS

HOLD

SISO

MB85AS8MT MB85AS8MT

SCK

CS

HOLD

SISO

MB85AS8MT

SPI

Microcontroller

MOSI : Master Out Slave In
MISO : Master In Slave Out
SS : Slave Select

System Configuration with SPI Port

System Configuration without SPI Port

Microcontroller

■ SERIAL PERIPHERAL INTERFACE (SPI)

MB85AS8MT works as a slave of SPI. More than 2 devices can be connected by using microcontroller
equipped with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus
connected to use.

DS501-00060-2v0-E 5

MB85AS8MT

■ STATUS REGISTER

Bit No. Bit Name Function

Status Register Write Protect
This is a bit composed of nonvolatile memories (ReRAM). WPEN protects

7 WPEN

6 to 4 

3 BP1

2 BP0

writing to a status register (refer to “■ WRITING PROTECT”) relating with
WP

input. Writing with the WRSR command and reading with the RDSR

command are possible.
Not Used Bits

These are bits composed of volatile memories, writing with the WRSR
command is possible. These bits are not used b ut th ey ar e r ea d with th e
RDSR command.
Initial value is “000”.

Block Protect
This is a bit composed of nonvolatile memory. This defines size of write
protect block for the WRITE command (refer to “■ BLOCK PROTECT”).
Writing with the WRSR command and reading with t he RDSR com man d
are possible.

Write Enable Latch
This indicates ReRAM Array and status register are writable. The WREN
command is for setting, and the WRDI command is for resettin g. With the
RDSR command, reading is possible but writing is not possible with the

1WEL

0WIP

WRSR command. WEL is reset after the following operations.
After power ON.

The rising edge of CS
The end of writing process after WRSR command recognition.
The end of writing process after WRITE command recognition.

Write In Progress
This indicates ReRAM Array and status register are in writing process.
During this writing process, any commands except RDSR will not be exe­cuted (refer to “2. WIP polling”). With the RDSR command, reading is pos­sible but writing is not possible with the WRSR command.

after WRDI command recognition.

■ OP-CODE

MB85AS8MT accepts 10 kinds of command specified in op-code. Op-code is a code composed of 8 bits
shown in the table below. Do not input invalid codes other than those codes. If CS
op-code, the command are not performed.

Name Description Op-code

WREN Set Write Enable Latch 0000 0110

WRDI Reset Write Enable Latch 0000 0100B

is risen while inputting

B

RDSR Read Status Register 0000 0101B

WRSR Write Status Register 0000 0001B

READ Read Memory Code 0000 0011B

WRITE Write Memory Code 0000 0010B

RDID Read Device ID 1001 1111B
RDUID Read Device ID and Unique ID 1000 0011B
SLEEP

Enter Sleep Mode (Power Down Mode)

PWDN 1110 0010B

6 DS501-00060-2v0-E

1011 1001B

MB85AS8MT

SO

SCK

SI

CS

00000110

High-Z

76543210

InvalidInvalid

SO

SCK

SI

CS

00000100

High-Z

76543210

InvalidInvalid

■ COMMAND

 WREN

The WREN command sets WEL (Write Enable Latch) . WEL has to be set with the WREN command before
writing operation (WRSR command and WRITE command) .

 WRDI

The WRDI command resets WEL (Write Enable Latch) . Writing operation (WRSR command and WRITE
command) are not performed when WEL is reset.

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MB85AS8MT

SO

SCK

SI

CS

00000101

High-Z

76543210

Invalid

MSB

76543210

Data Out

LSB

Invalid

SO

SCK

SI

CS

00000001

76543210

Data In

MSB

76543210

High-Z

LSB

76543210

Instruction

 RDSR

The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input
to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. In the
RDSR command, repeated reading of status r egister is enabled by sen ding SCK continuously bef ore rising

.

of CS

 WRSR

The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR
op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable La tch) is not able to be written with WRSR
command. A SI value correspondent to bit 1 is ignored. Bit 0 of the sta tus register cannot be writ ten. The SI
value corresponding to bit 0 is ignored. WP
and do not change the WP

After rising edge of CS

signal level until the end of command sequence.

, MB85AS8MT starts writing operation to nonvolatile register and set WIP bit in status

signal level shall be fixed before performing WRSR command,

register to “1”. After this writing opera tion has fin ished, reset this WIP b it from “1” t o “0”. Although th e RDSR
command is executable for WIP polling during this writing process, any other commands will not be performed.

8 DS501-00060-2v0-E

MB85AS8MT

CS

SCK

SI

Invalid

MSB

LSB

MSB

Data Out

LSB

High-Z

Invalid

450123 26276 7 8 9 10 11 12 13 14 15 38 3928 29 30 31 32 33 34 35 36 37

00000011X

32

XXX 1817

16

54

SO

76 3

10

54 210

24-bit Address

OP-CODE

19

CS

SCK

Data In

SI

MSB

24-bit Address

OP-CODE

LSB MSB LSB

High-Z

10 110123456789

14 15 26 31 3212 13 27 28 29 30 33 34 35 36 37 38 39

0000001 30XXXX 210

SO

18 17 16 5 4 3 2 1 0765419

 READ

The READ command reads ReRAM memory cell array data. Arbitrar y 24 bits address and op-code of READ
are input to SI. The 4-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output
synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS
command is completed, but keeps on reading with automatic address increment which is enabled by con­tinuously sending clocks to SCK in unit of 8 cycles before CS

rising. When it reaches the most significant

address, it rolls over to the starting address, and reading cycle keeps on infinitely.

is risen, the READ

 WRITE

The WRITE command writes data to ReRAM memory cell array. WRITE op-code, arbitrary 24 bits of address
and 8 bits of writing data are input to SI. The 4-bit upper add ress bit is invalid.

During the CS
size is 256 bytes during this CS

is low, input writing data are temporary saved in the data register . The maximum writing data

= low period. If the input writing data are more than 8 bits, it is possible to
continue writing with automatic address increment. When it reaches the most significant address, it rolls
over to the starting address, and writing cycle can be continued up to 256 bytes (which is the size of data
register). Data exceed 256 bytes can not be written.

After rising edge of CS

, MB85AS8MT starts writing operation to nonvolatile memory and set WIP bit in status
register to “1”. After this writing opera tion has fin ished, reset this WIP b it from “1” t o “0”. Although th e RDSR
command is executable for WIP polling during this writing process, any other commands will not be performed.

DS501-00060-2v0-E 9

MB85AS8MT

SO

SCK

SI

CS

MSB

76543210

Data OutData Out

High-Z

LSB

111098

333231 393837363534

Invalid

30282931

10011111

201364578

bit

7 6 5 4 3 2 1 0Hex

Manufacturer ID 0000010004

H Fujitsu

Continuation code 011111117F

H

Proprietary use Density Hex

Product ID (1st Byte)10101010AA

H Density: 01010B  8 Mbit

Proprietary use Hex

Product ID (2nd Byte)0000001103

H

 RDID

The RDID command reads fixed Device ID. Aft er per f orming RDID op-cod e t o SI, 3 2-cycle clock is in put t o
SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. The output
is in order of Manufacturer ID (8bit)/Continuation code (8bit)/Product ID (1st Byte)/Product ID (2nd Byte).
In the RDID command, SO holds the output state of the last bit in 32-bit Device ID until CS

is risen.

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