Fujitsu LH530 FH1A Schematics

1

2

3

4

5

6

7

8

Intel Calpella

BlOCK DIAGRAM

A A

SYSTEM

POWER

AC/BATT
CONNECTOR

DDR3-SODIMM1

B B

DDR3-SODIMM2

RESET CIRCUIT

BATT
CHARGER

RUN POWER SW

+3V_S5/+5V_S5
+3V_SUS/+5V_SUS
+5V_RUN/+3V_RUN/+1.8V_RUN

CHA

Dual Channel DDR3
1066 1.5V

INTEL DISCRETE SYSTEM DIAGRAM

POWER

+1.5V_SUS/+0.75V_DDR_VTT
+1.05V_PCH
+1.05V_VTT

CRT

LVDS

CPU VRREGULATOR
DC/DC

+3VPCU/+5VPCU/

CRT

LVDS

CPU

Arrandale 35W

37.5mm X 37.5mm

( rPGA 989 )

PCI-E x16

FAN & THERMAL

CLOCK

SLG8SP585VTR
(QFN-32)

AMD

PARK-LP

PP;PP

7'3:

( S3 )

DDR3 800MHz

01

CHB

VRAM

DMI X 4

SATA-ODD

SATA

PCH

SATA-HDD

SATA

82801IBM

(HM55)

C C

IHDA

AUDIO/AMP

ALC269

27mm X 25mm

USB2.0 x 3

USB2.0

PCIEx1

PCIEx2

64Mx16x2,32bit

USB conn x 3

Card Reader SD MS CARD
RTS5159

LAN
Realtek 10/100/ LAN RTL8103EL

MINI-CARD
WLAN

SPI

FLASH
2Mbyts

Audio
SPK conn

Audio

LPC

Jacks

EC

ITE8502

D D

SPI PS/2

FLASH
2Mbyts

1

2

http://laptop-motherboard-schematic.blogspot.com/

3

18X8

Touchpad

Keyboard

4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Tuesday, December 15, 2009

Tuesday, December 15, 2009

Tuesday, December 15, 2009

Date: Sheet

Date: Sheet of

5

6

Date: Sheet of

7

PROJECT :

BLOCK DIAGRAM

BLOCK DIAGRAM

BLOCK DIAGRAM

FH1A

FH1A

FH1A

of

145

145

145

8

1A

1A

1A

1

2

3

4

5

6

7

8

Table of Contents

PAGE DESCRIPTION

Schematic Block Diagram

01
02

Front Page
Clock Generator

03

04-07

Arrandale

08-13

A A

B B

C C

Ibex Peak-M
DDRIII SO-DIMM(204P)

14-15

16

LCD/CCD CONN

17

CRT CONN

18

Card Reader (RTS5159)

19

LAN RTL8103EL/RJ45
HDD/ODD/HOLE

20

USB/BLUE TOOTH

21
22

MINI-Card (WLAN)/ XDP
KB/TOUCH PAD/LED

23
24

CODEC (ALC269)
EC_ ITE8502

25
26

FAN/SW CON
+5V/+3V (RT8206B)

27

+1.05V/ +1.8V (RT8204C)

28

CPU Core ( ADP3212)

29

+1.05V_VTT (VT358)

30
31

DDR3 (RT8207)

32

DISCHARGE/3VS5/5VS5/LAN
CHARGER (ISL88731)

33
34

Clock Distribution

35

Power Tree

36

SMBUS Address

37

PARK-S3_PCIE_Interface

38

PARK-S3_Main

39

PARK-S3_GND/LVDS/Straps

40

PARK-S3_Power_and_NC

41

PARK-S3_MEM_Interface

42

PARK_VRAM (DDR3 BGA96)

43

+VGACORE (RT8208/1.8V)

44

+1.5V_VGA/+1.0V_VGA

SUSB#,SUSC#,SUSD#

+1.5VSUS/+3VSUS/+5VSUS

+1.5V_RUN/+1.8V_RUN
/+3V_RUN/+5V_RUN

+VGPU_CORE/+3V_GPU/+1.8V_GPU
/+1.5V_GPU/+1.0V_GPU

+1.05V_PCH/+1.05V_VTT
/+0.75V_DDR_VTT

VR_PWRGD_CLKEN#

ACIN

+3VPCU/+5VPCU

NBSWON#

RVCC_ON

ICH_RSMRST#

DNBSWON#

SUSON

MAINON

DGPU_PWR_EN

MAINON2

HWPG

VRON

+VCC_CORE

T1

T2

T5

Power Sequence

T3

3ms~20ms

02

IMVP_PWRGD

MPWROK

H_VTTPWRGD

DRAMPWROK

VCCPPWRGOOD

PLTRST#

CPU_RST#

D D

T1: RVCCON TO RSMRST# = 30ms (spec:mini 10ms)

T4

T2: RSMRST# TO-DNBSWON = 110ms (spec:mini 100ms)

T3: MAINON2 TO VRON = 110ms (spec:mini 99ms)

Quanta Computer Inc.

Quanta Computer Inc.

T4: VRON TO MPWROK = 10ms (HWPG NEED TO BE HIGH at that time)

Note: IMVP_CLK_EN# (inverted) assertion to SYS_PWROK/PCH_PWROK assertion.

Size Document Number Rev

Size Document Number Rev

SPEC:3ms~20ms

1

2

http://laptop-motherboard-schematic.blogspot.com/

3

T5: MAINON to MAINON2 =500us

4

5

6

Size Document Number Rev

Tuesday, December 15, 2009

Tuesday, December 15, 2009

Tuesday, December 15, 2009

Date: Sheet

Date: Sheet of

Date: Sheet of

7

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Frontpage

Frontpage

Frontpage

FH1A

FH1A

FH1A

245

245

245

8

1A

1A

1A

of

5

D D

+3V_RUN

L11 BLM21PG600SN1DL11 BLM21PG600SN1D

C148

C185

C185

10U/10V_8

10U/10V_8

C C

CLK_PCH_14M10

C149

C149

0.1U/16V_4

0.1U/16V_4

0.1uF near the every power pin.

+3V_RUN

Place the 33 ohm
resistors close to the CK 505

C148

0.1U/16V_4

0.1U/16V_4

CK_PWRGD_R

CLK_PCH_14M

R139 10K/J_4R139 10K/J_4
R125 33/J_4R125 33/J_4

40mil

C179

C179

0.1U/16V_4

0.1U/16V_4

4

C181

C181

0.1U/16V_4

0.1U/16V_4

CGDAT_SMB10,14,15
CGCLK_SMB10,14,15

C165

C165

0.1U/16V_4

0.1U/16V_4

+3.3V_CLK_VDD

+VDDIO_CLK

CPU_SEL

XTAL_OUT
XTAL_IN

C145

C145

*33P/50V_4

*33P/50V_4

1

5
17
24
29
15
18

9

2

8
12
21
26

16
25
30

27
28

31
32

C146

C146
*33P/50V_4

*33P/50V_4

SLG8SP585VTR

SLG8SP585VTR

3

VDD_USB
VDD_LCD
VDD_SRC
VDD_CPU
VDD_REF
VDD_SRC_IO
VDD_CPU_IO

VSS_SATA
VSS_USB
VSS_LCD
VSS_SRC
VSS_CPU
VSS_REF

CPU_STOP#
CK_PWRGD/PD#_3.3
REF_0/CPU_SEL

XOUT
XIN

SDATA
SCLK

CK505

CK505

QFN32

QFN32

CPU-0

CPU-0#

CPU-1

CPU-1#

DOT96T_LPR
DOT96C_LPR

SRC-2

SRC-2#

SRC-1/SATA

SRC-1#/SATA#

27MHz_nonSS

27MHz_SS

GND

CLK_BUF_BCLK_P

23

CLK_BUF_BCLK_N

22
20

19

CLK_BUF_DREFCLKP

3

CLK_BUF_DREFCLKN

4

CLK_BUF_PCIE_3GPLLP

13

CLK_BUF_PCIE_3GPLLN

14

CLK_BUF_DREFSSCLKP

10

CLK_BUF_DREFSSCLKN

11

27MHZ_NONSS

6

27MHZ_SS

7

33

U6

U6

2

R343 33_4R343 33_4
R416 *33_4R416 *33_4

CLK_BUF_BCLK_P 10
CLK_BUF_BCLK_N 10

CLK_BUF_DREFCLKP 10
CLK_BUF_DREFCLKN 10

CLK_BUF_PCIE_3GPLLP 10
CLK_BUF_PCIE_3GPLLN 10

CLK_BUF_DREFSSCLKP 10

EVGA-XTALI
CLK_27M_SS

CLK_BUF_DREFSSCLKN 10
EVGA-XTALI 38

CLK_27M_SS 38

A-01

Realtek: 0.1uFx3pcs, 22uFx1pcs
IDT: 0.1uFx2pcs, 10uFx1pcs

1

+3V_RUN

L12 BLM21PG600SN1D

Y1

XTAL_IN XTAL_OUT

B B

+3V_S5

C166

C166
33P/50V_4

33P/50V_4

Y1

21

14.318MHZ

14.318MHZ
C173

C173
33P/50V_4

33P/50V_4

1 2

R142 *0/J_8R142 *0/J_8

+1.05V_PCH

R144 0/J_8R144 0/J_8

L12 BLM21PG600SN1D

805

805

C186

C186
10U/10V_8

10U/10V_8

40mil

C167

C167

0.1U/16V_4

0.1U/16V_4

+VDDIO_CLK

C180

C180

0.1U/16V_4

0.1U/16V_4

HP: 10u x2pcs

C182

C182

0.1U/16V_4

0.1U/16V_4

5

R140 0/J_4R140 0/J_4

VR_PWRGD_CLKEN#29

TC7SZ04FU(T5L,F,T)

TC7SZ04FU(T5L,F,T)

A A

5

2

U8

U8

4

3

http://laptop-motherboard-schematic.blogspot.com/

CK_PWRGD_R

+3V_RUN

R126

R126
*4.7K/J_4

*4.7K/J_4

1 2

CPU_SEL

R127

R127

4.7K/J_4

4.7K/J_4

1 2

4

C152

C152
*10P/50V_4

*10P/50V_4

EMI Capacitor

PIN 30 CPU_0 CPU_1

0(default)

1(0.7V-1.5V)

133MHz

100MHz 100MHz

3

133MHz

CPU_SEL:
SLG date sheet (V0.2) P15:
High Voltage: Min 0.7V, Max 1.5V.
Low Voltage: Min Vss-0.3V, Max 0.35V.
Realtek date sheet(V1.2) P11:
High Voltage: Min 0.7V, Max 1.5V.
Low Voltage: Min Vss-0.3V, Max 0.35V.
IDT date sheet(V0.7) P10:
High Voltage: Min 0.7V, Max 1.5V.
Low Voltage: Min Vss-0.3V, Max 0.35V.

SLG,IDT: +1.05V
Realtek: +3.3V

2

Place each 0.1uF cap as close as
possible to each VDD IO pin. Place
the 10uF caps on the VDD_IO plane.

+VDDIO_CLK:
SLG date sheet (V0.2) P15: Min 1.05V,Max3.465V.
Realtek date sheet(V1.2) P11: Min 1.05V,Max 3.3V.
IDT date sheet(V0.7) P10: Min 0.9975V,Max 3.465V.

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

Tuesday, December 15, 2009

Tuesday, December 15, 2009

Tuesday, December 15, 2009

PROJECT :

Clock Generator

Clock Generator

Clock Generator

FH1A

FH1A

FH1A

of

345

345

345

1

1A

1A

1A

5

4

3

2

1

04

U19A

U19A

DMI_TXN08

D D

DMI_TXN18
DMI_TXN28
DMI_TXN38

DMI_TXP08
DMI_TXP18
DMI_TXP28
DMI_TXP38

DMI_RXN08
DMI_RXN18
DMI_RXN28
DMI_RXN38

DMI_RXP08
DMI_RXP18
DMI_RXP28
DMI_RXP38

A-02

C C

FDI_FSYNC0
FDI_FSYNC1

FDI_INT
FDI_LSYNC0

FDI_LSYNC1

A24
C23
B22
A21

B24
D23
B23
A22

D24
G24
F23
H23

D25
F24
E23
G23

E22
D21
D19
D18
G21
E19
F21
G18

D22
C21
D20
C18
G22
E20
F20
G19

F17
E17

C17
F18

D17

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]

FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]

FDI_FSYNC[0]
FDI_FSYNC[1]

FDI_INT
FDI_LSYNC[0]

FDI_LSYNC[1]

Disable Integrated Graphics

A-02

R218 1K/F_4R218 1K/F_4

RN4 1KX4-0402RN4 1KX4-0402

B B

FDI_INT

2
4
6
8

FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

Clarksfield/Auburndale

Clarksfield/Auburndale

1
3
5
7

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS
PEG_RX#[0]

PEG_RX#[1]
PEG_RX#[2]

DMI Intel(R) FDI

DMI Intel(R) FDI

PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]

PCI EXPRESS -- GRAPHICS

PCI EXPRESS -- GRAPHICS

PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

Disable Integrated Graphics

Processor Pullups Processor Compensation Signals

+1.05V_VTT

R75

R75

49.9/F_4

49.9/F_4

H_CATERR#
H_PROCHOT#_D

A A

H_CPURST#

5

R58

R58
68/F_4

68/F_4

R64

R64
*68/J_4

*68/J_4

R48

R48

49.9/F_4

49.9/F_4

B26
A26
B27
A25

K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31

J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30

L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26

L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25

R65

R65

49.9/F_4

49.9/F_4

PEG_ICOMPI

PEG_RXN15
PEG_RXN14
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXN9
PEG_RXN8
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0

PEG_RXP15
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXP11
PEG_RXP10
PEG_RXP9
PEG_RXP8
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0

PEG_TXN14_C
PEG_TXN13_C
PEG_TXN12_C
PEG_TXN11_C
PEG_TXN10_C
PEG_TXN9_C
PEG_TXN8_C
PEG_TXN7_C
PEG_TXN6_C
PEG_TXN5_C
PEG_TXN4_C
PEG_TXN3_C
PEG_TXN2_C
PEG_TXN1_C
PEG_TXN0_C

PEG_TXP15_C
PEG_TXP14_C
PEG_TXP13_C
PEG_TXP12_C
PEG_TXP11_C
PEG_TXP10_C
PEG_TXP9_C
PEG_TXP8_C
PEG_TXP7_C
PEG_TXP6_C
PEG_TXP5_C
PEG_TXP4_C
PEG_TXP3_C
PEG_TXP2_C
PEG_TXP1_C
PEG_TXP0_C

R52

R52
20/F_4

20/F_4

R251 49.9/F_4R251 49.9/F_4

R254 750/F_4R254 750/F_4

C378 0.1U/10V_4C378 0.1U/10V_4
C380 0.1U/10V_4C380 0.1U/10V_4

C381 0.1U/10V_4C381 0.1U/10V_4
C382 0.1U/10V_4C382 0.1U/10V_4
C383 0.1U/10V_4C383 0.1U/10V_4
C384 0.1U/10V_4C384 0.1U/10V_4
C385 0.1U/10V_4C385 0.1U/10V_4
C386 0.1U/10V_4C386 0.1U/10V_4
C387 0.1U/10V_4C387 0.1U/10V_4
C388 0.1U/10V_4C388 0.1U/10V_4
C389 0.1U/10V_4C389 0.1U/10V_4
C390 0.1U/10V_4C390 0.1U/10V_4
C391 0.1U/10V_4C391 0.1U/10V_4
C392 0.1U/10V_4C392 0.1U/10V_4
C393 0.1U/10V_4C393 0.1U/10V_4

C394 0.1U/10V_4C394 0.1U/10V_4
C395 0.1U/10V_4C395 0.1U/10V_4
C396 0.1U/10V_4C396 0.1U/10V_4
C397 0.1U/10V_4C397 0.1U/10V_4
C398 0.1U/10V_4C398 0.1U/10V_4
C399 0.1U/10V_4C399 0.1U/10V_4
C400 0.1U/10V_4C400 0.1U/10V_4
C401 0.1U/10V_4C401 0.1U/10V_4
C402 0.1U/10V_4C402 0.1U/10V_4
C403 0.1U/10V_4C403 0.1U/10V_4
C404 0.1U/10V_4C404 0.1U/10V_4
C405 0.1U/10V_4C405 0.1U/10V_4
C406 0.1U/10V_4C406 0.1U/10V_4
C407 0.1U/10V_4C407 0.1U/10V_4
C408 0.1U/10V_4C408 0.1U/10V_4
C409 0.1U/10V_4C409 0.1U/10V_4

H_COMP0
H_COMP1
H_COMP2
H_COMP3

R54

R54
20/F_4

20/F_4

4

PEG_RXN15 37
PEG_RXN14 37
PEG_RXN13 37
PEG_RXN12 37
PEG_RXN11 37
PEG_RXN10 37
PEG_RXN9 37
PEG_RXN8 37
PEG_RXN7 37
PEG_RXN6 37
PEG_RXN5 37
PEG_RXN4 37
PEG_RXN3 37
PEG_RXN2 37
PEG_RXN1 37
PEG_RXN0 37

PEG_RXP15 37
PEG_RXP14 37
PEG_RXP13 37
PEG_RXP12 37
PEG_RXP11 37
PEG_RXP10 37
PEG_RXP9 37
PEG_RXP8 37
PEG_RXP7 37
PEG_RXP6 37
PEG_RXP5 37
PEG_RXP4 37
PEG_RXP3 37
PEG_RXP2 37
PEG_RXP1 37
PEG_RXP0 37

PEG_TXN15PEG_TXN15_C
PEG_TXN14
PEG_TXN13
PEG_TXN12
PEG_TXN11
PEG_TXN10
PEG_TXN9
PEG_TXN8
PEG_TXN7
PEG_TXN6
PEG_TXN5
PEG_TXN4
PEG_TXN3
PEG_TXN2
PEG_TXN1
PEG_TXN0

PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP11
PEG_TXP10
PEG_TXP9
PEG_TXP8
PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0

A-03

H_PECI11

H_PROCHOT#_D29

H_THERM11

H_CPURST#22

PM_SYNC8

PEG_TXN15 37
PEG_TXN14 37
PEG_TXN13 37
PEG_TXN12 37
PEG_TXN11 37
PEG_TXN10 37
PEG_TXN9 37
PEG_TXN8 37
PEG_TXN7 37
PEG_TXN6 37
PEG_TXN5 37
PEG_TXN4 37
PEG_TXN3 37
PEG_TXN2 37
PEG_TXN1 37
PEG_TXN0 37

PEG_TXP15 37
PEG_TXP14 37
PEG_TXP13 37
PEG_TXP12 37
PEG_TXP11 37
PEG_TXP10 37
PEG_TXP9 37
PEG_TXP8 37
PEG_TXP7 37
PEG_TXP6 37
PEG_TXP5 37
PEG_TXP4 37
PEG_TXP3 37
PEG_TXP2 37
PEG_TXP1 37
PEG_TXP0 37

HWPG25,27,43

DDR3 Compensation Signals

R112

R112
130/F_4

130/F_4

T14T14

T7T7

HWPG

R113

R113

24.9/F_4

24.9/F_4

XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TCLK

H_PWRGOOD11,22

PM_DRAM_PWRGD8

H_PWRGD_XDP22

R280 2K/F_4R280 2K/F_4

PLTRST#10,18,19,22

SM_RCOMP_2
SM_RCOMP_1
SM_RCOMP_0

R114

R114
100/F_4

100/F_4

R59 *51/J_4R59 *51/J_4
R253 *51/J_4R253 *51/J_4
R61 *51/J_4R61 *51/J_4
R39 *51/J_4R39 *51/J_4

R271 0/J_4R271 0/J_4

H_PROCHOT#_D

H_THERM

H_CPURST#

PM_DRAM_PWRGD

H_VTTPWRGD

R101 1.5K/F_4R101 1.5K/F_4

H_VTTPWRGD

R282

R282
1K/F_4

1K/F_4

+1.05V_VTT

3

T13T13

R105 0/J_4R105 0/J_4

R102

R102

750/F_4

750/F_4

H_COMP3
H_COMP2
H_COMP1
H_COMP0

TP_SKT0CC#

H_CATERR#

H_PECI_ISO

H_THERM

TEMP_FAIL38

A-05

+3V_RUN

C369

C369
*0.1U/10V_4

*0.1U/10V_4

U19B

U19B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

Clarksfield/Auburndale

Clarksfield/Auburndale

CPU THERMTRIP

IMVP_PWRGD8,29

R76 33/J_4R76 33/J_4

R417 *4.7K_4R417 *4.7K_4

2

PM_THRMTRIP# STUP AS SHORT AS PASSPBLE

CPU THERM SENSOR

4

R360

R360
*0_4

*0_4

R362

R362
*0_4

*0_4

1
2

MISC THERMAL

MISC THERMAL

CLOCKS

CLOCKS

DDR3

MISC

DDR3

MISC

PWR MANAGEMENT

PWR MANAGEMENT

JTAG & BPM

JTAG & BPM

+1.05V_VTT

3

Q2

2

2N7002EQ22N7002E

1

R72 100K/J_4R72 100K/J_4

R77

R77
1K/J_4

1K/J_4

2

Q1

SYS_SHDN#H_THERM_R

1 3

MMBT3904Q1MMBT3904

Q21

Q21
*MMBT3904-7-F

*MMBT3904-7-F

1 3

U24

U24

SYS_SHDN_1# SYS_SHDN#

5

VDD

OS

CTRL

3

GND

Vtemp

*BDE0900G

*BDE0900G

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PM_EXT_TS#[0]
PM_EXT_TS#[1]

PRDY#
PREQ#

TRST#

TDI_M

TDO_M

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

R361 *0/J_4R361 *0/J_4

(6

2

http://laptop-motherboard-schematic.blogspot.com/

A16
B16

AR30
AT30

E16
D16

A18
A17

F6
AL1

AM1
AN1

AN15
AP15

AT28
AP27

AN28

TCK

AP28

TMS

AT27
AT29

TDI

AR27

TDO

AR29
AP29

AN25

AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23

SYS_SHDN# 27

DDR3_DRAMRST#_C

SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2

XDP_PREQ#
XDP_TCLK

XDP_TMS
XDP_TRST#

XDP_TDI_R
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M

H_DBR#_R

XDP_OBS0_R

R28 0/J_4R28 0/J_4

XDP_OBS1_R

R37 0/J_4R37 0/J_4

XDP_OBS2_R

R32 0/J_4R32 0/J_4

XDP_OBS3_R

R29 0/J_4R29 0/J_4

XDP_OBS4_R

R36 0/J_4R36 0/J_4

XDP_OBS5_R

R30 0/J_4R30 0/J_4

XDP_OBS6_R

R33 0/J_4R33 0/J_4

XDP_OBS7_R

R31 0/J_4R31 0/J_4

XDP_TDI_R
XDP_TDO_M

XDP_TDI_M
XDP_TDO_R

DDR3_DRAMRST#_C

CLK_CPU_BCLKP 11
CLK_CPU_BCLKN 11

CLK_BCLK_ITPP 22
CLK_BCLK_ITPN 22

CLK_PCIE_3GPLLP 10
CLK_PCIE_3GPLLN 10

A-04

Disable UMA

for S3 power reduction

R91 10K/J_4R91 10K/J_4
R86 10K/J_4R86 10K/J_4

T41T41
T38T38
T39T39

R43 0/J_4R43 0/J_4C379 0.1U/10V_4C379 0.1U/10V_4

R103 0/J_4R103 0/J_4
R83 0/J_4R83 0/J_4

XDP_PRDY# 22
XDP_PREQ# 22

XDP_TCLK 22
XDP_TMS 22
XDP_TRST# 22

XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7

R249 0/J_4R249 0/J_4
R41 *0/J_4R41 *0/J_4

R44

R44
0/J_4

0/J_4

R250 *0/J_4R250 *0/J_4
R257 0/J_4R257 0/J_4

12
12

For S3 power reduction

R330 *0/J_4R330 *0/J_4

2N7002W-7-F

2N7002W-7-F

Q16

Q16

31

2

R331

R331
100K/J_4

100K/J_4

+1.5V_RUN

R294

R294

*1.1K/F_4

*1.1K/F_4

R293

R293

750/F_4

750/F_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

Tuesday, December 15, 2009

Tuesday, December 15, 2009

Tuesday, December 15, 2009

R329 *0/J_4R329 *0/J_4
R325 0/J_4R325 0/J_4

C370

C370

0.1U/25V/X7R

0.1U/25V/X7R

PM_DRAM_PWRGD

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

ARRANDALE 1/4

ARRANDALE 1/4

ARRANDALE 1/4

+1.05V_VTT

PM_EXTTS#0 14
PM_EXTTS#1 15

R80

R80

*12.4K/F_4

*12.4K/F_4

XDP_TRST#

+1.5V_SUS

R332

R332
1K/F_4

1K/F_4

R288 1.5K/F_4R288 1.5K/F_4

1

XDP_DBRESET# 8,22
XDP_OBS[0:7] 22

XDP_TDI 22
XDP_TDO 22

R259

R259
51/J_4

51/J_4

DDR3_DRAMRST# 14,15

DDR3_CORL_EC 25
DDR3_CORL_PCH 11

HWPG

FH1A

FH1A

FH1A

of

445

445

445

1A

1A

1A

5

4

3

2

1

ARRANDALE PROCESSOR (DDR3)

U19C

U19C

U19D

U19D

05

AA6

SA_CK[0]

D D

M_A_DQ[63:0]14

C C

B B

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

M_A_BS014
M_A_BS114
M_A_BS214

M_A_CAS#14
M_A_RAS#14
M_A_WE#14

AG5

AJ10
AL10

AK12

AK8

AK11

AN8
AM10
AR11

AL11

AM9

AN9

AT11

AP12
AM12
AN12
AM13

AT14

AT12

AL13
AR14

AP14

A10
C10

B10
D10
E10

F10

H10

G10

AH5
AF5
AK6
AK7
AF6

AJ7
AJ6

AJ9

AL7
AL8

AC3
AB2

AE1
AB3
AE9

J10

C7
A7

A8
D8

E6
F7
E9
B7
E7
C6

G8
K7

J8

G7

J7

L7
M6
M8

L9

L6
K8
N8
P9

U7

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_CK#[0]
SA_CKE[0]

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AA7
P7

Y6
Y5
P6

AE2
AE8

AD8
AF9

B9
D7
H7
M7
AG6
AM7
AN10
AN13

C9
F8
J9
N9
AH7
AK9
AP11
AT13

C8
F9
H9
M9
AH8
AK10
AN11
AR13

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7

M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7

M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_CLKP0 14
M_A_CLKN0 14
M_A_CKE0 14

M_A_CLKP1 14
M_A_CLKN1 14
M_A_CKE1 14

M_A_CS0# 14
M_A_CS1# 14

M_A_ODT0 14
M_A_ODT1 14

M_A_DM[7:0] 14

DM signals are not present on Clarkfield
processor. All DM signal can be left as
NC on Clarkfield and connect directly to
GND on So-DIMM side for Clarkfield
design only

M_A_DQSN[7:0] 14

M_A_DQSP[7:0] 14

M_A_A[15:0] 14

M_B_DQ[63:0]15

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60M_A_A0
M_B_DQ61
M_B_DQ62
M_B_DQ63

M_B_BS015
M_B_BS115
M_B_BS215

M_B_CAS#15
M_B_RAS#15
M_B_WE#15

AF3

AG1

AK1
AG4
AG3

AH4

AK3

AK4
AM6

AN2

AK5

AK2
AM4
AM3

AP3

AN5

AT4

AN6

AN4

AN3

AT5

AT6

AN7

AP6

AP8

AT9

AT7

AP9

AR10
AT10

AB1

AC5

AC6

AJ3

AJ4

B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2

G1
G5

K2
L3

M1

K5
K4

M4

N5

W5

R7

Y7

J6
J3

J2
J1
J5

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

DDR SYSTEM MEMORY - B

DDR SYSTEM MEMORY - B

SB_CK[0]
SB_CK#[0]
SB_CKE[0]

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DM[0]

SB_DM[1]

SB_DM[2]

SB_DM[3]

SB_DM[4]

SB_DM[5]

SB_DM[6]

SB_DM[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

SB_MA[7]

SB_MA[8]

SB_MA[9]

SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

W8
W9
M3

V7
V6
M2

AB8
AD6

AC7
AD1

D4
E1
H3
K1
AH1
AL2
AR4
AT8

D5
F4
J4
L4
AH2
AL4
AR5
AR8

C5
E3
H4
M5
AG2
AL5
AP5
AR7

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQSN0
M_B_DQSN1
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7

M_B_DQSP0
M_B_DQSP1
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_CLKP0 15
M_B_CLKN0 15
M_B_CKE0 15

M_B_CLKP1 15
M_B_CLKN1 15
M_B_CKE1 15

M_B_CS0# 15
M_B_CS1# 15

M_B_ODT0 15
M_B_ODT1 15

M_B_DM[7:0] 15

DM signals are not present on Clarkfield
processor. All DM signal can be left as
NC on Clarkfield and connect directly to
GND on So-DIMM side for Clarkfield
design only

M_B_DQSN[7:0] 15

M_B_DQSP[7:0] 15

M_B_A[15:0] 15

Clarksfield/Auburndale

Clarksfield/Auburndale

A A

Channel A DQ[15,32,48,54], DM[5]
Requires minimum 12mils spacing
with all other signals, including data signals.

5

http://laptop-motherboard-schematic.blogspot.com/

Channel B DQ[16,18,36,42,56,57,60,61,62]
Requires minimum 12mils spacing
with all other signals, including data signals.

4

3

Clarksfield/Auburndale

Clarksfield/Auburndale

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Tuesday, December 15, 2009

Tuesday, December 15, 2009

Tuesday, December 15, 2009

Date: Sheet

Date: Sheet of

2

Date: Sheet of

PROJECT :

ARRANDALE 2/4

ARRANDALE 2/4

ARRANDALE 2/4

FH1A

FH1A

FH1A

545

545

545

1

1A

1A

1A

of

5

U19F

CPU Core Power

+VCC_CORE=4.8 max

+VCC_CORE

D D

C C

B B

A A

U19F

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

Clarksfield/Auburndale

Clarksfield/Auburndale

1.1V RAIL POWER

1.1V RAIL POWER

CPU CORE SUPPLY

CPU CORE SUPPLY

POWER

POWER

PROC_DPRSLPVR

CPU VIDS

CPU VIDS

VTT_SELECT

VCC_SENSE
VSS_SENSE

VSS_SENSE_VTT

SENSE LINES

SENSE LINES

AH14

VTT0_1

AH12

VTT0_2

AH11

VTT0_3

AH10

VTT0_4

J14

VTT0_5

J13

VTT0_6

H14

VTT0_7

H12

VTT0_8

G14

VTT0_9

G13

VTT0_10

G12

VTT0_11

G11

VTT0_12

F14

VTT0_13

F13

VTT0_14

F12

VTT0_15

F11

VTT0_16

E14

VTT0_17

E12

VTT0_18

D14

VTT0_19

D13

VTT0_20

D12

VTT0_21

D11

VTT0_22

C14

VTT0_23

C13

VTT0_24

C12

VTT0_25

C11

VTT0_26

B14

VTT0_27

B12

VTT0_28

A14

VTT0_29

A13

VTT0_30

A12

VTT0_31

A11

VTT0_32

AF10

VTT0_33

AE10

VTT0_34

AC10

VTT0_35

AB10

VTT0_36

Y10

VTT0_37

W10

VTT0_38

U10

VTT0_39

T10

VTT0_40

J12

VTT0_41

J11

VTT0_42

J16

VTT0_43

J15

VTT0_44

VTT0_43,VTT0_44:(Intel feedback)
They are connected to hidden page for
intel validation purpose.

H_PSI#

AN33

PSI#

VID0

AK35

VID[0]

VID1

AK33

VID[1]

VID2

AK34

VID[2]

VID3

AL35

VID[3]

VID4

AL33

VID[4]

VID5

AM33

VID[5]

VID6

AM35

VID[6]

DPRSLPVR

AM34

G15

AN35

ISENSE

AJ34
AJ35

B15

VTT_SENSE

A15

VSS_SENSE_VTT:
SC(V1.0)P20
Connect VSS_SENSE_VTT to GND
or can be left floating.
Note: CRB has the VSS_SENSE_VTT floating.

AUBURNDALE/CLARKSFIELD PROCESSOR (POWER)

5

4

+1.05V_VTT=1.8 max

C103

C103

C318

C318

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

C105

C105

C102

C102

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

+1.05V_VTT

C329

C329

C313

C313

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

C308

C308

C96

C96

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

H_PSI# 29

VID0 29
VID1 29
VID2 29
VID3 29
VID4 29
VID5 29
VID6 29
DPRSLPVR 29

H_VTTVID1 30

I_MON 29

VTT_SENSE 30
VSS_SENSE_VTT 30

4

+1.05V_VTT

C311

C311

C309

C107

C107

10U/6.3V_8

10U/6.3V_8

C326

C326

10U/6.3V_8

10U/6.3V_8

C304

C304
22U/6.3V_8

22U/6.3V_8

+1.05V_VTT

C309
*10U/6.3V_8

*10U/6.3V_8

*10U/6.3V_8

*10U/6.3V_8

C99

C99

10U/6.3V_8

10U/6.3V_8

+1.05V_VTT

C101

C101

C319

C319
22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

C316

C316

C317

C317
22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

C315

C315

C331

C331

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

+VCC_CORE

VCC_SENSE & VSS_SENSE:
SC(V1.0)P19

R216

R216

100- ±1% pull-down to GND near processor

100/F_4

100/F_4

VCCSENSE 29
VSSSENSE 29

R217

R217
100/F_4

100/F_4

PROC_DPRSLPVR:
SC(V1.0)P19:
It is important to have the resistor stuffing options
in the design for the Turbo functionality.
The stuffing and no-stuffing of the resistors
will depend on the POC configuration of AUB
and CFD
CRB(V1.0)P67:
uses 1K pull-up and pull-down resistors
CRB default setting is "1"

3

ARRANDALE PROCESSOR (GRAPHICS POWER)

U19G

U19G

AT21

VAXG1

AT19

VAXG2

AT18

VAXG3

AT16

VAXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

Clarksfield/Auburndale

Clarksfield/Auburndale

Note:
For Validating IMVP VR R814 should be STUFF
and R827 NO_STUFF

3

GRAPHICS

GRAPHICS

FDI PEG & DMI

FDI PEG & DMI

POWER

POWER

VID0
VID1
VID2
VID3
VID4
VID5
VID6
DPRSLPVR
H_PSI#

SENSE

SENSE

VSSAXG_SENSE

LINES

LINES

GFX_DPRSLPVR

GRAPHICS VIDs

GRAPHICS VIDs

DDR3 - 1.5V RAILS

DDR3 - 1.5V RAILS

1.1V1.8V

1.1V1.8V

VAXG_SENSE

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

GFX_VR_EN

GFX_IMON

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

VTT0_59
VTT0_60
VTT0_61
VTT0_62

VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68

VCCPLL1
VCCPLL2
VCCPLL3

R225

R225
1K/J_4

1K/J_4

R226

R226
*1K/J_4

*1K/J_4

R227

R227
1K/J_4

1K/J_4

R228

R228
*1K/J_4

*1K/J_4

AR22
AT22

AM22
AP22
AN22
AP23
AM23
AP24
AN24

AR25
AT25
AM24

AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

P10
N10
L10
K10

J22
J20
J18
H21
H20
H19

L26
L27
M26

R230

R230
1K/J_4

1K/J_4

R231

R231
*1K/J_4

*1K/J_4

R220 1K/F_4R220 1K/F_4

C125

C125

1U/6.3V_4

1U/6.3V_4

10U/6.3V_8

10U/6.3V_8

22U/6.3V_8

22U/6.3V_8

C42

C42

1U/6.3V_4

1U/6.3V_4

+1.05V_VTT

R233

R233

R236

R236
*1K/J_4

*1K/J_4

*1K/J_4

*1K/J_4

R237

R237

R234

R234

1K/J_4

1K/J_4

1K/J_4

1K/J_4

C124

C124
1U/6.3V_4

1U/6.3V_4

+

+

C122

C122
330U/2.5V_7343

330U/2.5V_7343

7343

7343

2.5

2.5

C104

C104

C330

C330

1U/6.3V_4

1U/6.3V_4

R239

R239
1K/J_4

1K/J_4

R240

R240
*1K/J_4

*1K/J_4

C50

C50

2

10U/6.3V_8

10U/6.3V_8

22U/6.3V_8

22U/6.3V_8

2

C127

C127
1U/6.3V_4

1U/6.3V_4

C106

C106

C314

C314

C65

C65

2.2U/6.3V_6

2.2U/6.3V_6

R243

R243
*1K/J_4

*1K/J_4

R244

R244
1K/J_4

1K/J_4

A-06A-06

Disable UMA

C126

C126

C128

C128

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4

C121

C121
22U/6.3V_8

22U/6.3V_8

+1.05V_VTT

+

+

C110

C110

*330U/2.5V_7343

*330U/2.5V_7343

C66

C66

4.7U/6.3V_6

4.7U/6.3V_6

R209

R209

R208

R208
1K/J_4

1K/J_4

*1K/J_4

*1K/J_4

R213

R213

R214

R214

*1K/J_4

*1K/J_4

1K/J_4

1K/J_4

C120

C120
22U/6.3V_8

22U/6.3V_8

+1.8V_RUN

22U/6.3V_8

22U/6.3V_8

+1.5V_RUN

C297

C297

1

For S3 power reduction

Check to ensure that 4 stitching caps per SODIMM
connector between SODIMM 1.5V and GND are placed as
close as possible to the connectors – caps should be
evenly distributed between the connectors

+VCC_CORE

C302

C302

C54

C54

C281

C281

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

C276

C276

C38

C38

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

C56

C56

C79

C79

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

C300

C300

C301

C301

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

C37

C37

C57

C57

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

+

+

+

C277

C277
*470U/6.3V_7343

*470U/6.3V_7343

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

+

C90

C90
*470U/6.3V_7343

*470U/6.3V_7343

ARRANDALE 3/4

ARRANDALE 3/4

ARRANDALE 3/4

Tuesday, December 15, 2009

Tuesday, December 15, 2009

Tuesday, December 15, 2009

C52

C52

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

C59

C59

C58

C58

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

C36

C36

C81

C81

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

C286

C286

C80

C80

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

C303

C303

C78

C78

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

06

C291

C291

C53

C53

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

C280

C280

C285

C285

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

C55

C55

C299

C299

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

C82

C82

C35

C35

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

FH1A

FH1A

FH1A

of

645

645

645

1A

1A

1A

http://laptop-motherboard-schematic.blogspot.com/

5

ARRANDALE PROCESSOR (GND)

U19I

U19H

U19H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

AR20

VSS8

AR17

D D

C C

B B

VSS9

AR15

VSS10

AR12

VSS11

AR9

VSS12

AR6

VSS13

AR3

VSS14

AP20

VSS15

AP17

VSS16

AP13

VSS17

AP10

VSS18

AP7

VSS19

AP4

VSS20

AP2

VSS21

AN34

VSS22

AN31

VSS23

AN23

VSS24

AN20

VSS25

AN17

VSS26

AM29

VSS27

AM27

VSS28

AM25

VSS29

AM20

VSS30

AM17

VSS31

AM14

VSS32

AM11

VSS33

AM8

VSS34

AM5

VSS35

AM2

VSS36

AL34

VSS37

AL31

VSS38

AL23

VSS39

AL20

VSS40

AL17

VSS41

AL12

VSS42

AL9

VSS43

AL6

VSS44

AL3

VSS45

AK29

VSS46

AK27

VSS47

AK25

VSS48

AK20

VSS49

AK17

VSS50

AJ31

VSS51

AJ23

VSS52

AJ20

VSS53

AJ17

VSS54

AJ14

VSS55

AJ11

VSS56

AJ8

VSS57

AJ5

VSS58

AJ2

VSS59

AH35

VSS60

AH34

VSS61

AH33

VSS62

AH32

VSS63

AH31

VSS64

AH30

VSS65

AH29

VSS66

AH28

VSS67

AH27

VSS68

AH26

VSS69

AH20

VSS70

AH17

VSS71

AH13

VSS72

AH9

VSS73

AH6

VSS74

AH3

VSS75

AG10

VSS76

AF8

VSS77

AF4

VSS78

AF2

VSS79

AE35

VSS80

Clarksfield/Auburndale

Clarksfield/Auburndale

VSS

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

U19I

K27

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

Clarksfield/Auburndale

Clarksfield/Auburndale

4

VSS

VSS

NCTF

NCTF

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7

AT35
AT1
AR34
B34
B2
B1
A35

3

2

1

ARRANDALE PROCESSOR( RESERVED, CFG)

U19E

CFG0

CFG3
CFG4

CFG7

U19E

AP25

RSVD1

AL25

RSVD2

AL24

RSVD3

AL22

RSVD4

AJ33

RSVD5

AG9

RSVD6

M27

RSVD7

L28

RSVD8

J17

SA_DIMM_VREF

H17

SB_DIMM_VREF

G25

RSVD11

G17

RSVD12

E31

RSVD13

E30

RSVD14

AM30

CFG[0]

AM28

CFG[1]

AP31

CFG[2]

AL32

CFG[3]

AL30

CFG[4]

AM31

CFG[5]

AN29

CFG[6]

AM32

CFG[7]

AK32

CFG[8]

AK31

CFG[9]

AK28

CFG[10]

AJ28

CFG[11]

AN30

CFG[12]

AN32

CFG[13]

AJ32

CFG[14]

AJ29

CFG[15]

AJ30

CFG[16]

AK30

CFG[17]

H16

RSVD_TP_86

B19

RSVD15

A19

RSVD16

A20

RSVD17

B20

RSVD18

U9

RSVD19

T9

RSVD20

AC9

RSVD21

AB9

RSVD22

C1

RSVD_NCTF_23

A3

RSVD_NCTF_24

J29

RSVD26

J28

RSVD27

A34

RSVD_NCTF_28

A33

RSVD_NCTF_29

C35

RSVD_NCTF_30

B35

RSVD_NCTF_31

Clarksfield/Auburndale

Clarksfield/Auburndale

RSVD_NCTF_37

RSVD_NCTF_40
RSVD_NCTF_41

RSVD_NCTF_42
RSVD_NCTF_43

RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57

RSVD_TP_59
RSVD_TP_60

RESERVED

RESERVED

RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

RSVD32
RSVD33

RSVD34
RSVD35

RSVD36

RSVD38
RSVD39

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53

RSVD58

KEY
RSVD62
RSVD63
RSVD64
RSVD65

VSS

AJ13
AJ12

AH25
AK26

AL26
AR2

AJ26
AJ27

AP1
AT2

AT3
AR1

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32

E15
F15
A2
D15
C15
AJ15
AH15

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

AP34

Can be left NC is Intel CRM

R215

R215

implementation; ESD/DG

0/J_4

0/J_4

recommendation to GND

07

10

CFG4

A A

The Clarkfield processor's PCI Express interface may
not meet PCI Express 2.0 jitter specifications. Intel
recommends placing a 3.01K +/- 5% pull down resistor to
VSS on CFG[7] pin for both rPGA and BGA components.
This pull down resistor should be removed when this
issue is fixed.

5

CFG0
CFG3
CFG4
CFG7

4

R245 *3.01K/F_4R245 *3.01K/F_4
R35 *3.01K/F_4R35 *3.01K/F_4
R34 *3.01K/F_4R34 *3.01K/F_4
R246 *3.01K/F_4R246 *3.01K/F_4

(Display Port
Presence)

CFG0
(PCI-Epress
Configuration Select)

CFG3
(PCI-Epress Static
Lane Reversal)

Disabled; No Physical Display Port
attached to Embedded Diplay Port

Single PEG

Normal Operation

3

Enabled; An external Display port
device is connected to the Embedded
Display port

Bifurcation enabled

Lane Numbers Reversed

2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

Friday, December 04, 2009

Friday, December 04, 2009

Friday, December 04, 2009

PROJECT :

ARRANDALE 4/4

ARRANDALE 4/4

ARRANDALE 4/4

FH1A

FH1A

FH1A

of

745

745

1

745

1A

1A

1A

http://laptop-motherboard-schematic.blogspot.com/

5

4

3

2

1

IBEX PEAK-M (DMI,FDI,GPIO)

U18C

U18C

DMI_RXN04
DMI_RXN14
DMI_RXN24
DMI_RXN34

XDP_DBRESET#4,22

PM_DRAM_PWRGD4

ICH_RSMRST#25

SUS_PWR_ACK25

DNBSWON#25

AC_PRESENT25

CLKRUN#

XDP_DBRESET#

PM_RI#
PCIE_WAKE#
PM_BATLOW#
AC_PRESENT
SUS_PWR_ACK

DMI_RXP04
DMI_RXP14
DMI_RXP24
DMI_RXP34

DMI_TXN04
DMI_TXN14
DMI_TXN24
DMI_TXN34

DMI_TXP04
DMI_TXP14
DMI_TXP24
DMI_TXP34

+1.05V_PCH

PCH_PWRGD

R300 8.2K_4R300 8.2K_4

R296 1K/J_4R296 1K/J_4

R275 10K/J_4R275 10K/J_4
R81 10K/J_4R81 10K/J_4
R289 8.2K/J_4R289 8.2K/J_4
R111 8.2K/J_4R111 8.2K/J_4
R109 8.2K/J_4R109 8.2K/J_4

R57 49.9/F_4R57 49.9/F_4

R107 0/J_4R107 0/J_4

R265 0/J_4R265 0/J_4

R98 0/J_4R98 0/J_4

+3V_RUN

+3V_S5

IMVP_PWRGD4,29

MPWROK16,25

DMI_ZCOMP

XDP_DBRESET#

SYS_PWROK

PWROK

MEPWROK

LAN_RST#

ICH_RSMRST#

SUS_PWR_ACK

AC_PRESENT

PM_BATLOW#

PM_RI#

PCH_PWRGD
ICH_RSMRST#
LAN_RST#
PM_SLP_LAN#_R

D D

C C

B B

A A

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IbexPeak-M_R1P0

IbexPeak-M_R1P0

R99 10K/J_4R99 10K/J_4
R263 10K/J_4R263 10K/J_4
R273 10K/J_4R273 10K/J_4
R85 10K/J_4R85 10K/J_4

+3V_RUN +3V_S5

R115

R115
*2K_4

*2K_4

C111

C111
*0.1U_4

*0.1U_4

DMI

FDI

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

System Power Management

SLP_LAN# / GPIO29

C109 *0.1U/10V_4C109 *0.1U/10V_4

U5

U5

2
1

4

MC74VHC1G08DFT2G

MC74VHC1G08DFT2G

3 5

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

PCH_PWRGD

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

BJ14
BF13
BH13
BJ12
BG14

J12

Y1

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

PCIE_WAKE#

CLKRUN#

RSV_LPCPD#

ICH_SUSCLK

SLP_M#_R

PM_SLP_LAN#_R

A-02

Disable UMA

PCIE_WAKE# 19

T17T17

T25T25

SIO_SLP_S5# 25

SIO_SLP_S4# 25

SIO_SLP_S3# 25

T16T16

T51T51

PM_SYNC 4

A-07

R38 1K/D_4R38 1K/D_4

http://laptop-motherboard-schematic.blogspot.com/

5

4

3

IBEX PEAK-M (LVDS,DDI)

U18D

U18D

AB48

AB46

AP39
AP41

AT43
AT42

AV53
AV51

BB47
BA52
AY48
AV47

BB48
BA50
AY49
AV48

AP48
AP47

AY53

AT49

AU52

AT53

AY51

AT48

AU50

AT51

AA52
AB53
AD53

AD48
AB51

T48
T47

Y48

Y45

V48

V51
V53

Y53
Y51

L_BKLTEN
L_VDD_EN

L_BKLTCTL
L_DDC_CLK

L_DDC_DATA
L_CTRL_CLK

L_CTRL_DATA
LVD_IBG

LVD_VBG
LVD_VREFH

LVD_VREFL

LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

IbexPeak-M_R1P0

IbexPeak-M_R1P0

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

LVDS

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

CRT

2

BJ46
BG46

BJ48
BG48

BF45

SDVO_INTN

BH45

SDVO_INTP

T51
T53

BG44

DDPB_AUXN

BJ44

DDPB_AUXP

AU38

DDPB_HPD

BD42

DDPB_0N

BC42

DDPB_0P

BJ42

DDPB_1N

BG42

DDPB_1P

BB40

DDPB_2N

BA40

DDPB_2P

AW38

DDPB_3N

BA38

DDPB_3P

Y49
AB49

BE44

DDPC_AUXN

BD44

DDPC_AUXP

AV40

DDPC_HPD

BE40

DDPC_0N

BD40

DDPC_0P

BF41

DDPC_1N

BH41

DDPC_1P

BD38

DDPC_2N

BC38

DDPC_2P

BB36

DDPC_3N

BA36

DDPC_3P

U50
U52

BC46

DDPD_AUXN

BD46

DDPD_AUXP

AT38

DDPD_HPD

BJ40

DDPD_0N

BG40

DDPD_0P

BJ38

DDPD_1N

BG38

DDPD_1P

BF37

DDPD_2N

BH37

DDPD_2P

BE36

DDPD_3N

BD36

DDPD_3P

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

IBEX PEAK-M 1/6

IBEX PEAK-M 1/6

IBEX PEAK-M 1/6

Tuesday, December 15, 2009

Tuesday, December 15, 2009

Tuesday, December 15, 2009

1

08

FH1A

FH1A

FH1A

of

845

845

845

1A

1A

1A

5

+VCC_RTC

RTC BATTERY

D18

R348

R348

+3VPCU

1K/J_4

1K/J_4

D D

+5VPCU

R351 *2.2K/F_4R351 *2.2K/F_4

R349

R349
*4.7K_4

*4.7K_4

R350

R350
*15K_4

*15K_4

C C

CODEC

ACZ_SYNC_R24
ACZ_RST#_R24
ACZ_SDOUT_R24
ACZ_BIT_CLK_R24

Place all series terms close to PCH except for SDIN input
lines,which should be close to source.Placement of R773, R775,
R776 & R777 should equal distance to the T split trace point.
Basically, keep the same distance from T for all series
termination resistors.

B B

+3V_RUN

1 2

R295 *1K/J_4R295 *1K/J_4

+3V_S5

Res. of TDI near PCH

R315

R315

R306

R306

200/J_4

200/J_4

200/J_4

200/J_4

A A

R316

R316
100/J_4

100/J_4

R307

R307
100/J_4

100/J_4

R312

R312
200/J_4

200/J_4

R290

R290
100/J_4

100/J_4

*MMBT3904

*MMBT3904

PCBEEP

R305

R305
*20K/J_4

*20K/J_4

R304

R304
*10K/J_4

*10K/J_4

5

Q17

Q17

2

D18

2 1

CH501H-40

CH501H-40

+VCCRTC3

D17

D17

2 1

CH501H-40

CH501H-40

R347

R347
1K/J_4

1K/J_4

13

CON11

CON11

1

1

2

2

AAA-BAT-054-K01

AAA-BAT-054-K01

bat-ap-aaa-bat-054-k01-2p

bat-ap-aaa-bat-054-k01-2p

A-08

R264

R264
1M/F_4

1M/F_4

A-09

Flash Descriptor Security Override

R252 33/J_4R252 33/J_4
R238 33/J_4R238 33/J_4
R258 33/J_4R258 33/J_4
R242 33/J_4R242 33/J_4 T50T50

C295

C295
*27P/50V_4

*27P/50V_4

50

50

ACZ_SYNC
ACZ_RST#
ACZ_SDOUT
ACZ_BIT_CLK

No Reboot strap.

Low = Default.

PCBEEP

High = No Reboot.

JTAG
Test Pads are need to put on
the same side of mother board.

PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_RST#

NC all Res. when
PCH is
production stage.

Res. of TDO
PCH ES1 stage : NC
PCH ES2 stage : pop

GPIO33

(Internal 20K/F pull high to +3.3V_RUN)

Note : GPIO33 is a signal used for Flash
Descriptor Security Override/ME Debug
Mode.This signal should be only asserted
lowthrough an external pull-down in
manufacturing or debug environments
ONLY.

4

R267 20K/F_4R267 20K/F_4

C307

C307

1U/6.3V_4

1U/6.3V_4

R266 20K/F_4R266 20K/F_4

Note : Only pop when PCH is production
stage & need "JTAG boundary Scan".
Remember to depop XDP side Res.

C306

C306

1U/6.3V_4

1U/6.3V_4

INTVRMEN(Internal Voltage Regulator Enable) :
This signal enables the internal 1.05 V regulators.
This signal must be always pulled-up to VccRTC.

Low = Enabled
High = Disabled

R308 51/J_4R308 51/J_4

4

PCH_JTAG_TCK_BUF

MEFW_OVERRIDE25

3

C310

C310

15P/50V_4

15P/50V_4

23

Y5

R272

R272
10M/J_4

10M/J_4

4 1

C312

C312

32.768KHZY532.768KHZ

15P/50V_4

15P/50V_4

Cap values depend on Xtal

+VCC_RTC

CODEC

R270 330K/J_4R270 330K/J_4

PCBEEP24

ACZ_SDIN024

ACZ_BIT_CLK
ACZ_SYNC
PCBEEP
ACZ_RST#

A-09

ACZ_SDOUT

ME_FW_OVERRIDE

For PCH 32Mbit (4M Byte)

SPI_CS0#

R311 15/J_4R311 15/J_4

SPI_CLK

R292 15/J_4R292 15/J_4

SPI_SI

R323 15/J_4R323 15/J_4

SPI_SO

R313 15/J_4R313 15/J_4

R53 1K/F_4R53 1K/F_4

GPIO13_PCH

PR83 10K/F_4PR83 10K/F_4

PCH_JTAG_TCK_BUF
PCH_JTAG_TMS

T49T49

PCH_JTAG_TDI

T45T45

PCH_JTAG_TDO

T47T47

PCH_JTAG_RST#

T48T48

SPI_CLK
SPI_CS0#

SPI_CS1#

T20T20

SPI_SI
SPI_SO

SPI_CS0#_R
SPI_CLK_R
SPI_SI_R
SPI_SO_R

3

2

IBEX PEAK-M (HDA,JTAG,SATA)

U18A

RTC_X1
RTC_X2

RTC_RST#
SRTC_RST#

SM_INTRUDER#
PCH_INVRMEN

1 2

C328

C328
22P/50V_4

22P/50V_4

50

50

B13
D13

C14
D17
A16
A14

A30
D29

P1

C30

G30
F30
E32
F32

B29

H32

J30

M3
K3
K1

BA2
AV3
AY3

AY1
AV1

R314

R314
10K/J_4

10K/J_4

U20

U20

1

CE#

6

SCK

5

SI

2

SO

3

WP#

MX25L1605DM2I

MX25L1605DM2I

U18A

RTCX1
RTCX2

RTCRST#
SRTCRST#
INTRUDER#
INTVRMEN

HDA_BCLK
HDA_SYNC
SPKR
HDA_RST#

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

HDA_SDO

HDA_DOCK_EN# / GPIO33
HDA_DOCK_RST# / GPIO13

JTAG_TCK
JTAG_TMS
JTAG_TDI

J2

JTAG_TDO

J4

TRST#

SPI_CLK
SPI_CS0#
SPI_CS1#

SPI_MOSI
SPI_MISO

IbexPeak-M_R1P0

IbexPeak-M_R1P0

8

VDD

7

HOLD#

4

VSS

RTCIHDA

RTCIHDA

SPI JTAG

SPI JTAG

+3V_RUN+3V_RUN

C327

C327

0.1U/10V_4

0.1U/10V_4

10

10

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

FWH4 / LFRAME#

LDRQ1# / GPIO23

LPC

LPC

SATA0RXN
SATA0RXP
SATA0TXN

SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN

SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN

SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN

SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA

SATA

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

SATA0GP / GPIO21
SATA1GP / GPIO19

R291

R291
10K/J_4

10K/J_4

LDRQ0#

SERIRQ

2

RP4

RP4

R_LAD0

D33

R_LAD1

B33

R_LAD2

C32

R_LAD3

A32
C34
A34

F34
AB9

AK7
AK6
AK11
AK9

AH6
AH5
AH9
AH8

AF11
AF9
AF7
AF6

SATA port 2/3 are not support in HM55 .

AH3
AH1
AF3
AF1

AD9
AD8
AD6
AD5

AD3
AD1
AB3
AB1

AF16

SATA_COMP

AF15

SATA_ACT#

T3

R66 10K/J_4R66 10K/J_4

Y9

1 2

R298 10K/J_4R298 10K/J_4

V1

1 2

1

2

3

4

5

6

7

8

R363 47/F_4R363 47/F_4

R327 10K/J_4R327 10K/J_4

R62 37.4/F_4R62 37.4/F_4

R319 10K/J_4R319 10K/J_4

47X4-0402

47X4-0402

RESET JUMP

RTC_RST#

SRTC_RST#

G1

G1
*SHORT_ PAD

*SHORT_ PAD

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

LAD0 22,25
LAD1 22,25
LAD2 22,25
LAD3 22,25

LFRAME# 22,25

+3V_RUN

IRQ_SERIRQ 25

SATA_RXN0 20
SATA_RXP0 20
SATA_TXN0 20
SATA_TXP0 20

SATA_RXN1 20
SATA_RXP1 20
SATA_TXN1 20
SATA_TXP1 20

+1.05V_PCH

+3V_RUN

SATA_LED# 23

+3V_RUN

(Near ROOM DOOR)

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

IBEX PEAK-M 2/6

IBEX PEAK-M 2/6

IBEX PEAK-M 2/6

Tuesday, December 15, 2009

Tuesday, December 15, 2009

Tuesday, December 15, 2009

12

1

T52

T52
*PAD_2

*PAD_2

1

SATA HDD

SATA ODD

FH1A

FH1A

FH1A

09

1A

1A

1A

of

945

945

945

http://laptop-motherboard-schematic.blogspot.com/

5

E

R

4

3

2

1

IBEX PEAK-M (PCI,USB,NVRAM)

U18E

U18E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

D D

PCI_PIRQA#

T10T10

PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

T31T31

C C

GNT3#11

PCIRST#:
DG(V1.0) P277
Can be left unconnected.

PAR:
SC(V1.0) P36
Can be left unconnected
if not using PCI.

PME:
DG(V1.0) P277
Can be left unconnected.

A-10

CLK_LPC_DEBUG22

B B

CLK_PCI_850225

CLKOUT_PCI[0..4]:
22 ohm series resistor is recommend
(single & double load) on PDG v1.1

Reserve capacitor pads for
improving WWAN.

CLK_LPC_DEBUG

C33 *27P/50V_4

C33 *27P/50V_4

CLK_PCI_8502

C31 *27P/50V_4

C31 *27P/50V_4

Non-iAMT

A A

C108 0.1U/16V_4C108 0.1U/16V_4

PCI_PLTRST#

PCI_PLTRST#37

CLK_LPC_DEBUG

R23 22/F_4R23 22/F_4
R21 22/F_4R21 22/F_4

CLK_PCI_FB CLK_PCI_FB_C

R22 22/F_4R22 22/F_4

50

50
50

50

Add Buffers as needed for
Loading and fanout concerns.

+3V_RUN

U4

U4

2
1

MC74VHC1G08DFT2G

MC74VHC1G08DFT2G

3 5

T37T37

T5T5
T12T12

T32T32
T35T35

T21T21

T19T19

4

PCI_REQ0#
HDMI_PWR_CTRL
SB_WWAN_PCIE_RST#
USB_MCARD1_DET#

PCI_GNT0#
GNT#1

GNT#2
GNT3#

PCH_IRQH_GPIO2
SB_WLAN_PCIE_RST#
BT_DET#
PCH_IRQH_GPIO5

PCI_RST#

PCI_SERR#
PCI_PERR#

PCI_IRDY#
PCI_DEVSEL#

PCI_FRAME#
PCI_PLOCK#
PCI_STOP#

PCI_TRDY#

PME#

PCI_PLTRST#

CLK_LPC_DEBUG_C
CLK_PCI_8502_CCLK_PCI_8502

PLTRST# 4,18,19,22

A-11

5

E36
H48
E40

C40
M48
M45

F53
M40
M43

J36
K48
F40
C42
K46

M51

J52
K51
L34
F42

J40

G46

F44

M47

H36

J50

G42

H47

G34
G38

H51
B37
A44

F51
A46
B45

M53

F48
K45
F36
H53

B41
K53
A36
A48

K6

E44
E50

A42
H44
F46
C46

D49
D41

C48

M7
D5

N52
P53
P46
P51
P48

IbexPeak-M_R1P0

IbexPeak-M_R1P0

AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C/BE0#
C/BE1#
C/BE2#
C/BE3#

PIRQA#
PIRQB#
PIRQC#
PIRQD#

REQ0#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

GNT0#
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

PCIRST#
SERR#

PERR#

IRDY#
PAR
DEVSEL#
FRAME#

PLOCK#
STOP#

TRDY#
PME#
PLTRST#
CLKOUT_PCI0

CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8

NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11

NVRAM

NVRAM

NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

PCI

PCI

NV_WR#0_RE#
NV_WR#1_RE#

USB

USB

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC6# / GPIO10
OC7# / GPIO14

BT_DET#
PCH_IRQH_GPIO2
SB_WWAN_PCIE_RST#
SB_WLAN_PCIE_RST#

OC7#
OC5#
OC3#
OC4#

+3V_S5

PCH_IRQH_GPIO5
PCI_REQ0#
PCI_PIRQB#
USB_MCARD1_DET#

+3V_RUN

PCI_STOP#
PCI_PIRQA#
PCI_PIRQC#
PCI_IRDY#

+3V_RUN

http://laptop-motherboard-schematic.blogspot.com/

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

NV_DQS0
NV_DQS1

NV_ALE
NV_CLE

NV_RCOMP

NV_RB#

NV_WE#_CK0
NV_WE#_CK1

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC5# / GPIO9

RP2

RP2

6
7
8
9

10

10P8R-8.2K

10P8R-8.2K

RP3

RP3

6
7
8
9

10

10P8R-8.2K

10P8R-8.2K

RP1

RP1

6
7
8
9

10

10P8R-8.2K

10P8R-8.2K

4

AY9
BD1
AP15
BD8

AV9
BG8

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

BD3
AY6

AU2
AV7
AY8

AY5
AV11

BF5

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

B25
D25

N16
J16
F16
L16
E14
G16
F12
T15

OC0#~OC7#:
DG(V1.0)P214
Pin Default Port Mapping
OC0# Port0,Port1
OC1# Port2,Port3
OC2# Port4,Port5

NV_ALE 11
NV_CLE 11

USBP1- 21

USB PORT 1(DB)

USBP1+ 21
USBP2- 21

USB PORT 2(MB)

USBP2+ 21

USBP4- 21

USB PORT 4(MB)

USBP4+ 21

USB port 6/7 are not support in HM55 .

USBP8- 16

CAMERA

USBP8+ 16
USBP9- 21

BT

USBP9+ 21

USBP11- 22

WLAN

USBP11+ 22
USBP12- 18

CARD READER

USBP12+ 18

USB_BIAS

R260 22.6/F_4R260 22.6/F_4

OC0#
OC1#
OC2#
OC3#
OC4#
OC5#
OC6#
OC7#

+3V_S5

OC2#
OC6#
OC1#
OC0#

+3V_RUN

PCI_TRDY#
PCI_FRAME#
HDMI_PWR_CTRL
PCI_PIRQD#

+3V_RUN

PCI_SERR#
PCI_PERR#
PCI_PLOCK#
PCI_DEVSEL#

+3V_RUN

R235 8.2K/J_4R235 8.2K/J_4
R232 8.2K/J_4R232 8.2K/J_4
R229 8.2K/J_4R229 8.2K/J_4
R212 8.2K/J_4R212 8.2K/J_4

5
4
3
2
1

5
4
3
2
1

5
4
3
2
1

PCIE Clock Request

+3V_S5

+3V_RUN

PCIECLKRQ{0,3,4,5,6,7}# should have a
10K pull-up to +V3.3A.PCIECLKRQ{1,2}
should have a 10K pull-up to +3.3S

Boot BIOS Strap

PCI_GNT0# GNT#1

00

0

1

11

Place TX DC blocking caps close PCH.

LAN

PCIE_RXN222
PCIE_RXP222
PCIE_TXN222
PCIE_TXP222

PCIE_RXN619
PCIE_RXP619
PCIE_TXN619
PCIE_TXP619

C68 0.1U/10V_4C68 0.1U/10V_4
C62 0.1U/10V_4C62 0.1U/10V_4

C43 0.1U/10V_4C43 0.1U/10V_4
C48 0.1U/10V_4C48 0.1U/10V_4

MiniWLAN

PCIE port 7/8 are not support in HM55 .

LAN

CARD_CLK_REQ#_R

LOM_CLK_REQ#_R

MINI1CLK_REQ#_R
CLK_PCIE_REQ2#_R

Boot BIOS Location

LPC

PCI

Reserved (NAND)

SPI

3

CLK_PCIE_MINI2N22
CLK_PCIE_MINI2P22

MINI2CLK_REQ#22

CLK_PCIE_LOMN19
CLK_PCIE_LOMP19

CLK_LAN_REQ#19

CLK_PCIE_REQ3#
CLK_PCIE_REQ5#

CLK_PEG0_REQ#

PEG_CLKREQ#

PCI_GNT0#
GNT#1

R303 0/J_4R303 0/J_4

R279 0/J_4R279 0/J_4

CLK_PCIE_REQ3#

CARD_CLK_REQ#_R

CLK_PCIE_REQ5#

LOM_CLK_REQ#_R

PCH_SMBDATA22

PCH_SMBCLK22

MiniWLAN

R277 10K/J_4R277 10K/J_4
R97 10K/J_4R97 10K/J_4
R309 10K/J_4R309 10K/J_4
R96 10K/J_4R96 10K/J_4
R278 10K/J_4R278 10K/J_4 R469
R108 *10K/J_4R108 *10K/J_4

R310 10K/J_4R310 10K/J_4

R317 10K/J_4R317 10K/J_4
R297 10K/J_4R297 10K/J_4

R46 1K/J_4R46 1K/J_4
R45 1K/J_4R45 1K/J_4

1

0

IBEX PEAK-M (PCI-E,SMBUS,CLK)

U18B

U18B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PCIE_TXN2_C
PCIE_TXP2_C

PCIE_TXN6_C
PCIE_TXP6_C

CLK_PEG0_REQ#

CLK_PCIE_REQ2#_R

MINI1CLK_REQ#_R

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IbexPeak-M_R1P0

IbexPeak-M_R1P0

CLKOUT_PEG_A_P/N,CLKOUT_PEG_B_P/N,
CLKOUT_DMI_P/N,support GEN-1 and GEN-2

SMB_CLK_ME1

SMB_DATA_ME1

PCH_SMBDATA

+3V_RUN

+3V_RUN

PCH_SMBCLK

1

1

2N7002E

2N7002E

Q13 2N7002EQ13 2N7002E

3

Q12 2N7002EQ12 2N7002E

3

2

2

2

2

2

PCI-E*

PCI-E*

Controller

Controller

PEG

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

From CLK BUFFER

From CLK BUFFER

Clock Flex

Clock Flex

Q142N7002E Q142N7002E

3

R469

2.2K/F_4

2.2K/F_4

R468

R468

2.2K/F_4

2.2K/F_4

Q15

Q15

3

1

R322

R322

2.2K/F_4

2.2K/F_4

R287

R287

2.2K/F_4

2.2K/F_4

1

SMBus

SMBus

Link

Link

SML0ALERT# / GPIO60

SML1ALERT# / GPIO74

PEG_A_CLKRQ# / GPIO47

CLKIN_SATA_N / CKSSCD_N

CLKIN_SATA_P / CKSSCD_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

MBCLK2 25,38

A-12

MBDATA2 25,38

CGDAT_SMB 3,14,15

CGCLK_SMB 3,14,15

RSV_SMBALERT#

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

CLKIN_DMI_N
CLKIN_DMI_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

B9

PCH_SMBCLK

H14

PCH_SMBDATA

C8

RSV_ICH_CL_RST1#

J14

SMB_CLK_ME0

C6

SMB_DATA_ME0

G8

LPD_SPI_INTR#

M14

SMB_CLK_ME1

E10

SMB_DATA_ME1

G12

T13
T11
T9

PEG_CLKREQ#

H1

AD43
AD45

AN4
AN2

AT1
AT3

AW24
BA24

AP3
AP1

F18
E18

AH13
AH12

P41

CLK_PCI_FB

J42

XTAL25_IN

AH51

XTAL25_OUT

AH53

XCLK_RCOMP

AF38

T45

P43

T42

R223 33/J_4R223 33/J_4

N50

CLKOUTFLEX3:
EDS(V1.0) :support 48MHz
33MHz and 14.31818MHz.

CLKOUTFLEX[0..3]:
PDG v1.1: 22 ohm series resistor is
recommend (PCI & non PCI routing,
single & double load)

T46T46

A-04

CLKIN_PCILOOPBACK:

0214

PDG (V1.1): 22 ohm series resistor
is recommend

R211 0/J_4R211 0/J_4

R49 90.9/F_4R49 90.9/F_4

CLK_FLEX0

CLK_FLEX1

CLK_FLEX2

C288

C288
*10P_4

*10P_4

EMI USE

SMBALERT# / GPIO11

SML1CLK / GPIO58

SML1DATA / GPIO75

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKIN_BCLK_N
CLKIN_BCLK_P

CLKIN_DOT_96N
CLKIN_DOT_96P

XCLK_RCOMP

A-13

XTAL25_IN

*1M/F_4

*1M/F_4

XTAL25_OUT

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

IBEX PEAK-M 3/6

IBEX PEAK-M 3/6

IBEX PEAK-M 3/6

Tuesday, December 15, 2009

Tuesday, December 15, 2009

Tuesday, December 15, 2009

C283 *18P/50_4C283 *18P/50_4

R210

R210

2 1

C282 *18P/50_4C282 *18P/50_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

10

+3V_S5

R27610K/J_4 R27610K/J_4

FOR DDR3 SPD/CLOCK G

R2852.2K/J_4 R2852.2K/J_4

EXPRESS CARD/MINI CA

R2812.2K/J_4 R2812.2K/J_4

R8410K/J_4 R8410K/J_4
R2862.2K/J_4 R2862.2K/J_4

0 FOR INTEL LAN

R1062.2K/J_4 R1062.2K/J_4

R27410K/J_4 R27410K/J_4
R2836.8K/J_4 R2836.8K/J_4

1 FOR EC

R2846.8K/J_4 R2846.8K/J_4

SML0CLK/SML0DATA:
DG(V1.1) P255: The 82577 SMBus
signals
(SMB_DATA and SMB_CLK) cannot be
connected to any other
devices other than the PCH.
Connect the SMB_DATA and SMB_CLK
pins
to the PCH SML0DATA and SML0CLK
pins,
respectively.

CLK_PCIE_VGAN 37
CLK_PCIE_VGAP 37

CLK_PCIE_3GPLLN 4
CLK_PCIE_3GPLLP 4

CLK_BUF_PCIE_3GPLLN 3
CLK_BUF_PCIE_3GPLLP 3

CLK_BUF_BCLK_N 3
CLK_BUF_BCLK_P 3

CLK_BUF_DREFCLKN 3
CLK_BUF_DREFCLKP 3

CLK_BUF_DREFSSCLKN 3
CLK_BUF_DREFSSCLKP 3

CLK_PCH_14M 3

A-13

+1.05V_PCH

T1T1

T4T4

T2T2

CLK_48M_CR 18

0214

Y4

Y4
*25.0000 MHz

*25.0000 MHz

FH1A

FH1A

FH1A

10 45

10 45

10 45

1A

1A

1A

of

5

4

3

2

1

IBEX PEAK-M (GPIO,VSS_NCTF,RSVD)

U18F

S_GPIO

T11T11

T8T8
T18T18

T23T23

T24T24
T43T43

SIO_EXT_SMI#
SIO_EXT_SCI#
GPIO7
SWI#
GPIO12_PCH
PCH_GPIO15
SATA4GP
GPIO17
GPIO22_PCH

GPIO27

TP_PCH_GPIO28
GPIO34
GPIO35
SATA2GP
SATA3GP
GPIO38
GPIO39
GPIO45
DDR3_CORL_PCH
SV_SET_UP
TEMP_ALERT#
BIOS_WP#

SIO_EXT_SMI#25
SIO_EXT_SCI#25

D D

GPIO24 register not cleared by CF9h reset event.
GPIO27 reserve for internal VR.

C C

B B

SWI#25

R74 *10K/J_4R74 *10K/J_4

DDR3_CORL_PCH4

TEMP_ALERT#25
BIOS_WP#25

U18F

Y3

BMBUSY# / GPIO0

C38

TACH1 / GPIO1

D37

TACH2 / GPIO6

J32

TACH3 / GPIO7

F10

GPIO8

K9

LAN_PHY_PWR_CTRL / GPIO12

T7

GPIO15

AA2

SATA4GP / GPIO16

F38

TACH0 / GPIO17

Y7

SCLOCK / GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI# / GPIO34

V6

SATACLKREQ# / GPIO35

AB7

SATA2GP / GPIO36

AB13

SATA3GP / GPIO37

V3

SLOAD / GPIO38

P3

SDATAOUT0 / GPIO39

H3

PCIECLKRQ6# / GPIO45

F1

PCIECLKRQ7# / GPIO46

AB6

SDATAOUT1 / GPIO48

AA4

SATA5GP / GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IbexPeak-M_R1P0

IbexPeak-M_R1P0

MISC

MISC

CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P

GPIO

GPIO

CPU

CPU

NCTF

NCTF

RSVD

RSVD

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_PCIE7N
CLKOUT_PCIE7P

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18

TP19
NC_1
NC_2
NC_3
NC_4
NC_5

INIT3_3V#

TP24

AH45
AH46

AF48
AF47

SIO_A20GATE

U2

AM3
AM1
BG10

SIO_RCIN#

T1
BE10

PCH_THRMTRIP#_R

BD10

BA22

TP1

AW22

TP2

BB22

TP3

AY45

TP4

AY46

TP5

AV43

TP6

AV45

TP7

AF13

TP8

M18

TP9

N18
AJ24
AK41
AK42
M32
N32
M30
N30
H12
AA23
AB45
AB38
AB42
AB41
T39

T22T22

P6
C10

SIO_A20GATE 25

CLK_CPU_BCLKN 4
CLK_CPU_BCLKP 4
H_PECI 4
SIO_RCIN# 25
H_PWRGOOD 4,22

R71 56/J_4R71 56/J_4

(Both these should be close to PCH)

+1.05V_VTT

R69

R69
56/J_4

56/J_4

GPIO45
TP_PCH_GPIO28
SWI#
PCH_GPIO15
BIOS_WP#
GPIO12_PCH
DDR3_CORL_PCH

H_THERM 4

GPIO7
GPIO17
GPIO22_PCH
GPIO34
GPIO38
GPIO39
SIO_EXT_SMI#
SIO_EXT_SCI#
SIO_RCIN#
SIO_A20GATE
SATA2GP
TEMP_ALERT#
SATA3GP
SATA4GP

DMI Termination Voltage

NV_CLE

NV_ALE10
NV_CLE10

Set to Vcc when LOW

Set to Vcc/2 when HIGH

R79 *1K/J_4R79 *1K/J_4
R78 *1K/J_4R78 *1K/J_4

Danbury Technology Enabled

NV_ALE

High = Enable

Low = Disable

11

R87 10K/J_4R87 10K/J_4
R68 10K/J_4R68 10K/J_4
R94 10K/J_4R94 10K/J_4
R110 1K/J_4R110 1K/J_4
R104 10K/J_4R104 10K/J_4
R93 10K/J_4R93 10K/J_4
R100 10K/J_4R100 10K/J_4

R51 10K/J_4R51 10K/J_4
R40 10K/J_4R40 10K/J_4
R89 10K/J_4R89 10K/J_4
R92 10K/J_4R92 10K/J_4
R88 10K/J_4R88 10K/J_4
R318 10K/J_4R318 10K/J_4
R47 10K/J_4R47 10K/J_4
R42 10K/J_4R42 10K/J_4
R320 10K/J_4R320 10K/J_4
R321 10K/J_4R321 10K/J_4
R73 10K/J_4R73 10K/J_4
R302 10K/J_4R302 10K/J_4
R70 10K/J_4R70 10K/J_4
R301 10K/J_4R301 10K/J_4

+1.8V_RUN

+3V_S5

+3V_RUN

+3V_RUN

R82 10K/J_4R82 10K/J_4

A A

R222 *1K/J_4R222 *1K/J_4

A16 swap override Strap/Top-Block
Swap Override jumper

GNT3#

GPIO35

GNT3# 10

Low = A16 swap
override/Top-Block
Swap Override enabled
High = Default

5

R95 *1K/J_4R95 *1K/J_4

Integrated Clock Chip Enable

(Reserve to validate for future platforms)

RSV_WOL_EN
(GPIO8)

Enable when sampled low
Disable when sampled high

http://laptop-motherboard-schematic.blogspot.com/

SWI#

SV_SET_UP 1-X High = Strong (Default)

4

S_GPIO
SV_SET_UP

R299 10K/J_4R299 10K/J_4
R90 10K/J_4R90 10K/J_4

3

BMBUSY#:
If not used, require a weak pull-up (8.2- Kȍ to 10 kȍ) to Vcc3_3.
CRB(V1.0)P28: it has 1K PU and 100 ohm on this net for validation purpose.

BMBUSY#:(Intel feedback)
Follow CRB checklist, 1K is
for intel BIOS validation purpose.

2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

Monday, December 07, 2009

Monday, December 07, 2009

Monday, December 07, 2009

PROJECT :

IBEX PEAK-M 4/6

IBEX PEAK-M 4/6

IBEX PEAK-M 4/6

1

FH1A

FH1A

FH1A

11 45

11 45

11 45

of

1A

1A

1A

5

4

3

2

1

POWER

U18G

IBEX PEAK-M (POWER)

D D

VCCAPLLEXP = 100mA max

VCCAPLLEXP:
This pin can be left as no connect in
On-Die VR enabled mode (default).

VCCIO = 3.208A max

C C

+1.05V_PCH

T40T40

C70

C70
10U/10V_8

10U/10V_8

10

10
805

805

+1.05V_PCH

+1.05V_PCH

C85

C85
1U/6.3V_4

1U/6.3V_4

+3V_RUN

VCCCORE=1.524A max

C26

C26

10U/10V_8

10U/10V_8

1U/6.3V_4

1U/6.3V_4

10

10

+1.05V_LAN_VCCAPLL_EXP

C76

C76

C67

C67

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4

C77

C77

C75

C75
1U/6.3V_4

1U/6.3V_4

VCC3_3 = 0.357A max

C49

C49

0.1U/16V_4

0.1U/16V_4

VCCFDIPLL = 100mA max

VCCVRM = 0.035A max

+1.05V_VCCFDIPLL

T42T42

+1.8V_RUN

+1.05V_PCH

VCCIO = 3.208A max

B B

+1.05V_PCH

A A

5

U18G

AB24

VCCCORE[1]

AB26

VCCCORE[2]

AB28

VCCCORE[3]

AD26

VCCCORE[4]

AD28

VCCCORE[5]

AF26

VCCCORE[6]

AF28

VCCCORE[7]

AF30

VCCCORE[8]

AF31

VCCCORE[9]

AH26

VCCCORE[10]

AH28

VCCCORE[11]

AH30

VCCCORE[12]

AH31

VCCCORE[13]

AJ30

VCCCORE[14]

AJ31

VCCCORE[15]

AK24

VCCIO[24]

BJ24

VCCAPLLEXP

AN20

VCCIO[25]

AN22

VCCIO[26]

AN23

VCCIO[27]

AN24

VCCIO[28]

AN26

VCCIO[29]

AN28

VCCIO[30]

BJ26

VCCIO[31]

BJ28

VCCIO[32]

AT26

VCCIO[33]

AT28

VCCIO[34]

AU26

VCCIO[35]

AU28

VCCIO[36]

AV26

VCCIO[37]

AV28

VCCIO[38]

AW26

VCCIO[39]

AW28

VCCIO[40]

BA26

VCCIO[41]

BA28

VCCIO[42]

BB26

VCCIO[43]

BB28

VCCIO[44]

BC26

VCCIO[45]

BC28

VCCIO[46]

BD26

VCCIO[47]

BD28

VCCIO[48]

BE26

VCCIO[49]

BE28

VCCIO[50]

BG26

VCCIO[51]

BG28

VCCIO[52]

BH27

VCCIO[53]

AN30

VCCIO[54]

AN31

VCCIO[55]

AN35

VCC3_3[1]

AT22

VCCVRM[1]

BJ18

VCCFDIPLL

AM23

VCCIO[1]

IbexPeak-M_R1P0

IbexPeak-M_R1P0

PCH EDS(V1.0) P84
+NVRAM_VCCQ:

1.8 V supply for Dual Channel NAND interface.
This power is supplied by core
well. If unused, this pin should
be connected to Vcc3_3.

L7 10uHL7 10uH

*220U/2.5V_3528 3528

*220U/2.5V_3528 3528

L18 10uHL18 10uH

*220U/2.5V_3528 3528

*220U/2.5V_3528 3528

POWER

VCC CORE

VCC CORE

PCI E*

PCI E*

+1.1V_VCCADPLLA

+

+

C30

C30

+1.1V_VCCADPLLB

+

+

C289

C289

VCCADAC[1]
VCCADAC[2]

VSSA_DAC[1]

CRTLVDS

CRTLVDS

VSSA_DAC[2]

VCCALVDS

VSSA_LVDS

VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]

VCC3_3[2]
VCC3_3[3]
VCC3_3[4]

HVCMOS

HVCMOS

VCCVRM[2]

VCCDMI[1]

DMI

DMI

VCCDMI[2]

VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]

VCCME3_3[1]

NAND / SPI

NAND / SPI

VCCME3_3[2]
VCCME3_3[3]

FDI

FDI

VCCME3_3[4]

VCCME3_3:
EDS(V1.0)P84:supply for the Intel Management Engine.This is a separate power plane
that may or may not be powered in S3–S5 states.
This plane must be on in S0
and other times the Intel Management Engine is used.

C34

C34
1U/6.3V_4

1U/6.3V_4

C294

C294

1U/6.3V_4

1U/6.3V_4

4

A-14

+VCCA_DAC_1_2

AE50
AE52
AF53
AF51

A-15

AH38
AH39

AP43
AP45
AT46
AT45

AB34
AB35
AD35

AT24

AT16
AU16

AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15

AM8
AM9
AP11
AP9

C44

C44

0.1U/16V_4

0.1U/16V_4

VCCVRM = 0.035A max

VCCDMI = 0.061A max

C93

C93
1U/6.3V_4

1U/6.3V_4

VCCPNAND = 0.156A max

C86

C86

0.1U/16V_4

0.1U/16V_4

VCCME3_3 = 0.085A max

C46

C46

0.1U/16V_4

0.1U/16V_4

R141 0_6R141 0_6

VCCTX_LVDS = 0.066A max

VCC3_3 = 0.357A max

+3V_RUN

+1.8V_RUN

R63 0/J_4R63 0/J_4
R60 *0/J_4R60 *0/J_4

+1.8V_RUN

+3V_RUN

T36T36

+1.05V_PCH

+1.05V_VTT
+1.05V_PCH

+1.05V_PCH

VCCADAC = 100mA max

+3V_RUN

VCCACLK

DCPSUSBYP

C87

C87

0.1U/16V_4

0.1U/16V_4

C45

C275

C275

22U/6.3V_8

22U/6.3V_8

+1.8V_RUN

VCCADPLLA = 0.072A max

VCCADPLLB = 0.073A max

C45

C29

C29

22U/6.3V_8

22U/6.3V_8

C100 0.1U/16V_4C100 0.1U/16V_4

+1.1V_VCCADPLLA

+1.1V_VCCADPLLB

1U/6.3V_4

1U/6.3V_4

VCCIO = 3.208A max

C40

C40

C64

C64

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4

C95 0.1U/16V_4C95 0.1U/16V_4

C89 0.1U/16V_4C89 0.1U/16V_4

VCCSUS3_3 = 0.163A max

+3V_S5

VCC3_3 = 0.357A max

+3V_RUN

V_CPU>1mA

+1.05V_VTT

4.7U/10V_8

4.7U/10V_8

+VCC_RTC

C73

C73

0.1U/16V_4

0.1U/16V_4

C47

C47

0.1U/16V_4

0.1U/16V_4

C84

C84

C92

C92

0.1U/16V_4

0.1U/16V_4

C321

C321
1U/6.3V_4

1U/6.3V_4

VCCRTC = 2mA max

3

DCPRTC

C51

C51
1U/6.3V_4

1U/6.3V_4

DCPSST

DCPSUS

C91

C91

0.1U/16V_4

0.1U/16V_4

C322

C322

0.1U/16V_4

0.1U/16V_4

AP51
AP53

AF23
AF24

Y20

AD38
AD39
AD41
AF43
AF41
AF42

V39
V41
V42
Y39
Y41
Y42

V9

AU24

BB51
BB53

BD51
BD53

AH23

AJ35

AH35
AF34
AH34
AF32

V12

Y22

P18
U19
U20
U22

V15

V16

Y16

AT18

AU18

A12

C323

C323

0.1U/16V_4

0.1U/16V_4

U18J

U18J

VCCACLK[1]
VCCACLK[2]

VCCLAN[1]
VCCLAN[2]

DCPSUSBYP

VCCME[1]
VCCME[2]
VCCME[3]
VCCME[4]
VCCME[5]
VCCME[6]
VCCME[7]
VCCME[8]
VCCME[9]
VCCME[10]
VCCME[11]
VCCME[12]

DCPRTC

VCCVRM[3]

VCCADPLLA[1]
VCCADPLLA[2]

VCCADPLLB[1]
VCCADPLLB[2]

VCCIO[21]
VCCIO[22]
VCCIO[23]

VCCIO[2]
VCCIO[3]
VCCIO[4]
DCPSST

DCPSUS

VCCSUS3_3[29]
VCCSUS3_3[30]
VCCSUS3_3[31]
VCCSUS3_3[32]

VCC3_3[5]
VCC3_3[6]
VCC3_3[7]

V_CPU_IO[1]

V_CPU_IO[2]

VCCRTC

IbexPeak-M_R1P0

IbexPeak-M_R1P0

POWER

POWER

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]

VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]

USB

USB

VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]

VCCSUS3_3[28]

Clock and Miscellaneous

Clock and Miscellaneous

PCI/GPIO/LPC

PCI/GPIO/LPC

VCCSATAPLL[1]
VCCSATAPLL[2]

SATA

SATA

PCI/GPIO/LPC

PCI/GPIO/LPC

CPU

CPU

RTC

RTC

HDA

HDA

VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]

VCCIO[56]

V5REF_SUS

V5REF

VCC3_3[8]

VCC3_3[9]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]

VCCIO[9]

VCCVRM[4]

VCCIO[10]

VCCIO[11]

VCCIO[12]

VCCIO[13]

VCCIO[14]

VCCIO[15]

VCCIO[16]

VCCIO[17]

VCCIO[18]

VCCIO[19]

VCCIO[20]

VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]

VCCSUSHDA

2

V24
V26
Y24
Y26

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

U23
V23
F24

K49

J38
L38
M36
N36
P36
U35

AD13

AK3
AK1

AH22

AT20

AH19
AD20
AF22
AD19

AF20
AF19
AH20

AB19
AB20
AB22
AD22

AA34
Y34
Y35
AA35

L30

C71

C71
1U/6.3V_4

1U/6.3V_4

C74

C74

0.1U/16V_4

0.1U/16V_4

+1.05V_PCH

+V5REF_SUS

C83

C83
1U/6.3V_4

1U/6.3V_4

+V5REF

C32

C32
1U/6.3V_4

1U/6.3V_4

C60

C60

0.1U/16V_4

0.1U/16V_4

C94

C94

0.1U/16V_4

0.1U/16V_4

+1.05V_VCCSATAPLL

VCCVRM = 0.035A max

+1.8V_RUN

+1.05V_PCH

R55 0/J_4R55 0/J_4

C61

C61
1U/6.3V_4

1U/6.3V_4

VCCIO = 3.208A max

+1.05V_PCH

VCCSUS3_3 = 0.163A max

+3V_S5

C72

C72

0.1U/16V_4

0.1U/16V_4

VCCIO = 3.208A max

R56 100/J_4R56 100/J_4

1 2

D3 SDM10K45-7-FD3 SDM10K45-7-F

R18 100/J_4R18 100/J_4
D2 SDM10K45-7-FD2 SDM10K45-7-F

21

1 2

21

+3V_RUN

+5V_S5

V5REF_SUS>1mA

+3V_S5

V5REF>1mA

+5V_RUN
+3V_RUN

VCC3_3 = 0.357A max

T44T44

VCCIO = 3.208A max

+1.05V_PCH

C69

C69
1U/6.3V_4

1U/6.3V_4

VCCME = 1.998A max

VCCSUSHDA = 6mA max

+3V_S5

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Tuesday, December 15, 2009

Tuesday, December 15, 2009

Tuesday, December 15, 2009

Date: Sheet

Date: Sheet of

Date: Sheet of

PROJECT :

IBEX PEAK-M 5/6

IBEX PEAK-M 5/6

IBEX PEAK-M 5/6

1

12

FH1A

FH1A

FH1A

12 45

12 45

12 45

1A

1A

1A

of

http://laptop-motherboard-schematic.blogspot.com/

5

4

3

2

1

13

U18I

U18I

AY7

VSS[159]

IBEX PEAK-M (GND)

D D

U18H

U18H

AB16

VSS[0]

AA19

VSS[1]

AA20

VSS[2]

AA22

VSS[3]

AM19

VSS[4]

AA24

VSS[5]

AA26

VSS[6]

AA28

VSS[7]

AA30

VSS[8]

AA31

VSS[9]

AA32

VSS[10]

AB11

VSS[11]

AB15

VSS[12]

AB23

VSS[13]

AB30

VSS[14]

AB31

VSS[15]

AB32

VSS[16]

AB39

VSS[17]

AB43

VSS[18]

AB47

AC2
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49

AD7

AF12

AH49

AU4

AF35
AP13

AN34

AF45
AF46
AF49

AG2
AG52
AH11
AH15
AH16
AH24
AH32

AV18
AH43
AH47

AH7

AJ19

AJ20

AJ22

AJ23

AJ26

AJ28

AJ32

AJ34

AK12
AM41
AN19

AK26

AK22

AK23

AK28

AB5
AB8

AE2
AE4

Y13

AF5
AF8

AJ2

AT5

AJ4

VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

IbexPeak-M_R1P0

IbexPeak-M_R1P0

C C

B B

A A

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47

B11
B15
B19
B23
B31
B35
B39
B43
B47

BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49

BB5
BC10
BC14
BC18

BC2
BC22
BC32
BC36
BC40
BC44
BC52

BH9
BD48
BD49

BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50

BE6

BE8

BF3
BF49
BF51
BG18
BG24

BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47

BH7

C12

C50

D51

E12

E16

E20

E24

E30

E34

E38

E42

E46

E48

G10

G14

G18

G22

G32

G36

G40

G44

G52
AF39

H16

H20

H30

H34

H38

H42

VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]

B7

VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]

E6

VSS[238]

E8

VSS[239]

F49

VSS[240]

F5

VSS[241]
VSS[242]
VSS[243]
VSS[244]

G2

VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]

H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14

IbexPeak-M_R1P0

IbexPeak-M_R1P0

Size Document Number Rev

Size Document Number Rev

5

4

3

2

http://laptop-motherboard-schematic.blogspot.com/

Size Document Number Rev

Date: Sheet

Friday, December 04, 2009

Friday, December 04, 2009

Friday, December 04, 2009

Date: Sheet of

Date: Sheet of

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

IBEX PEAK-M 6/6

IBEX PEAK-M 6/6

IBEX PEAK-M 6/6

1

FH1A

FH1A

FH1A

13 45

13 45

13 45

1A

1A

1A

of

5

4

3

2

1

+3V_RUN

+1.5V_SUS

PM_EXTTS#0

100
105
106
111
112
117
118
123
124

199

122
125

198

126

75
76
81
82
87
88
93
94
99

77

30

1

2
3
8

9
13
14
19
20
25
26
31
32
37
38
43

JDIM1B

JDIM1B

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

VDDSPD
NC1

NC2
NCTEST

EVENT#
RESET#

VREF_DQ
VREF_CA

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

2-2013311-1

2-2013311-1

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

(204P)

(204P)

VTT1
VTT2

G1
G2

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

203
204

G1
G2

Intel is requesting that customers implement
all methods (M1 and M2 and M3
described below) to generate and control
Reference voltage for Data/Strobe inputs
(VREFDQ) on Clarksfield based platforms.
for fine tuning of the VREFDQ levels to
optimize the voltage and timing margins.

M1:Fixed voltage resistor divider or
DDR Voltage Regulator drives the Vref
M2:A set of Digital potentiometers
and op amps are added on the motherboard (one pair
for each channel). This circuit is controlled by
SMBUS (SMB_CLK & SMB_DATA) on PCH.
M3:Intel investigating future processor
VREF_DQ generation to replace M1 and M2. This
would require routing processor signal balls
J17 and H17 to SO-DIMM connectors
directly.

+0.75V_DDR_VTT

14

JDIM1A

107

119

109
108

114
121
101
103
102
104

115
110
113
197
201
202
200

116
120

136
153
170
187

137
154
171
188

135
152
169
186

98
97
96
95
92
91
90
86
89
85

84
83

80
78

79

73
74

11
28
46
63

12
29
47
64

10
27
45
62

JDIM1A

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA

ODT0
ODT1

DM0
DM1
DM2
DM3
DM4
DM5
DM6

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

DM7
DQS0

DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

2-2013311-1

2-2013311-1

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45

(204P)

(204P)

DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

M_A_A[15:0]5

+3V_RUN

D D

R134

R134
*10K

*10K

R137

R137
10K

10K

C C

C144

C144

*33P/50V_4

*33P/50V_4

B B

R135

R135
*10K

*10K

DIMM0_SA1

DIMM0_SA0

R138

R138
10K

10K

CGCLK_SMB
CGDAT_SMB

C143

C143
*33P/50V_4

*33P/50V_4

SMbus address A0

M_A_BS05
M_A_BS15
M_A_BS25
M_A_CS0#5
M_A_CS1#5
M_A_CLKP05
M_A_CLKN05
M_A_CLKP15
M_A_CLKN15
M_A_CKE05
M_A_CKE15
M_A_CAS#5
M_A_RAS#5
M_A_WE#5

CGCLK_SMB3,10,15
CGDAT_SMB3,10,15

M_A_ODT05
M_A_ODT15

M_A_DM[7:0]5

M_A_DQSP[7:0]5

M_A_DQSN[7:0]5

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

DIMM0_SA0
DIMM0_SA1
CGCLK_SMB
CGDAT_SMB

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7

M_A_DQ[63:0] 5

PM_EXTTS#04

DDR3_DRAMRST#4,15

+SMDDR_VREF_DIMM0

+1.5V_SUS +DDR_VTTREF

R128

R128

R131

R131

1K/J_4

1K/J_4

*0/J_4

*0/J_4

12

R130

R130
1K/J_4

1K/J_4

C156

C156

0.1U/16V_4

0.1U/16V_4

16

16

+SMDDR_VREF_DQ0

+SMDDR_VREF_DIMM0

+1.5V_SUS

C141

C141
10U/6.3V_6

+3V_RUN

10U/6.3V_6

C147

C147

2.2U/6.3V_6

2.2U/6.3V_6

C163

C163
10U/6.3V_6

10U/6.3V_6

A A

Place these Caps near So-Dimm1.

C161

C161

C137

C137
10U/6.3V_6

10U/6.3V_6

C153

C153
10U/6.3V_6

10U/6.3V_6

C151

C151

0.1U/16V_4

0.1U/16V_4

5

C162

C162
10U/6.3V_6

10U/6.3V_6

+0.75V_DDR_VTT

10U/6.3V_6

10U/6.3V_6

C160

C160

0.1U/10V_4

0.1U/10V_4

C136

C136
1U/6.3V_4

1U/6.3V_4

C138

C138

0.1U/10V_4

0.1U/10V_4

C133

C133
1U/6.3V_4

1U/6.3V_4

C140

C140

0.1U/10V_4

0.1U/10V_4

C159

C159

0.1U/10V_4

0.1U/10V_4

C139

C139

0.1U/1V_4

0.1U/1V_4

C134

C134
1U/6.3V_4

1U/6.3V_4

+SMDDR_VREF_DIMM0

C164

C164

2.2U/6.3V_6

+

+

C202

C202
*330U/2.5V_7343

*330U/2.5V_7343

7343

7343

2.5

2.5

C132

C132

C135

C135

10U/10V_8

10U/10V_8

1U/6.3V_4

1U/6.3V_4

10

10
805

805

http://laptop-motherboard-schematic.blogspot.com/

4

C155

C155

0.1U/16V_4

0.1U/16V_4

2.2U/6.3V_6

+SMDDR_VREF_DQ0

C154

C154

0.1U/16V_4

0.1U/16V_4

C158

C158

2.2U/6.3V_6

2.2U/6.3V_6

3

+1.5V_SUS +DDR_VTTREF

R129

R129
1K/J_4

1K/J_4

12

R132

R132
1K/J_4

1K/J_4

R136

R136
*0/J_6

*0/J_6

R133 0_6R133 0_6

C157

C157

0.1U/16V_4

0.1U/16V_4

16

16

M1 VREF

+SMDDR_VREF_DQ0

2

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Tuesday, December 15, 2009

Tuesday, December 15, 2009

Tuesday, December 15, 2009

Date: Sheet

Date: Sheet of

Date: Sheet of

DDR3 DIMM-1

DDR3 DIMM-1

DDR3 DIMM-1

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

FH1A

FH1A

FH1A

of

14 45

14 45

14 45

1A

1A

1A