Unit used: 10cm ( 4" diameter), Cone type
Maximum music power handling capacity: 60 Watts
Nominal impedance: 6 ohms
General
Power requirements: AC 120V, 60Hz (1000,US,CA)
AC 230V, 50Hz (XE,UK)
AC 230-240V,50Hz (AU)
AC 220V, 60Hz (KR)
Power consumption: 100 Watts
1.4W (standby mode)
Dimensions (W x H x D):Approx. 200(W) x 400(H) x 320(D) mm
Approx. 7.9" x 15.9" x 12.6"
Weight: :Approx.8.7 kg (19.4 lbs)
Main Speaker with Subwoofer (magnetic shield)
Main Speaker
Unit used: 10cm (4" diameter), Cone type
Maximum music power handling capacity: 60 Watts(peak)
Nominal impedance: 6 ohms
Subwoofer
Unit used: 13cm ( 5.1" diameter), Cone type
Maximum music power handling capacity: 60 Watts (peak)
Nominal impedance: 6 ohms
General
Dimensions (W x H x D): Approx 200(W) x 400(H) x 320(D) mm
Approx. 7.9" x 15.9" x 12.6"
Weight: Approx. 5.8 kg (13.2 lbs)
IMPORTANT INFORMATION
Because its products are subject to continuous improvement,
SANYO reserves the right to modify product designs and
specifications without notice and without incurring any obligation.
Specifications subject to change without notice.
DVD Video Player Section
Type: DVD/CD player
Playback standard : PAL or NTSC
Laser: Semiconductor laser, wavelength 650 nm
Laser output (Continuous wave max.)
1mW (DVD)
0.5mW (CD)
Frequency range (digital audio):
4 Hz to 44 kHz (DVD fs: 96 kHz)
Signal to noise ratio: More than 105 dB
Harmonic distortion (digital audio): 0.003 %
Wow and flutter: Below measurable level
- 1 -
LASER BEAM SAFETY PRECAUTION
SUB
WOOFER
VIDEO IN
AUDIO IN
VIDEO OUT SELECT
RGB
S-VIDEO
S-VIDEO OUT
(DVD ONLY)
MONITOR
VIDEO OUT
AUDIO OUT
R
L
R
VIDEO
AUX/TV
LRL
R
L
OPTICAL
DIGITAL OUT
TV SYSTEM
AV EURO
CONNECTOR
(RGB OUT)
PAL
NTSC
SPEAKERS(6ΩMIN.)
XE,UK,SS,AU
XE,SS
CAUTION – INVISIBLE LASER RADIATION WHEN OPEN AND
INTERLOCKS DEFEATED. AVOID EXPOSURE TO BEAM.
ADVARSEL – USYNLIG LASER STRÅLING VED ÅBNING, NÅR
SIKKERHEDSAFBRYDERE ER UDE AF FUNKTION, UNDGÅ UDS ÆTTELSE
FOR STRÅLING.
VARNING – OSYNLIG LASER STRÅLNING NÄR DENNA DEL ÄR ÖPPNAD
OCH SPÄRR ÄR URKOPPLAD. STRÅLEN ÄR FARLIG.
VORSICHT – UNSICHTBARE LASERSTRAHLUNG TRITT AUS, WENN
DECKEL GEÖFFNET UND WENN SICHERHEITSVERRIEGELUNG
ÜBERBRÜCKT IST. NICHT, DEM STRAHL AUSSETZEN.
VARO – AVATTAESSA JA SUOJALUKITUS OHITETTAESSA OLET ALTTIINA
NÄKYMÄTTÖMÄLLE LASERSÄTEILYLLE. ÄLÄ KATSO SÄTEESEEN.
DVD MECHANISM REPLACEMENT
1. Cautionary instructions in handling the assy
(Safety instructions)
Optical pickup
The laser beam used in the pickup is classified as "class 2". Exposing
your eyes or skin to the beam is harmful. Take care not to do so.
(Caution against static electricity and leakage voltage)
Ground securely the work tables, tools, fixtures, soldering irons
(including those made of ceramic) and measuring instruments used
in the production lines and inspection departments that handle
loaders. The workers shall also be grounded.
(Cautionary instructions in handling)
Do not touch the object lens when handling a loader, or the lens
will be stained, resulting in inadequate playability.
There is no power supply protection circuit provided for this product
or adjustment/inspection device. Short-circuiting may lead to fire or
damage.
Take care so as to protect from exposure to water, the entry of
metallic pieces or dew condensation.
In particular, a strong magnet adjacent to the pickup will not only
get inoperative but can damage the pickup if a small metallic piece,
such as a screw or swarm, enters.
The loader edge can cause injury if inadvertently handled.
Do not touch a rotating disk, or injury may result.
This product is a precision device. Handle carefully.
A shock or dropping will cause misalignment or destruction. If it
should occur, refer to clause 2.
This product is so designed as to endure an initial shock equivalent
to a drop from a height of approx. 90 cm under the packed condition.
After the initial shock, the resistivity will still remain at a level of 50
to 60 G, but the mechanical robustness
The entry and deposition of dirt into or on the pickup lens or moving
section will cause malfunction or degradation.
SPEAKERS(6ΩMIN.)
TV SYSTEM
L
R
SUB
WOOFER
VIDEO IN
LRL
AUDIO IN
R
VOLTAGE SELECTOR
PAL
NTSC
OPTICAL
DIGITAL OUT
C
R
C
B
VIDEO
AUX/TV
230V
115V
COMPONENT
VIDEO OUT
(DVD ONLY)
XE,UKSS,AU
(Connectors)
Do not connect or disconnect while power is on.
Connecting or disconnecting signal wires or the main power cord
when the power is on may destruct the unit or fixture.
When connecting, push all the way in securely.
An insufficient insertion may cause a bad contact, leading to an
erroneous operation.
Do not connect or disconnect roughly by an excessively strong force,
or a broken wire or bad contact may result.
Semiconductors are connected. Do not touch connector terminals
directly.
If the worker is grounded, there is nothing to worry about static
electricity, but the rust on the connector terminal surface caused
by the touch may result in bad contact.
(Power source)
The power source need be good in quality (free from instantaneous
interruptions or noises).
A low quality power source may well cause malfunction.
(Storage)
Do not place or store in a dusty place or a place where dew
condensation is possible.
The entry and deposition of dirt or dust into or on the pickup lens or
moving section will cause malfunction or degradation.
Also, dew condensation causes rust ; the rust penetrate into the
precision part of a pickup, causing malfunction, or degrading the
optical quality of the internal lens and reflector, which also leads to
malfunction.
- 2 -
MONITOR
VIDEO OUT
AUDIO OUT
RLY
VIDEO OUT SELECT
COMPONENT
S-VIDEO
S-VIDEO OUT
(DVD ONLY)
REMOVAL & INSTALLATION
Remove the power supply cord from AC outlet.
All wiring should be returned to the original position after work is completed.
Check and maintenance can do, if operate the following order.
1. Removal Rear Panel2. Removal Power supply P.W.B.
3
CN439
2
4
CN438
2
CN472
CN471
3
CN475 CN477
CN476
CN470
CN474
UK,XE only
3. Removal Front grill Block
3
CN439
1
1
2
1
3
1
4
1000,XE,UK,US,CA,AU
5
2
4
SS,KR
- 3 -
MECHANISM REPLACEMENT
FLOIL OIL
G-2000B
FLOIL OIL
G-2000B
1. TRAY and BASE MechanismPart
FLOIL OIL
G-474B
3. TRAY Part
MOLYKOTE
EM-50L
GREASE
CDF-409
GREASE
CDF-409
2. BASE Mechanism Mounting Part
SILICON GREASE
KS-64
MOLYKOTE
EM-50L
MOLYKOTE
EM-50L
4. BASE Mechanism Part
MOLYKOTE
EM-50L
MOLYKOTE
EM-50L
Do not remove the pick-up from base mechanism because of
adjustment difficulty.
- 4 -
MECHANISM OPERATION
1.How to setting the TRAY
1. Move the SLIDE left side.
2. Match the Hole of GEAR
LARGE TOOTH
5 and Hole of CHASSIS 4.
GREASE
EM-50L
RIB
6. Match the hole of GEAR 7 and hole of chassis while turning
GEAR 6.
7. Match the mark of LOADING GEAR
8 and gear of TRAY
where see horn hole 9 of tray.
8. Push a TRAY with the state that turned the entire surface of a
TRAY into approximately 5 degrees the lower part slowly.
RIB
CHASSIS HOLE
4
GEAR HOLE
5
GREASE
EM-50L
GREASE
EM-50L
3. Match the mark of GEAR 2 and mark of GEAR 3, and then
install the BOSS.
4. Turn the GEAR
1 counterclockwise, and then SLIDE move
right side.
5. The GEAR
1 move from side to side.
TRAY
7
6
HOLE
8
MARKER
MARKER
LOARDING
GEAR
9
MOTOR
CHASSIS
FRONT SIDE
3
2
2
MARKER
1
3
MARKER
- 5 -
DVD P.W.BOARD OPERATION
1. General operation diagram ( This is a basic general operation diagram)
The circuit mounted on the Loader part (Frontend Board) is configured as shown, which is divided into following bl;ocks according to
main IC's.
BHTP106IC10042Bottom Hold Signal(Analog)V TP620------------
PHTP107IC10044Peak Hold Signal(Analog) UTP611-----------DEFTP230IC10046High : When passing defectionH+TP619-----------LD1TP122Q1004EDVD Laser Power Supply(Analog)U+TP618-----------LD2TP124Q1005ECD Laser Power Supply(analog)U-TP617------------
EACH PRECAUTION IN THIS MANUAL SHOULD BE FOLLOWED DURING SERVICING. COMPONENTS IDENTIFIED WITH THE IEC
!!
!
SYMBOL
SPECIAL SIGNIFICANCE. WHEN REPLACING A COMPONENT IDENTIFIED BY
OR PARTS WITH THE SAME RATINGS OF RESISTANCE, WATTAGE OR VOLTAGE THAT ARE DESIGNATED IN THE PARTS LIST
IN THIS MANUAL. LEAKAGE-CURRENT OR RESISTANCE MEASUREMENTS MUST BE MADE TO DETERMINE THAT EXPOSED
PARTS ARE ACCEPTABLY INSULATED FROM THE SUPPLY CIRCUIT BEFORE RETURNING THE PRODUCT TO THE CUSTOMER.
CAUTION:Regular type resistors and capacitors are not listed. To know those values, refer to the schematic diagram.
IN THE PARTS LIST AND THE SCHEMATIC DIAGRAM DESIGNATED COMPONENTS IN WHICH SAFETY CAN BE OF
!!
!
, USE ONLY THE REPLACEMENT PARTS DESIGNATED,
Regular type resistors are less than 1/4 W Carbon type and Chip type resistors.
Regular type capacitors are less than 50 V and less than 1000 µF type of Ceramic type, Electrical type and Chip type.
409 416 6406 IC BA033FP
IC105409 408 9804 IC 74VHC74MTC,D_FRIP_FROP
or409 415 7909 IC TC74VHC74FT,D_FRIP_FROP
IC110409 482 0209 IC K4S161622D-TC80,SDRAM2MB
or410 349 2502 IC EM636165TS-8,SDRAM2MB
or410 349 2601 IC KM416S1120DT-G8,SDRAM2MB
or409 482 0209 IC K4S161622D-TC80,SDRAM2MB
IC111409 482 0209 IC K4S161622D-TC80,SDRAM2MB
or410 349 2502 IC EM636165TS-8,SDRAM2MB
or410 349 2601 IC KM416S1120DT-G8,SDRAM2MB
or409 482 0209 IC K4S161622D-TC80,SDRAM2MB
IC112409 431 9000 IC 74VHC244MTC
or410 372 5709 IC MC74VHC244DT-R2
or410 316 1804 IC TC74VHC244FT-EL
IC113410 377 4707 IC 74VHCT244AMTC-X
or410 372 5808 IC MC74VHCT244ADT-R2
or410 314 3404 IC TC74VHCT244AFT-EL
IC116409 482 0100 IC L64030,MICON
IC117409 482 0209 IC K4S161622D-TC80,SDRAM2MB
or410 349 2502 IC EM636165TS-8,SDRAM2MB
or410 349 2601 IC KM416S1120DT-G8,SDRAM2MB
or409 482 0209 IC K4S161622D-TC80,SDRAM2MB
IC118410 368 2002 IC LE28DW8102T-90-MPB,FLASH
IC127409 460 3307 IC L64021D,MPEG
IC130409 482 0001 IC BMR-0302E,RESET
IC131409 438 7504 IC PCM1723E,DAC
IC132409 039 8603 IC NJM4560M
IC133409 484 7602 IC NC7SZ08P5
or409 368 5809 IC TC7SH08FU
IC135409 484 7602 IC NC7SZ08P5
or409 368 5809 IC TC7SH08FU
DM20614 310 6869 ASSY,PWB MECHA-SW,SW PWB
S011645 032 2044 SWITCH,LEVER,CHUCK END SW
S012645 032 2051 SWITCH,LEVER,TRAY OPEN END
W001614 310 6562 ASSY,WIRE,SW PWB CONNECT
W002614 301 1798 ASSY,WIRE,LOADING M
- 58 -
IC BLOCK DIAGRAM & DESCRIPTION
- DVD LOADER section -
IC100 LA9702WL-MPB (Front End Processor forDVD Player)
No Na meDescription
1 RFNRF signal - input
2 RFPRF signal + input
3 PD1Pickup signal input
4 PD2Pickup signal input
5 PD3Pickup signal input
6 PD4Pickup signal input
7 PD5Pickup signal input
8 PD6Pickup signal input
9 PD7Pickup signal input
10 PD8Pickup signal input
11 PD9Pickup signal input
12 VCCPower (Servo signal)
13 LDD1APC1 output
14 LDS1APC1 monitor voltage input
15 LDD2APC2 output
16 LDS2APC2 monitor voltage input
17 GN DGND. (Servo signal)
18 SGCServo gain control terminal (RREC, FE, TE)
19 FEBLFocus balance adjusting terminal
20 TEBLTracking balance adjusting terminal
21 VGARF gain adjusting terminal
22 BSTEqualizer boost adjusting terminal
23 FOSTFocus offset adjusting terminal
24 TOSTTracking offset adjusting terminal
25 BCATH BCA threshold adjusting terminal
26 REFIStandard voltage setting terminal
27 SREFstandard voltage output for servo signal
28 RRECReflection output
29 FEFocus error output
30 TETracking error output
31 THCCondencer connection terminal to setting TE hold time constant
32 W OWobble output terminal
33 ISETResistance connection terminal to setting BPF center frequency
34 WOIPush-pull signal input
35 W O OPush-pull signal output
36 TEOTE gain setting terminal for 3 beam
37 TENTE gain setting terminal for 3 beam
38 CPResistance to setting charge pump gain, Condenser connection terminal
39 BHIResistance connection terminal to setting bottom hold detect parameters
40 RFONRF - output
Note 1: When the external data bus width = 16 bits, this serves as the data bus; when the external data bus width = 8 bit, this serves as the I/O port.
2: According to the register setting, this can serve as the I/O port.
Power supply inputApply 5V ± 0.5V to Vcc, and 0V to Vss.
MD0MD0Input Connect this pin to Vcc.
MD1MD1Input Connect this pin to Vss.
RESETReset inputInput The microcomputer is reset when Vss-level voltage is applied to this pin.
X
IN
OUT
X
BYTE
CDSEL
CC
AV
AV
SS
REF
V
0/A16
P0
P0
7/A23
P1
0/D0
P1
7/D7
0/D8
P2
P2
7/D15
Clock inputInput
Clock outputOutput
External data bus width
select input
Clock division select
input
,
Analog power supply
input
Reference voltage inputInput This is the reference voltage input pin for the A-D converter and the D-A converter.
-
Address (high-order)
output
Data (low-order) I/OI/O
-
I/O port p2,
Data (high-order) I/O
P30 - P33I/O port P3I/O
P4
0
- P47I/O port P4I/O
P5
0
- P57I/O port P5I/O
0
- P67I/O port P6I/O
P6
P7
0
- P77I/O port P7I/O
P8
0
- P87I/O port P8I/O
P10
0/A0
-
Address (low-order)
P10
P11
P11
output
7A7
0/A8
-
Address (middle-order)
output
7/A15
NMINon-mask able interruptInput This pin is for a non-mask able interrupt.
IN
Note : The X
-input-clock division select bit is used to determine whether the input clock to pin XIN is to be divided or not.
OutputDescription
_
These are input and output pins of the internal clock generating circuit. Connect a ceramic or
quartz-crystal resonator between the X
clock source should be connected to the X
IN
and X
IN
pin, and the X
OUT
pins. When an external clock is used., the
This pin determines whether the external data bus has an 8-bit width or 16-bit width for the
memory expansion mode or microprocessor mode. The width is 16 bits when V
Input
voltage is input, and 8 bits when V
CC
-level voltage is applied. When BYTE=VSS level, by the
resister setting, the external data bus for each of areas CS
IN
Input
_
Output
This pin determines the X
level at pin X
IN
.
Power supply input pins for the A-D converter and the D-A converter. Connect AV
and AV
SS
to VSS externally.
Address (A
16-A23
) is output. These pins also function as I/O port pins according to the resister
setting.
The low-order 8 bits of data (D
width, address (LA
0
-LA7) output and data (D0-D7) input/output can be performed with the time-
-input-clock division select bit's (note) state at reset and the input
0-D7
) are input /output. When the external data bus has an 8-bit
sharing method, according to the resister setting.
■ When 8-bit external data bus is used.
Port P2 is an 8-bit I/O port. This port has an I/O direction resister, and each pin can be
programmed for input or output. These pins enter the input mode at reset.
I/O
■ When 16-bit external data bus is used.
The high-order 8 bits of data (D
8
- D15) are input or output.
P30 functions as an input pin of RDY; and P31, P32. P33 function as the output pins of RD,
BLW, BHW, respectively. P30 also functions as an I/O port pin according to the resister
setting. When the external data has a width of 8 bits, be BHW pin functions
0
- P44 function as output or input pins of ALE, 1, HLDA, HOLD, CS0, and P45 - P47 as I/
P4
port pins, respectively. According to the resister setting, P40 - P43 also function as I/O port
5
pins, and P4
- P47 as output pins of CS1 - CS3.
Port P5 is an 8-bit I/O port. This port has an I/O direction resister, and each pin can be
programmed for input or output. These pins enter the input mode at reset. These pins also
function as I/O pins for timers A0 - A3, output pins for the real-time output pins for the realtime output, and input pins for the key-input interrupt.
Port P6 is an 8-bit I/O port. This port has an I/O direction resister, and each pin can be
programmed for input or output. These pins enter the input mode at reset. These pins also
function as I/O pins for timers A4, input pins for external interrupt inputs INT
pins for timers B0 - B2.
Port P7 is an 8-bit I/O port. This port has an I/O direction resister, and each pin can be
programmed for input or output. These pins enter the input mode at reset. These pins also
function as input pins for the A-D converter, output pins for the D-A converter, and input pins
for INT
2
, INT3, and INT4.
Port P8 is an 8-bit I/O port. This port has an I/O direction resister, and each pin can be
programmed for input or output. These pins enter the input mode at reset.
These pins also function as I/O pins for UART0, UART1, and input pins for INT
Output Address (A
Output
Address (A8-A15) is output. These pins also function as I/O port pins according to the resister
setting.
0-A7
) is output.
OUT
pin s
1
to CS3 can have a width of 8 bits.
SS
-level
CC
to VCC,
0
- INT2, and input
3
and INT4.
- 63 -
IC BLOCK DAIGRAM & DESCRIPTION
IC502 M51953BFP (Reset)
OUTER
POWER
NC
SUPPLY
8765
1234
NCNCNCGND
IC504 TC7SHU04FU (Inverter)
M51953BFP
1
NC
2
IN A
OUT
PUT
DELAY
CAPACITY
POWER
SUPPLY
7
R1
R2
1.25V
4
GNDOUTER DELAY
V
CC
5
5
CAPACITY
(CD)
218 TERMINAL:NC3
6
OUTPUT
GND
3
OUT Y
4
IC550 LE28C1001ATS-S-90-MPB (Flash Memory)
A16~A0
10~20
CE
OE
WE
30
32
Address
Buffers
&
Latches
Control Logic
7
X-
Decoder
1,048,576 bit
Super Flash
EEPROM
Cell Array
Y-Decoder
I/O Buffers &
Data Latches
29~25,23~21
DQ7~DQ0
Pin Name
A16-A0
DQ7-DQ0
CE
OE
WE
Vcc
Vss
NC
Address Inputs
Data Input/Output
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
A11
A9
A8
A13
A14
NC
WE
Vcc
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 Pin TSOP Normal
(Top View)
32
OE
31
A10
30
CE
29
DQ7
28
DQ6
27
DQ5
26
DQ4
25
DQ3
24
Vss
23
DQ2
22
DQ1
21
DQ0
20
A0
19
A1
18
A2
17
A3
- 64 -
IC BLOCK DAIGRAM & DESCRIPTION
IC601 BA5937AFP (Power Driver)
28 2736252423 2221 201918171615
x2Dx2
D
THERMAL
SHUT
DOWN
DD
x2x2
1234567891011121314
LEVEL
SHIFT
LEVEL
SHIFT
+
-
+
-
+
MUTE
CH1,4
VCC(CH3)VCC(CH1,4)
-
+
LEVEL
SHIFT
VCC(CH2)
IC602 BA6849FP (CD-ROM Motor Driver)
DRIVER
A3
2
GAIN
A2
A1
4
7
CONTROL
TL
x2
Dx2D
x2x2
TSD
SENSE AMP
+
FWD REV
VOLTAGE
CTRL
DD
CURRENT
-
LOGIC
V
PIN NO. NAMEDESCRIPTION
1
OUT-1
2
OUT-2
3
IN 1-1
4
IN 1-2
5
NC
6
NC
7
MUTE
8
GND
9
NC
10
VCC2
11
NC
12
OUT2-2
13
OUT2-1
14
GND
28
RNF
VM1
27
26
VM2
CC
25
VCC
24
FG
DRIVER CH1 (-)
DRIVER CH1 (+)
DRIVER CH1
DRIVER CH1 GAIN
NOT USED
NOT USED
CH1,4 MUTE CONTROL
GND
NOT USED
VCC(CH2)
NOT USED
DRIVER CH2 LOARDING (+)
DRIVER CH2 LOARDING (-)
SUB STRAIGHT GND
Pin NameI/O Function Description Pin NameI/O Function Description
VSS1,2Power pin (-) * 1S7/T7 to * Output for VFD display controller segment/timing with internal
VDD1,2,3,4Power pin (+) * 1S15/T15 pull-down resisitor in common.
O
VPPower pin (+) for the VFD output pull-down resist* Internal pull-down resistor output
* 8-bit input/output portS16 to S31* Output for VFD display conroller segment
Input/output port* Other function
I/OP00 - P07
* Input for port 0 interrupt S16 ~ S23 : High voltage input port PC0 ~ PC7
I/O
* Inout for HOLD release S24 ~ S31 : High voltage input port PD0 ~ PD7
* 15V withstand at N-channel open drain outputS32 to S47* Output for VFD display conroller segment
* 8-bit input/output port* Other function
Input/output can be specified in bit unit S32 ~ S39 : High voltage input port PE0 ~ PC7
* Other pin functions S40 ~ S47 : High voltage I/O port PF0 ~ PD7
P10 : SIO0 data outputS48 to S51* Output for VFD display conroller segment
P11 : SIO0 data input/bus input/output* Other function
I/OP10 -P17
P12 : SIO0 clock input/output S48 ~ S51 : High voltage I/O port PG0 ~ PD3
P13 : SIO1 data ouputRESI Reset pin
P14 : SIO1 data input/bus input/outputXT1/P74I * Input pin for 32.768kHz crystal oscillation
P15 : SIO1 clock input/output* Other function
P16 : Buzzer output P74 for input port
P17 : Timer output (PWM0 output) Incase of non use, connect to VDD1
* 8-bit input/output portXT2/P75O * Output pin for 32.768kHz crystal oscillation
P30 - P37
Input/output in bit unit* Other function
* 15V withstand at N-channel open drain output P75 for input port
I/O
P70 - P73I/O * 4-bit input/output port* In case of non use,
P74 - P75I
Input/output port
* 2-bit input port
* Other pin functions
P70 : INT0 input/Hold release/N ch-Tr.
output for watchdog timer
P71 : INT1 input/ HOLD release input
P72 : INT2 input/timer 0 event input
P73 : INT3 input with noise filter/timer 0 event input
P74 : Input pin XT1 for 32.768kHz crystal resonator oscillation
P75 : Output pin XT2 for 32.768kHz crystal resonator oscillation
At using as oscillator, should be left opened
At using as a port, connect to VDD1
CF1I Input pin for ceramic resonator oscillation
CF2O Output pin for ceramic resonator oscillation
* All of port options (except pull-up resistor of port 0) can be specified in bit unit.
* A state of pins at reset
P80 - P83I * 4-bit input/output port
P84 - P87I/O Input/output in bit unit
* 4-bit input port
* Other function
AD input port (8 port pins)
S0/T0 to S6/T6 O Output for VFD display controller segment/timing in common
- 66 -
IC BLOCK DAIGRAM & DESCRIPTION
- POWER section -
IC470 STK402-230 (3 Channel AF Power Amplifier)
1
CH1 IN
2
CH1 NF
3
NC
4
567
BIAAS
Pre. +VCC
CH1 - VE
CH1 +VE
89
CC
+ V
10
CC
- V
CH2 +VE
11 121314
CC
CH2 - VE
Pre - V
SUB GND.
15 161718
CH3 IN
CH2 IN
CH2 NF
CH3 NF
CH3 +VE
IC491,493 PQ1CZ31H2ZP (Chopper Regulater)
12
V
IN
Overcurrent
detection
circuit
Overheat
detection
circuit
Constant-
voltage
circuit
Q
R
S
-
+
PWM
Comp.
Oscillation
circuit
ON/OFF
Circuit
Error Amp.
-
+
V
REF
5
4
V
OUT
ON/OFF
Oadj
- PRE-AMP section -
IC450 LC75342M (2 Band Equalizer)
LSELO LIN LTRELBASS1 LBASS2LOUT
10 97658
L4
19
CH3 - VE
11
L3
12
L2
13
L1
14
NC
15
NC
16
R1
17
R2
18
R3
19
R4
20
21 2224252623
RSELO RIN RTRERBASS1 RBASS2ROUT
IC451 LA2615 (Surround Signal Processor)
GCRGLRPOGLPFDNCVCCL-OUTR-OUT
P16P15P14P13P12P11P10P9
3
COM
CONTROL
CIRCUIT
LOGIC
CIRCUIT
CONTROL
CIRCUIT
LVref
CCB
INTERFACE
RVref
Vcc
4
TEST
3
SS
V
2
CE
1
DI
30
CL
29
V
DD
28
Vref
27
NC
A
SW
B
IC492 NJM7805FA, KIA7805API (Regulater)
1. INPUT
2. COMMON
3. OUTPUT
123
ANALOG
SURROUND
P1P2P3P4P5P6P7P8
CONT1CONT2CONT3GNDHFFCVREFL-INR-IN
ATTLEVEL
VREF
ON/OFF
B
A
IC452, 453 KIA4558S (Operational Amplifier)
AB
123456789
CC
V
OUT A
- IN A
EE
V
+ IN A
+ IN B
- IN B
SW
OUT B
CC
V
- 67 -
IC BLOCK DAIGRAM & DESCRIPTION
123
1. INPUT
2. COMMON
3. OUTPUT
g
- VIDEO section -
IC410 MM1508XNRE
(2-Input 1-Output Switch with 6dB AMP)
1
SW
OUT
Vcc
Clamp
DRV.
2
6dB
Clamp
3
Bias
6
IN1
5
GND
4
IN2
- MPEG section -
IC101 24LC16BT, S524L50X51 (16K EEPROM)
1
A0
2
A1
3
A2
4
V
SS
8
24LC16B
7
6
5
V
CC
WP
SCL
SDA
IC495 NJM7805FA, KIA7805API (Regulater)
IC104 BA033FP (Regulater)
3
2
1
GND
OUT
V
CC
NameFunction
V
SS
SDA
SCL
WP
V
CC
A0,A1,A2
IC103 BA25BCOFP (Voltage Regulater)
Vcc
GND
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+2.5V to 5.5V Power Supply
No Internal Connection
1
Vref
2
REFFERENCE
1
Vcc
GND
VOLTAGE
2
3
OUT
IC105 74VHC74MTC, TC74VHC74FT (Flip-Flop)
CLR1
1
D1D1
2
3
CK1
PR1
4
5
Q1
6
3
OUT
Q1
GND
7
CK1
PR1
Q1
D2
CLR2
Q2
CLR1
Q1
CK2
PR2
Q2
Truth Table
InputsOutput
X
X
H(Note 1)
X
Q
L
H
L
H
Qn
CLR
L
H
L
H
H
H
PR
H
L
L
H
H
H
D
CK
X
X
X
L
H
X
- 68 -
14
13
12
11
10
9
8
Q
H
L
H(Note 1)
H
L
Qn
Vcc
CLR2
D2
CK2
PR2
Q2
Q2
Function
Clear
Preset
No Change
IC BLOCK DAIGRAM & DESCRIPTION
IC102 ADV7170KSU (VIDEO Encoder)
SET
ALSB
BLANK
P0
TTX
GND
Input/
Output
TTXREQ
SCRESET/
RTC
AA
V
GND
I
I
I/O
I/O
I/O
I
I/O
I
O
O
O
O
O
I
I/O
I
I
I
O
P
G
R
V
REF
33
DAC A
32
31
30
29
28
27
26
25
24
23
RESET
DAC B
V
AA
GND
AA
V
DAC D
DAC C
COMP
SDATA
SCLOCK
Vss
RESET
CLOCK
DATA
P7-P0
P15-P8
HSYNC
FIELD/VSYNC
BLANK
1,11,20,28,30
22
4-2
43-38
14-12
9-5
15
16
17
Function
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7-P0) or 16-Bit YCrCb Pixel Port (P15-P0).
P0 represents the LSB.
TTL Clock Input. Requires a stable 27 MHz reference Clock for standard operation. Alternatively, a 24.52 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.
HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to output (Master
Mode) or accept (Slave Mode) Sync signals.
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may be
configured to output (Master Mode) or accept (Slave Mode) these control signals.
Video Blanking Control Signal. The pixel inputs are ignored when this is Logic Level "0."
This signal is optional.
This pin can be configured as an input by setting MR22 and MR21 of Mode Register 2. It
can be configured as a subcarrier reset pin, in which case a high-to-low transition on this
pin will reset the subcarrier to Field 0. Alternatively, it may be configured as a Real-Time
Control (RTC) input.
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
A 150 Ω resistor connected from this pin to GND is used to control full-scale amplitudes of
the video signals.
Compensation Pin. Connect a 0.1 µ F Capacitor from COMP to VAA. For Optimum Dynamic
Performance in low power mode, the value of the COMP capacitor can be lowered to as low
as 2.2 nF.
PAL/NTSC Composite Video Output. Full-Scale Output is 180 IRE (1286 mV) for NTSC
and 1300 mV for PAL.
RED/S-Video C/V Analog Output.
GREEN/S-Video Y/Y Analog Output.
BLUE/Composite/U Analog Output.
MPU Port Serial Interface Clock Input.
MPU Port Serial Data Input/Output.
TTL Address Input. This signal set up the LSB of the MPU address.
The input resets the on chip timing generator and sets the ADV7170/ADV7171 into default
mode. This is NTSC operation, Timing Slave Mode 0, 8 Bit Operation, 2 x Composite and
S Video out and DAC B powered ON and DAC D powered OFF.
Teletext Data/Defaults to VAA When Teletext not Selected (enables backward compatibility to
ADV7175/ADV7176).
Teletext Data Request Signal/ Defaults to GND when Teletext not Selected (enables backward
compatibility to ADV7175/ADV7176).
Power Supply (+3V to +5V).
Ground Pin.
GNDP4P3P2P1
CLOCK
44 43 42 41 4036 35 3439 38 37
1
AA
V
PIN 1
2
P5
IDENTIFIER
P6
3
P7
4
P8
5
P9
6
P10
7
P11
8
P12
9
10
GND
11
V
AA
12 13 14 15 1620 21 2217 18 19
P13
P14
Mnemonic
P15-P0
CLOCK
HSYNC
FIELD/VSYNC
BLACK
SCRESET/RTC
V
REF
R
SET
COMP
DAC A
DAC C
DAC D
DAC B
SCLOCK
SDATA
ALSB
RESET
TTX/V
TTXREQ/GND
AA
V
GND
ADV7170/ADV7171
PQFP/TQFP
TOP VIEW
(Not to Scale)
P15
HSYNC
FIELD/VSYNC
AA
TTXREQTTX
POWER
MANAGEMENT
CONTROL
(SLEEP MODE)
4:2:2 TO
4:4:4
INTER-
POLATOR
VIDEO TIMING
GENERATOR
4423241835
CLOCKSCLOCK SDATA ALSBSCRESET/RTCGND
YCrCb
TO
YUV
MATRIX
CGMS & WSS
INSERTION
Y
88
88
U
88
V
BLOCK
ADD
SYNC
ADD
BURST
2
I C MPU PORT
9
8
8
TELETEXT
INSERTION
INTER-
POLATOR
INTER-
POLATOR
3736
BLOCK
9
8
8
PROGRAMMABLE
LUMINANCE
FILTER
PROGRAMMABLE
CHROMINANCE
FILTER
REAL-TIME
CONTROL
CIRCUIT
10
10
1010
DDS BLOCK
YUV TO
MATRIX
U
V
SIN/COS
RBG
10
10
10
10
10,19,29,43
M
U
10
10-BIT
L
T
I
10
10-BIT
P
L
E
10
X
10-BIT
E
R
10
10-BIT
VOLTAGE
REFERENCE
CIRCUIT
DAC
DAC
DAC
DAC
DAC D(PIN 27)
27
DAC C(PIN 26)
26
GAC B(PIN 31)
31
DAC A(PIN 32)
32
V
REF
33
R
SET
34
COMP
25
- 69 -
IC BLOCK DAIGRAM & DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
XTI
SCKO
VCP
NC
MCKO
ML
MC
MD
RSTB
ZERO
VOUTR
GNDAVCA
VOUTL
CAP
BCKIN
DIN
LRCIN
NC
RSV
VDD
GNDD
GNDP
XTO
4
2
1
5
VCC
GND
IN A
IN B
OUT Y
3
IC110,111,117 EM636165TS,KM416S1120DT , K4S161622D
(1 Mega x 16 Synchronous DRAM)
IC133,135,137 TC7SH08FU, NC7SZ08P5
(2 Input and Gate)
IC136 TC7SHU04FU, NC7SZU04P5 (Inverter)
5
4
V
OUT Y
- 70 -
NC
IN A
GND
1
2
3
8Vcc
7
6
5
CC
B: OUT
B: -IN
B: +IN
IC BLOCK DAIGRAM & DESCRIPTION
IC110,111,117 EM636165TS,KM416S1120DT, K4S161622D (1 Mega x 16 Synchr onous DRAM(SRAM))
SymbolTypeDescription
CLKInputClock: CLK is driven by the system clock. All SDRAM input signals are sampled on
the positive edge of CLK. CLK also increments the internal burst counter and controls
the output registers.
CKEInputClock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal.If CKE
goes low synchronously with clock(set-up and hold time same sa other inputs), the
internal clock is suspended from the next clock cycle and the state of output and
burst address is frozen as long as the CKE remains low. When both banks are in the
idle state, deactivating the clock controls the entry to the P ow er Do wn and Self Refresh
modes. CKE is synchronous except after the device enters Power Down and Self
Refresh modes, where CKE becomes asynchronous until exiting the same mode.
The input buffers, including CLK, are disabled during Power Down and Self Refresh
modes, providing low standby power.
A11InputBank Select: A11(BS) defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
AC-A10InputAddress Inputs: A0-A10 are sampled during the BankActivate command (row address
A0-A10 and Read/Write command (column address A0-A7 with A10 defining Auto
Precharge) to select one location out of the 256K available in the respective bank.
During a Precharge command, A10 is sampled to determine if both banks are to be
precharged (A10-HIGT). The address inputs also provide the op-code during a Mode
Register Set command.
CS#InputChip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS# is sampled HIGH. CS# provides for
external bank selection on systems with multiple banks. It is considered part of
the command code.
RAS#InputRow A d d r e s s S t r o b e : The RAS# signal defines the operation commands in conjunction
with the CAS# and WE# signals and is latched at the positive edges of CLK. When
RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the
BankActivate command or the Precharge command is selected by the WE# signal.
When the WE# is asserted "HIGH," the BankActivate command is selected and the
bank designated by BS is turned on to the active state. When the WE# is asserted
"LOW," the Precharge command is selected and the bank designated by BS is
switched to the idle state after the precharge operation.
CAS#InputColumn Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is
started by asserting CAS#"LOW." Then, the Read or Write command is selected by
asserting WE# "LOW" or "HIGH."
WE#InputWrite Enable: The WE# signal defines the operation commands in conjunction with
the RAS# and CAS# signals and is latched at the positive edges of CLK. The WE#
input is used to select the BankActivate or Precharge command and Read or Write
command.
LDQM,
UDQM
DQC-DQ15 Input /
NC-No Connect: These pins should be left unconnected.
DDQ
V
SSQ
V
DD
V
SS
V
InputData Input/Output Mask: LDQM and HDQM are byte specific , nonpersistent I/O b uff er
controls. The I/O buffers are placed in a high-z state when DQM is sampled HIGH.
Input data is masked when DQM is sampled HIGH during a write cycle. Output data
is masked (two-clock latency) when DQM is sampled HIGH during a read cycle.
UDQM masks DQ15-DQ8, and LDQM masks DQ7-DQ0.
Data I/O: The DQ0-15 input and output data are synchronized with the positive edges
Output
of CLK. The I/Os are byte-maskable during Reads and Writes.
SupplyDQ Power: Provide isolated power to DQs for improved noise immunity.(3.3V±0.3V)
SupplyDQ Ground: Provide isolsted ground to DQs for improved noise immunity.(0V)
SupplyPower Supply: +3.3V±0.3V
SupplyGround
- 71 -
IC BLOCK DAIGRAM & DESCRIPTION
FL601 Vaccum Fluorescent Display
132
PINNO
CONNECTION
PINNO
CONNECTION
1)Fn:Filamentpin
2)nG:Gridpin
3)Pn:Anodepin
4)NP:Nopin
12345678910111213141516
F1F1NPP1P2P3P4P5P6P7P8P9P10P11P12P13
17181920212223242526272829303132
P14P15P16P17P188G7G6G5G4G3G2G1GNPF2F2
1G2G3G4G5G6G7G8G
S16S16
2GS1S2S3S4S5S6S7S8
S9S10S11S12S13S14S15
3GS1S2S3S4S5S6S7S8
S9S10S11S12S13S14S15
4GS1S2S3S4S5S6S7S8
S9S10S11S12S13S14S15S16
5G
S1S2S3S4S5S6S7S8
S9S10S11S12S13S14S15
6GS1S2S3S4S5S6S7S8S9
S10
S11S12S13S14S15S16
7G
S1S2S3S4S5S6S7S8
S9S10S11S12S13S14S15
P1P2P3P4P5P6P7P8P9
P10
P11P12P13P14P15P16
1GS1S2S3S4S5S6S7S8
S9S10S11S12S13S14S15
P17P18
S12
8GS1S2S3S4S5S6S7S8S9
S10
S11S12S13S14S15
S3S1
S8
S13S15
S11
(1G~8G)
S6
S5S4
S2
S7
S14
S9
S10
- 72 -
MEMO
- 73 -
SCHEMATIC DIAGRAM (MPEG)
- 74 -- 75 -
This is a basic schematic diagram.
WIRING DIAGRAM (MPEG A SIDE)
- 77 -- 76 -
WIRING DIAGRAM (MPEG B SIDE)
- 79 -- 78 -
SCHEMATIC DIAGRAM (AMP for 1000,US,CA)
This is a basic schematic diagram.
- 80 -- 81 -
PRODUCT SAFETY
NOTICE
Each precaution in this manual
should be followed during
servicing. Components identified
with the IEC symbol
parts list and the schematic
diagram designated
components in which safety can
be of special significance. When
replacing a component identified
!!
!
, use only the replacement
by
parts designated, or parts with
the same ratings of resistance,
wattage or voltage that are
designated in the parts list in this
manual. Leakage-current or
resistance measurements must
be made to determine that
exposed parts are acceptably
insulated from the supply circuit
before returning the product to
the customer.
in the
!!
!
SCHEMATIC DIAGRAM (AMP for XE,UK)
This is a basic schematic diagram.
- 86 -
- 87 -
PRODUCT SAFETY
NOTICE
Each precaution in this manual
should be followed during
servicing. Components
identified with the IEC symbol
in the parts list and the
!!
!
schematic diagram designated
components in which safety
can be of special significance.
When replacing a component
identified by
replacement parts designated,
or parts with the same ratings
of resistance, wattage or
voltage that are designated in
the parts list in this manual.
Leakage-current or resistance
measurements must be made
to determine that exposed
parts are acceptably insulated
from the supply circuit before
returning the product to the
customer.
!!
!
, use only the
WIRING DAIGRAM (PRE-AMP for XE,UK)
- 88-
WIRING DIAGRAM (POWER AMP for XE,UK)
- 89 -
SCHEMATIC DIAGRAM (AMP for SS)
This is a basic schematic diagram.
- 92 -
- 93 -
PRODUCT SAFETY
NOTICE
Each precaution in this manual
should be followed during
servicing. Components identified
with the IEC symbol
parts list and the schematic
diagram designated components
in which safety can be of special
significance. When replacing a
component identified by
only the replacement parts
designated, or parts with the
same ratings of resistance,
wattage or voltage that are
designated in the parts list in this
manual. Leakage-current or
resistance measurements must
be made to determine that
exposed parts are acceptably
insulated from the supply circuit
before returning the product to
the customer.
in the
!!
!
!!
!
, use
WIRING DIAGRAM (PRE-AMP for SS,KR)
- 94 -
WIRING DIAGRAM (POWER AMP for SS,KR)
- 95 -
WIRING DIAGRAM (VIDEO-AMP for SS,KR)
- 96 -
WIRING DIAGRAM (SOCKET-A for SS)
- 97 -
SCHEMATIC DIAGRAM (AMP for KR)
This is a basic schematic diagram.
- 98 -- 99 -
PRODUCT SAFETY
NOTICE
Each precaution in this manual
should be followed during
servicing. Components
identified with the IEC symbol
in the parts list and the
!!
!
schematic diagram designated
components in which safety can
be of special significance. When
replacing a component identified
!!
!
, use only the replacement
by
parts designated, or parts with
the same ratings of resistance,
wattage or voltage that are
designated in the parts list in this
manual. Leakage-current or
resistance measurements must
be made to determine that
exposed parts are acceptably
insulated from the supply circuit
before returning the product to
the customer.
WIRING DIAGRAM (SOCKET-A for KR)
- 100-
WIRING DIAGRAM (REGULATOR & DIGITAL OUT)
REGULATOR
DIGITAL OUT (10000,US,CA)
DIGITAL OUT (XE,UK)DIGITAL OUT (SS)
DIGITAL OUT (KR)DIGITAL OUT (AU)
- 101 -
SCHEMATIC DIAGRAM (AMP for AU)
This is a basic schematic diagram.
- 102 -- 103 -
PRODUCT SAFETY
NOTICE
Each precaution in this manual
should be followed during
servicing. Components
identified with the IEC symbol
in the parts list and the
!!
!
schematic diagram designated
components in which safety can
be of special significance. When
replacing a component identified
!!
!
, use only the replacement
by
parts designated, or parts with
the same ratings of resistance,
wattage or voltage that are
designated in the parts list in this
manual. Leakage-current or
resistance measurements must
be made to determine that
exposed parts are acceptably
insulated from the supply circuit
before returning the product to
the customer.
SCHEMATIC DIAGRAM (FRONT for 1000,XE,UK,US,CA)
- 110 -- 111 -
This is a basic schematic diagram.
SCHEMATIC DIAGRAM (FRONT for SS,KR)
This is a basic schematic diagram.
- 113 -- 112 -
WIRING DIAGRAM (FRONT for SS,KR)
- 114 -
WIRING DIAGRAM (FRONT for AU)
- 115 -
SCHEMATIC DIAGRAM (FRONT for AU)
- 116 -- 117 -
This is a basic schematic diagram.
SCHEMATIC DIAGRAM (DVD)
Top left zoon,There is the drawing which zoomed to 120,121 pages.Top right zoon,There is the drawing which zoomed to 124,125 pages.
Bottom left zoon,There is the drawing which zoomed to 122,123 pages.
This is a basic schematic diagram.
- 118 -
Bottom right zoon,There is the drawing which zoomed to 126,127 pages.
- 119 -
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