Fairchild Semiconductor MM74HC245AWMX, MM74HC245ASJX, MM74HC245ACW, MM74HC245AMTC, MM74HC245AMTCX Datasheet
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September 1983
Revised February 1999
MM74HC245A Octal 3-STATE Transceiver
© 1999 Fairchild Semiconductor Corporation DS005165.prf www.fairchildsemi.com
MM74HC245A
Octal 3-STATE Transceiver
General Description
The MM74HC245A 3-STATE bidirectional buffer utilizes
advanced silicon-gate CMOS technology, and is intended
for two-way asynchronous communication between data
buses. It has high drive current out puts which enable high
speed operation even when driving large bus capacitances. This circuit possesses the low power co nsumption
and high noise immunity usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky
TTL circuits.
This device has an active LOW enable input G
and a direction control input, DIR. When DIR is HIGH, data flows from
the A inputs to the B outputs. When DIR is LOW, data flows
from the B inputs to the A outputs. The MM74HC245A
transfers true data from one bus to the other.
This device can drive up to 15 LS-TTL Loads, and does not
have Schmitt trigg er inputs. All inputs are protected from
damage due to static discharge by diodes to V
CC
and
ground.
Features
■ Typical propagation delay: 13 ns
■ Wide power supply range: 2–6V
■ Low quiescent current: 80 µA maximum (74 HC)
■ 3-STATE outputs for connection to bus oriented systems
■ High output drive: 6 mA (minimum)
■ Same as the 645
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.
Connection Diagram
Pin Assignments f or DIP, SOIC, SOP and TSSOP
Top View
Truth Table
H = HIGH Level
L = LOW Level
X = Irrelevant
Order Number Package Number Package Description
MM74HC245AWM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC245ASJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC245AMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC245AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Control
Inputs Operation
G
DIR
L L B data to A bus
L H A data to B bus
HX Isolation
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MM74HC245A
Logic Diagram
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MM74HC245A
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Maximum Ratings are those values beyond which damage to the
device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation te mperature d erating — pl astic “N” pa ckage: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Note 4: For a powe r supply o f 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4. 5V valu es shou ld be u sed when
designing with this supply. Worst case V
IH
and VIL occur at V
CC
= 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3 .8 5V.) The worst c as e leakage cur-
rent (I
IN
, ICC, and IOZ) occur for CMOS at the higher voltage and so th e 6. 0V values should be used.
Supply Voltage (VCC) −0.5 to +7.0V
DC Input Voltage DIR and G
pins (VIN) −1.5 to V
CC
+1.5V
DC Input/Output Voltage (V
IN
, V
OUT
) −0.5 to V
CC
+0.5V
Clamp Diode Current (I
CD
) ±20 mA
DC Output Current, per pin (I
OUT
) ±35 mA
DC V
CC
or GND Current, per pin (ICC) ±70 mA
Storage Temperature Range (T
STG
) −65°C to +150°C
Power Dissipation (P
D
)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
L
)
(Soldering 10 second s) 260°C
Min Max Units
Supply Voltage (V
CC
)26V
DC Input or Output Voltage
(V
IN
, V
OUT
)0V
CC
V
Operating Temperature Range (T
A
) −40 +85 °C
Input Rise/Fall Times
(t
r
, tf) V
CC
= 2.0V 1000 ns
V
CC
= 4.5V 500 ns
V
CC
= 6.0V 400 ns
Symbol Parameter Conditions
V
CC
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Units
Typ Guaranteed Limits
V
IH
Minimum HIGH Level Input 2.0V 1.5 1.5 1.5 V
Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum LOW Level Input 2.0V 0.5 0.5 0.5 V
Voltage 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
OH
Minimum HIGH Level Output V
IN
= VIH or V
IL
Voltage |I
OUT
| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
V
IN
= VIH or V
IL
|I
OUT
| ≤ 6.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|I
OUT
| ≤ 7.8 mA 6.0V 5.7 5.48 5.34 5.2 V
V
OL
Maximum LOW Level Output V
IN
= VIH or V
IL
Voltage |I
OUT
| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
V
IN
= VIH or V
IL
|I
OUT
| ≤ 6.0 mA 4.5V 0.2 0.26 0.33 0.4 V
|I
OUT
| ≤ 7.8 mA 6.0V 0.2 0.26 0.33 0.4 V
I
IN
Input Leakage V
IN
= VCC to GND 6.0V ±0.1 ±1.0 ±1.0 µA
Current (G and DIR)
I
OZ
Maximum 3-STATE Output V
OUT
= VCC or GND 6.0V ±0.5 ±5.0 ±10 µA
Leakage Current
Enable G = V
IH
I
CC
Maximum Quiescent Supply V
IN
= VCC or GND 6.0V 8.0 80 160 µA
Current I
OUT
= 0 µA
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