Fairchild Semiconductor MM74HC08SJ, MM74HC08SJX, MM74HC08N, MM74HC08M, MM74HC08MTC Datasheet
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MM74HC08
Quad 2-Input AND Gate
MM74HC08 Quad 2-Input AND Gate
September 1983
Revised December 1999
General Description
The MM74HC08 AND gates utilize advanced silicon-gate
CMOS technology to achieve operating speeds similar to
LS-TTL gates with the low p ower con sum ption of standa rd
CMOS integrated cir cuits. The HC08 has buffered outputs,
providing high noise immunity and the ability to drive 10
LS-TTL loads. The 74HC logic family is functionally as well
as pin-out compatible with the standard 74LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to V
and ground.
CC
Features
■ Typical propagation delay: 7 ns (t
■ Fanout of 10 LS-TTL loads
■ Quiescent power consumpti on: 2 µA maximum at room
temperature
■ Low input current: 1 µA maximum
PHL
), 12 ns (t
PLH
)
Ordering Code:
Order Number Package Number Package Description
MM74HC08M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Wide
MM74HC08SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC08N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e. (Tape and Reel not available in N14A)
Connection Diagram
Top View
© 1999 Fairchild Semiconductor Corporation DS005297 www.fairchildsemi.com
Absolute Maximum Ratings(Note 1)
(Note 2)
Supply Voltage (VCC) −0.5 to +7.0V
DC Input Voltage (V
MM74HC08
DC Output Voltage (V
Clamp Diode Current (I
DC Output Current, per pin (I
or GND Current, per pin
DC V
CC
) ±50 mA
(I
CC
Storage Temperature Range (T
Power Dissipation (P
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
(Soldering 10 seconds) 260°C
) −1.5 to V
IN
) −0.5 to V
OUT
, IOK) ±20 mA
IK
) ±25 mA
OUT
) −65°C to +150°C
STG
)
D
)
L
CC
CC
Recommended Operating
Conditions
+1.5V
Supply Voltage (V
+0.5V
DC Input or Output Voltage 0 V
, V
(V
IN
OUT
Operating Temperature Range (T
Input Rise or Fall Times
, tf)V
(t
r
V
V
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation tem perature de rating — pla stic “N” pac kage: −
12 mW/°C from 65 °C to 85°C.
)26V
CC
)
) −40 +85 °C
A
= 2.0V 1000 ns
CC
= 4.5V 500 ns
CC
= 6.0V 400 ns
CC
Min Max Units
CC
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions
V
Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
IH
Input Voltage 4.5V 3.15 3.15 3.15 V
V
Maximum LOW Level 2.0V 0.5 0.5 0.5 V
IL
Input Voltage 4.5V 1.35 1.35 1.35 V
V
Minimum HIGH Level V
OH
Output Voltage |I
V
Maximum LOW Level V
OL
Output Voltage |I
I
Maximum Input Current V
IN
I
Maximum Quiescent Supply Current V
CC
Note 4: For a power supp ly of 5V ±1 0% the worst c ase ou tput volta ges (VOH, and VOL) occur for HC at 4.5V. Thus the 4. 5V valu es shoul d be use d when
designing with this supply. Worst case V
, ICC, and IOZ) occur for CMOS at the higher voltage and so th e 6. 0V values should be used.
rent (I
IN
and VIL occur at V
IH
= V
IN
IH
| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
OUT
V
= V
IN
IH
|I
| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
OUT
|I
| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
OUT
= VIH or V
IN
| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
OUT
V
= VIH or V
IN
|I
| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
OUT
|I
| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
OUT
= VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
IN
= VCC or GND 6.0V 2.0 20 40 µA
IN
I
= 0 µA
OUT
CC
V
CC
6.0V 4.2 4.2 4.2 V
6.0V 1.8 1.8 1.8 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
IL
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
IL
= 5.5V and 4.5V res pectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage c ur-
TA = 25°CTA = −40 to 85°CTA = −40 to 125°C
Typ Guaranteed Limits
V
Units
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AC Electrical Characteristics
V
= 5V, TA = 25°C, CL = 15 pF, tr = t
CC
= 6 ns
f
Symbol Parameter Conditions Typ
t
PHL
Maximum Propagation 12 20 ns
Delay, Output HIGH-to-LOW
t
PLH
Maximum Propagation 7 15 ns
Delay, Output LOW-to-HIGH
AC Electrical Characteristics
V
= 2.0V to 6.0V, C
CC
Symbol Parameter Conditions
t
PHL
t
PLH
t
, t
TLH
THL
C
PD
C
IN
Note 5: CPD determines the no load dynamic power con s um ption, PD = CPD V
= CPD VCC f + ICC.
I
S
= 50 pF, t
= t
L
= 6 ns (unless otherwise specified)
r
f
V
CC
Typ Guaranteed Limits
Maximum Propagation Delay, 2.0V 77 121 175 ns
Output HIGH-to-LOW 4.5V 15 24 35 ns
6.0V 13 20 30 ns
Maximum Propagation Delay, 2.0V 30 90 134 ns
Output LOW-to-HIGH 4.5V 10 18 27 ns
6.0V81523ns
Maximum Output 2.0V 30 75 110 ns
Rise and Fall Time 4.5V 8 15 22 ns
6.0V71319ns
Power Dissipation Capacitance (Note 5) (per gate) 38 pF
Maximum Input Capacitance 4 10 10 pF
2
f + ICC VCC, and the no load dynam ic current consumpt ion,
CC
Guaranteed
Limit
TA = 25°CTA = −40 to 125°C
MM74HC08
Units
Units
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