Fairchild Semiconductor ML4812CP Datasheet

April 1998

ML4812

Power Factor Controller

GENERAL DESCRIPTION

The ML4812 is designed to optimally facilitate a peak

FEATURES

■ Precision buffered 5V reference (±0.5%)

current control boost type power factor correction system.
Special care has been taken in the design of the ML4812
to increase system noise immunity. The circuit includes a

■ Current-input gain modulator reduces external

components and improves noise immunity
precision reference, gain modulator, error amplifier, over­voltage protection, ramp compensation, as well as a high

■ Programmable ramp compensation circuit

current output. In addition, start-up is simplified by an
under-voltage lockout circuit with 6V hysteresis.

In a typical application, the ML4812 functions as a
current mode regulator. The current which is necessary to

■ 1A peak current totem-pole output drive

■ Overvoltage comparator helps prevent output

voltage “runaway”
terminate the cycle is a product of the sinusoidal line
voltage times the output of the error amplifier which is
regulating the output DC voltage. Ramp compensation is

■ Wide common mode range in current sense

comparators for better noise immunity
programmable with an external resistor, to provide stable
operation when the duty cycle exceeds 50%.

■ Large oscillator amplitude for better noise immunity

BLOCK DIAGRAM (Pin Configuration Shown is for DIP Version)

OVP

5

I

SENSE

1

GM OUT

2

EA OUT

3

EA–

4

5V

5V

5V

+
–

+
–
–

ERROR

AMP

+
–

I

EA

SRQ

Q

UNDER
VOLTAGE
LOCKOUT

SHDN

OUT

V

V

32V

REF

CC

10

12

11

14

13

V

CC

PWR GND

I

SINE

6

RAMP COMP

7

C

T

16

R

T

8

GAIN MODULATOR

OSC

GND

15

5V

CLOCK

9

1kΩ

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ML4812

PIN CONFIGURATION

ML4812

16-Pin PDIP (P16)

1

I

SENSE

OVP

I

SINE

EA–

R

T

2

3

4

5

6

7

8

TOP VIEW

GM OUT

EA OUT

RAMP COMP

PIN DESCRIPTION

PIN NAME FUNCTION

ML4812

20-Pin PLCC (Q20)

16

C

T

15

GND

14

V

REF

13

V

CC

12

OUT

11

PWR GND

10

SHDN

9

CLOCK

EA OUT

PIN NAME FUNCTION

OVP

I

SINE

EA–

NC

4
5
6
7
8

SENSE

GM OUT

I

NC

CTGND

3212019

910111213

T

R

NC

SHDN

CLOCK

RAMP COMP

TOP VIEW

18
17
16
15
14

V

REF

V

CC

NC
OUT
PWR GND

1 I

SENSE

Input from the current sense
transformer to the non-inverting input
of the PWM comparator.

2 GM OUT Output of gain modulator.

A resistor to ground on this pin
converts the current to a voltage.
This pin is clamped to 5V and tied
to the inverting input of the PWM
comparator.

3 EA OUT Output of error amplifier.

4 EA– Inverting input to error amplifier.

5 OVP Input to over voltage comparator.

6 I

SINE

Current gain modulator input.

7 RAMP

COMP Buffered output from the oscillator

ramp (C

). A resistor to ground sets the

T

current which is internally subtracted
from the product of I

and IEA in

SINE

the gain modulator.

8R

T

Oscillator timing resistor pin. A 5V
source sets a current in the external
resistor which is mirrored to charge
C

.

T

9 CLOCK Digital clock output.

10 SHDN A TTL compatible low level on this pin

turns off the output.

11 PWR GND Return for the high current totem pole

output.

12 OUT High current totem pole output.

13 V

14 V

CC

REF

Positive Supply for the IC.

Buffered output for the 5V voltage
reference.

15 GND Analog signal ground.

16 C

T

Timing capacitor for the oscillator.

2 REV. 1.0 10/10/2000

ABSOLUTE MAXIMUM RATINGS

ML4812

Absolute maximum ratings are those values beyond
which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and
functional device operation is not implied.

Junction Temperature ............................................. 150°C

Storage Temperature Range ..................... –65°C to 150°C

Lead Temperature (soldering 10 sec.) ..................... 260°C

Thermal Resistance (θ

)

JA

20-Pin PLCC .................................................... 60°C/W

Supply Current (I

) ............................................... 30mA

CC

16-Pin PDIP .................................................... 65°C/W

Output Current Source or Sink (OUT) DC................ 1.0A

Output Energy (capacitive load per cycle) .................. 5µJ

Gain Modulator I

SINE

Input (I

) ......................... 1.2mA

SINE

Error Amp Sink Current (EA OUT).......................... 10mA

Oscillator Charge Current ........................................ 2mA

Analog Inputs (I

, EA–, OVP) ............... –0.3V to 5.5V

SENSE

OPERATING CONDITIONS

Temperature Range

ML4812CX ................................................ 0°C to 70°C

ML4812IX ............................................. –40°C to 85°C

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, VCC = 15V , RT = 14kΩ, CT = 1000pF, TA = Operating Temperature Range (Notes 1, 2).

PARAMETER CONDITIONS MIN TYP MAX UNITS

OSCILLATOR

Initial Accuracy TJ = 25°C 91 98 105 kHz
Voltage Stability 12V < VCC < 18V 0.3 %
Temperature Stability 2%
Total Variation Line, temperature 90 108 kHz
Ramp Valley to Peak 3.3 V
RT Voltage 4.8 5.0 5.2 V
Discharge Current (RT open) TJ = 25°C, VCT= 2V 7.8 8.4 9.0 mA

VCT = 2V 7.3 8.4 9.3 mA
Clock Out Voltage Low RL = 16kΩ 0.2 0.5 V
Clock Out Voltage High RL = 16kΩ 3.0 3.5 V

REFERENCE

Output Voltage TJ = 25°C, IO = 1mA 4.95 5.00 5.05 V
Line Regulation 12V < VCC < 25V 2 20 mV
Load Regulation 1mA < IO < 20mA 2 20 mV
Temperature Stability 0.4 %
Total Variation Line, load, temp. 4.9 5.1 V
Output Noise Voltage 10Hz to 10kHz 50 µV
Long Term Stability TJ = 125°C, 1000 hours 5 25 mV
Short Circuit Current V

ERROR AMPLIFIER

Input Offset Voltage ±15 mV
Input Bias Current –0.1 –1.0 µA
Open Loop Gain 1 < V
PSRR 12V < VCC < 25V 60 75 dB
Output Sink Current V
Output Source Current V
Output High Voltage I
Output Low Voltage I
Unity Gain Bandwidth 1.0 MHz

= 0V –30 –85 –180 mA

REF

< 5V 60 75 dB

EA OUT

EA OUT

EA OUT

EA OUT

EA OUT

= 1.1V, V
= 5.0V, V

= –0.5mA, V

= 1mA, V

= 6.2V 2 12 mA

EA–

= 4.8V –0.5 –1.0 mA

EA–

= 4.8V 5.3 5.5 V

EA–

= 6.2V 0.5 1.0 V

EA–

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ML4812

ELECTRICAL CHARACTERISTICS (Continued)

PARAMETER CONDITIONS MIN TYP MAX UNITS

GAIN MODULATOR

I

Input Voltage I

SINE

Output Current (GM OUT) I

Bandwidth 200 kHz
PSRR 12V < VCC < 25V 70 dB

OVP COMPARATOR

Input Offset Voltage Output Off –25 +5 mV
Hysteresis Output On 95 105 115 mV
Input Bias Current –0.3 –3 µA
Propagation Delay 150 ns

PWM COMPARATOR: I

SENSE

Input Offset Voltage ±15 mV
Input Offset Current ±1 µA
Input Common Mode Range –0.2 5.5 V
Input Bias Current –2 –10 µA
Propagation Delay 150 ns
I

Trip Point V

LIMIT

OUTPUT

Output Voltage Low I

Output Voltage High I

Output Voltage Low in UVLO I
Output Rise/Fall Time CL = 1000pF 50 ns
Shutdown V

UNDER-VOLTAGE LOCKOUT

Startup Threshold 15 16 17 V
Shutdown Threshold 9 10 11 V
V

Good Threshold 4.4 V

REF

SUPPLY

Supply Current Start-Up, VCC = 14V, TJ = 25°C 0.8 1.2 mA

Internal Shunt Zener Voltage ICC = 30mA 25 30 34 V

= 500µA 0.4 0.7 0.9 V

SINE

= 500µA, EA– = V

SINE

I

= 500µA, EA– = V

SINE

I

= 1mA, EA– = V

SINE

I

= 500µA, EA– = V

SINE

I

RAMP COMP

GM OUT

OUT

I

OUT

OUT

I

OUT

OUT

IH

V

IL

IIL, V

IIH, V

= 50µA

= 5.5V 4.8 5 5.2 V

= –20mA 0.1 0.4 V
= –200mA 1.6 2.2 V
= 20mA 13 13.5 V
= 200mA 12 13.4 V
= –5mA, VCC = 8V 0.1 0.8 V

= 0V –1.5 mA

SHDN

= 5V 10 µA

SHDN

–20mV 430 470 510 µA

REF

+ 20mV 3 10 µA

REF

– 20mV 860 940 1020 µA

REF

– 20mV, 455 µA

REF

2.0 V

0.8 V

Operating, TJ = 25°C2025mA

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: V

is raised above the Startup Threshold first to activate the IC, then returned to 15V.

CC

4 REV. 1.0 10/10/2000

FUNCTIONAL DESCRIPTION

ML4812

OSCILLATOR

The ML4812 oscillator charges the external capacitor (C
with a current (I

) equal to 5/R

SET

. When the capacitor

SET

T

voltage reaches the upper threshold, the comparator
changes state and the capacitor discharges to the lower
threshold through Q1. While the capacitor is discharging,
Q2 provides a high pulse.

The Oscillator period can be described by the following
relationship:

EXTERNAL

CLOCK

C

SYNC

R

SYNC

I

SET

R

C

SYNC

10

R

T

9

T

C

T

16

T

8.4mA

I

SET

5.6V

Q

2

+

-

TT T

=+

OSC RAMP DEADTIME

)

where:

V

OUT

V

IN

=

-

D

1

ON

and:

´

CV

T RAM P VA LLEY TO PE AK

T

DEADTIME

(kΩ)

T

R

=

10

8

5

3

2

1

10 100 1000

5nF 2nF

10nF

20nF

OSCILLATOR FREQUENCY (kHz)

84.

-

mA I

SET

90%

1nF

85%

MAXIMUM DUTY CYCLE (%)

80%

70%

Figure 2. Oscillator Timing Resistance vs. Frequency

15

V

CC

14

13

SOURCE SATURATION

LOAD TO GROUND

SINK SATURATION

LOAD TO V

3

2

1

OUTPUT SATURATION VOLTAGE (V)

0

0 200 400 800

CC

OUTPUT CURRENT (mA)

VCC = 15V

80µs PULSED LOAD

120Hz RATE

GND

600

CLOCK

RAMP PEAK

RAMP VALLEY

Figure 1. Oscillator Block Diagram

V(CT)

Q

1

t

D

Figure 3. Output Saturation Voltage vs. Output Current

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