Fairchild Semiconductor DM96S02N, DM96S02MX, DM96S02M, DM96S02CW Datasheet

January 1992 Revised June 1999

DM96S02 Dual Retriggerable Resettable Monostable Multivibrator

General Description

The DM96S02 is a dual retriggerable and resettable monostable multivibrator. This one-shot provides exceptionally wide delay range, pulse width stability, predictable accuracy and immunity to noise . The puls e width is set by

an external resistor and capacitor. Resistor values up to 2.0 MΩ for the DM96S02 reduce required capacitor values. Hysteresis is provided on the positive trigger input of the DM96S02 for increased noise immunity.

Order Code:

Devices also availab le in Tape and Reel. S pecify by appending the suffix let t er “X” to the ordering code.

Logic Diagram

VCC = Pin 16 GND = Pin 8

Pin Descriptions

Connection Diagram

Triggering Truth Table

H = HIGH Voltage Level ≥ V

L = LOW Voltage Level ≤ V

X = Immaterial (either H or L) H → L = HIGH-to-LOW Voltage Level transition

L → H = LOW-to-HIGH Voltage Lev el transition

Order Number Package Number Package Description

DM96S02M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM96S02N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Names Description

0 Trigger Input (Active Falling Edge) I1 Schmitt Trigger Input (Active Rising-Edge) C

Direct Clear Input (Active-LOW) Q1 - 2 True Pulse Output Q

1 - 2 Complementary Pulse Output

X1, 2

External Capacitor Connection R

X1,2

External Resistor Connection

Pin Number

Operation

5(11) 4(12) 3(13)

H → L L H Trigger

HL → HH Trigger XXLReset

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DM96S02

Functional Description

The 96S02 dual retr iggerab le re settabl e m onostab le mu ltivibrator has tow DC coupled trigger inputs per function, one active LOW (I

0) and one active HIGH (I1). The I1 input utilizes an internal Schmitt trigger with hysteresis of 0.3V to provide increased noise i mmunity. The use of active HIGH and LOW inputs al lo ws wither rising or fallin g edg e trig ger ing and optional non-retriggerable operation. The inputs are DC coupled making triggering independent of input transition times. Wh en input conditions for triggering are met the Q out put goes HIGH and the exte rnal ca pacitor is rapidly discharged an d then allowe d to recharge. An input

trigger which occurs during the timing cycle will retrigger the circuit and result in Q remaining HIGH. The output pulse may be term inated (Q to the LO W sta te) a t any time by setting the Direct Clear input LOW. Retriggering may be inhibited by tying the Q

output to I0 or the Q output to I1. Differential sensi ng techniques are used to obtain excellent stability over temperature and power supply variations and a feedback Darlington capacitor discharge circuit minimizes pulse width variatio n from un it to unit. S chottky T TL output stages provide high switching speeds and out put compatibility with all TTL logic families.

Block Diagram

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DM96S02

Operation Notes

TIMING

1. An external resistor (R

) and an external capacitor (CX)

are required as shown in the Logic Diagram. The value of R

may vary from 1.0 kΩ to 2.0 MΩ (DM96S02).

2. The value of C

may vary from 0 to any necessary

value available. If however, the capacitor has significant leakage relative t o V

CC/RX

the timing equat ions

may not represent the pulse width obtained.

3. Polarized capacitors ma y be used d irectly. The (+) terminal of a polarized capacitor is connected to pin 1(15), the (−) terminal to pin 2(14) and R

. Pin 1(15) will

remain positive with respect to pin 2(14) during the timing cycle. However, during quiescent (non-triggered) conditions, pin 1(15) may go negative with r espect to pin 2(14) depending on values of R

and VCC. for val-

ues of R

≥ 10 kΩ the maximum amount of capacitor

reverse polarity, pin 1(15) negative wit h respect to pin 2(14) is 500 mV. Most tantalum electrolytic capacitors are rated for safe reve rse bias operation up to 5% of their working forward voltage ra ting; therefor e, capacitors having a rating of 10 WVdc or higher should be used with the DM96S02 when R

≥ 10 kΩ.

4. The output pulse width t

for RX ≥ 10 kΩ and CX ≥ 1000 pF is determined as follows: t

= 0.55 RXC

Where RX is in kΩ, CX is in pF, t is in ns or RTX is in kΩ, CX is in µF, t is in ms.

5. The output pulse width for R

< 10 kΩ or CX < 1000 pF

should be determined from pulse width versus C

graphs.

6. To obtain variable pulse width by remote trim ming, the following circuit is recommended:

7. Under any operating condition, C

and RX (Min) must

be kept as close to the circui t as possible to min imize stray capacitance and reduce noise pickup.

8. V

and ground wiri ng should conform to good high

frequency standards so that switching transients on V

and ground leads do not cause interaction

between one shots. Use of a 0.01 µF to 0.1µF bypass capacitor between V

and ground located near the

circuit is recommended.

TRIGGERING

1. The minimum negative pulse width into I

0 is 8.0 ns; the

minimum positive pulse width into I1 is 12 ns.

2. Input signals to the DM96S 02 exhibiting slow or noisy transitions should use the positive trigger input I1 which contains a Schmitt trigger.

3. When non-retriggerable operation is required, i.e., when input triggers are to be ignored duri ng quasi-stable state, input latching is used to inhibit retriggering.

4. An overriding active LOW l evel direct cle ar is provi ded on each multivibrator. By applying a LOW to the clear, any timing cycle can be termina ted or any new cycle inhibited until the LOW reset input is removed. Trigger inputs will not produce spikes in the output when the reset is held LOW. A LOW-to-HIGH transition o n C

will not trigger the DM96S02. If the CD input goes HIGH coincident with a trigger transition, the circuit will

respond to the trigger.

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