Fairchild Semiconductor DM74S280N, DM74S280M Datasheet

DM74S280
9-Bit Parity Generator/Checker

DM74S280 9-Bit Parity Generator/Checker

August 1986
Revised May 2000

General Description

These universal, nine-bit parity generators/ch eckers utilize
Schottky-clamped TTL hi gh -pe rfo rm anc e ci rcu itry, and fea­ture odd/even outputs to facilitate operation of either odd or
even parity applications. The word-length capability is ea s­ily expanded by cascading.

The DM74S280 can be used to upgr ade the perfor mance
of most systems utilizing the DM74180 parity generator/
checker. Although the DM74S280 is implemented without
expander inputs, the correspo nding funct ion is provi ded by
the availability of all input at pin 4, and no internal connec­tion at pin 3. This perm its the DM 74S2 80 to be substitut ed
for the 180 in existing designs to produce an identical func­tion, even if DM74S280’s are mixed with existing 180’s.

Input buffers are provided so that each input represents
only one normal 74S lo ad, and full fan-out to 10 normal
Series 74S loads is available fro m each of the outputs at
low logic levels. A fan-out to 20 normal Series 74S loads is
provided at high logic levels, to facilitate connection of
unused inputs to used inputs.

Features

■ Generates either odd or even parity for nine data lines

■ Cascadable for N-bits

■ Can be used to upgrade existing systems using MSI par-

ity circuits

■ Typical data-to-output delay—14 ns

Ordering Code:

Order Number Package Number Package Description

DM74S280M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74S280N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also availab l e in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram Function Table

Number of Inputs Outputs

(A Thru I) that are HIGH ∑ Even ∑ Odd

0, 2, 4, 6, 8 H L
1, 3, 5, 7, 9 L H

© 2000 Fairchild Semiconductor Corporation DS006483 www.fairchildsemi.com

Logic Diagram

DM74S280

Typical Applications

Three DM74S280’s can be used to implement a 25-line
parity generator/checker. This arrangement will provide
parity in typically 25 ns. (See Figure 1.)

Longer word lengths can be implemented by cascading
DM74S280’s. As shown in Figure 2, parity can be gener-
ated for word lengths up to 81 bits in typically 25 ns.

FIGURE 1. 25-Line Parity/Generator Checker

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FIGURE 2. 81-Line Parity/Generator Checker