Fairchild Semiconductor DM74S153N, DM74S153CW Datasheet
© 2000 Fairchild Semiconductor Corporation DS006469 www.fairchildsemi.com
August 1986
Revised April 2000
DM74S153 Dual 1-of-4 Line Data Selector/Multiplexer
DM74S153
Dual 1-of-4 Line Data Selector/Multiplexer
General Description
Each of these data selectors/multiplexers contains inverters and drivers to supply fully complementary, on-chip,
binary decoding data selection to the AND-OR-invert
gates. Separate strob e inputs ar e provided for each of the
two four-line sections.
Features
■ Permits multiplexing from N lines to 1 line
■ Performs parallel-to-serial conversion
■ Strobe (enable) line pr ovided for cascading (N lines to
n lines)
■ High fan-out, low-impedance, totem-pole outputs
■ Typical average propagation delay times
From data 6 ns
From strobe 9.5 ns
From select 12 ns
■ Typical power dissipation 225 mW
Ordering Code:
Connection Diagram Function Table
Select inputs A and B are common to both sections.
H = HIGH Level
L = LOW Level
X = Don’t Care
Order Number Package Number Package Description
DM74S153N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Select
Data Inputs Strobe Output
Inputs
B A C0 C1 C2 C3 G Y
XXXXXX H L
LL L X X X L L
LLH X X X L H
LH X L X X L L
LH X H X X L H
HL X X L X L L
HL X X H X L H
HH X X X L L L
HH X X X H L H
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DM74S153
Logic Diagram
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