Fairchild Semiconductor DM74ALS646WMX, DM74ALS646WM, DM74ALS646NT Datasheet

© 2000 Fairchild Semiconductor Corporation DS009172 www.fairchildsemi.com

October 1986
Revised February 2000

DM74ALS646 Octal 3-STATE Bus Transceiver and Register

DM74ALS646
Octal 3-STATE Bus Transceiver and Register

General Description

This device incorpor ates an octal bus transceiver and an
octal D-type register configured to enable multiplexed
transmission of data from bus to bus or internal reg ister to
bus.

This bus transceiver features totem-p ole 3-STATE outputs
designed specifically fo r driving highly-capacitive or rela­tively low-impedance loa ds. Th e hi gh -im ped ance state and
increased high-logic level dr ive provides this device with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without the need f or
interface or pull-up components. They are particularly
attractive for imple menting buffer registers, I/O ports, bidi­rectional bus drivers, and working registers.

The registers in the DM74 ALS646 are edge-triggered D­type flip-flops. On the positive tra nsition of the clock ( CAB
or CBA), the input bus data is stored into the appropria te
register. The CAB input controls the tr ansfer of data into
the A register and the CBA input controls the B register.

The SAB and SBA control pins are provided to select
whether real-time data or stored data is transferred. A LOW
input level selects real-time data, and a HIGH level selects

stored data. The select controls have a “make before
break” configuration to eliminate a glitch which wo uld nor­mally occur in a typical multiplexer during the transition
between store and real-time data.

The enable G

and direction control pins provide four modes
of operation: real-tim e data trans fer from bus A to B, real­time data transfer from bus B to A, real-time bus A and/or B
data transfer to in ternal storage, or intern ally stored data
transfer to bus A or B.

When the enable G

pin is LOW, the direction pin selects
which bus receives data. When the enable G pin is HIGH,
both buses become disabled yet their input function is still
enabled.

Features

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full tempera-

ture and V

CC

range

■ Advanced oxide-isolated, ion-implanted Schottky TTL
process

■ 3-STATE buffer outputs drive bus lines directly

■ Multiplexed real-time and stored data

■ Independent registers for A and B buses

Ordering Code

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Order Number Package Number Package Description

DM74ALS646WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74ALS646NT N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

www.fairchildsemi.com 2

DM74ALS646

Connection Diagram

Function Table

H = HIGH Logic Level
L = LOW Logic Level
X = Don’t Care (Either LOW or HIGH Logic Levels in cl uding transitions)
H/L = Either LOW or HIGH Logic Level excluding transitions
↑ = Positive going edge of puls e

Note 1: The data output functions ma y be enabled or disabled by various sign als at the G

and DIR inputs. Data input functions are always enabled, i.e., data

at the bus pins will be s to red on every LOW-to-HIGH transition on the clock inputs.

Logic Diagram

Inputs Data I/O (Note 1)

Operation or Function

G

DIR CAB CBA SAB SBA A1 thru A8 B1 thru B8

XX↑ X X X Input Not Specified Store A, B Unspecified
XXX↑ X X Not Specified Input Store B, A Unspecified
HX↑↑X X Input Input Store A and B Data
H X H/L H/L X X Input Input Isolation, Hold Storage

L L X X X L Output Input Real-Time B Data to a Bus
L L X H/L X H Output Input Stored B Data to a Bus
L H X X L X Input Output Real-Time A Data to B Bus
L H H/L X H X Input Output Stored A Data to B Bus