Fairchild Semiconductor DM74ALS574AWMX, DM74ALS574AWM, DM74ALS574ASJX, DM74ALS574ASJ, DM74ALS574AN Datasheet
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© 2000 Fairchild Semiconductor Corporation DS006110 www.fairchildsemi.com
September 1986
Revised February 2000
DM74ALS574A Octal D-Type Edge-Triggered Flip-Flop with 3-STATE Outputs
DM74ALS574A
Octal D-Type Edge-Triggered Flip-Flop
with 3-STATE Outputs
General Description
These 8-bit register s feature totem-pole 3- STATE outputs
designed specifically fo r driving highly-capacitive or relatively low-impedance loa ds. Th e hi gh -im ped ance state and
increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bu s-or ga nized sy stem w ith ou t n eed fo r interface or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight flip-flops of the DM74ALS574A are edge-triggered D-type flip-flops. On the positive transition of the
clock, the Q outputs will be set to the logic states that were
set up at the D inputs.
A buffered output control input ca n be used to place the
eight outputs in either a normal l ogic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-impedance state the outputs ne ither load nor dr ive the bus lines
significantly.
The output control does not affect the i nternal oper ation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are OFF.
Features
■ Switching specifications at 50 pF
■ Switching specifications guaranteed over full tempera-
ture and V
CC
range
■ Advanced oxide-isolated, ion-implanted Schottky TTL
process
■ Functionally equivalent with DM74LS374
■ Improved AC perfo rma nce ov er DM74LS374 at app roxi -
mately half the power
■ 3-STA T E buffer-type outputs drive bus lines directly
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagram
Order Number Package Number Package Description
DM74ALS574AWM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74ALS574ASJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS574AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
www.fairchildsemi.com 2
DM74ALS574A
Function Table
L = LOW State
H = HIGH State
X = Don’t Care
↑ = Positive Edge Transition
Z = High Impedance State
Q
0
= Previous Condit ion of Q
Logic Diagram
Output
Clock D
Output
Control Q
L ↑ HH
L ↑ LL
LLXQ
0
HXXZ
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DM74ALS574A
Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings ” are those val ues beyond w hich
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the condition s
for actual device operation.
Recommended Operating Conditions
Note 2: The (↑) arrow indicates t he positive edge of the Clo c k is us ed for reference.
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C.
Supply Voltage 7V
Input Voltage 7V
Voltage Applied to Disabled Output 5.5V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Typical θ
JA
N Package 56.0°C/W
M Package 75.0°C/W
Symbol Parameter Min Nom Max Units
V
CC
Supply Voltage 4.5 5 5.5 V
V
IH
HIGH Level Input Voltage 2 V
V
IL
LOW Level Input Voltage 0.8 V
I
OH
HIGH Level Output Current −2.6 mA
I
OL
LOW Level Output Current 24 mA
f
CLOCK
Clock Frequency 0 35 MHz
t
W
Width of Clock Pulse
HIGH 14 ns
LOW 14 ns
t
SU
Data Setup Time (Note 2) 15 ↑ ns
t
H
Data Hold Time (Note 2) 0 ↑ ns
T
A
Free Air Operating Temperature 0 70 °C
Symbol Parameter Conditions Min Typ Max Units
V
IK
Input Clamp Voltage VCC = 4.5V, II = −18 mA −1.2 V
V
OH
HIGH Level VCC = 4.5V
IOH = Max 2.4 3.2 V
Output Voltage VIL = VIL Max
VCC = 4.5V to 5.5V IOH = −400 µAVCC − 2V
V
OL
LOW Level VCC = 4.5V
IOL = 12 mA 0.25 0.4 V
Output Voltage VIH = 2V
IOL = 24 mA 0.35 0.5 V
I
I
Input Current at Max Input Voltage VCC = 5.5V, VIH = 7V 0.1 mA
I
IH
HIGH Level Input Current VCC = 5.5V, VIH = 2.7V 20 µA
I
IL
LOW Level Input Current VCC = 5.5V, VIL = 0.4V −0.2 mA
I
O
Output Drive Current VCC = 5.5V, VO = 2.25V −30 −112 mA
I
OZH
OFF-State Output Current VCC = 5.5V, VIH = 2V
20 µA
HIGH Level Voltage Applied VO = 2.7V
I
OZL
OFF-State Output Current d VCC = 5.5V, VIH = 2V
−20 µA
LOW Level Voltage Applied VO = 0.4V
I
CC
Supply Current VCC = 5.5V Outputs HIGH 11 18 mA
Outputs Open Outputs LOW 17 27 mA
Outputs Disabled 17 28 mA
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