Fairchild Semiconductor DM74ALS521WMX, DM74ALS521WM, DM74ALS521N Datasheet

September 1986 Revised April 2000

DM74ALS520 • DM74ALS521 8-Bit Comparator

General Description

These comparators perf orm an “equal to” comparison of two 8-bit words with provision for expansion or external enabling. The matc hing of the two 8-bit input plus a logic LOW on the EN

input produces t he output A = B on the DM74ALS520 and DM74ALS521. The DM74ALS520 and DM74ALS521 have totem pole outputs for wire AND cascading. Additionally, the DM74ALS520 is provided with B input pull up termination resistors for analog or switch data.

Features

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full tempera-

ture and V

range

■ Advanced oxide-isolated, ion-implanted Schottky TTL process

■ Functionally and pin for pin compatible with LS family counterpart

■ Improved output transient handling capability

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram Function Table

H = HIGH Logic Level L = LOW Logic Level X = Don't Care

Ordering Code Package Number Package Description

DM74ALS520WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74ALS520N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74ALS521WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide SM74ALS521N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs Output

Data A = B

LA = BL LA ≠ BH HXH

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DM74ALS520 • DM74ALS521

Logic Diagram

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