Fairchild Semiconductor DM74ALS273WMX, DM74ALS273WM, DM74ALS273SJX, DM74ALS273SJ, DM74ALS273N Datasheet

© 2000 Fairchild Semiconductor Corporation DS006216 www.fairchildsemi.com

April 1984
Revised February 2000

DM74ALS273 Octal D-Type Edge-Tr iggered Flip-Flop with Clear

DM74ALS273
Octal D-Type Edge-Triggered Flip-Flop with Clear

General Description

These monolithic, positive-edge-triggered flip-flops utilize
TTL circuitry to implement D-type flip-flop logic with a direct
clear input.

Information at the D inputs meeting the setup requirements
is transferred to th e Q outputs on the positive-goi ng edge
of the clock pulse. Clo ck triggering occurs at a pa rticular
voltage level and is not directly related to the transition time
of the positive-going pulse. When the clock input is at
either the HIGH or LOW le vel, the D input signal has no
effect at the output.

Features

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full tempera-

ture and V

CC

range

■ Buffer-type outputs and improved AC offer significant
advantage over DM74LS273.

■ Advanced oxide-isolated, ion-implanted Schottky TTL
process

■ Functionally and pin-for-pin compatible with
DM74LS273.

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram

Order Number Package Number Package Description

DM74ALS273WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74ALS273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS273MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS273N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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DM74ALS273

Function Table

(Each Flip-Flop)

L = LOW State
H = HIGH State
X = Don’t Care
↑ = Positive Edge Transition
Q0 = Previous Condit ion of Q

Logic Diagram

Inputs Output

Clear Clock D Q

LXX L
H ↑ HH
H ↑ LL
HLXQ

0

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DM74ALS273

Absolute Maximum Ratings(Note 1)

Note 1: The “Absolute M aximu m R atin gs” are t hose valu es b eyo nd w hich

the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the condition s
for actual device operation.

Recommended Operating Conditions

Note 2: The (↑) arrow indicates t he positive edge of the Clo c k is us ed for reference.

Electrical Characteristics

over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C.

Switching Characteristics

over recommended operating free air temperature range.

Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Typical θ

JA

N Package 60.0°C/W
M Package 79.0°C/W

Symbol Parameter Min Nom Max Units

V

CC

Supply Voltage 4.5 5 5.5 V

V

IH

HIGH Level Input Voltage 2 V

V

IL

LOW Level Input Voltage 0.8 V

I

OH

HIGH Level Output Current −2.6 mA

I

OL

LOW Level Output Current 24 mA

f

CLK

Clock Frequency 0 35 MHz

t

W(CLK)

Width of Clock Pulse HIGH 14 ns

LOW 14 ns

t

W

Width of Clear Pulse LOW 10 ns

t

SU

Data Setup Time (Note 2) 10↑

ns

Clear Inactive 15↑

t

H

Data Hold Time 0↑ ns

T

A

Free Air Operating Temperature 0 70 °C

Symbol Parameter Conditions Min Typ Max Units

V

IK

Input Clamp Voltage VCC = 4.5V, II = −18 mA −1.5 V

V

OH

HIGH Level VCC = 4.5V IOH = −2.6 mA 2.4 3.3 V
Output Voltage VCC = 4.5V to 5.5V IOH = −400 µAVCC − 2V

V

OL

LOW Level

VCC = 4.5V

IOL = 12 mA 0.25 0.4 V

Output Voltage IOL = 24 mA 0.35 0.5 V

I

I

Input Current @ Maximum Input Voltage VCC = 5.5V, VIH = 7V 0.1 mA

I

IH

HIGH Level Input Current VCC = 5.5V, VIH = 2.7V 20 µA

I

IL

LOW Level Input Current VCC = 5.5V, VIL = 0.4V −0.2 mA

I

O

Output Drive Current VCC = 5.5V VO = 2.25V −30 −112 mA

I

CC

Supply Current VCC = 5.5V Outputs HIGH 11 20 mA

Outputs OPEN Outputs LOW 19 29 mA

Symbol Parameter Conditions From To Min Max Units

f

MAX

Maximum Clock Frequency VCC = 4.5V to 5.5V 35 MHz

t

PHL

Propagation Delay Time RL = 500Ω

Clear Any Q 4 18 ns

HIGH-to-LOW Level Output CL = 50 pF

t

PLH

Propagation Delay Time

Clock Any Q 2 12 ns

LOW-to-HIGH Level Output

t

PHL

Propagation Delay Time

Clock Any Q 3 15 ns

HIGH-to-LOW Level Output