Fairchild Semiconductor DM74ALS253N, DM74ALS253MX, DM74ALS253M Datasheet

April 1984 Revised February 2000

DM74ALS253 3-STATE Dual 1-of-4 Line Data Selector/Multiplexer

General Description

This Data Selector/Multi plexer contain s full on-chip decoding to select one-of-four data sources as a result of a unique two-bit binary code at the Select Inputs. Each of the two Data Selector/Multipl e xer c irc uits have the i r own sep arate Data and Output Contr ol inputs an d a non- inver ting 3STATE output buffer. The Output Contro l inputs, when at the high level, place the correspondi ng output in the high impedance OFF-State. In order to prevent bus access conflicts, output disable times a re shorter than output enabl e times. The Select i npu t b uffers inco rp ora te internal overlap features to ensure tha t select inpu t changes do not cause invalid output transients.

Features

■ Advanced oxide-isolated, ion-implanted Schottky TTL process

■ Switching performan ce is gu aranteed over full tempe rature and V

supply range

■ Pin and functional compatible with LS family counterpart

■ Improved output transient handling capability

■ Output control circuit ry incorporates po wer-up 3-STATE

feature

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram Function Table

Address inputs A an d B are common to both sec t ions H = HIGH Level L = LOW Level X = Don't Care Z = High Impedance

Order Number Package Number Package Description

DM74ALS253M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS253N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Select Data Inputs Output Output Inputs Control

BAC0C1C2C3 G

XXXXXX H Z LL L X X X L L LLH X X X L H LH X L X X L L LH X H X X L H HL X X L X L L HL X X H X L H HHXXXL L L HHXXXH L H

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DM74ALS253

Logic Diagram

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