Fairchild Semiconductor DM74ALS244AWMX, DM74ALS244AWM, DM74ALS244ASJX, DM74ALS244ASJ, DM74ALS244AN Datasheet

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© 2000 Fairchild Semiconductor Corporation DS006212 www.fairchildsemi.com
September 1986 Revised February 2000
DM74ALS244A Octal 3-STATE Bus Driver
DM74ALS244A Octal 3-STATE Bus Driver
General Description
This octal 3-STATE bus driver is designed to provide the designer with flexibility in implementing a bus interface with memory, microprocessor, or communication systems. This device offers 64-extended temperature Grade product guaranteeing perfo rmance from 40°C to +85°C. T he out­put 3-STATE gating control i s organized into two sep arate groups of four buffers, and both control inpu ts enable the respective outputs when s et logic LOW. The 3-STATE cir­cuitry contains a feature that maintains the buffer outputs in 3-STATE (high impedance state) during power supply ramp-up or ramp-down. This eliminates bus glitching prob­lems that arise during power-up and power-down.
Features
Advanced low power oxide-isolated ion-implanted Schottky TTL process
Functional and pin compatible with the 74LS counterpart
Improved switching per formance with less power dissi-
pation compared with the 74LS counte rpa rt
Switching response specified into 500 and 50 pF load
Switching response specific ations guaranteed over full
temperat ure and V
CC
supply range
PNP input design reduces input loading
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagram
Function Table
H = HIGH Level Logic State L = LOW Level Logic State X = Don't Care (Either LOW or HIGH Level Logic State) Z = High Impedance (OFF) State
Logic Diagram
Order Number Package Number Package Description
DM74ALS244AWM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74ALS244ASJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74ALS244AMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide DM74ALS244AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Input Output
G
AY
LL L LH H
HX Z
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DM74ALS244A
Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratin gs” are those v alues beyon d which
the safety of the dev ice cannot be guaranteed. T he device sh ould not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommend ed O peratin g Cond itions” t able w ill defin e the co ndition s for actual device operation.
Recommended Operating Conditions
Electrical Characteristics
over recommended operating free air temperature (unless otherwise specified)
Switching Characteristics
over recommended operating free-air temperature range
Supply Voltage, V
CC
7V Input Voltage 7V Voltage Applied to Disabled Output 5.5V Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range 65°C to +150°C Typical θ
JA
N Package 60.5°C/W M Package 79.8°C/W
Symbol Parameter Min Typ Max Units
V
CC
Supply Voltage 4.5 5 5.5 V
V
IH
HIGH Level Input Voltage 2 V
V
IL
LOW Level Input Voltage 0.8 V
I
OH
HIGH Level Output Current −15 mA
I
OL
LOW Level Output Current 24 mA
T
A
Operating Free-Air Temperature 0 70 °C
Symbol Parameter Conditions Min Typ Max Units
V
IK
Input Clamp Voltage VCC = 4.5V, II = 18 mA 1.5 V
V
OH
HIGH Level VCC = 4.5V to 5.5V IOH = 0.4 mA VCC−2V Output Voltage VCC = 4.5V IOH = 3 mA 2.4 V
IOH = Max 2 V
V
OL
LOW Level VCC = 4.5V
0.35 0.5 V
Output Voltage IOL = 24 mA
I
I
Input Current at Maximum Input Voltage VCC = 5.5V, VI = 7V 0.1 mA
I
IH
HIGH Level Input Current VCC = 5.5V, VI = 2.7V 20 µA
I
IL
LOW Level Input Current VCC = 5.5V, VIL = 0.4V 0.1 mA
I
O
Output Drive Current VCC = 5.5V, VO = 2.25V 30 112 mA
I
OZH
HIGH Level 3-STATE Output Current VCC = 5.5V, VO = 2.7V 20 µA
I
OZL
LOW Level 3-STATE Output Current VCC = 5.5V, VO = 0.4V 20 µA
I
CC
Supply Current VCC = 5.5V
915mA
Outputs HIGH Outputs LOW 15 24 mA Outputs 3-STATE 17 27 mA
Symbol Parameter Conditions
From
(Input)To(Output)
Min Max Units
t
PLH
Propagation Delay Time VCC = 4.5V to 5.5V,
A Y 3 10 ns
LOW-to-HIGH Level Output CL = 50 pF,
t
PHL
Propagation Delay Time R1 = 500Ω,
A Y 3 10 ns
HIGH-to-LOW Level Output R2 = 500Ω,
t
PZH
Output Enable Time to HIGH Level Output TA = Min to Max G Y 3 20 ns
t
PZL
Output Enable Time to LOW Level Output G Y 3 20 ns
t
PHZ
Output Disable Time from HIGH Level Output G Y 2 10 ns
t
PLZ
Output Disable Time from LOW Level Output G Y 1 13 ns
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