Fairchild Semiconductor DM74ALS162BN, DM74ALS162BMX, DM74ALS162BM Datasheet

April 1984 Revised February 2000

DM74ALS161B • DM74ALS162B • DM74ALS163B Synchronous Four-Bit Counter

General Description

These synchronous presettabl e counters feature an internal carry look ahead for app lication in hig h speed co unting designs. The DM74ALS162 B is a four-bit decade count er, while the DM74ALS161 B and DM74ALS163B are fo ur-bit binary counters. The DM74ALS161B clears asynchronously, while the DM74ALS162B and DM74ALS163B cl ear synchronously. The carry output is decoded to prevent spikes during normal counting mode of operation. Synchronous operation is provid ed by having all flip- flops clocked simultaneously so that outputs change coincident with each other when so in structed by count ena ble inputs a nd internal gating. This mode of op eration elim inates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positivegoing) edge of the clock input waveform.

These counters are fully programmable, that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load in pu t disab les th e co unter and causes the outputs to agree with se t up data aft er the next clock pulse regard less of the levels of enable input. LOW-to-HIGH transitions at the load input are perfectly acceptable regardless of the log ic levels on the clock or enable inputs.

The DM74ALS161B clear fun ction is asynchron ous. A low level at the clear input sets all four of the flip-flop outputs LOW regardless of the levels of clock, load or enable inputs. These two counters are provided with a clear on power-up feature. The DM74ALS162B and DM74ALS163B clear function is synchronous; and a low level at the clear input sets all four of the flip-flop outputs LOW after the next clock pulse, regardless o f the levels of enable in puts. This synchronous clear allows the count length to be modified easily, as decoding the maximum count desired can be accomplished with one e xterna l NAND gate. The gate ou tput is connected to the clear i nput to synchronously clear the counter to all low outputs. LOW-to-HIGH transitions at the clear input of the DM74 ALS162B and DM74ALS1 63B are also permissible regardl e ss of th e levels o f logic on t he clock, enable or load inputs.

The carry look ahead circuitry provides for cascading counters for n bit synchronous application without additional gating. Instrumental in accomplishing this function are two count enable inputs (P and T) and a ripple carry output. Both count enable inputs must be HIGH to count. The T input is fed forward to ena ble th e ripp l e carry output. The ripple carry output thus enabled will produce a high level output pulse w ith a duration approxim ately equal to the high level portion of QA output. This high level overflow ripple carry pulse can be used to enable successive cascaded stages. HIGH-to-LOW level transitions at the enable P or T inputs of the DM74ALS161B through DM74ALS163B may occur re gardless of the logi c level on the clock.

The DM74ALS161B through DM74ALS163B feature a fully independent clock cir cuit. changes made to control inputs (enable P or T, or load) that will modify the operating mode will have no effect until clocking occurs. The function of the counter (whether enabl ed, disabled, loading or counting) will be dictated solely by the conditions meeting the stable set-up and hold times.

Features

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full tempera-

ture and V

range

■ Advanced oxide-isolated, ion-implanted Schottky TTL process

■ Functionally and pin-for-pin compatible with Schottky and low power Schottky TTL counterpart

■ Improved AC performance over Schottky and low power Schottky counterparts

■ Synchronously programmable

■ Internal look ahead for fast counting

■ Carry out put for n-bit cascading

■ Synchronous counting

■ Load control line

■ ESD inputs

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Order Number Package Number Package Description

DM74ALS161BM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS161BN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74ALS162BM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS162BN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74ALS163BM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS163BN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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DM74ALS161B • DM74ALS162B • DM74ALS163B

Connection Diagram Mode Select Table

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

Logic Diagrams

DM74ALS161B

Clear Load Enable T Enable P

Action on the Rising

Clock Edge (



)

L X X X Reset (Clear) H L X X Load (P

→ Qn) H H H H Count (Increment) H H L X No Change (Hold) H H X L No Change (Hold)

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DM74ALS161B • DM74ALS162B • DM74ALS163B

Logic Diagrams (Continued)

DM74ALS162B

DM74ALS163B

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