Fairchild Semiconductor DM74ALS153SJ, DM74ALS153N, DM74ALS153MX, DM74ALS153M Datasheet
© 2000 Fairchild Semiconductor Corporation DS006204 www.fairchildsemi.com
April 1984
Revised February 2000
DM74ALS153 Dual 1-of-4 Line Data Selector/Multiplexer
DM74ALS153
Dual 1-of-4 Line Data Selector/Multiplexer
General Description
This Data Selector/Multi plexer contain s full on-chip decoding to select one-of-four data sources as a result of a
unique two-bit binary code at the Select inputs. Each of the
two Data Selector/Multipl e xer c irc uits have the i r own sep arate Data and Strobe inputs and a non-inverting output
buffer. The Select inputs A and B are common to both sections. The Strobe inputs, whe n at the HIGH level, disable
their associated data inputs and force the corresponding
output to the LOW st ate. The Select inp ut buffers inco rporate internal overlap featu res to ensure that select input
changes do not cause invalid output transients.
Features
■ Advanced oxide-isolated, ion-implanted Schottky TTL
process
■ Switching performan ce is gu aranteed over full tempe rature and V
CC
supply range
■ Pin and functional compatible with LS family counterpart
■ Improved output transient handling capability
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagram Function Table
Select inputs A and B are common to both sections.
H = HIGH Level
L = LOW Level
X = Don't Care
Order Number Package Number Package Description
DM74ALS153M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS153SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS153N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Select
Data Inputs Strobe Output
Inputs
B A C0 C1 C2 C3 G Y
XXXXXX H L
LLLXXX L L
LLHXXX L H
LHXLXX L L
LHXHXX L H
HLXXLX L L
HLXXHX L H
HHXXXL L L
HHXXXH L H
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DM74ALS153
Logic Diagram
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