Fairchild Semiconductor DM74ALS137N, DM74ALS137MX, DM74ALS137M Datasheet

February 1991 Revised February 2000

DM74ALS137 3 to 8 Line Decoder/Demultiplexer with Address Latches

General Description

The ALS137 is a three line to eigh t line decoder/demultiplexer with latches on the thr ee address i nputs. When the latch-enable input (GL

) is LOW, the ALS137 acts as a

decoder/demultiplexer . When GL

goes from LOW-to-HIGH, the address present at the select inputs (A, B, an d C) is stored in the latches. Furth er a ddr ess ch ang es a re ign or ed as long as GL

remains HIGH. The output enable controls,

G1 and G2

, control the state o f the outputs independently of the select or latch-enable inputs. A ll of the outputs are HIGH unless G1 is HIG H and G2

is LOW. The ALS137 is ideally suited for implementing glitch-free decoders in strobed (stored-address) ap plications in bus-oriented systems.

Features

■ Combines decoder and 3-bit address latch

■ Incorporates 3 enable inputs to simplify cascading

■ Low power dissipation: 28 mW typ

■ Switching specifications guaranteed over full tempera-

ture and V

range

■ Advanced oxide-isolated, ion-implanted Schottky TTL process

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram Function Table

L = LOW State H = HIGH State X = Don't Care

Order Number Package Number Package Description

DM74ALS137M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS137N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs

Outputs

Enable Select

G1 G2 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

XX HX XXHHHHHHHH X L XX XXHHHHHHHH L HL L L L LHHHHHHH L HL L L HHLHHHHHH L HL L HL HHLHHHHH L HL L HHHHHLHHHH L HL H L LHHHHLHHH LHLHLHHHHHHLHH L HL HH LHHHHHHLH L HL HH HHHHHHHHL H H L X X X Output corresponding to stored

address, L; all others, H

www.fairchildsemi.com 2

DM74ALS137

Logic Diagram

+ 4 hidden pages