Fairchild Semiconductor CD4011BCM, CD4011BCCW, CD4011BCSJ, CD4011BCN, CD4011BCMX Datasheet
October 1987
Revised January 1999
CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate • Quad 2-Input NAND Buffered B Series Gate
© 1999 Fairchild Semiconductor Corporation DS005939.prf www.fairchildsemi.com
CD4001BC/CD4011BC
Quad 2-Input NOR Buffered B Series Gate •
Quad 2-Input NAND Buffered B Series Gate
General Description
The CD4001BC and CD4011BC quad gates are monolithic
complementary MOS (CMOS) integrated circuits constructed with N- and P-ch annel enhancement mode transistors. They have equal source and sink current
capabilities and conform to standard B series output drive.
The devices also have buffered outputs which improve
transfer characteristics by providing very high gain.
All inputs are protected against static discharge with diodes
to V
DD
and VSS.
Features
■ Low power TTL:
Fan out of 2 driving 74L compatibility: or 1 driving 74LS
■ 5V–10V–15V parametric ratings
■ Symmetrical output characteristics
■ Maximum input leakage 1 µA at 15V over full
temperat ure range
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to t he ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC and SOP
CD4001BC
Top View
Pin Assignments for DIP and SOIC
CD4011BC
Top Vi ew
Order Number Package Number Package Description
CD4001BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
CD4001BCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4001BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
CD4011BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
CD4011BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
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CD4001BC/CD4011BC
Schematic Diagrams
CD4001BC
1
/4 of device shown
J = A
+ B
Logical “1” = HIGH
Logical “0” = LOW
All inputs protected by st andard
CMOS protection c irc uit .
CD4011BC
1
/4 of device shown
J = A • B
Logical “1” = HIGH
Logical “0” = LOW
All inputs protected by st andard
CMOS protection c irc uit .
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CD4001BC/CD4011BC
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: “Absolute Maximum Rat ings” are tho se values beyond which the
safety of the device cannot be guaranteed. E x c ept for “ Operating Temperature Range” they are not mea nt to imply that the devices sh ould be operated at these limits. The Electrical Charac t eristics tables provide c onditions
for actual device operation.
Note 2: All voltages measured with res pect t o V
SS
unless otherwise s peci-
fied.
DC Electrical Characteristics (Note 2)
Note 3: IOL and IOH are tested one output at a ti m e.
AC Electrical Characteristics (Note 4)
CD4001BC: TA = 25°C, Input tr; tf = 20 ns. CL = 50 pF, RL = 200k. Typical temperature coefficient is 0.3%/°C.
Note 4: AC Parameters are guaranteed by DC correlated testing.
Voltage at any Pin −0.5V to VDD +0.5V
Power Dissipation (P
D
)
Dual-In-Line 700 mW
Small Outline 500 mW
V
DD
Range −0.5 VDC to +18 V
DC
Storage Temperature (TS) −65°C to +150°C
Lead Temperature (T
L
)
(Soldering, 10 seconds ) 260°C
Operating Range (V
DD
)3 V
DC
to 15 V
DC
Operating Temperature Range
CD4001BC, CD4011BC −40°C to +85°C
Symbol Parameter Conditions
−40°C +25°C +85°C
Units
Min Max Min Typ Max Min Max
I
DD
Quiescent Device VDD = 5V, VIN = VDD or V
SS
1 0.004 1 7.5 µA
Current VDD = 10V, VIN = VDD or V
SS
20.0052 15µA
VDD = 15V, VIN = VDD or V
SS
40.0064 30µA
V
OL
LOW Level VDD = 5V 0.05 0 0.05 0.05 V
Output Voltage VDD = 10V |IO| < 1 µA 0.05 0 0.05 0.05 V
VDD = 15V 0.05 0 0.05 0.05 V
V
OH
HIGH Level VDD = 5V 4.95 4.95 5 4.95 V
Output Voltage VDD = 10V |IO| < 1 µA 9.95 9.95 10 9.95 V
VDD = 15V 14.95 14.95 15 14.95 V
V
IL
LOW Level VDD = 5V, VO = 4.5V 1.5 2 1.5 1.5 V
Input Voltage VDD = 10V, VO = 9.0V 3.0 4 3.0 3.0 V
VDD = 15V, VO = 13.5V 4.0 6 4.0 4.0 V
V
IH
HIGH Level VDD = 5V, VO = 0.5V 3.5 3.5 3 3.5 V
Input Voltage VDD = 10V, VO = 1.0V 7.0 7.0 6 7.0 V
VDD = 15V, VO = 1.5V 11.0 11.0 9 11.0 V
I
OL
LOW Level Output VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 m A
Current VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA
(Note 3) VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA
I
OH
HIGH Level Output VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA
Current VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.9 mA
(Note 3) VDD = 15V, VO = 13.5V −3.6 −3.0 −8.8 −2.4 mA
I
IN
Input Current VDD = 15V, VIN = 0V −0.30 −10−5−0.30 −1.0 µA
VDD = 15V, VIN = 15V 0.30 10−50.30 1.0 µA
Symbol Parameter Conditions Typ Max Units
t
PHL
Propagation Delay Time, VDD = 5V 120 250 ns
HIGH-to-LOW Level VDD = 10V 50 100 ns
VDD = 15V 35 70 ns
t
PLH
Propagation Delay Time, VDD = 5V 110 250 ns
LOW-to-HIGH Level VDD = 10V 50 100 ns
VDD = 15V 35 70 ns
t
THL
, t
TLH
Transition Time VDD = 5V 90 200 ns
VDD = 10V 50 100 ns
VDD = 15V 40 80 ns
C
IN
Average Input Capacitance Any Input 5 7.5 pF
C
PD
Power Dissipation Capacity Any Gate 14 pF
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