Fairchild Semiconductor 74F138SJX, 74F138SJ, 74F138SCX, 74F138SC, 74F138PC Datasheet

© 1999 Fairchild Semiconductor Corporation DS009478 www.fairchildsemi.com

April 1988
Revised July 1999

74F138 1-of-8 Decoder/Demultiplexer

74F138
1-of-8 Decoder/Demultiplex er

General Description

The F138 is a high-speed 1-of-8 decoder/demultiplexer.
This device is ideally suited for high-speed bipolar memory
chip select address decoding. The multiple input ena bles
allow parallel expans ion to a 1-of-24 dec oder using just
three F138 devices or a 1-of-32 dec oder using fo ur F138
devices and one inverter.

Features

■ Demultiplexing capability

■ Multiple input enable for easy expansion

■ Active LOW mutually exclusive outputs

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F138SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F138PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F138

Unit Loading/Fan Out

Tr uth Table

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

Functional Description

The F138 high-speed 1-of-8 decoder/demultiplexer
accepts three binary weighted inputs (A

0, A1, A2

) and,

when enabled, provides eight mutually exclusive active
LOW outputs (O

0–O7

). The F138 features three Enable

inputs, two active LOW (E

1, E2

) and one active HIGH (E3).

All outputs will be HIGH unless E

1

and E2 are LOW and E

3

is HIGH. This multiple enable functi on allows easy parallel

expansion of the de vice to a 1-of-32 (5 lines to 32 lines)
decoder with just f our F138 dev ices and one i nverte r (S ee
Figure 1). The F138 can be used as an 8-outpu t demulti­plexer by using one of the active LOW Enable inputs as the
data input and the other Enable inputs as strobes. The
Enable inputs which are not used must be permanently tied
to their appropriate active HIGH or active LOW state.

FIGURE 1. Expans ion to 1-of-32 Decoding

Pin Names Description

U.L. Input I

IH/IIL

HIGH/LOW Output IOH/I

OL

A0–A

2

Address Inputs 1.0/1.0 20 µA/−0.6 mA

E

1

, E

2

Enable Inputs (Active LOW) 1.0/1.0 20 µA/−0.6 mA

E

3

Enable Input (Active HIGH) 1.0/1.0 20 µA/−0.6 mA

O

0–O7

Outputs (Active LOW) 50/33.3 −1 mA/20 mA

Inputs Outputs

E

1

E2E3A0A1A2O0O1O2 O3O4O5O6O

7

HXXXXXHHH HHHHH
XHXXXXHHHHHHHH
XXLXXXHH HHHHHH

LLHLLLLHHHHHHH
LLHHLLHL HHHHHH
LLHLHLHH L HHHHH
LLHHHLHH HLHHHH
LLHLLHHH H HLHHH
LLHHLHHH HHHLHH
LLHLHHHH HHHHLH
LLHHHHHH H HHHHL