Fairchild Semiconductor 74ACT399SJX, 74ACT399SJ, 74ACT399SCX, 74ACT399SC, 74ACT399PC Datasheet

© 1999 Fairchild Semiconductor Corporation DS009789 www.fairchildsemi.com

June 1988
Revised November 1999

74AC399 • 74ACT399 Quad 2-Port Register

74AC399 • 74ACT399
Quad 2-Port Register

General Description

The AC/ACT399 is th e logi cal equ ivale nt of a quad 2 -input
multiplexer feeding into four edge-triggered flip-flops. A
common Select input determines which of the two 4-bit
words is accepted. The selected data enters the flip-flop on
the rising edge of the clock.

Features

■ ICC reduced by 50%

■ Select inputs from two data sources

■ Fully positive edge-triggered operation

■ Outputs source/sink 24 mA

■ AC/ACT399 has TTL-compat ibl e input s

Ordering Code:

Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Pin Descriptions

FACT is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

74AC399SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74AC399PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT399SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74ACT399SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT399PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Names Description

S Common Select Input
CP Clock Pulse Input
I

0a–I0d

Data Inputs from Source 0

I

1a–I1d

Data Inputs from Source 1

Q

a–Qd

Register True Outputs

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74AC399 • 74ACT399

Functional Description

The AC/ACT399 is a high-speed quad 2-port registe r. It
selects four bits of d ata from eith er of two sour ces (Ports)
under control of a co mmon Select inpu t (S). The selecte d
data is transferred to a 4-bit output register synchronous
with the LOW-to-HIGH tr ansition of the Clock inpu t (CP).
The 4-bit D-type output register is fully edge-triggered. The
Data inputs (I

0x

, I1x) and Select input ( S) must be stable

only a setup time prior to and hold time after the LOW-to­HIGH transition of the Clock input for predictable operation.

Function Table

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial



= LOW-to-HIGH Clock Transition

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Inputs Outputs

SI

0

I

1

CP Q Q

LL X



LH

LH X



HL

HX L



LH

HX H



HL

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74AC399 • 74ACT399

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute max imum ratings are those values beyond w hich damage

to the device may occu r. The databook spe cificatio ns shou ld be met, wit h­out exception, to ensure that the system de sign is relia ble over its p ower
supply, temperature, and outp ut/input loa ding variab les. National d oes not
recommend operation of FACT circuits outside databook specif ic at ions.

DC Electrical Characteristics for AC

Note 2: All outputs loaded; thres holds on input associate d w it h output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: I

IN

and ICC @ 3.0V are guaranteed to be less than or equa l t o th e respective limit @ 5.5V VCC.

Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I

IK

)

V

I

= −0.5V −20 mA

V

I

= VCC + 0.5V +20 mA

DC Input Voltage (V

I

) −0.5V to VCC + 0.5V

DC Output Diode Current (I

OK

)

V

O

= −0.5V −20 mA

V

O

= VCC + 0.5V +20 mA

DC Output Voltage (V

O

) −0.5V to VCC + 0.5V

DC Output Sourceor

Sink Current (I

O

) ±50 mA

DC V

CC

or Ground Current

per Output Pin (I

CC

or I

GND

) ±50 mA

Storage Temperature (T

STG

) −65°C to +150°C

Junction Temperature (T

J

)

PDIP +140°C

Supply Voltage (V

CC

)
AC 2.0V to 6.0V
ACT 4.5V to 5.5V

Input Voltage (V

I

)0V to V

CC

Output Voltage (VO)0V to V

CC

Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t)

AC Devices
V

IN

from 30% to 70% of V

CC

VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate (∆V/∆t)

ACT Devices
V

IN

from 0.8V to 2.0V

V

CC

@ 4.5V, 5.5V 125 mV/ns

Symbol Parameter

V

CC

TA = +25°CTA = −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

V

IH

Minimum HIGH Level 3.0 1.5 2.1 2.1 V

OUT

= 0.1V

Input Voltage 4.5 2.25 3.15 3.15 V or VCC −0.1V

5.5 2.75 3.85 3.85

V

IL

Maximum LOW Level 3.0 1.5 0.9 0.9 V

OUT

= 0.1V

Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V

5.5 2.75 1.65 1.65

V

OH

Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V I

OUT

= −50 µA

5.55.495.4 5.4
VIN = VIL or V

IH

3.0 2.56 2.46 IOH= −12 mA

4.5 3.86 3.76 V I

OH

= −24 mA

5.5 4.86 4.76 I

OH

= −24 mA (Note 2)

V

OL

Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V I

OUT

= 50 µA

5.5 0.001 0.1 0.1
VIN = VIL or V

IH

3.0 0.36 0.44 IOL= 12 mA

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 2)

I

IN

Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µAVI = VCC, GND

I

OZ

Maximum 3-STATE VI (OE) = VIL, V

IH

Current 5.5 ±0.5 ±5.0 µAVI = VCC, GND

VO = VCC, GND

I

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

I

OHD

Output Current (Note 3) 5.5 −75 mA V

OHD

= 3.85V Min

I

CC

Maximum Quiescent Supply Current 5.5 4.0 40.0 µAVIN = VCC or GND