Fairchild Semiconductor 74ACT245SJX, 74ACT245SC, 74ACT245PC, 74ACT245MTCX, 74ACT245MTC Datasheet

© 1999 Fairchild Semiconductor Corporation DS009944 www.fairchildsemi.com

November 1988
Revised November 1999

74AC245 • 74ACT245 Octal Bidirectional Transceiver with 3-STATE

74AC245 • 74ACT245
Octal Bidirectional Transceiver with 3-STATE

Inputs/Outputs

General Description

The AC/ACT245 contai ns eight non-inverting bidirectional
buffers with 3-STATE outputs and is intended for bu s-ori­ented applications. Current sinking capability is 24 mA at
both the A and B p orts. The Transmit/Receive (T/R

) input
determines the directi on of data flow through the b idirec­tional transceiver. Transmit (active-HIGH) enables data
from A ports to B ports; Receive (active-LOW) enables
data from B ports to A ports. The Output Enable input,
when HIGH, disables both A and B ports by placing them in
a HIGH Z condition.

Features

■ ICC and IOZ reduced by 5 0%

■ Noninverting buffers

■ Bidirectional data path

■ A and B outputs source/sink 24 mA

■ ACT245 has TTL-compatible inputs

Ordering Code:

Device also available in Tape and Reel. Specify by appending su ffix le tter “X” to the ordering code.

FACT is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

74AC245SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74AC245SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC245MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC245PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT245SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACT245SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT245MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ACT245MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT245PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

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74AC245 • 74ACT245

Connection Diagram

Logic Symbols

IEEE/IEC

Pin Descriptions

Tr uth Table

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

Pin

Description

Names

OE

Output Enable Input

T/R

Transmit/Receive Input

A

0–A7

Side A 3-STATE Inputs or 3-STATE Outputs

B

0–B7

Side B 3-STATE Inputs or 3-STATE Outputs

Inputs

Outputs

OE

T/R

L L Bus B Data to Bus A
L H Bus A Data to Bus B
HXHIGH-Z State

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74AC245 • 74ACT245

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute max imum ratings are those values beyond w hich damage

to the device may occu r. The databook spe cificatio ns shou ld be met, wit h­out exception, to ensure that the system de sign is relia ble over its p ower
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specif ic at ions.

DC Electrical Characteristics for AC

Note 2: All outputs loaded; thres holds on input associate d w it h output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: I

IN

and ICC @ 3.0V are guaranteed to be less than or equa l t o th e respective limit @ 5.5V VCC.

Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I

IK

)

V

I

= −0.5V −20 mA

V

I

= VCC + 0.5V +20 mA

DC Input Voltage (V

I

) −0.5V to VCC + 0.5V

DC Output Diode Current (I

OK

)

V

O

= −0.5V −20 mA

V

O

= VCC + 0.5V +20 mA

DC Output Voltage (V

O

) −0.5V to VCC + 0.5V

DC Output Source

or Sink Current (I

O

) ±50 mA

DC V

CC

or Ground Current

per Output Pin (I

CC

or I

GND

) ±50 mA

Storage Temperature (T

STG

) −65°C to +150°C

Junction Temperature (T

J

)

PDIP 140°C

Supply Voltage (V

CC

)
AC 2.0V to 6.0V
ACT 4.5V to 5.5V

Input Voltage (V

I

)0V to V

CC

Output Voltage (VO)0V to V

CC

Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t)

AC Devices
V

IN

from 30% to 70% of V

CC

VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate (∆V/∆t)

ACT Devices
V

IN

from 0.8V to 2.0V

V

CC

@ 4.5V, 5.5V 125 mV/ns

Symbol Parameter

V

CC

(V)

T

A

= +25°CTA = −40°C to +85°C

Units Conditions

Typ Guaranteed Limits

V

IH

Minimum HIGH Level 3.0 1.5 2.1 2.1 V

OUT

= 0.1V

Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V

5.5 2.75 3.85 3.85

V

IL

Maximum LOW Level 3.0 1.5 0.9 0.9 V

OUT

= 0.1V

Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V

5.5 2.75 1.65 1.65

V

OH

Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V I

OUT

= −50 µA

5.5 5.49 5.4 5.4
VIN = VIL or V

IH

3.0 2.56 2.46 IOH = −12 mA

4.5 3.86 3.76 V I

OH

= −24 mA

5.5 4.86 4.76 I

OH

= −24 mA (Note 2)

V

OL

Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V I

OUT

= 50 µA

5.5 0.001 0.1 0.1
VIN = VIL or V

IH

3.0 0.36 0.44 IOL = 12 mA

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 2)

I

IN (Note 4)

Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAVI = VCC, GND

I

OLD

Dynamic Output 5.5 75 mA V

OLD

= 1.65V Max

I

OHD

Current Minimum (Note 3) 5.5 −75 mA V

OHD

= 3.85V Min
ICC (Note 4) Maximum Quiescent Supply Current 5.5 4.0 40.0 µAVIN = VCC or GND
I

OZT

Maximum I/O VI (OE) = VIL, V

IH

Leakage Current 5.5 ± 0.3 ± 3.0 µAVI = VCC, GND

VO = VCC, GND