Fairchild Semiconductor 74AC253CW, 74AC253SJX, 74AC253SJ, 74AC253SCX, 74AC253SC Datasheet
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© 1999 Fairchild Semiconductor Corporation DS009946 www.fairchildsemi.com
November 1988
Revised November 1999
74AC253 • 74ACT253 Dual 4-Input Multiplexer with 3-STATE Outputs
74AC253 • 74ACT253
Dual 4-Input Multiplexer with 3-STATE Outputs
General Description
The AC/ACT253 is a dual 4-input multiplexer with 3-STATE
outputs. It can select two bits of data fr om four sources
using common select inputs. The o utputs may be in dividually switched to a high impedance state with a HIGH on the
respective Output Enable (OE
) inputs, allowing the o utp uts
to interface directly with bus oriented systems.
Features
■ ICC and IOZ reduced by 5 0%
■ Multifunction capability
■ Noninverting 3-STATE outputs
■ Outputs source/sink 24 mA
■ ACT253 has TTL-compatible inputs
Ordering Code:
Device also available Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Diagrams
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC253SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74AC253SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC253PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT253SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74ACT253SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT253PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
I
0a–I3a
Side A Data Inputs
I
0b–I3b
Side B Data Inputs
S
0
, S
1
Common Select Inputs
OE
a
Side A Output Enable Input
OE
b
Side B Output Enable Input
Z
a
, Z
b
3-STATE Outputs
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74AC253 • 74ACT253
Functional Description
The AC/ACT253 contains two identical 4-input multiplexers
with 3-STATE outputs. They select two bits from four
sources selected by common Select inputs (S
0
, S1). The 4-
input multiplexers have individual Output Enable (OE
a
,
OE
b
) inputs which, wh en HIGH , fo rce the ou tpu ts to a high
impedance (High Z) st ate. This device is the logi c implementation of a 2-pole, 4-posit ion sw itch, wh ere the positio n
of the switch is determined by the logi c levels supplied to
the two select inpu ts. The logic equations for the outputs
are shown:
Z
a
= OEa • (I0a • S1 • S0 + I1a • S1 • S0 +
I
2a
• S1 • S0 + I3a • S1 • S0)
Z
b
= OEb • (I0b • S1 • S0 + I1b • S1 • S0 +
I
2b
• S1 • S0 + I3b • S1 • S0)
If the outputs of 3- STATE devices are tied together, all but
one device must be in the high impedance state to avoid
high currents that would exceed the maximum ratings.
Designers should ensure that Outp ut Enable signals to 3STATE devices whose outputs are tied together are
designed so that there is no overlap.
Tr uth Table
Address Inputs S0 and S1 are common to both sections.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Select
Data Inputs
Output
Outputs
Inputs Enable
S
0
S1I0I1I2I3OE Z
X X XXXX H Z
L L LXXX L L
L L HXXX L H
HLXLXXL L
HLXHXXL H
LHXXLXL L
LHXXHXL H
HHXXXLL L
HHXXXHL H
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74AC253 • 74ACT253
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute max imum ratings are those values beyond w hich damage
to the device may occu r. The databook spe cificatio ns shou ld be met, wit hout exception, to ensure that the system de sign is relia ble over its p ower
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specif ic at ions.
DC Electrical Characteristics for AC
Note 2: All outputs loaded; thres holds on input associate d w it h output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: I
IN
and ICC @ 3.0V are guaranteed to be less than or equa l t o th e respective limit @ 5.5V VCC.
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= −0.5V −20 mA
V
I
= VCC + 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC + 0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V −20 mA
V
O
= VCC + 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC + 0.5V
DC Output Source
or Sink Current (I
O
) ± 50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ± 50 mA
Storage Temperature (T
STG
) −65°C to +150°C
Junction Temperature (T
J
)
PDIP 140°C
Supply Voltage (V
CC
)
AC 2.0V to 6.0V
ACT 4.5V to 5.5V
Input Voltage (V
I
)0V to V
CC
Output Voltage (VO)0V to V
CC
Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t)
AC Devices
V
IN
from 30% to 70% of V
CC
VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V 125 mV/ns
Symbol Parameter
V
CC
(V)
T
A
= +25°CTA = −40°C to +85°C
Units Conditions
Typ Guaranteed Limits
V
IH
Minimum HIGH Level 3.0 1.5 2.1 2.1 V
OUT
= 0.1V
Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V
5.5 2.75 3.85 3.85
V
IL
Maximum LOW Level 3.0 1.5 0.9 0.9 V
OUT
= 0.1V
Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V
5.5 2.75 1.65 1.65
V
OH
Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V I
OUT
= −50 µA
5.5 5.49 5.4 5.4
VIN = VIL or V
IH
3.0 2.56 2.46 IOH = −12 mA
4.5 3.86 3.76 V I
OH
= −24 mA
5.5 4.86 4.76 I
OH
= −24 mA (Note 2)
V
OL
Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V I
OUT
= 50 µA
5.5 0.001 0.1 0.1
VIN = VIL or V
IH
3.0 0.36 0.44 IOL = 12 mA
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 2)
IIN (Note 4) Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAVI = VCC, GND
I
OZ
Maximum 3-STATE VI (OE) = VIL, V
IH
Current 5.5 ±0.25 ±2.5 µAVI = VCC, GND
VO = VCC, GND
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 3) 5.5 −75 mA V
OHD
= 3.85V Min
ICC (Note 4) Maximum Quiescent Supply Current 5.5 4.0 40.0 µAVIN = VCC or GND
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