March 1996
NDS8947
Dual P-Channel Enhancement Mode Field Effect Transistor
General Description Features
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer
power management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
________________________________________________________________________________
-4A, -30V. R
R
High density cell design for extremely low R
= 0.065Ω @ V
DS(ON)
= 0.1Ω @ V
DS(ON)
= -10V
GS
= -4.5V.
GS
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
Dual MOSFET in surface mount package.
5
6
7
8
4
3
2
1
Absolute Maximum Ratings T
Symbol Parameter NDS8947 Units
V
DSS
V
GSS
I
D
P
D
TJ,T
THERMAL CHARACTERISTICS
R
θ
R
θ
Drain-Source Voltage -30 V
Gate-Source Voltage -20 V
Drain Current - Continuous (Note 1a) -4 A
- Pulsed -15
Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9
Operating and Storage Temperature Range -55 to 150 °C
STG
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
JC
= 25°C unless otherwise noted
A
© 1997 Fairchild Semiconductor Corporation
NDS8947.SAM
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V
Zero Gate Voltage Drain Current
VDS = -24 V, V
GS
= 0 V
TJ = 55°C
-1 µA
-10 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
GS(th)
DS(ON)
Gate Threshold Voltage VDS = VGS, ID = -250 µA -1 -1.6 -2.8 V
-0.7 -1.2 -2.2
0.052 0.065
Static Drain-Source On-Resistance
TJ = 125°C
VGS = -10 V, ID = -4.0 A
Ω
TJ = 125°C 0.075 0.13
0.085 0.1
-5
I
g
D(on)
FS
VGS = -4.5 V, ID = -3.3 A
On-State Drain Current VGS = -10 V, VDS = -5 V -15 A
VGS = -4.5 V, VDS = -5 V
Forward Transconductance VDS = -10 V, ID = -4.0 A 7 S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 430 pF
VDS = -15 V, V
f = 1.0 MHz
GS
= 0 V,
Reverse Transfer Capacitance 160 pF
690 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 20 30 ns
VDD = -10 V, ID = -1 A,
V
= -10 V, R
GEN
GEN
= 6 Ω
Turn - Off Delay Time 40 50 ns
Turn - Off Fall Time 19 40 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 3.1 nC
Gate-Drain Charge 5.1 nC
VDS = -10 V,
ID = -4.0 A, VGS = -10 V
9 20 ns
21 30 nC
NDS8947.SAM
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
t
rr
Notes:
1. R
P
design while R
D
Typical R
Maximum Continuous Drain-Source Diode Forward Current -1.3 A
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = -1.3 A
(Note 2)
-0.85 -1.2 V
Reverse Recovery Time VGS = 0 V, IF = -1.3 A, dIF/dt = 100 A/µs 100 ns
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
is determined by the user's board design.
CA
θ
T
=
R
θ
T
J−TA
θJ A
JA
a. 78oC/W when mounted on a 0.5 in2 pad of 2oz copper.
b. 125oC/W when mounted on a 0.02 in2 pad of 2oz copper.
c. 135oC/W when mounted on a 0.003 in2 pad of 2oz copper.
J−TA
=
(t)
R
θJ C+RθCA
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
1a
2
= I
(t) × R
DS(ON)T
D
(t)
J
1b
1c
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%..
NDS8947.SAM
Typical Electrical Characteristics
-20
V = -10V
GS
-15
-10
-5
D
I , DRAIN-SOURCE CURRENT (A)
0
-6.0
V , DRAIN-SOURCE VOLTAGE (V)
DS
-5.0
-4.5
-4.0
-3.5
-3.0
-4-3-2-10
3
V = -3.5V
2.5
2
1.5
DS(on)
R , NORMALIZED
1
DRAIN-SOURCE ON-RESISTANCE
0.5
GS
- 4.0
-4.5
I , DRAIN CURRENT (A)
D
Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Gate
Voltage and Drain Current.
1.6
I = -4.0A
1.4
1.2
DS(ON)
R , NORMALIZED
0.8
DRAIN-SOURCE ON-RESISTANCE
0.6
D
V = -10V
GS
1
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
J
Figure 3. On-Resistance Variation with
Temperature.
2
V = -10V
GS
1.5
1
DS(on)
R , NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
0.5
I , DRAIN CURRENT (A)
D
T = 125°C
J
Figure 4. On-Resistance Variation with Drain
Current and Temperature.
-5.0
-6.0
-10
-20-16-12-8-40
25°C
-55°C
-20-16-12-8-40
-20
V = -10V
DS
-15
-10
-5
D
I , DRAIN CURRENT (A)
0
V , GATE TO SOURCE VOLTAGE (V)
GS
Figure 5. Transfer Characteristics.
T = -55°C
J
125°C
25°C
-6-5-4-3-2-1
1.2
V = V
1.1
1
0.9
th
0.8
V , NORMALIZED
0.7
GATE-SOURCE THRESHOLD VOLTAGE
0.6
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
J
DS
I = -250µA
D
Figure 6. Gate Threshold Variation with
Temperature.
GS
NDS8947.SAM
Typical Electrical Characteristics
1.1
I = -250µA
1.08
D
1.06
1.04
1.02
1
DSS
BV , NORMALIZED
0.98
0.96
DRAIN-SOURCE BREAKDOWN VOLTAGE
0.94
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
J
Figure 7. Breakdown Voltage Variation with
Temperature.
2000
1000
500
300
CAPACITANCE (pF)
200
100
f = 1 MHz
V = 0V
GS
0.1 0.2 0.5 1 2 5 10 30
-V , DRAIN TO SOURCE VOLTAGE (V)
DS
C
C
iss
oss
C
rss
20
V = 0V
10
GS
5
T = 125°C
J
1
0.1
0.01
S
-I , REVERSE DRAIN CURRENT (A)
0.001
0 0.4 0.8 1.2 1.6 2
25°C
-55°C
-V , BODY DIODE FORWARD VOLTAGE (V)
SD
Figure 8. Body Diode Forward Voltage Variation
with Current and Temperature.
10
I = -4.0A
D V = -5V
8
6
4
2
GS
-V , GATE-SOURCE VOLTAGE (V)
0
0 5 10 15 20 25
Q , GATE CHARGE (nC)
DS
-10V
g
-20V
Figure 9. Capacitance Characteristics.
12
V = -10V
DS
9
6
3
FS
g , TRANSCONDUCTANCE (SIEMENS)
0
I , DRAIN CURRENT (A)
D
T = -55°C
J
25°C
125°C
Figure 11. Transconductance Variation with Drain
Current and Temperature.
Figure 10. Gate Charge Characteristics.
-20-16-12-8-40
NDS8947.SAM
Typical Thermal Characteristics
- V , DRAIN-SOURCE CURRENT (V)
-I , DRAIN CURRENT (A)
2.5
2
1.5
1b
1
1c
0.5
STEADY-STATE POWER DISSIPATION (W)
0 0.2 0.4 0.6 0.8 1
2oz COPPER MOUNTING PAD AREA (in )
Total Power for Dual Operation
1a
Power for Single Operation
4.5"x5" FR-4 Board
T = 25 C
A
Still Air
o
2
Figure 12. SO-8 Dual Package Maximum
Steady-State Power Dissipation versus
Copper Mounting Pad Area.
50
20
10
5
RDS(ON) LIMIT
1
0.5
V = -10V
GS
D
0.1
0.05
0.01
SINGLE PULSE
R = See Note 1c
JA
θ
T = 25°C
A
0.1 0.2 0.5 1 2 5 10 30 50
DS
DC
10s
1ms
10ms
100ms
1s
100us
4.5
4
3.5
1b
1c
3
2.5
D
-I , STEADY-STATE DRAIN CURRENT (A)
2
0 0.1 0.2 0.3 0.4 0.5
2oz COPPER MOUNTING PAD AREA (in )
4.5"x5" FR-4 Board
o
T = 25 C
A
Still Air
V = -10V
GS
2
Figure 13. Maximum Steady- State Drain
Current versus Copper Mounting Pad
Area.
1a
Figure 14. Maximum Safe Operating Area.
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
r(t), NORMALIZED EFFECTIVE
0.002
TRANSIENT THERMAL RESISTANCE
0.001
0.0001 0.001 0.01 0.1 1 10 100 300
D = 0.5
0.2
R (t) = r(t) * R
JA
θ
0.1
0.05
0.02
0.01
Single Pulse
t , TIME (sec)
1
Figure 15. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change
depending on the circuit board design.
R = See Note 1c
JA
θ
P(pk)
t
1
t
2
T - T = P * R (t)
J
A
Duty Cycle, D = t / t
JA
θ
JA
θ
2
1
NDS8947.SAM
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
CoolFET™
CROSSVOLT™
2
E
CMOS
TM
FACT™
FACT Quiet Series™
®
FAST
FASTr™
GTO™
HiSeC™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench
QFET™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STA TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
Formative or
In Design
First Production
Full Production
Not In Production
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. D
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