March 1996
NDS8947
Dual P-Channel Enhancement Mode Field Effect Transistor
General Description Features
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer
power management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
________________________________________________________________________________
-4A, -30V. R
R
High density cell design for extremely low R
= 0.065Ω @ V
DS(ON)
= 0.1Ω @ V
DS(ON)
= -10V
GS
= -4.5V.
GS
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
Dual MOSFET in surface mount package.
5
6
7
8
4
3
2
1
Absolute Maximum Ratings T
Symbol Parameter NDS8947 Units
V
DSS
V
GSS
I
D
P
D
TJ,T
THERMAL CHARACTERISTICS
R
θ
R
θ
Drain-Source Voltage -30 V
Gate-Source Voltage -20 V
Drain Current - Continuous (Note 1a) -4 A
- Pulsed -15
Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9
Operating and Storage Temperature Range -55 to 150 °C
STG
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
JC
= 25°C unless otherwise noted
A
© 1997 Fairchild Semiconductor Corporation
NDS8947.SAM
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V
Zero Gate Voltage Drain Current
VDS = -24 V, V
GS
= 0 V
TJ = 55°C
-1 µA
-10 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
GS(th)
DS(ON)
Gate Threshold Voltage VDS = VGS, ID = -250 µA -1 -1.6 -2.8 V
-0.7 -1.2 -2.2
0.052 0.065
Static Drain-Source On-Resistance
TJ = 125°C
VGS = -10 V, ID = -4.0 A
Ω
TJ = 125°C 0.075 0.13
0.085 0.1
-5
I
g
D(on)
FS
VGS = -4.5 V, ID = -3.3 A
On-State Drain Current VGS = -10 V, VDS = -5 V -15 A
VGS = -4.5 V, VDS = -5 V
Forward Transconductance VDS = -10 V, ID = -4.0 A 7 S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 430 pF
VDS = -15 V, V
f = 1.0 MHz
GS
= 0 V,
Reverse Transfer Capacitance 160 pF
690 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 20 30 ns
VDD = -10 V, ID = -1 A,
V
= -10 V, R
GEN
GEN
= 6 Ω
Turn - Off Delay Time 40 50 ns
Turn - Off Fall Time 19 40 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 3.1 nC
Gate-Drain Charge 5.1 nC
VDS = -10 V,
ID = -4.0 A, VGS = -10 V
9 20 ns
21 30 nC
NDS8947.SAM
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
t
rr
Notes:
1. R
P
design while R
D
Typical R
Maximum Continuous Drain-Source Diode Forward Current -1.3 A
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = -1.3 A
(Note 2)
-0.85 -1.2 V
Reverse Recovery Time VGS = 0 V, IF = -1.3 A, dIF/dt = 100 A/µs 100 ns
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
is determined by the user's board design.
CA
θ
T
=
R
θ
T
J−TA
θJ A
JA
a. 78oC/W when mounted on a 0.5 in2 pad of 2oz copper.
b. 125oC/W when mounted on a 0.02 in2 pad of 2oz copper.
c. 135oC/W when mounted on a 0.003 in2 pad of 2oz copper.
J−TA
=
(t)
R
θJ C+RθCA
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
1a
2
= I
(t) × R
DS(ON)T
D
(t)
J
1b
1c
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%..
NDS8947.SAM