Fairchild FAN7389 service manual

FAN7389 3-Phase Half-Bridge Gate-Drive IC

FAN7389 — 3-Phase Half-Bridge Gate-Drive IC

March 2012

Features

 Floating Channel for Bootstrap Operation to +600V  Typically 350mA/650mA Sourcing/Sinking Current

Driving Capability for All Channels

 Extended Allowable Negative V

Signal Propagation at V

DD=VBS

Swing to -9.8V for

S

=15V

 Output In-Phase with Input Signal  Over-Current Shutdown Turns off All Six Drivers  Matched Propagation Delay for All Channels  3.3V and 5V Input Logic Compatible  Adjustable Fault-Clear Timing  Built-in Advanced Input Filter  Built-in Shoot-Through Prevention Logic  Built-in Soft Turn-Off Function  Common-Mode dv/dt Noise Canceling Circuit  Built-in UVLO Functions for All Channels

Applications

 3-Phase Motor Inverter Driver  Air Conditioners  Washing Machines  General-Purpose Three-Phase Inverters

Description

The FAN7389 is a monolithic three-phase half-bridge gate-drive IC designed for high-voltage, high-speed driving MOSFETs and IGBTs operating up to +600V.

Fairchild’s high-voltage process and common-mode noise canceling technique provide stable operation of high-side drivers under high-dv/dt noise circumstances.

An advanced level-shift circuit allows high-side gate driver operation up to V

The protection functions include under-voltage lockout and inverter over-current trip with an automatic faultclear function.

Over-current protection that terminates all six outputs can be derived from an external current-sense resistor. An open-drain fault signal is provided to indicate that an over-current or under-voltage shutdown has occurred.

The UVLO circuits prevent malfunction when VDD and

are lower than the specified threshold voltage.

V

BS

Output drivers typically source and sink 350mA and 650mA, respectively; which is suitable for three-phase half-bridge applications in motor drive systems.

= -9.8V (typical) for VBS =15V.

S

28-SOIC

Ordering Information

Part Number Package Operating Temperature Packing Method

FAN7389MX1

Note:

1. These devices passed wave soldering test by JESD22A-111.

(1)

28-SOIC -40 to +125°C Tape & Reel

Typical Application Diagram

Figure 1. 3-Phase BLDC Motor Drive Application

Internal Block Diagram

FAN7389 — 3-Phase Half-Bridge Gate-Drive IC

Figure 2. Functional Block Diagram

Pin Configuration

Pin Definitions

FAN7389 — 3-Phase Half-Bridge Gate-Drive IC

Figure 3. Pin Configuration

Pin Name Description

1 V

2 HIN1 Logic Input 1 for high-side gate 1 driver 3 HIN2 Logic Input 2 for high-side gate 2 driver 4 HIN3 Logic Input 3 for high-side gate 3 driver 5 LIN1 Logic Input 1 for low-side gate 1 driver 6 LIN2 Logic Input 2 for low-side gate 2 driver 7 LIN3 Logic Input 3 for low-side gate 3 driver

8 Fault output with open drain (indicates over-current and low-side under-voltage)

9 CS Analog input for over-current shutdown

10 EN Logic input for shutdown functionality

11 RCIN An external RC network input used to define the fault-clear delay

12 VSS Logic ground

13 COM Low-side driver return

14 LO3 Low-side gate driver 3 output

15 LO2 Low-side gate driver 2 output

16 LO1 Low-side gate driver 1 output

17, 21, 25 NC No connect

18 VS3 High-side driver 3 floating supply offset voltage

19 HO3 High-side driver 3 gate driver output

20 VB3 High-side driver 3 floating supply

22 VS2 High-side driver 2 floating supply offset voltage

23 HO2 High-side driver 2 gate driver output

24 VB2 High-side driver 2 floating supply

26 VS1 High-side driver 1 floating supply offset voltage

27 HO1 High-side driver 1 gate driver output

28 VB1 High-side driver 1 floating supply

DD

FO

Logic and low-side gate driver power supply voltage

FAN7389 — 3-Phase Half-Bridge Gate-Drive IC

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. T

Symbol Parameter Min. Max. Unit

=25°C, unless otherwise specified.

A

VS High-Side Floating Offset Voltage V

B1,2,3

-25.0 V

+0.3 V

B1,2,3

VB High-Side Floating Supply Voltage -0.3 625.0 V

VDD Low-Side and Logic-Fixed Supply Voltage -0.3 25.0 V

VHO High-Side Floating Output Voltage V

VLO Low-Side Floating Output Voltage V

V

HO1,2,3

-0.3 VDD+0.3 V

LO1,2,3

S1,2,3

-0.3 V

+0.3 V

B1,2,3

VIN Input Voltage (HINx, LINx, CS, and EN) -0.3 5.5 V

VFO

PW

HIN

Fault Output Voltage ( )

FO

High-Side Input Pulse Width 500 ns

-0.3 VDD+0.3 V

dVS/dt Allowable Offset Voltage Slew Rate ±50 V/ns

PD Power Dissipation

(2,3,4)

1.4 W

θJA Thermal Resistance 70 °C/W

TJ Junction Temperature 150 °C

T

Storage Temperature -55 150 °C

STG

Notes:

2. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material).

3. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages.

4. Do not exceed PD under any circumstances.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Max. Unit

V

High-Side Floating Supply Voltage V

B1,2,3

V

High-Side Floating Supply Offset Voltage 6-VDD 600 V

S1,2,3

VDD Low-Side and Logic Fixed Supply Voltage

V

High-Side Output Voltage

HO1,2,3

V

Low-Side Output Voltage

LO1,2,3

VFO Fault Output Voltage ( )

FO

VCS Current-Sense Pin Input Voltage

VIN Logic Input Voltage (HIN1,2,3 and LIN1,2,3)

TA Ambient Temperature

S1,2,3

10

V

S1,2,3

COM

-40

+10 V

+20 V

S1,2,3

20 V

V

B1,2,3

VDD V

5 V

+125 °C

Electrical Characteristics

V

BIAS (VDD

COM and are applicable to all six channels. The V applicable to the respective output leads: HO1,2,3 and LO1,2,3. The V V

BSUV

Symbol Parameter Conditions Min. Typ. Max. Unit

Low-Side Power Supply Section

V

Bootstrapped Power Supply Section

V

Gate Driver Output Section

Logic Input Section

Enable Control Section (EN)

V

, V

parameters are referenced to V

I

Quiescent VDD Supply Current V

QDD

I

Operating VDD Supply Current f

PDD

DDUV+

DDUV-

DDHYS

BSUV+

BSUV-

BSHYS

ILK Offset Supply Leakage Current V

I

Quiescent VBS Supply Current V

QBS

I

Operating VBS Supply Current f

PBS

VOH High-Level Output voltage, V

VOL Low-Level Output voltage, VO I

IO+ Output HIGH Short-Circuit Pulse Current

IO- Output LOW Short-Circuit Pulsed Current

VS

) = 15.0V and TA = 25°C unless otherwise specified. The VIN and IIN parameters are referenced to

BS1,2,3

.

S1,2,3

VDD Supply Under-Voltage Positive-Going Threshold

V

Supply Under-Voltage Negative-Going

DD

Threshold

VDD Supply Under-Voltage Lockout Hysteresis

VBS Supply Under-Voltage Positive-Going Threshold

VBS Supply Under-Voltage Negative-Going Threshold

VBS Supply Under-Voltage Lockout Hysteresis

BIAS-VO

Allowable Negative VS Pin Voltage for HIN Signal Propagation to HO

and IO parameters are referenced to V

O

=0V or 5V, EN=0V 200

LIN1,2,3

=20kHz, rms Value 400

LIN1,2,3

parameters are referenced to COM. The

DDUV

VDD=Sweep 7.5 8.5 9.3 V

=Sweep 7.0 8.0 8.7 V

V

DD

VDD=Sweep 0.5 V

V

=Sweep 7.5 8.5 9.3 V

BS1,2,3

V

=Sweep 7.0 8.0 8.7 V

BS1,2,3

V

=Sweep 0.5 V

BS1,2,3

B1,2,3=VS1,2,3

HIN1,2,3

I

=0mA (No Load) 100 mV

O

=0mA (No Load) 100 mV

O

(5)

V

=0V, VIN=5V with PW10µs

O

(5)

VO=15V, VIN=0V with PW10µs

=600V 10

=0V or 5V, EN=0V 10 50 80

=20kHz, rms Value 200 420 480

-9.8 -7.0 V

and COM and are

S1,2,3

250 350 mA

500 650 mA

A

VIH Logic "1" Input Voltage HIN1,2,3, LIN1,2,3 2.5 V

VIL Logic "0" Input Voltage HIN1,2,3, LIN1,2,3 0.8 V

I

RIN

V

I

Logic Input Bias Current (HO=LO=HIGH)

IN+

Logic Input Bias Current (HO=LO=LOW)

IN-

Logic Input Pull-Down Resistance

Enable Positive-Going Threshold Voltage 2.5 V

EN+

Enable Negative-Going Threshold Voltage 0.8 V

EN-

Logic Enable “1” Input Bias Current

EN+

Logic Enable “0” Input Bias Current

EN-

VIN=5V 100

VIN=0V 2

50

=5V (Pull-Down=150K)

V

EN

33

VEN=0V 2

A

K

A

FAN7389 — 3-Phase Half-Bridge Gate-Drive IC

Continued on the following page…

Electrical Characteristics

V

BIAS (VDD

COM and are applicable to all six channels. The V applicable to the respective output leads: HO1,2,3 and LO1,2,3. The V V

BSUV

Symbol Parameter Conditions Min. Typ. Max. Unit

Over-Current Protection Section

V

I

Fault Output Section

V

RCINTH+

V

RCINTH-

V

RCINHYS

I

V

R

DSRCIN

R

Note:

5. These parameters are guaranteed by design.

, V

parameters are referenced to V

CSTH+

Over-Current Detect Negative Threshold

CSTH-

CSHYS

CSIN

SOFT

) = 15.0V and TA = 25°C unless otherwise specified. The VIN and IIN parameters are referenced to

BS1,2,3

.

S1,2,3

Over-Current Detect Positive Threshold

(5)

Over-Current Detect Hysteresis

60 mV

Short-Circuit Input Current V

and IO parameters are referenced to V

O

(5)

400 500 600 mV

(5)

440 mV

=1V 5 10 15

CSIN

parameters are referenced to COM. The

DDUV

and COM and are

S1,2,3

Soft Turn-Off Sink Current 25 40 55 mA

RCIN Positive-Going Threshold Voltage 3.3 V

RCIN Negative-Going Threshold Voltage 2.6 V

RCIN Hysteresis Voltage 0.7 V

RCIN Internal Current Source C

RCIN

Fault Output Low Level Voltage V

FOL

RCIN On Resistance I

DSFO

Fault Output On Resistance I

=2nF 3 5 7 µA

RCIN

=1V, IFO=1.5mA 0.2 0.5 V

CS

=1.5mA 50 75 100

RCIN

=1.5mA 90 130 170

FO

A



FAN7389 — 3-Phase Half-Bridge Gate-Drive IC

Dynamic Electrical Characteristics

TA=25C, V

BIAS (VDD

Symbol Parameter Conditions Min. Typ. Max. Unit

tON Turn-On Propagation Delay V

t

Turn-Off Propagation Delay V

OFF

tR Turn-On Rise Time V

tF Turn-Off Fall Time V

tEN Enable LOW to Output Shutdown Delay 400 500 600 ns

t

CS Pin Leading-Edge Blanking Time

CSBLT

t

CSFO

t

CSOFF

t

FLT,IN

t

FLTCLR

DT Dead Time 250 300 350 ns

MDT Dead-Time Matching (All Six Channels) 50 ns

MT Delay Matching (All Six Channels) 50 ns

PM Output Pulse-Width Matching

Notes:

6. These parameters are guaranteed by design.

7. The minimum width of the input pulse should exceed 500ns to ensure the filtering time of the input filter is exceeded.

8. PM is defined as PW

Time from CS Triggering to From V

Time from CS Triggering to All Gate Outputs Turn-Off

Input Filtering Time

Fault-Clear Time RCIN: C

, V

BS1,2,3

IN

-PW

) = 15.0V, V

(7)

(HINx, LINx) 200 250 300 ns

(7)

(EN) 200 250 300 ns

.

OUT

= COM, and C

S1,2,3

(6)

200 300 400 ns

From V Turn-Off

(6,8)

PWIN > 1µs 50 100 ns

= 1000pF unless otherwise specified.

Load

LIN1,2,3=VHIN1,2,3

=1V to Turn-Off

CSC

=1V to Starting Gate

CSC

=2nF 1.3 ms

RCIN

=0V, V

=5V, V

=0V 20 50 100 ns

=5V 10 30 80 ns

FOFO

=0V 350 500 650 ns

S1,2,3

=0V 350 500 650 ns

S1,2,3

630 ns

640 ns