Fairchild FAN7383 service manual

FAN7383 Half-Bridge Gate-Drive IC

February 2007

Features

 Floating Channel Designed for Bootstrap Operation to

+600V.

 Typically 350mA/650mA Sourcing/Sinking Current

Driving Capability for Both Channels

 Extended Allowable Negative V

Signal Propagation at VDD=VBS=15V

 High-Side Output in Phase of IN Signal  Built-in UVLO Functions for Both Channels  Built-in Common-Mode dv/dt Noise Canceling Circuit  Typically Internal 330ns Minimum Dead-Time  Programmable Turn-On Delay Time Control

(Dead-Time)

Swing to -9.8V for

S

Applications

 SMPS  Motor Drive Inverter  Fluorescent Lamp Ballast  HID Ballast

Description

The FAN7383 is a half-bridge gate-drive IC with shutdown and programmable dead-time control functions for driving MOSFETs and IGBTs that operate up to +600V .

Fairchild’s high voltage process and common-mode noise canceling technique give stable operation of highside drivers under high-dv/dt noise circumstances.

An advanced level-shift circuit allows high-side gate driver operation up to V

The UVLO circuits for both channels prevent malfunction when VDD and VBS are lower than the specified

threshold voltage. Output drivers typically source/sink 350mA/650mA,

respectively, which is suitable for all kinds of half and full bridge inverter.

= -9.8V (typical) for VBS=15V.

S

14-SOP

1

Ordering Information

Part Number Package Pb-Free Operating Temperature Range Packing Method

FAN7383M

FAN7383MX

Note:

1. These devices passed wave soldering test by JESD22A-111.

(1)

14-SOP Yes -40°C ~ 125°C

Tube

Tape & Reel

Typical Application Circuit

V

DD

FAN7383 Half-Bridge Gate-Drive IC

V

R

BOOT

D

BOOT

DC

V

PWM IC

Control

DC

CC

PWM

Shutdown

R

DT

IN

1

SD

2

3

DT

4

V

DD

5

LO1

6

LO2

7

GND

HO1

HO2

NC

14

V

B

R

13

12

11

V

S

10

9

8

HON

R

HOFF

C

BOOT

R

LOFF

R

LON

Figure 1. Application Circuit for Half-Bridge Switching Power Supply

FAN7383 Rev.01

V

DD

IN

SD

FAN7383

DT

GND

HO1

HO2

LO1

LO2

V

B

V

S

Forward

M

Reverse

FAN7383 Rev.01

PHA

PHB

DC Motor

Controller

SD

V

DD

IN

SD

FAN7383

DT

GND

HO1

HO2

LO1

LO2

V

B

V

S

Figure 2. Application Circuit for Full-Bridge DC Motor Driver

Internal Block Diagram

SCHMITT

TRIGGER INPUT

SHOOT THOUGH

PREVENTION

DEAD-TIME

{ DTMIN=330nsec }

SD

DT

1

IN

2

3

UVLO

GENERATOR

HS(ON/OFF)

LS(ON/OFF)

PULSE

NOISE

CANCELLER

UVLO

R

S

DELAY

R

Q

Figure 3. Functional Block Diagram of FAN7383

DRIVER

14

V

B

HO1

13

HO2

12

V

11

S

V

4

DD

LO1

5

LO2

6

7

GND

FAN7383 Rev:01

FAN7383 Half-Bridge Gate-Drive IC

Pin Configuration

IN

SD

FAN7383 Half-Bridge Gate-Drive IC

1

2

FAN7383

14

13

V

B

HO1

DT

V

DD

LO1

LO2

GND

3

4

5

6

7

12

11

10

9

8

FAN7383 Rev:00

Figure 4. Pin Configuration (Top View)

Pin Definitions

Pin # Name Description

1 IN Logic Input for Gate Driver 2SD 3 DT Programmable Dead-Time Control with External Resistor 4V

DD

5 LO1 Low-Side Driver Source Output 6 LO2 Low-Side Driver Sink Output 7 GND Ground 8 N.C. Not connected

9 N.C. Not connected 10 N.C. Not connected 11 V

S

12 HO2 High-Side Driver Sink Output 13 HO1 High-Side Driver Source Output 14 V

B

Logic Input for Shutdown (Active Low)

Low-Side Supply Voltage

High-Side Floating Supply Return

High-Side Floating Supply

HO2

V

S

NC

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may a ffect device reliability. The absolute maximum ratings are stress ratings only. T

Symbol Parameter Min. Max. Unit

V

S

V

B

V

HO

V

DD

V

LO

V

IN

V

SD

V

DT

GND Logic ground V

/dt Allowable offset voltage slew rate 50 V/ns

dV

S

(2)(3)(4)

P

D

θ

JA

T

J

T

STG

Notes:

2. When mounted on 76.2 x 114.3 x 1.6mm PCB. (FR-4 glass epoxy material).

3. Please refer to: JESD51-2: Integral circuits thermal test method environmental conditions - Natural convection JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages

4. Do not exceed P

High-side offset voltage VB-25 VB+0.3 V High-side floating supply voltage -0.3 625 V High-side floating output voltage HO1, HO2 VS-0.3 VB+0.3 V Low-side and logic fixed supply voltage -0.3 25 V Low-side output voltage LO1, LO2 -0.3 VDD+0.3 V Logic input voltage (IN) -0.3 VDD+0.3 V Shutdown logic input voltage -0.3 VDD+0.3 V Dead-time control voltage -0.3 5.0 V

Power dissipation 1.0 W Thermal resistance, junction-to-ambient 110 °C/W Junction temperature 150 °C Storage temperature 150 °C

under any circumstances.

D

= 25°C unless otherwise specified.

A

-25 VDD+0.3 V

DD

FAN7383 Half-Bridge Gate-Drive IC

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal perfor mance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Condition Min. Max. Unit

V

B

V

S

V

DD

V

HO

V

LO

V

IN

T

A

High-side floating supply voltage VS+15 VS+20 V High-side floating supply offset voltage 6-V

DD

600 V Low-side supply voltage 15 20 V High-side (HO) output voltage V

S

Low-side (LO) output voltage GND V Logic input voltage (IN) GND V

V

DD DD

B

V V V

Ambient temperature -40 125 °C