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1. This evaluation board/kit or development tool is designed for use for engineering evaluation,
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user should cease to use it when any abnormal issue occurs, even during proper and safe use.
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This manual describes the setup and operation of the S5U13781R00C100 reference board.
The reference board is designed as an evaluation platform for the S1D13781 Display Controller. The
S5U13781R00C100 reference board has host controller connector, LCD panel connector, clock generator,
SPI flash memory (16Mbit), power regulation circuit for S1D13781 core and DC/DC converter for LED
back light.
This user manual is updated as appropriate. Please check the Seiko Epson Website at
http://www.epson.jp/device/semicon_e/product/lcd_controllers/index.htm for the latest revision of this
document before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
The S5U13781R00C100 reference board includes the following features:
QFP 100pin S1D13781F00A100 Display Controller
2.54mm pitch vias for host bus interface header
2.54mm pitch vias for LCD panel header
Connection area with 2.54mm pitch vias for header and FPC (0.5mm pitch 55 electrode)
connector to connect LCD panel.
On-board 24MHz crystal
On-board voltage booster for LED back light (38V 60mA Maximum output at 5V input)
On-board voltage regulator with 1.5V output from 3.3V/5.5V input for COREVDD and
The S1D13781 has three configuration inputs, CNF[2:0], which are used to configure the S1D13781 host
interface type as described in Table 3-1, Signal Allocation for Host Interface.
The S5U13781R00C100 reference board defaults to the SPI interface (the default setting for CNF[2:0] =
111).
Table 3-1 Signal Allocation for Host Interface
Notes:
“H” means direct connection to IOVDD
“L” means direct connection to GND
“Low” means internal pull-down for address bus active
TE is determined by REG[22h] Display Settings Register bits 6-5
Short: Enables regulator
Short: Regulator output current +20mA
Regulator output current +20mA
Regulator output current +20mA
Power supply for VDDIO /
VDDDCDC
J4 3
4
External power supply to VDDIO
External power supply to VDDDCDC
On board OSC setting
J6 1-2
Short: Disable on board OSC
On board OSC input
J7 1
External clock input in case of OSC disable
J3
J2
J6
J1
J4
3.2 Jumper setting
The S5U13781R00C100 reference board includes jumpers which control the functions described in Table
3-2, Jumper settings. For jumper locations on the reference board, see Figure 3-1, Jumper Pin Locations.
IOVDD for U4 (S1D13781 Display Controller)
Power supply for Y1 (SG-310SCF 24MHz OSC)
Power supply for D2(SML-E12M8WT86 LED)
2.7V ~ 3.6V
VDDDCDC
Input
Power supply for U1 (BU15TD3WG 1.5V LDO regulator)
Power supply for U3(TPS61161A voltage booster)
2.7V ~ 5.5V
FLASH-VCC
Input
Power supply for U2(M25P16-VMN6P SPI flash memory
2.7V ~ 3.6V
VDDCORE
Output
COREVDD and PLLVDD for U4 (S1D13781 LCD
controller)
1.5V (Fixed)
LED+ / LED-
Output
LED back light power supply
VDDDCDC ~ 38V
3.3 Power Supply
The S5U13781R00C100 reference board is designed to supply VDDCORE (1.5V) and LED back light
power (LED+/LED-) from the 2.7V to 5.5V input of J4-4 (VDD DCDC).
The voltage output of 2.7V to 3.3V from J4-3 (VDDIO) is used for the U4 (S1D13781 Display
Controller) power supply, D2 (LED indicator) and Y1(SG-310SCF 24MHz OSC).
The power for U2 (M25P-16-VMN6P SPI flash memory) is supplied via J1-2 (FLASH-VCC).
3.3.1 VDDCORE
VDDCORE (1.5V) is generated from U1 (BU15TD3WG Voltage regulator) and is used to supply power
to COREVDD and PLLVDD of U4 (S1D13781 Display Controller).
3.3.2 LED Back Light LED+/LED- Power Supply
The LED back light power supply (Maximum voltage between LED+ and LED- is 38V) is generated by
U3 (TPS61161A voltage booster).
The output current is set by J3 as described in Table 3-2, Jumper Settings. Connecting one of J3 3-4, J3 56 or J3 7-8 allows 20mA, connecting any two of them allows 40mA and connecting all of them allows
60mA output, maximum.
Table 3-3 Power Supply for S5U13781R00C100
Note: Do not short the power supply pins to any other pins.
The S5U13781R00C100 reference board has via for host interface and panel interface connectors (J4, J5,
J8, J9 and J10).
To locate of these connectors on the reference board, see Figure 4-1, Reference Board Connector
Locations.
Figure 4-1 Reference Board Connector Locations
4.1 J4 Host Interface Connector
The host interface pins of S1D13781 are connected to J4 of the S5U13781R00C100 reference board. See
Figure 7-1, S5U13781R00C100 Schematic Diagram (1 of 2), and Figure 7-2, S5U13781R00C100 Schematic Diagram (2 of 2), for detailed pin allocation.
4.2 J5 Panel Interface Connector
The panel interface pins of the S1D13781 are connected to J5 of the S5U13781R00C100 reference board.
See Figure 7-1, S5U13781R00C100 Schematic Diagram (1 of 2), and Figure 7-2, S5U13781R00C100 Schematic Diagram (2 of 2), for detailed pin allocation.
S5U13781R00C100 reference board includes Y1 (SG-310SCF 24MHz oscillator) for the CLKI input of
the S1D13781.
The output of the oscillator is disabled by connecting J6 1-2 and enabled by disconnecting.
5.2 SPI flash memory
The S5U13781R00C100 reference board includes SPI NOR FLASH standard memory of 16Mbit
capacity. It can be used as external image data storage for the S1D13781.