Epson S1D13743, S5U13743P00C100 User Manual

Page 1
S1D13743 Mobile Graphics Engine
S5U13743P00C100 Evaluation Board
User Manual
Document Number: X70A-G-001-01
Status: Revision 1.0
Issue Date: 2007/08/15
Revision 1.0
Page 2
Page 2 Epson Research and Development
Evaluation Board/Kit and Development Tool Important Notice
1. This evalua tion board /kit o r dev elop ment to ol is desig ned fo r use for en ginee ring e valu ation, demo nstr ation, or dev elop­ment purposes only. Do not use it for other purposes. It is not intended to meet the requirements of design for finished products.
2. This evaluation board/kit or development tool is intended for use by an electronics engineer and is not a consumer product. The user should use it properly and in a safe manner. Seiko Epson do es not assume any responsibility or liability of any kind of damage and/or fire caused by the use of it. The user should cease to use it when any abnormal issue occurs even during proper and safe use.
3. The part used for this evaluation board/kit or development tool may be changed without any notice.
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any lia­bility of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or cir­cuit and, further, there is no representation that this material is applicabl e to products requiring high lev el reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. When exporting the products or technology described in this material, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You are requested not to use, to resell, to export and/or to otherwise dispose of the products (and any technical information furnished, if any) for the development and/or manufacture of weapon of mass destruction or for other military purposes.
All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective companies.
©SEIKO EPSON CORPORATION 2007 - 2012, All rights reserved.
S1D13743 S5U13743P00C100 Evaluation Board User Manual X70A-G-001-01 Issue Date: 2007/08/15
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Table of Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Configuration DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3.2 Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.1 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.2 Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.3 S1D13743 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Power Save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5.1 Direct Host Bus Interface Support . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5.2 Connecting to the Epson S5U13U00P00C100 USB Adapter Board . . . . . . . . . 15
4.6 LCD Panel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.7 GPIO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.1 EPSON Display Controllers (S1D13743) . . . . . . . . . . . . . . . . . . . . 27
9.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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1 Introduction

This manual describes the setup and operation of the S5U13743P00C100 Evaluation Board. The evaluation board is designed as an evaluation platform for the S1D13743 Mobile Graphics Engine.
The S5U13743P00C100 evaluation boar d ca n be used with many native platforms via the host connector which provides the appropriate signals to support a variety of CPUs. The S5U13743P00C100 evaluation board can also connect to the S5U13U00P00C100 USB Adapter board so that it can be used with a laptop or desktop computer, via USB 2.0.
This user manual is updated as appropriate. Please check the Epson Research and Devel­opment Website at www.erd.epson.com for the latest revision of this document before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at documentation@erd.epson.com.
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2 Features

The S5U13743P00C100 Evaluation Board includes the following features:
• 121-pin FCBGA S1D13743 Mobile Graphics Engine
• Header with all S1D13743 Host Bus Interface signals
• Headers for connection to the S5U13U00P00C100 USB Adapter board
• Headers for connecting to LCD panels
• Header for S1D13743 GPIO pins (optional)
• On-board 4MHz oscillator
• 14-pin DIP socket (if a clock other than 4MHz must be used)
• 3.3V input power
• On-board voltage regulator with 1.5V output
• On-board voltage regulator with adjustable 6~24V output, 40mA max., to provide power for LED backlight of LCD panels.
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DIP Switch
SW1
Vancouver Design Center

3 Installation and Configuration

The S5U13743P00C100 evaluation board incorporates a DIP switch, jumpers, and 0 ohm resistors which allow it to be used with a variety of different configurations.

3.1 Configuration DIP Switch

The S1D13743 has 3 configuration inputs (CNF[2:0]). A DIP switch (SW1) is used to configure CNF[2:0] as described below.

Table 3-1: Summary of Power-On/Reset Options

SDU13743P00C100
SW1-[4:1] Config
SW1-[1] CNF0
SW1-[2] CNF1 Host Data is 16-bit Host data is 8-bit
SW1-[3] CNF2 PIOVDD output current = 6.5mA PIOVDD output current = 2.5mA
SW1-[4] - not used
S1D13743
CNF[2:0] Config
1 (ON) 0 (OFF)
Host Data lines are normal Host data lines are swapped
Power-On/Reset State
= Required settings when using S5U13U00P00C100 USB Adapter board
The following figure shows the location of DIP switch SW1 on the S5U13743P00C100 board.

Figure 3-1: Configuration DIP Switch (SW1) Location

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3.2 Configuration Jumpers

The S5U13743P00C100 has 6 jumpers whi ch configure various boar d settings. The jumper positions for each function are shown below.
Jumper Function Position 1-2 Position 2-3 No Jumper
JP1 COREVDD Normal
JP2 PLLVDD Normal
JP3 IOVDD Normal
JP4 IOVDD Source H1 connector, pin 32
JP5 PIOVDD Normal
JP6 PIOVDD Source H4 connector, pin 8
= Required settings when using S5U13U00P00C100 USB Adapter board
3.3VDD
3.3VDD
COREVDD current
measurement
PLLVDD current
measurement
IOVDD current
measurement
PIOVDD current
measurement
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JP3 JP5 JP1 JP2
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JP1, JP2, JP3, JP5 - Power Supplies for the S1D13743
JP1, JP2, JP3, JP5 can be used to measure the current consumption of each S1D13743 power supply. When the jumper is at position 1-2, normal operation is selected. When no jumper is installed, the current consumption for each power supply can be measured by connecting an ammeter to pin 1 and 2 of the jumper.
The jumper associated with each power supply is as follows:
JP1 for COREVDD JP2 for PLLVDD JP3 for IOVDD JP5 for PIOVDD

Figure 3-2: Configuration Jumper Locations (JP1, JP2, JP3, JP5)

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JP4
JP4 - IOVDD Source
JP4 is used to select the source for the IOVDD supply voltage. When the jumper is at position 1-2, the IOVDD voltage must be provided to the H1 connector, pin 32. When the jumper is at position 2-3, the IOVDD voltage is provided by the 3.3V power supply of the board.

Figure 3-3: Configuration Jumper Location (JP4)

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JP6
Vancouver Design Center
JP6 - SIOVDD Source
JP6 is used to select the source for the PIOVDD supply voltage. When the jumper is at position 1-2, the PIOVDD voltage must be provided to the H4 connector, pin 8. When the jumper is at position 2-3, the PIOVDD voltage is provided by the 3.3V power supply of the board.

Figure 3-4: Configuration Jumper Location (JP6)

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Note

4 Technical Description

4.1 Power

4.1.1 Power Requirements

The S5U13743P00C100 evaluation board requires an external regulated power supply (3.3V / 0.5A). The power is supplied to the evaluation board through pin 34 of the H1 header, or pin 5 of the P2 header.
The green LED ‘3.3V Power’ is turned on when 3.3V power is applied to the board.

4.1.2 Voltage Regulators

The S5U13743P00C100 evaluation board has an on-board linear regulator to provide the
1.5V power required by the S1D13743 Mobile Graphics Engine. It also has a step-up
switching voltage regul ator t o genera te adjus tabl e 6~24V, which can be used to power the LED backlight on some LCD panels.

4.1.3 S1D13743 Power

The S1D13743 Mobile Graphics Engine requires 1.5V and 1.65~3.6V power supplies.
1.5V power for COREVDD and PLLVDD is provided by an on-board linear voltage
regulator.
IOVDD can be in the range of 1.65~3.6V. When JP4 is set to the 2-3 position, IOVDD is connected to 3.3V. If a di fferent voltage is required f or IOVDD, set JP4 t o the 1-2 p osition and connect the external power supply to pin 32 of connector H1.
If the IOVDD voltage is less than 3.0V, an oscillator working at the selected IOVDD voltage must be used.
PIOVDD is the power used by the LCD interface and can be in the range of 1.65~3.6V. When JP6 is set to the 2-3 positi on, PIOVDD is connected to 3.3V. If a diffe rent voltage i s needed for PIOVDD because of the LCD panel requirements, set JP6 to the 1-2 position and connect the external power supply to pin 8 of connector H4.
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Note
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4.2 Clocks

The clock for the S1D13743 Mobile Graphics Engine is provided by a 4MHz oscillator.
The S5U13743P00C100 evaluation board has a DIP14 footprint for an optional second oscillator, Y2. This is provided for cases requiring a different clock frequency for the S1D13743 Mobile Graphics Eng ine . To use Y2, an oscillator must be popul at ed in the Y2 footprint and the following board modifications must be made.
1. Remove R10 (33 ohm resistor, size 0402) to cut the output of Y1.
2. Populate R13 with a 33 ohm resistor, size 0402, to connect the output of Y2 to the CLKI input of the S1D13743 Mobile Graphics Engine.
If the board is configured for an IOVDD voltage below 3.0V, an oscillator working at the selected IOVDD voltage must be used at Y2. The on-board 4MHz oscillator is not specified to work below a 3.0V supply voltage.
The S1D13743 MGE can output the input clock on the CLKOUT pin depending o n the state of the CLKOUTEN input. Both these signals ar e available on the H4 connec tor: CLKOUT on pin 1 and CLKOUTEN on pin 4. On the board the CLKOUTEN pin is pulled down which disables the CLKOUT signal. Note that connector H4 is not populated on the S5U13743P00C100 evaluation board.

4.3 Reset

4.4 Power Save

The S1D13743 Mobile Graphics Engine on the S5U13743P00C100 evaluation board can be reset using a push-button (SW2), or via an active low reset signal from the host devel­opment platform (pin 33 on the H1 connector).
The S1D13743 chip has an input called PWRSVE that will enable (when high) or disable (when low) the power save mode. This signal is avail able on pin 5 of the H4 connector. On the board the PWRSVE pin is pulled down which means power save mode is controlled only by the S1D13743 register setting. Note that connector H4 is not populated on the S5U13743P00C100 evaluation board.
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H1

4.5 Host Interface

4.5.1 Direct Host Bus Interface Support

All S1D13743 host interface pins are available on connector H1 which allows the S5U13743P00C100 evaluation board to be connected to a variety of development platforms. For detailed S1D13743 pin mapping, refer to the S1D13743 Hardware Functional Specification, document number X70A-A-001-xx.
The following figure shows the location of host bus connector H1. H1 is a 0.1x0.1” 34-pin header (17x2).
Figure 4-1: Host Bus Connector Location (H1)
For the pinout of connector H1, see “Schematic Diagrams” on page 21.
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Note
P1
P2
Vancouver Design Center

4.5.2 Connecting to the Epson S5U13U00P00C100 USB Adapter Board

The S5U13743P00C100 evaluatio n board is de signed to co nnect to a S5U1 3U00P00 C100 USB Adapter Board. The USB adapter board provides a simple connection to any computer via a USB 2.0 connection. The S5U13743P00C100 directly connects to the USB adapter board through connectors P1 and P2.
The USB adapter board also supplies the 3.3V power requir ed by the S5U13743P00C100. IOVDD should be selected for 3.3V and JP4 should be set to the 2-3 position.
When the S5U13743P00C100 is connected to the S5U13U00P00C100 USB Adapter board, there are 2 LEDs on S5U13743P00C100 which provide a qui ck visual status of the USB adapter. LED1 blinks to i ndicate that the USB a dapter bo ard is a ctive. LED2 turns on to indicate that the USB has been enumerated by the PC.
The following diagram shows the location of connectors P1 and P2. P1 and P2 are 40-pin headers (20x2).
Figure 4-2: USB Adapter Connector Locations (P1 and P2)
For the pinout of connectors P1 and P2, see “Schematic Diagrams” on page 21.
A windows driver must be installed on the PC when the S5U13743P00C100 is used with the S5U13U00P00C100 USB Adapter Board. The S1D13xxxUSB driver is avail­able at www.erd.epson.com.
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Note
H2
H3

4.6 LCD Panel Interface

The LCD interface signals are available on connectors H2 and H3. For S1D13743 LCD interface pin mapping, refer to the S1D13743 Hardware Functional Specification, document number X70A-A-001-xx.
Connector H2 is 0.1x0.1” 2 0-pin header (10x2) and con nector H3 is 0.1x0.1” 40-pi n header (20x2). For the pinout of connectors H2 and H3, see “Schematic Diagrams” on page 21.
On the evaluation board there is an adjustable 6~24V, 40mA max. power supply. This voltage is provided only on connector H3 (it is not used elsewhere on the board). It is intended for use to power t he LED backlig ht on some LCD panels . The voltage is adjust ed by the R24 pot.
For LCD panels that use a CCFL backlight, an external power supply must be used to provide power to the inverter for the CCFL backlight. Usually, the inverter current con­sumption is higher than the maximum 40mA current available from the on-board volt­age regulator.
The following diagram shows the location of the LCD panel connectors H2 and H3.

Figure 4-3: LCD Panel Connectors Location (H2, H3)

S1D13743 S5U13743P00C100 Evaluation Board User Manual X70A-G-001-01 Issue Date: 2007/08/15
For the pinout of connectors H2 and H3, see “Schematic Diagrams” on page 21.
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H4
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4.7 GPIO Connections

The S1D13743 Mobile Graphics Engine has 8 GPIO pins . All the GPIO pins ar e routed to the H4 connector. Note that connector H4 is not populated on the S5U13743P00C100 evaluation board.
The following figure shows the location of the GPIO connector, H4.

Figure 4-4: GPIO Connector Location (H4)

For the pinout of connector H4, see “Schematic Diagrams” on page 21.
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5 Parts List

Table 5-1: Parts List

Item Qty Reference Part Description Mfg / Mfg PN / Notes
C1, C2, C3, C4, C9, C12,
116
212
3 1 C10 1nF C0402
4 1 C11 10uF C0805
5 1 C29 100uF 4V T C3528 Kemet T494B107M004AS
6 2 C31, C33 0.01uF C0402
7 1 C34 4.7uF 10V T C3528 Kemet T491B475K010AS
8 1 C35 10pF C0402
9 1 C36 1uF 50V C1206 TDK C3216X7R1H105K
10 3 D1, D2, D3 LED0603
11 1 D4 MBR0530 SOD-123
12 2 F1, F2 ACF451832-222
13 1 H1 HEADER_17X2 AMP 1-87215-7
14 1 H2 Extended LCD Connector Samtec TST-110-01-G-D
15 1 H3 LCD Connector Samtec TST-120-01-G-D
16 0 H4 HEADER 8X2 Samtec TSW-108-07-G-D
17 4 JP1, JP2, JP3, JP5 SIP2
18 2 JP4, JP6 SIP3
19 2 L1, L2 Ferrite R0603
C13, C14, C18, C19, C20, C21, C26, C27, C28, C30,
C32
C5, C6, C7, C8, C15, C16, C17, C22, C23, C24, C25,
0.1uF C0402
0.01uF C0402
Yageo America
04022F104Z7B20D
Yageo America
0402ZRY5V7BB103
Yageo America
04022R102K9B20D
Panasonic - ECG ECJ-CV50J106M
Kemet
C0402C103K4RACTU
Panasonic - ECG
ECJ-0EC1H100D
Panasonic - SSG
LNJ308G8LRA
LED GREEN SS TYPE
LOW CUR SMD
Micro Commercial Co.
MBR0530-TP
TDK ACF451832-222
FILTER 3-TERM 60MHZ
300MA SMD
CONN HEADER VERT
2POS .100 TIN or
GENERIC
CONN HEADER VERT
3POS .100 TIN or
GENERIC
Steward
HZ0603B751R-10
FERRITE 200MA 938
OHMS 0603 SMD
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Table 5-1: Parts List
Item Qty Reference Part Description Mfg / Mfg PN / Notes
Panasonic - ECG
ELL-6SH100M
20 1 L3 10uH IND_ELL6
COIL 10UH 1300MA
CHOKE SMD
21 2 P1, P2 HEADER_20X2 HDR2X20/2MM 3M 151240-8422-RB
22 3 R1, R2, R3 10k R0402
23 3 R4, R7, R19 0 R0603
24 1 R5 150k 1% R0402
25 5 R6, R8, R9, R11, R20 0 R0402
26 1 R10 33 1% R0402
27 0 R12, R13 NP R0402
28 3 R14, R15, R16 270 1% R0402
29 3 R17, R18, R23 47k R0402
30 1 R21 887k 1% RC0603
31 1 R22 22k R0402
32 1 R24 200k
33 6
SH1, SH2, SH3, SH4,
SH5, SH6
.100 in. Jumper Shunt Not Applicable
34 1 SW1 SW4_DIPSW4 DIPSW4
35 1 SW2 SW TACT-SPST SW_EVQQW
36 2 TPGND1, TP3.3VDD1 TP_SMT TP_1206
37 0 TP1, TP2, TP3, TP4 T POINT F SIP1
38 1 U1 S1D13743
Panasonic - ECG
EVN-5ESX50B25
Sullins Electronics Corp.
STC02SYAN
JUMPER SHORTING TIN
CTS Corp 218-4LPST
SWITCH DIP HALF
PITCH 4POS
ITT Industries
KSC241GLFS
SWITCH TACT SILVER
PLT GULLWING
Keystone 5015
PC TEST POINT
MINIATURE SMT
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Table 5-1: Parts List
Item Qty Reference Part Description Mfg / Mfg PN / Notes
Texas Instruments
TPS76915DBVT
39 1 U2 TPS76915DBVT SOT23-5
IC 1.5V 100MA LDO REG
SOT-23-5
TI TPS61040DVBR
40 1 U3 TPS61040 SOT23-5
41 1 Y1 4M OSC
42 0 Y2 14-Pin DIP AMP 2-641609-1
IC CONV DC/DC BOOST
LP SOT-23-5
Connor-Winfield
CWX823-4.0M
OSC 4.0000MHz 3.3V
50ppm SMD
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5
5
4
4
3
3
2
2
1
1
D
D
C
C
B B
A A
VD12
VD0
MD12
VD20
VD13
MD10
VD15
VD4
MD13
VD7
MD8
MD2
VD16
MD14
VD22
VD9
VD5
MD15
MD9
VD8
MD11 VD11
VD2
VD18
MD3
VD17
VD23
VD21
VD3
VD10
VD6MD6
MD5
MD1
VD14
VD1
MD7
MD0
VD19
MD4
VD24
VD25
VD26
VD27
VD28
VD29
VD30
VD31
VD32
VD33
VD34
VD35
1.5VDD
CORE
CORE
IO
PIOVDD
PIO
PIOIO PLL
1.5VDD
PLL
IOVDD
IOVDD_IN
3.3VDD
PIOVDD_IN
3.3VDD
PIOVDD
IOVDD
IOVDD
VD[35:0]
3
VS
3HS3
PCLK3DE
3
MD[15:0]
2
CLKI2
RESET#
2
GPIO_IN T
2
CS#2RD#2WE#
2TE2
D/C#
2
CLKOUTEN 3
CLKOUT
3
PWRSVE3
GPIO7
3
GPIO63GPIO53GPIO43GPIO33GPIO23GPIO13GPIO0
3
Title
Size Document Number Rev
Date:
Sheet of
<Doc> 1.0
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B
13Saturday, Ju ne 09, 2007
Title
Size Document Number Rev
Date:
Sheet of
<Doc> 1.0
S1D13742/S1 D13 74 3 PF BG A 121
B
13Saturday, Ju ne 09, 2007
Title
Size Document Number Rev
Date:
Sheet of
<Doc> 1.0
S1D13742/S1 D13 74 3 PF BG A 121
B
13Saturday, Ju ne 09, 2007
Place a 0.01uF a nd a 0.1uF cap on eac h COREVDD
power pin of the S1D1374 2/S1D743
Place a 0.01uF a nd a 0.1uF cap on ea ch IOVDD
power pins of the S1D137 42 /S1 D13 74 3
Place a 0.01uF a nd a 0.1uF cap on ea ch PIOVDD
power pins of the S1D137 42 /S1 D13 74 3
C7
0.01uFC70.01uF
C24
0.01uF
C24
0.01uF
L1
FerriteL1Ferrite
C6
0.01uFC60.01uF
R1
10kR110k
The pin names enclosed in brac kets applies to S1D13743 only.
U1
S1D13742 (S1D13 743)
The pin names enclosed in brac kets applies to S1D13743 only.
U1
S1D13742 (S1D13 743)
MD0C1MD1C3MD2B2MD3
A5
MD4A6MD5
A7
MD6A8MD7
A9
MD8
B8
MD9B9MD10
B10
MD11
C2
MD12
B3
MD13
B5
MD14
B6
MD15
B7
W
E#
C8
RD#
C9
CS#C7D/C#
C10
TED2GPIO_INT
D3
RESET#
D1
VD0
L9
VD1L8VD2
L7
VD3L6VD4L5VD5
L4
VD6
L3
VD7
K10
VD8
K9
VD9
K8
VD10
K7
VD11
K6
VD12
K5
VD13
K4
VD14
J11
VD15
J10
VD16
J9
VD17
J8
VD18
J7
VD19J6VD20
J5
VD21
J4
VD22
H11
VD23
H10
VD24 (NC)
H9
VD25 (NC)H8VD26 (NC)
G11
VD27 (NC)
G10
VD28 (NC)G9VD29 (NC)G8VD30 (NC)
F11
VD31 (NC)
F10
VD32 (NC)
F9
VD33 (NC)
F8
VD34 (NC)
E11
VD35 (NC)
E10VSD10HSD9
PCLK
D11DEC11
CLKI
A4
CLKOUT
A3
CLKOUTEN
B4
CNF2H3CNF1
G3
CNF0
F3
TESTEN
E3
GPIO0
G1
GPIO1
G2
GPIO2
H1
GPIO3H2GPIO4J1GPIO5J2GPIO6K2GPIO7
K3
PWRSVE
J3
TEST2
E2
TEST1E1TEST0
F1
SCANEN
F2
VCP
D5
CoreVDD
D7
CoreVDD
E4
CoreVDD
G7
CoreVDD
H6
IOVDD
C4
IOVDD
D8
IOVDD
H4
PIOVDD
E8
PIOVDD
G4
PIOVDD
H5
PIOVDD
H7
PLLVDD
D4
PLLVSS
D6
VSS
C5
VSS
C6
VSS
E5
VSS
E6
VSS
E7
VSS
F4
VSS
F5
VSS
F6
VSS
F7
VSS
G5
VSS
G6
NC
A1
NC
A2
NC
A10
NC
A11
NC
B1
NC
B11
NC
E9
NC
K1
NC
K11
NC
L1
NC
L2
NC
L10
NC
L11
C20
0.1uF
C20
0.1uF
C23
0.01uF
C23
0.01uF
R2
10kR210k
C5
0.01uFC50.01uF
R3
10kR310k
C21
0.1uF
C21
0.1uF
C22
0.01uF
C22
0.01uF
C19
0.1uF
C19
0.1uF
JP5
PIOVDD
JP5
PIOVDD
1
2
JP2
PLLVDD
JP2
PLLVDD
1
2
JP4
IOVDD SOURCE
JP4
IOVDD SOURCE
123
C4
0.1uFC40.1uF
SH5
.100 in. Jum p er Shunt
SH5
.100 in. Jum p er Shunt
SH2
.100 in. Jum p er Shunt
SH2
.100 in. Jum p er Shunt
C25
0.01uF
C25
0.01uF
SH4
.100 in. Jumper Shunt
SH4
.100 in. Jumper Shunt
C18
0.1uF
C18
0.1uF
C17
0.01uF
C17
0.01uF
C10
1nF
C10
1nF
L2
FerriteL2Ferrite
C3
0.1uFC30.1uF
SW1
SW4_DIPSW4
SW1
SW4_DIPSW4
123
4
876
5
C16
0.01uF
C16
0.01uF
JP3
IOVDD
JP3
IOVDD
1
2
C14
0.1uF
C14
0.1uF
JP6
PIOVDD SOURCE
JP6
PIOVDD SOURCE
123
SH3
.100 in. Jum p er Shunt
SH3
.100 in. Jum p er Shunt
C2
0.1uFC20.1uF
C9
0.1uFC90.1uF
JP1
COREVDD
JP1
COREVDD
1
2
SH1
.100 in. Jum p er Shunt
SH1
.100 in. Jum p er Shunt
C13
0.1uF
C13
0.1uF
C15
0.01uF
C15
0.01uF
C11
10uF
C11
10uF
SH6
.100 in. Jumper Shunt
SH6
.100 in. Jumper Shunt
C1
0.1uFC10.1uF
C8
0.01uFC80.01uF
C12
0.1uF
C12
0.1uF
Vancouver Design Center

6 Schematic Diagrams

S5U13743P00C100 Evaluation Board User Manual S1D13743 Issue Date: 2007/08/15 X70A-G-001-01

Figure 6-1: S5U13743P00C100 Schematics (1 of 3)

Revision 1.0
Page 22
Page 22 Epson Research and Development
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B B
A A
WE#
MD12
MD14
RD#
MD15
MD13
MD11
MD0
MD9
MD2
MD4
MD6
GPIO_INT
CS#
MD1
MD3
MD5
MD7
MD8
MD10
D/C#
HEARTBEAT ENUMERATED
HEARTBEAT ENUMERATED
MD12
MD14
MD4
MD6
CS#
MD9
MD11
GPIO_INT
MD5
MD7
MD13
MD15
MD0
MD2
MD1
MD3
WE#
MD8
MD10
D/C#
RD#
3.3VDD
3.3VDD
IOVDD
IOVDD_IN
3.3VDD
IOVDD
3.3VDD
1.5VDD
IOVDD
3.3VDD
CS#
1
MD[15:0]
1
RD#
1
WE#
1
RESET#
1TE1
GPIO_INT
1
D/C#
1
CLKI
1
RESET#
1
Title
Size Document Numbe r Rev
Date:
Sheet of
<Doc> 1.0
Host connectors / 1.5V power / clock / reset
B
23Saturday, June 09, 2007
Title
Size Document Numbe r Rev
Date:
Sheet of
<Doc> 1.0
Host connectors / 1.5V power / clock / reset
B
23Saturday, June 09, 2007
Title
Size Document Numbe r Rev
Date:
Sheet of
<Doc> 1.0
Host connectors / 1.5V power / clock / reset
B
23Saturday, June 09, 2007
TTL/CMOS
Oscillator
Y2
14-Pin DIPY214-Pin DIP
OE
1
OUT
8
GND
7
VDD
14
Y1
4M OSCY14M OSC
OE
1
OUT
3
GND
2
VDD
4
TP3.3VDD1
TP_SMT
TP3.3VDD1
TP_SMT
1
R5R5
150k 1%
C33
0.01uF
C33
0.01uF
R10
33 1%R10 33 1%
TP3TP3
R15
270 1%
R15
270 1%
C26
0.1uF
C26
C31
0.01uF
C31
0.01uF
P1
HEADER_20X2P1HEADER_20X2
2468101214161820222426283032343638
40
13579
111315171921232527293133353739
TPGND1
TP_SMT
TPGND1
TP_SMT
1
SW2
SW TACT-SPS T
SW2
SW TACT-SPS T
2
4 3
1
C30
0.1uF
C30
0.1uF
D2
LED2D2LED2
AK
R7 0R7 0
R6
0R60
R8 0R8 0
D1
LED1D1LED1
AK
R4 0R4 0
C32
0.1uF
C32
0.1uF
R14
270 1%
R14
270 1%
C27
0.1uF
C27
0.1uF
TP1TP1
R11
0R11 0
R12 NPR12 NP
R16
270 1%
R16
270 1%
+
C29
100uF 4V T+C29
100uF 4V T
12
R90R9
0
H1
HEADER_17X2H1HEADER_17X2
246810121416182022242628303234
13579
1113151719212325272931
33
R13 NPR13 NP
C28
0.1uF
C28
0.1uF
D3
3.3V PowerD33.3V Power
AK
P2
HEADER_20X2P2HEADER_20X2
2468101214161820222426283032343638
40
13579
111315171921232527293133353739
TP2TP2
U2
TPS76915DB VTU2TPS76915DB VT
Vin
1
GND
2
/EN
3
Vout
5
NC/FB
4

Figure 6-2: S5U13743P00C100 Schematics (2 of 3)

S1D13743 S5U13743P00C100 Evaluation Board User Manual X70A-G-001-01 Issue Date: 2007/08/15
Revision 1.0
Page 23
Epson Research and Development Page 23
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B B
A A
VD30
VD32
VD34
VD27
VD29
VD31
VD33
VD35
VD18
VD10
VD15
VD11
VD16
VD17
VD5
VD14
VD9
VD3
VD4
VD12
VD13
VD6
VD7
VD8
VD2
VD1
VD0
VD19
VD20 VD21
VD22
VD24
VD23
VD25
VD26
VD28
12VDD3.3VDD
PIOVDD_IN
IOVDD
12VDD
PIOVDD
GPIO0
1
GPIO21GPIO41GPIO6
1GPIO71
GPIO11GPIO3
1
CLKOUTEN
1
PWRSVE
1
CLKOUT
1
GPIO5
1
HS
1VS1
PCLK1DE
1
VD[35:0]
1
Title
Size Document Numbe r Rev
Date:
Sheet of
<Doc> 1.0
LCD Connectors/ GPIO connector
B
33Saturday, June 09, 2007
Title
Size Document Numbe r Rev
Date:
Sheet of
<Doc> 1.0
LCD Connectors/ GPIO connector
B
33Saturday, June 09, 2007
Title
Size Document Numbe r Rev
Date:
Sheet of
<Doc> 1.0
LCD Connectors/ GPIO connector
B
33Saturday, June 09, 2007
Internal Step Up 6 to 24V
Power Supply
Typical 12V @ 40mA
Vout=1.233x[1+R103/(R105+R106)] (V)
R24
200k
R24
200k
13
2
TP4TP4
R21
887k 1%
R21
887k 1%
H4
HEADER 8X2H4HEADER 8X2
2468101214
16
13579
111315
U3
TPS61040U3TPS61040
VIN5EN
4
GND
2SW1FB3
C36
1uF 50V
C36
1uF 50V
+
C34
4.7uF 10V T
+
C34
4.7uF 10V T
12
F2
ACF451832-22 2F2ACF451832-22 2
1
2
3
R200R20
0
R22
22k
R22
22k
H3
LCD ConnectorH3LCD Connector
2468101214161820222426283032343638
40
13579
111315171921232527293133353739
R17
47k
R17
47k
R19
0
R19
0
R18
47k
R18
47k
C35
10pF
C35
10pF
R23
47k
R23
47k
L3
10uHL310uH
H2
Extended LCD ConnectorH2Extended LCD Connector
13579
1113151719
24681012141618
20
F1
ACF451832-222F1ACF451832-222
1
2
3
D4
MBR0530D4MBR0530
A K
Vancouver Design Center

Figure 6-3: S5U13743P00C100 Schematics (3 of 3)

S5U13743P00C100 Evaluation Board User Manual S1D13743 Issue Date: 2007/08/15 X70A-G-001-01
Revision 1.0
Page 24
Page 24 Epson Research and Development

7 Board Layout

Figure 7-1: S5U13743P00C100 Board Layout - Top View

S1D13743 S5U13743P00C100 Evaluation Board User Manual X70A-G-001-01 Issue Date: 2007/08/15
Revision 1.0
Page 25
Epson Research and Development Page 25 Vancouver Design Center

Figure 7-2: S5U13743P00C100 Board Layout - Bottom View

S5U13743P00C100 Evaluation Board User Manual S1D13743 Issue Date: 2007/08/15 X70A-G-001-01
Revision 1.0
Page 26
Page 26 Epson Research and Development

8 References

8.1 Documents

• Epson Research and Developmen t, Inc., S1D1374 3 Hardware Funct ional Speci fication , document number X70A-A-001-xx.

8.2 Document Sources

• Epson Research and Development Website: http://www.erd.epson.com.
S1D13743 S5U13743P00C100 Evaluation Board User Manual X70A-G-001-01 Issue Date: 2007/08/15
Revision 1.0
Page 27
Epson Research and Development Page 27
Japan
Seiko Epson Corporation IC International Sales Group 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp/
Hong Kong
Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 http://www.epson.com.hk/
Taiwa n
Epson Taiwan Technology & Trading Ltd. 14F, No. 7 Song Ren Road Taipei 110, Taiwan, ROC Tel: 02-8786-6688 Fax: 02-8786-6677 http://www.epson.com.tw/
Singapore
Epson Singapore Pte Ltd 1 HarbourFront Place #03-02 HarbourFront Tower One Singapore, 098633 Tel: (65) 6586-5500 Fax: (65) 6271-3182 http://www.epson.com.sg/
Europe
Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110 http://www.epson-electronics.de/
North America
Epson Electronics America, Inc. 2580 Orchard Parkway San Jose, CA 95131, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com/
Vancouver Design Center

9 Technical Support

9.1 EPSON Display Controllers (S1D13743)

9.2 Ordering Information

To order the S5U13743P00C100 Evalu ation Board , contact t he Epson sales r epresent ative in your area and order part number S5U13743P00C100.
S5U13743P00C100 Evaluation Board User Manual S1D13743 Issue Date: 2007/08/15 X70A-G-001-01
Revision 1.0
Page 28
Page 28 Epson Research and Development

Change Record

X70A-G-001-01 Revision 1.0 - Issued: August 15, 2007
• created from X63A-G-002-01
• updated for the S1D13743
S1D13743 S5U13743P00C100 Evaluation Board User Manual X70A-G-001-01 Issue Date: 2007/08/15
Revision 1.0
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