4. PAD .................................................................................................................................................................8-4
9. ABSOLUTE MAXIMUM RATINGS ................................................................................................................8-64
10. DC CHARACTERISTICS...............................................................................................................................8-65
12. THE MPU INTERFACE (REFERENCE EXAMPLES) ...................................................................................8-81
13. CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLE).....................................................8-82
14. CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLES) ..................................................8-83
15. A SAMPLE TCP PIN ASSIGNMENT.............................................................................................................8-84
16. EXTERNAL VIEW OF TCP PINS..................................................................................................................8-85
– i –
Rev. 2.4a
S1D15605 Series
1. DESCRIPTION
The S1D15605 Series is a series of single-chip dot matrix
liquid crystal display drivers that can be connected
directly to a microprocessor bus. 8-bit parallel or serial
display data sent from the microprocessor is stored in
the internal display data RAM and the chip generates a
liquid crystal drive signal independent of the mi croprocessor. Because the chips in the S1D15605
contain 65 × 132 bits of display data RAM and there is
a 1-to-1 correspondence between the liquid crystal
panel pixels and the internal RAM bits, these chips
enable displays with a high degree of freedom.
The S1D15606
circuits and 132 segment output circuits, so that a single
chip can drive a 49 × 132 dot display (capable of
displaying 8 columns × 4 rows of a 16 × 16 dot kanji
font). The S1D15607
output circuits and 132 segment output circuits, so that
a single chip can drive 33 × 132 dot display (capable of
displaying 8 columns × 2 rows of 16 × 16 dot kanji
fonts). Thanks to the built-in 55 common output circuits
and 132 segment output circuits, the S1D15608
is capable of displaying 55 × 132 dots (11 columns × 4
lines using 11 × 12 dots Kanji font) with a single chip.
The S1D15609
circuits and 132 segment output circuits, so that a single
chip can drive 53 × 132 dot display (capable of displaying
11 columns × 4 rows of 11 × 12 dot kanji fonts).
Moreover, the capacity of the display can be extended
through the use of master/slave structures between
chips.
The chips are able to minimize power consumption
because no external operating clock is necessary for the
display data RAM read/write operation. Furthermore,
because each chip is equipped internally with a lowpower liquid crystal driver power supply, resistors for
liquid crystal driver power voltage adjustment and a
display clock CR oscillator circuit, the S1D15605 Series
chips can be used to create the lowest power display
system with the fewest components for highperformance portable devices.
*****
*****
chips contain 49 common output
*****
chips contain 33 common
chips contain 53 common output
*****
*****
2. FEATURES
• Direct display of RAM data through the display data
RAM.
RAM bit data: “1” Display on
“0” Display off
(during normal display)
• RAM capacity
65 × 132 = 8580 bits
• Display driver circuits
S1D15605
S1D15606
S1D15607
S1D15608
S1D15609
*****
*****
*****
*****
*****
:65 common output and 132
segment outputs
:49 common output and 132
segment outputs
:33 common outputs and 132
segment outputs
:55 common outputs and 132
segment outputs
:53 common outputs and 132
segment outputs
• High-speed 8-bit MPU interface (The chip can be
connected directly to the both the 80x86 series MPUs
and the 68000 series MPUs)
/Serial interfaces are supported.
• Abundant command functions
Display data Read/Write, display ON/OFF, Normal/
Reverse display mode, page address set, display start
line set, column address set, status read, display all
points ON/OFF, LCD bias set, electronic volume,
read/modify/write, segment driver direction select,
power saver, static indicator, common output status
select, V5 voltage regulation internal resistor ratio
set.
• Static drive circuit equipped internally for indicators.
(1 system, with variable flashing speed.)
• Low-power liquid crystal display power supply circuit
equipped internally.
Booster circuit (with Boost ratios of Double/Triple/
Quad, where the step-up voltage reference power
supply can be input externally)
High-accuracy voltage adjustment circuit (Thermal
gradient –0.05%/°C or –0.2%/°C or external input)
V
5 voltage regulator resistors equipped internally,
V
1 to V4 voltage divider resistors equipped internally,
electronic volume function equipped internally,
voltage follower.
• CR oscillator circuit equipped internally (external
clock can also be input)
• Extremely low power consumption
Operating power when the built-in power supply is
used (an example)
DDPowerShared with the MPU power supply terminal VCC.13
V
No. of
Pins
Supply
SSPowerThis is a 0V terminal connected to the system GND.9
V
Supply
SS2PowerThis is the reference power supply for the step-up voltage circuit for the4
V
Supplyliquid crystal drive.
RSPowerThis is the externally-input VREG power supply for the LCD power supply2
V
Supplyvoltage regulator.
These are only enabled for the models with the VREG external input option.
1, V2,PowerThis is a multi-level power supply for the liquid crystal drive. The voltage10
V
V
3, V4,Supplyapplied is determined by the liquid crystal cell, and is changed through the
V
5use of a resistive voltage divided or through changing the impedance using
an op. amp. Voltage levels are determined based on V
DD, and must
maintain the relative magnitudes shown below.
V
DD (= V0) ≥ V1≥ V2≥ V3≥ V4≥ V5
Master operation: When the power supply turns ON, the internal power
supply circuits produce the V1 to V4 voltages shown below. The voltage
settings are selected using the LCD bias set command.
CAP1+ODC/DC voltage converter. Connect a capacitor between this terminal and2
the CAP1- terminal.
CAP1–ODC/DC voltage converter. Connect a capacitor between this terminal and2
the CAP1+ terminal.
CAP2+ODC/DC voltage converter. Connect a capacitor between this terminal and2
the CAP2- terminal.
CAP2–ODC/DC voltage converter. Connect a capacitor between this terminal and2
the CAP2+ terminal.
CAP3–ODC/DC voltage converter. Connect a capacitor between this terminal and2
the CAP1+ terminal.
OUTI/ODC/DC voltage converter. Connect a capacitor between this terminal and2
V
V
SS2.
RIOutput voltage regulator terminal. Provides the voltage between VDD and2
V
V5 through a resistive voltage divider.
These are only enabled when the V
5 voltage regulator internal resistors are
not used (IRS = LOW).
These cannot be used when the V
5 voltage regulator internal resistors are
used (IRS = HIGH).
No. of
Pins
8–20EPSONRev. 2.4a
System Bus Connection Terminals
S1D15605 Series
Pin NameI/OFunction
D7 to D0I/OThis is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit8
standard MPU data bus.
(SI)When the serial interface is selected (P/S = LOW), then D7 serves as the
(SCL)serial data input terminal (SI) and D6 serves as the serial clock input
terminal (SCL). At this time, D0 to D5 are set to high impedance.
When the chip select is inactive, D0 to D7 are set to high impedance.
A0IThis is connect to the least significant bit of the normal MPU address bus,1
and it determines whether the data bits are data or a command.
A0 = HIGH: Indicates that D0 to D7 are display data.
A0 = LOW: Indicates that D0 to D7 are display control data.
RESIWhen RES is set to LOW, the settings are initialized.1
The reset operation is performed by the RES signal level.
CS1IThis is the chip select signal. When CS1 = LOW and CS2 = HIGH, then the2
CS2chip select becomes active, and data/command I/O is enabled.
RDI• When connected to an 8080 MPU, this is active LOW.1
(E)This pin is connected to the RD signal of the 8080 MPU, and the
S1D15605 series data bus is in an output status when this signal is LOW.
• When connected to a 6800 Series MPU, this is active HIGH.
This is the 6800 Series MPU enable clock input terminal.
WRI• When connected to an 8080 MPU, this is active LOW.1
(R/W)This terminal connects to the 8080 MPU WR signal. The signals on
the data bus are latched at the rising edge of the WR signal.
• When connected to a 6800 Series MPU:
This is the read/write control signal input terminal.
When R/W = HIGH: Read.
When R/W = LOW: Write.
P/SIThis is the parallel data input/serial data input switch terminal.1
P/S = HIGH: Parallel data input.
P/S = LOW: Serial data input.
The following applies depending on the P/S status:
No. of
Pins
P/SData/CommandDataRead/Write Serial Clock
HIGHA0D0 to D7RD, WR
LOWA0SI (D7)Write onlySCL (D6)
When P/S = LOW, D0 to D5 are HZ. D0 to D5 may be HIGH, LOW or Open.
RD (E) and WR (P/W) are fixed to either HGIH or LOW.
With serial data input, RAM display data reading is not supported.
CLSITerminal to select whether or enable or disable the display clock internal1
oscillator circuit.
CLS = HIGH: Internal oscillator circuit is enabled
CLS = LOW: Internal oscillator circuit is disabled (requires external input)
When CLS = LOW, input the display clock through the CL terminal.
When using the S1D15605 Series as a master or slave, set respective
CLS pins at the same level.
M/SIThis terminal selects the master/slave operation for the S1D15605 Series1
chips. Master operation outputs the timing signals that are required for the
LCD display, while slave operation inputs the timing signals required for the
liquid crystal display, synchronizing the liquid crystal display system.
M/S = HIGH: Master operation
M/S = LOW: Slave operation
The following is true depending on the M/S and CLS status:
The following is true depending on the M/S and CLS status.
M/SCLSCL
HIGHHIGH
LOW
LOWHIGH
LOW
Output
Input
Input
Input
When the S1D15605 Series chips are used in master/slave mode, the
various CL terminals must be connected.
FRI/OThis is the liquid crystal alternating current signal I/O terminal.1
M/S = HIGH: Output
M/S = LOW: Input
When the S1D15605 Series chip is used in master/slave mode, the various
FR terminals must be connected.
DOFI/OThis is the liquid crystal display blanking control terminal.1
M/S = HIGH: Output
M/S = LOW: Input
When the S1D15605 Series chip is used in master/slave mode, the various
DOF terminals must be connected.
FRSOThis is the output terminal for the static drive.1
This terminal is only enabled when the static indicator display is ON when
in master operation mode, and is used in conjunction with the FR terminal.
IRSIThis terminal selects the resistors for the V
5 voltage level adjustment.1
IRS = HIGH: Use the internal resistors
IRS = LOW: Do not use the internal resistors. The V
5 voltage level is
regulated by an external resistive voltage divider attached to the VR
terminal.
This pin is enabled only when the master operation mode is selected.
It is fixed to either HIGH or LOW when the slave operation mode is selected.
HPMIThis is the power control terminal for the power supply circuit for liquid1
crystal drive.
HPM = HIGH: Normal mode
HPM = LOW: High power mode
This pin is enabled only when the master operation mode is selected.
It is fixed to either HIGH or LOW when the slave operation mode is selected.
8–22EPSONRev. 2.4a
Liquid Crystal Drive Terminals
S1D15605 Series
Pin NameI/OFunction
SEG0OThese are the liquid crystal segment drive outputs. Through a combination132
toof the contents of the display RAM and with the FR signal, a single level is
SEG131selected from V
RAM DATAFROutput Voltage
HIGHHIGHVDDV2
HIGHLOWV5V3
LOWHIGHV2VDD
LOWLOWV3V5
Power save—VDD
COM0OThese are the liquid crystal common drive outputs.
to
COMn
Part No.COM
S1D15605
S1D15606
S1D15607
S1D15608
S1D15609
Through a combination of the contents of the scan data and with the
FR signal, a single level is selected from V
DD, V2, V3, and V5.
*****
*****
*****
*****
*****
COM 0 ~ COM 63
COM 0 ~ COM 47
COM 0 ~ COM 31
COM 0 ~ COM 53
COM 0 ~ COM 51
Normal DisplayReverse Display
Part No.No. of pins
S1D15605
S1D15606
S1D15607
S1D15608
S1D15609
DD, V1, V4, and V5.
*****
*****
*****
*****
*****
64
48
32
54
52
No. of
Pins
Scan DataFROutput Voltage
HIGHHIGHV5
HIGHLOWVDD
LOWHIGHV1
LOWLOWV4
Power Save—VDD
COMSOThese are the COM output terminals for the indicator. Both terminals2
output the same signal.
Leave these open if they are not used.
When in master/slave mode, the same signal is output by both master and
slave.
Test Terminals
Pin NameI/OFunction
TEST0 to 9
I/OThese are terminals for IC chip testing.14
TEST0 to 4 and 7 to 9 should be open, TEST 5 and 6 should be fixed to
HIGH.
Total:288 pins for the S1D15605
272 pins for the S1D15606
256 pins for the S1D15607
278 pins for the S1D15608
276 pins for the S1D15609
No. of
*****
*****
*****
*****
*****
Pins
.
.
.
.
.
Rev. 2.4aEPSON8–23
S1D15605 Series
6. DESCRIPTION OF FUNCTIONS
The MPU Interface
Selecting the Interface Type
With the S1D15605 Series chips, data transfers are done
through an 8-bit bi-directional data bus (D7 to D0) or
P/SCS1CS2A0RDWRC86D7D6D5~D0
HIGH: Parallel Input
LOW: Serial InputCS1CS2A0———SISCL(HZ)
“—” indicates fixed to either HIGH or to LOW. HZ is in the state of High Impedance.
The Parallel Interface
When the parallel interface has been selected (P/S =
HIGH), then it is possible to connect directly to either an
HIGH: 6800 Series MPU Bus
LOW: 8080 MPU BusCS1CS2A0RDWRD7~D0
CS1CS2A0RDWRC86D7D6D5~D0
P/SCS1CS2A0RDWRD7~D0
CS1CS2A0ER/WD7~D0
through a serial data input (SI). Through selecting the P/
S terminal polarity to the HIGH or LOW it is possible to
select either parallel data input or serial data input as
shown in Table 1.
Table 1
8080-system MPU or a 6800 Series MPU (as shown in
Table 2) by selecting the C86 terminal to either HIGH
or to LOW.
Table 2
Moreover, data bus signals are recognized by a
combination of A0, RD (E), WR (R/W) signals, as
shown in Table 3.
Shared6800 Series8080 Series
A0R/WRDWR
1101Reads the display data
1010Writes the display data
0101Status read
0010Write control data (command)
Table 3
Function
8–24EPSONRev. 2.4a
S1D15605 Series
The Serial Interface
When the serial interface has been selected (P/S =
LOW) then when the chip is in active state (CS1 = LOW
and CS2 = HIGH) the serial data input (SI) and the serial
clock input (SCL) can be received. The serial data is
read from the serial data input pin in the rising edge of
the serial clocks D7, D6 through D0, in this order. This
data is converted to 8 bits parallel data in the rising edge
CS1
CS2
SI
SCL
A0
D7
D6D5D4D3D2D7D6D5D4D3D2D1D0
1234567891011121314
of the eighth serial clock for the processing.
The A0 input is used to determine whether or the serial
data input is display data or command data; when A0 =
HIGH, the data is display data, and when A0 = LOW
then the data is command data. The A0 input is read and
used for detection every 8th rising edge of the serial
clock after the chip becomes active.
Figure 1 is a serial interface signal chart.
Figure 1
* When the chip is not active, the shift registers and the counter are reset to their initial states.
* Reading is not possible while in serial interface mode.
* Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend that
operation be rechecked on the actual equipment.
The Chip Select
The S1D15605 Series chips have two chip select
terminals: CS1 and CS2. The MPU interface or the
serial interface is enabled only when CS1 = LOW and
CS2 = HIGH.
When the chip select is inactive, D0 to D7 enter a high
impedance state, and the A0, RD, and WR inputs are
inactive. When the serial interface is selected, the shift
register and the counter are reset.
Accessing the Display Data RAM and the
Internal Registers
Data transfer at a higher speed is ensured since the MPU
is required to satisfy the cycle time (
tCYC) requirement
alone in accessing the S1D15605 Series. Wait time may
not be considered.
And, in the S1D15605 Series chips, each time data is
sent from the MPU, a type of pipeline process between
LSIs is performed through the bus holder attached to the
internal data bus.
For example, when the MPU writes data to the display
data RAM, once the data is stored in the bus holder, then
it is written to the display data RAM before the next data
write cycle. Moreover, when the MPU reads the display
data RAM, the first data read cycle (dummy) stores the
read data in the bus holder, and then the data is read from
the bus holder to the system bus at the next data read
cycle.
There is a certain restriction in the read sequence of the
display data RAM. Please be advised that data of the
specified address is not generated by the read instruction
issued immediately after the address setup. This data is
generated in data read of the second time. Thus, a
dummy read is required whenever the address setup or
write cycle operation is conducted.
This relationship is shown in Figure 2.
Rev. 2.4aEPSON8–25
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